From 2a241466d2069fe5c264726abda649c2904ea324 Mon Sep 17 00:00:00 2001
From: rmsyn <github@weathered-steel.dev>
Date: Sat, 11 Jan 2025 10:37:15 +0000
Subject: [PATCH] riscv: define mvendorid CSR with macro helpers

Uses CSR macro helpers to define the `mvendorid` CSR register.
---
 riscv/CHANGELOG.md              |  1 +
 riscv/src/register/mvendorid.rs | 36 +++++----------------------------
 2 files changed, 6 insertions(+), 31 deletions(-)

diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index 3894d740..c09ef787 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -28,6 +28,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Use CSR helper macros to define `mstatus` register
 - Use CSR helper macros to define `mstatush` register
 - Use CSR helper macros to define `mtvec` register
+- Use CSR helper macros to define `mtvendorid` register
 
 ## [v0.12.1] - 2024-10-20
 
diff --git a/riscv/src/register/mvendorid.rs b/riscv/src/register/mvendorid.rs
index 5c621478..41f5f2ba 100644
--- a/riscv/src/register/mvendorid.rs
+++ b/riscv/src/register/mvendorid.rs
@@ -1,34 +1,8 @@
 //! mvendorid register
 
-use core::num::NonZeroUsize;
-
-/// mvendorid register
-#[derive(Clone, Copy, Debug)]
-pub struct Mvendorid {
-    bits: NonZeroUsize,
-}
-
-impl Mvendorid {
-    /// Returns the contents of the register as raw bits
-    #[inline]
-    pub fn bits(&self) -> usize {
-        self.bits.get()
-    }
-
-    /// Returns the JEDEC manufacturer ID
-    #[inline]
-    pub fn jedec_manufacturer(&self) -> usize {
-        self.bits() >> 7
-    }
-}
-
-read_csr!(0xF11);
-
-/// Reads the CSR
-#[inline]
-pub fn read() -> Option<Mvendorid> {
-    let r = unsafe { _read() };
-    // When mvendorid is hardwired to zero it means that the mvendorid
-    // csr isn't implemented.
-    NonZeroUsize::new(r).map(|bits| Mvendorid { bits })
+read_only_csr! {
+    /// `mvendorid` register
+    Mvendorid: 0xF11,
+    mask: 0xffff_ffff,
+    sentinel: 0,
 }