From 95292c87b6ce705905263fae5976fa424a0fe654 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= Date: Wed, 24 Jan 2024 00:02:30 +0100 Subject: [PATCH 1/2] avoid spurious errors from LLVM --- riscv-rt/CHANGELOG.md | 3 +++ riscv-rt/build.rs | 4 ++-- riscv-rt/src/asm.rs | 19 +++++++++++++++++++ 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md index a1b7beb8..427cfcdd 100644 --- a/riscv-rt/CHANGELOG.md +++ b/riscv-rt/CHANGELOG.md @@ -7,6 +7,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +### Added + +- Patch in assembly code to avoid spurious errors from LLVM ## [v0.12.0] - 2024-01-14 diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs index b0302bb6..fa405808 100644 --- a/riscv-rt/build.rs +++ b/riscv-rt/build.rs @@ -34,8 +34,8 @@ fn parse_target(target: &str, cargo_flags: &str) -> (u32, HashSet) { .unwrap(); let mut extensions: HashSet = arch.chars().skip_while(|c| c.is_ascii_digit()).collect(); - // get rid of the 'g' shorthand extension - if extensions.remove(&'g') { + // expand the 'g' shorthand extension + if extensions.contains(&'g') { extensions.insert('i'); extensions.insert('m'); extensions.insert('a'); diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs index 0eedebe6..4c242238 100644 --- a/riscv-rt/src/asm.rs +++ b/riscv-rt/src/asm.rs @@ -19,6 +19,25 @@ macro_rules! cfg_global_asm { }; } +// Provisional patch to avoid LLVM spurious errors when compiling in release mode. +// This patch is somewhat hardcoded and relies on the fact that the rustc compiler +// only supports a limited combination of ISA extensions. This patch should be +// removed when LLVM fixes the issue. Alternatively, it must be updated when rustc +// supports more ISA extension combinations. +// +// Related issues: +// - https://github.com/rust-embedded/riscv/issues/175 +// - https://github.com/rust-lang/rust/issues/80608 +// - https://github.com/llvm/llvm-project/issues/61991 +cfg_global_asm!( + #[cfg(all(riscv32, riscvm))] + ".attribute arch, \"rv32im\"", + #[cfg(all(riscv64, riscvm, not(riscvg)))] + ".attribute arch, \"rv64im\"", + #[cfg(all(riscv64, riscvg))] + ".attribute arch, \"rv64g\"", +); + // Entry point of all programs (_start). It initializes DWARF call frame information, // the stack pointer, the frame pointer (needed for closures to work in start_rust) // and the global pointer. Then it calls _start_rust. From aa088e847446b616eafd615a8bb36a4a5c9aa7b6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= Date: Wed, 24 Jan 2024 00:10:32 +0100 Subject: [PATCH 2/2] minor fix --- riscv-rt/src/asm.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs index 4c242238..ea4b5233 100644 --- a/riscv-rt/src/asm.rs +++ b/riscv-rt/src/asm.rs @@ -30,6 +30,7 @@ macro_rules! cfg_global_asm { // - https://github.com/rust-lang/rust/issues/80608 // - https://github.com/llvm/llvm-project/issues/61991 cfg_global_asm!( + "// Provisional patch to avoid LLVM spurious errors when compiling in release mode.", #[cfg(all(riscv32, riscvm))] ".attribute arch, \"rv32im\"", #[cfg(all(riscv64, riscvm, not(riscvg)))]