From c92affa472297a7ae43980639544b06c4a1fbfdd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= Date: Wed, 8 Nov 2023 10:16:47 +0100 Subject: [PATCH] Transition to cargo workspace --- .github/workflows/changelog.yaml | 17 +++++++++--- Cargo.toml | 29 +++------------------ CHANGELOG.md => riscv/CHANGELOG.md | 1 + riscv/Cargo.toml | 26 ++++++++++++++++++ build.rs => riscv/build.rs | 0 {src => riscv/src}/asm.rs | 0 {src => riscv/src}/critical_section.rs | 0 {src => riscv/src}/delay.rs | 0 {src => riscv/src}/interrupt.rs | 0 {src => riscv/src}/lib.rs | 0 {src => riscv/src}/macros.rs | 0 {src => riscv/src}/register.rs | 0 {src => riscv/src}/register/cycle.rs | 0 {src => riscv/src}/register/cycleh.rs | 0 {src => riscv/src}/register/hpmcounterx.rs | 0 {src => riscv/src}/register/instret.rs | 0 {src => riscv/src}/register/instreth.rs | 0 {src => riscv/src}/register/macros.rs | 0 {src => riscv/src}/register/marchid.rs | 0 {src => riscv/src}/register/mcause.rs | 0 {src => riscv/src}/register/mcounteren.rs | 0 {src => riscv/src}/register/mcycle.rs | 0 {src => riscv/src}/register/mcycleh.rs | 0 {src => riscv/src}/register/medeleg.rs | 0 {src => riscv/src}/register/mepc.rs | 0 {src => riscv/src}/register/mhartid.rs | 0 {src => riscv/src}/register/mhpmcounterx.rs | 0 {src => riscv/src}/register/mhpmeventx.rs | 0 {src => riscv/src}/register/mideleg.rs | 0 {src => riscv/src}/register/mie.rs | 0 {src => riscv/src}/register/mimpid.rs | 0 {src => riscv/src}/register/minstret.rs | 0 {src => riscv/src}/register/minstreth.rs | 0 {src => riscv/src}/register/mip.rs | 0 {src => riscv/src}/register/misa.rs | 0 {src => riscv/src}/register/mscratch.rs | 0 {src => riscv/src}/register/mstatus.rs | 0 {src => riscv/src}/register/mstatush.rs | 0 {src => riscv/src}/register/mtval.rs | 0 {src => riscv/src}/register/mtvec.rs | 0 {src => riscv/src}/register/mvendorid.rs | 0 {src => riscv/src}/register/pmpaddrx.rs | 0 {src => riscv/src}/register/pmpcfgx.rs | 0 {src => riscv/src}/register/satp.rs | 0 {src => riscv/src}/register/scause.rs | 0 {src => riscv/src}/register/scounteren.rs | 0 {src => riscv/src}/register/sepc.rs | 0 {src => riscv/src}/register/sie.rs | 0 {src => riscv/src}/register/sip.rs | 0 {src => riscv/src}/register/sscratch.rs | 0 {src => riscv/src}/register/sstatus.rs | 0 {src => riscv/src}/register/stval.rs | 0 {src => riscv/src}/register/stvec.rs | 0 {src => riscv/src}/register/time.rs | 0 {src => riscv/src}/register/timeh.rs | 0 55 files changed, 44 insertions(+), 29 deletions(-) rename CHANGELOG.md => riscv/CHANGELOG.md (99%) create mode 100644 riscv/Cargo.toml rename build.rs => riscv/build.rs (100%) rename {src => riscv/src}/asm.rs (100%) rename {src => riscv/src}/critical_section.rs (100%) rename {src => riscv/src}/delay.rs (100%) rename {src => riscv/src}/interrupt.rs (100%) rename {src => riscv/src}/lib.rs (100%) rename {src => riscv/src}/macros.rs (100%) rename {src => riscv/src}/register.rs (100%) rename {src => riscv/src}/register/cycle.rs (100%) rename {src => riscv/src}/register/cycleh.rs (100%) rename {src => riscv/src}/register/hpmcounterx.rs (100%) rename {src => riscv/src}/register/instret.rs (100%) rename {src => riscv/src}/register/instreth.rs (100%) rename {src => riscv/src}/register/macros.rs (100%) rename {src => riscv/src}/register/marchid.rs (100%) rename {src => riscv/src}/register/mcause.rs (100%) rename {src => riscv/src}/register/mcounteren.rs (100%) rename {src => riscv/src}/register/mcycle.rs (100%) rename {src => riscv/src}/register/mcycleh.rs (100%) rename {src => riscv/src}/register/medeleg.rs (100%) rename {src => riscv/src}/register/mepc.rs (100%) rename {src => riscv/src}/register/mhartid.rs (100%) rename {src => riscv/src}/register/mhpmcounterx.rs (100%) rename {src => riscv/src}/register/mhpmeventx.rs (100%) rename {src => riscv/src}/register/mideleg.rs (100%) rename {src => riscv/src}/register/mie.rs (100%) rename {src => riscv/src}/register/mimpid.rs (100%) rename {src => riscv/src}/register/minstret.rs (100%) rename {src => riscv/src}/register/minstreth.rs (100%) rename {src => riscv/src}/register/mip.rs (100%) rename {src => riscv/src}/register/misa.rs (100%) rename {src => riscv/src}/register/mscratch.rs (100%) rename {src => riscv/src}/register/mstatus.rs (100%) rename {src => riscv/src}/register/mstatush.rs (100%) rename {src => riscv/src}/register/mtval.rs (100%) rename {src => riscv/src}/register/mtvec.rs (100%) rename {src => riscv/src}/register/mvendorid.rs (100%) rename {src => riscv/src}/register/pmpaddrx.rs (100%) rename {src => riscv/src}/register/pmpcfgx.rs (100%) rename {src => riscv/src}/register/satp.rs (100%) rename {src => riscv/src}/register/scause.rs (100%) rename {src => riscv/src}/register/scounteren.rs (100%) rename {src => riscv/src}/register/sepc.rs (100%) rename {src => riscv/src}/register/sie.rs (100%) rename {src => riscv/src}/register/sip.rs (100%) rename {src => riscv/src}/register/sscratch.rs (100%) rename {src => riscv/src}/register/sstatus.rs (100%) rename {src => riscv/src}/register/stval.rs (100%) rename {src => riscv/src}/register/stvec.rs (100%) rename {src => riscv/src}/register/time.rs (100%) rename {src => riscv/src}/register/timeh.rs (100%) diff --git a/.github/workflows/changelog.yaml b/.github/workflows/changelog.yaml index 2ea7fb89..ad78b0a7 100644 --- a/.github/workflows/changelog.yaml +++ b/.github/workflows/changelog.yaml @@ -1,4 +1,4 @@ -name: Check CHANGELOG.md +name: Changelog check on: merge_group: @@ -12,9 +12,18 @@ jobs: - name: Checkout code uses: actions/checkout@v4 - - name: Check for CHANGELOG.md + - name: Check which component is modified + uses: dorny/paths-filter@v2 + id: changes + with: + filters: | + riscv: + - 'riscv/**' + + - name: Check for CHANGELOG.md (riscv) + if: steps.changes.outputs.riscv == 'true' uses: dangoslen/changelog-enforcer@v3 with: + changeLogPath: ./riscv/CHANGELOG.md skipLabels: 'skip changelog' - missingUpdateErrorMessage: 'Please add a changelog entry in the CHANGELOG.md file.' - + missingUpdateErrorMessage: 'Please add a changelog entry in the riscv/CHANGELOG.md file.' diff --git a/Cargo.toml b/Cargo.toml index 9606eac5..0b7406f5 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,26 +1,5 @@ -[package] -name = "riscv" -version = "0.10.1" -edition = "2021" -rust-version = "1.59" -repository = "https://github.com/rust-embedded/riscv" -authors = ["The RISC-V Team "] -categories = ["embedded", "hardware-support", "no-std"] -description = "Low level access to RISC-V processors" -keywords = ["riscv", "register", "peripheral"] -license = "ISC" - -[package.metadata.docs.rs] -all-features = true -default-target = "riscv64imac-unknown-none-elf" -targets = [ - "riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf", - "riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf", +[workspace] +resolver = "2" +members = [ + "riscv", ] - -[features] -critical-section-single-hart = ["critical-section/restore-state-bool"] - -[dependencies] -critical-section = "1.1.2" -embedded-hal = "1.0.0-rc.1" diff --git a/CHANGELOG.md b/riscv/CHANGELOG.md similarity index 99% rename from CHANGELOG.md rename to riscv/CHANGELOG.md index bd788989..e1881c1f 100644 --- a/CHANGELOG.md +++ b/riscv/CHANGELOG.md @@ -20,6 +20,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Changed +- Transitioning to cargo workspace - Update `embedded-hal` dependency to v1.0 (bumps MSRV to 1.60) - `misa::MXL` renamed to `misa::XLEN` - Removed `bit_field` dependency diff --git a/riscv/Cargo.toml b/riscv/Cargo.toml new file mode 100644 index 00000000..9606eac5 --- /dev/null +++ b/riscv/Cargo.toml @@ -0,0 +1,26 @@ +[package] +name = "riscv" +version = "0.10.1" +edition = "2021" +rust-version = "1.59" +repository = "https://github.com/rust-embedded/riscv" +authors = ["The RISC-V Team "] +categories = ["embedded", "hardware-support", "no-std"] +description = "Low level access to RISC-V processors" +keywords = ["riscv", "register", "peripheral"] +license = "ISC" + +[package.metadata.docs.rs] +all-features = true +default-target = "riscv64imac-unknown-none-elf" +targets = [ + "riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf", + "riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf", +] + +[features] +critical-section-single-hart = ["critical-section/restore-state-bool"] + +[dependencies] +critical-section = "1.1.2" +embedded-hal = "1.0.0-rc.1" diff --git a/build.rs b/riscv/build.rs similarity index 100% rename from build.rs rename to riscv/build.rs diff --git a/src/asm.rs b/riscv/src/asm.rs similarity index 100% rename from src/asm.rs rename to riscv/src/asm.rs diff --git a/src/critical_section.rs b/riscv/src/critical_section.rs similarity index 100% rename from src/critical_section.rs rename to riscv/src/critical_section.rs diff --git a/src/delay.rs b/riscv/src/delay.rs similarity index 100% rename from src/delay.rs rename to riscv/src/delay.rs diff --git a/src/interrupt.rs b/riscv/src/interrupt.rs similarity index 100% rename from src/interrupt.rs rename to riscv/src/interrupt.rs diff --git a/src/lib.rs b/riscv/src/lib.rs similarity index 100% rename from src/lib.rs rename to riscv/src/lib.rs diff --git a/src/macros.rs b/riscv/src/macros.rs similarity index 100% rename from src/macros.rs rename to riscv/src/macros.rs diff --git a/src/register.rs b/riscv/src/register.rs similarity index 100% rename from src/register.rs rename to riscv/src/register.rs diff --git a/src/register/cycle.rs b/riscv/src/register/cycle.rs similarity index 100% rename from src/register/cycle.rs rename to riscv/src/register/cycle.rs diff --git a/src/register/cycleh.rs b/riscv/src/register/cycleh.rs similarity index 100% rename from src/register/cycleh.rs rename to riscv/src/register/cycleh.rs diff --git a/src/register/hpmcounterx.rs b/riscv/src/register/hpmcounterx.rs similarity index 100% rename from src/register/hpmcounterx.rs rename to riscv/src/register/hpmcounterx.rs diff --git a/src/register/instret.rs b/riscv/src/register/instret.rs similarity index 100% rename from src/register/instret.rs rename to riscv/src/register/instret.rs diff --git a/src/register/instreth.rs b/riscv/src/register/instreth.rs similarity index 100% rename from src/register/instreth.rs rename to riscv/src/register/instreth.rs diff --git a/src/register/macros.rs b/riscv/src/register/macros.rs similarity index 100% rename from src/register/macros.rs rename to riscv/src/register/macros.rs diff --git a/src/register/marchid.rs b/riscv/src/register/marchid.rs similarity index 100% rename from src/register/marchid.rs rename to riscv/src/register/marchid.rs diff --git a/src/register/mcause.rs b/riscv/src/register/mcause.rs similarity index 100% rename from src/register/mcause.rs rename to riscv/src/register/mcause.rs diff --git a/src/register/mcounteren.rs b/riscv/src/register/mcounteren.rs similarity index 100% rename from src/register/mcounteren.rs rename to riscv/src/register/mcounteren.rs diff --git a/src/register/mcycle.rs b/riscv/src/register/mcycle.rs similarity index 100% rename from src/register/mcycle.rs rename to riscv/src/register/mcycle.rs diff --git a/src/register/mcycleh.rs b/riscv/src/register/mcycleh.rs similarity index 100% rename from src/register/mcycleh.rs rename to riscv/src/register/mcycleh.rs diff --git a/src/register/medeleg.rs b/riscv/src/register/medeleg.rs similarity index 100% rename from src/register/medeleg.rs rename to riscv/src/register/medeleg.rs diff --git a/src/register/mepc.rs b/riscv/src/register/mepc.rs similarity index 100% rename from src/register/mepc.rs rename to riscv/src/register/mepc.rs diff --git a/src/register/mhartid.rs b/riscv/src/register/mhartid.rs similarity index 100% rename from src/register/mhartid.rs rename to riscv/src/register/mhartid.rs diff --git a/src/register/mhpmcounterx.rs b/riscv/src/register/mhpmcounterx.rs similarity index 100% rename from src/register/mhpmcounterx.rs rename to riscv/src/register/mhpmcounterx.rs diff --git a/src/register/mhpmeventx.rs b/riscv/src/register/mhpmeventx.rs similarity index 100% rename from src/register/mhpmeventx.rs rename to riscv/src/register/mhpmeventx.rs diff --git a/src/register/mideleg.rs b/riscv/src/register/mideleg.rs similarity index 100% rename from src/register/mideleg.rs rename to riscv/src/register/mideleg.rs diff --git a/src/register/mie.rs b/riscv/src/register/mie.rs similarity index 100% rename from src/register/mie.rs rename to riscv/src/register/mie.rs diff --git a/src/register/mimpid.rs b/riscv/src/register/mimpid.rs similarity index 100% rename from src/register/mimpid.rs rename to riscv/src/register/mimpid.rs diff --git a/src/register/minstret.rs b/riscv/src/register/minstret.rs similarity index 100% rename from src/register/minstret.rs rename to riscv/src/register/minstret.rs diff --git a/src/register/minstreth.rs b/riscv/src/register/minstreth.rs similarity index 100% rename from src/register/minstreth.rs rename to riscv/src/register/minstreth.rs diff --git a/src/register/mip.rs b/riscv/src/register/mip.rs similarity index 100% rename from src/register/mip.rs rename to riscv/src/register/mip.rs diff --git a/src/register/misa.rs b/riscv/src/register/misa.rs similarity index 100% rename from src/register/misa.rs rename to riscv/src/register/misa.rs diff --git a/src/register/mscratch.rs b/riscv/src/register/mscratch.rs similarity index 100% rename from src/register/mscratch.rs rename to riscv/src/register/mscratch.rs diff --git a/src/register/mstatus.rs b/riscv/src/register/mstatus.rs similarity index 100% rename from src/register/mstatus.rs rename to riscv/src/register/mstatus.rs diff --git a/src/register/mstatush.rs b/riscv/src/register/mstatush.rs similarity index 100% rename from src/register/mstatush.rs rename to riscv/src/register/mstatush.rs diff --git a/src/register/mtval.rs b/riscv/src/register/mtval.rs similarity index 100% rename from src/register/mtval.rs rename to riscv/src/register/mtval.rs diff --git a/src/register/mtvec.rs b/riscv/src/register/mtvec.rs similarity index 100% rename from src/register/mtvec.rs rename to riscv/src/register/mtvec.rs diff --git a/src/register/mvendorid.rs b/riscv/src/register/mvendorid.rs similarity index 100% rename from src/register/mvendorid.rs rename to riscv/src/register/mvendorid.rs diff --git a/src/register/pmpaddrx.rs b/riscv/src/register/pmpaddrx.rs similarity index 100% rename from src/register/pmpaddrx.rs rename to riscv/src/register/pmpaddrx.rs diff --git a/src/register/pmpcfgx.rs b/riscv/src/register/pmpcfgx.rs similarity index 100% rename from src/register/pmpcfgx.rs rename to riscv/src/register/pmpcfgx.rs diff --git a/src/register/satp.rs b/riscv/src/register/satp.rs similarity index 100% rename from src/register/satp.rs rename to riscv/src/register/satp.rs diff --git a/src/register/scause.rs b/riscv/src/register/scause.rs similarity index 100% rename from src/register/scause.rs rename to riscv/src/register/scause.rs diff --git a/src/register/scounteren.rs b/riscv/src/register/scounteren.rs similarity index 100% rename from src/register/scounteren.rs rename to riscv/src/register/scounteren.rs diff --git a/src/register/sepc.rs b/riscv/src/register/sepc.rs similarity index 100% rename from src/register/sepc.rs rename to riscv/src/register/sepc.rs diff --git a/src/register/sie.rs b/riscv/src/register/sie.rs similarity index 100% rename from src/register/sie.rs rename to riscv/src/register/sie.rs diff --git a/src/register/sip.rs b/riscv/src/register/sip.rs similarity index 100% rename from src/register/sip.rs rename to riscv/src/register/sip.rs diff --git a/src/register/sscratch.rs b/riscv/src/register/sscratch.rs similarity index 100% rename from src/register/sscratch.rs rename to riscv/src/register/sscratch.rs diff --git a/src/register/sstatus.rs b/riscv/src/register/sstatus.rs similarity index 100% rename from src/register/sstatus.rs rename to riscv/src/register/sstatus.rs diff --git a/src/register/stval.rs b/riscv/src/register/stval.rs similarity index 100% rename from src/register/stval.rs rename to riscv/src/register/stval.rs diff --git a/src/register/stvec.rs b/riscv/src/register/stvec.rs similarity index 100% rename from src/register/stvec.rs rename to riscv/src/register/stvec.rs diff --git a/src/register/time.rs b/riscv/src/register/time.rs similarity index 100% rename from src/register/time.rs rename to riscv/src/register/time.rs diff --git a/src/register/timeh.rs b/riscv/src/register/timeh.rs similarity index 100% rename from src/register/timeh.rs rename to riscv/src/register/timeh.rs