From 399c59813f76196b5b52ba132a569360cff330d3 Mon Sep 17 00:00:00 2001
From: David Reiss <dreiss@meta.com>
Date: Sun, 24 Mar 2024 20:06:01 -0700
Subject: [PATCH 1/2] impl From<usize> for Mcause

This is useful unit tests that want test trap handlers.
---
 riscv/CHANGELOG.md           | 4 ++++
 riscv/src/register/mcause.rs | 7 +++++++
 2 files changed, 11 insertions(+)

diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index 5807dccc..63fd8110 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Added
+
+- Add `Mcause::from(usize)` for use in unit tests
+
 ### Fixed
 
 - Fixed `sip::set_ssoft` and `sip::clear_ssoft` using wrong address
diff --git a/riscv/src/register/mcause.rs b/riscv/src/register/mcause.rs
index efe9e6a7..ff7f730b 100644
--- a/riscv/src/register/mcause.rs
+++ b/riscv/src/register/mcause.rs
@@ -6,6 +6,13 @@ pub struct Mcause {
     bits: usize,
 }
 
+impl From<usize> for Mcause {
+    #[inline]
+    fn from(bits: usize) -> Self {
+        Self { bits }
+    }
+}
+
 /// Trap Cause
 #[derive(Copy, Clone, Debug, PartialEq, Eq)]
 pub enum Trap {

From b3c100a8e2bef7a46b3913f728bebd5064bc7c97 Mon Sep 17 00:00:00 2001
From: David Reiss <dreiss@meta.com>
Date: Sun, 24 Mar 2024 20:08:09 -0700
Subject: [PATCH 2/2] Implement Mstatus.bits()

---
 riscv/CHANGELOG.md            | 1 +
 riscv/src/register/mstatus.rs | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index 63fd8110..82c3e204 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Added
 
 - Add `Mcause::from(usize)` for use in unit tests
+- Add `Mstatus.bits()`
 
 ### Fixed
 
diff --git a/riscv/src/register/mstatus.rs b/riscv/src/register/mstatus.rs
index 4f225ac2..c8d85ef6 100644
--- a/riscv/src/register/mstatus.rs
+++ b/riscv/src/register/mstatus.rs
@@ -65,6 +65,12 @@ impl From<bool> for Endianness {
 }
 
 impl Mstatus {
+    /// Returns the contents of the register as raw bits
+    #[inline]
+    pub fn bits(&self) -> usize {
+        self.bits
+    }
+
     /// Supervisor Interrupt Enable
     #[inline]
     pub fn sie(&self) -> bool {