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riscv: Add missing CSR's #1

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dvc94ch opened this issue Nov 20, 2017 · 3 comments
Open
3 of 13 tasks

riscv: Add missing CSR's #1

dvc94ch opened this issue Nov 20, 2017 · 3 comments
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@dvc94ch
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dvc94ch commented Nov 20, 2017 •
edited by romancardenas
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  • mpu
  • mdelet /mideleg
  • perf counters
  • senvcfg
  • scontext
  • mconfigptr
  • mtinst
  • mtval2
  • Machine Configuration registers
  • Machine Non-Maskable Interrupt Handling registers
  • Machine Counter Setup registers
  • Machine Debug/Trace registers
  • Machine Dabug Mode registers
@dvc94ch dvc94ch changed the title TODO Add missing CSR's Feb 28, 2018
@romancardenas romancardenas changed the title Add missing CSR's riscv: Add missing CSR's Nov 27, 2023
romancardenas pushed a commit that referenced this issue Dec 28, 2023
Merge pull request #1 from Jascha-N/fix-hprintln
81535b4 
fix typo in hprintln!
@bjorn3
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bjorn3 commented Aug 13, 2024

The Advanced Interrupt Architecture specification defines a bunch more CSR's:

  • miselect
  • mireg
  • mtopei
  • mtopi
  • mvien
  • mvip
  • siselect
  • sireg
  • stopei
  • stopi
  • hvien
  • hvictl
  • hviprio1
  • hviprio2
  • vsiselect
  • vsireg
  • vstopei
  • vstopi

@romancardenas
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Good point!

Maybe it would be a better idea to open a new issue where we can discuss how to implement the AIA in our ecosystem

@bjorn3
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bjorn3 commented Aug 19, 2024

Opened #226

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@dvc94ch @romancardenas @bjorn3