From 0c9b4841d0f26022f5b5c9f168d2ab9fc1936a04 Mon Sep 17 00:00:00 2001 From: purplethunder <43519497+purplethunder@users.noreply.github.com> Date: Wed, 29 Nov 2023 16:18:47 -0700 Subject: [PATCH 01/11] Pin embedded-hal to 1.0.0-rc.1 embedded-hal 1.0.0-rc.2 introduces backwards incompatible changes. This change pins the crate to 1.0.0-rc.1. --- riscv/Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/Cargo.toml b/riscv/Cargo.toml index 821ba0e5..bdae8024 100644 --- a/riscv/Cargo.toml +++ b/riscv/Cargo.toml @@ -24,4 +24,4 @@ critical-section-single-hart = ["critical-section/restore-state-bool"] [dependencies] critical-section = "1.1.2" -embedded-hal = "1.0.0-rc.1" +embedded-hal = "=1.0.0-rc.1" From 9c946165d4e329f8c45c4df37dd16356832857cc Mon Sep 17 00:00:00 2001 From: Aaron Gowatch Date: Wed, 29 Nov 2023 21:52:09 -0700 Subject: [PATCH 02/11] Implement DelayNs for McycleDelay --- riscv/src/delay.rs | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/riscv/src/delay.rs b/riscv/src/delay.rs index 7650670c..bcdfa7ac 100644 --- a/riscv/src/delay.rs +++ b/riscv/src/delay.rs @@ -1,6 +1,6 @@ //! Delay devices and providers use crate::register::mcycle; -use embedded_hal::delay::DelayUs; +use embedded_hal::delay::DelayNs; /// Machine mode cycle counter (`mcycle`) as a delay provider #[derive(Copy, Clone)] @@ -19,12 +19,17 @@ impl McycleDelay { } } -impl DelayUs for McycleDelay { +impl DelayNs for McycleDelay { #[inline] fn delay_us(&mut self, us: u32) { + self.delay_ns(us * 1000) + } + + #[inline] + fn delay_ns(&mut self, ns: u32) { let t0 = mcycle::read64(); - let us_64: u64 = us.into(); - let clock = (us_64 * (self.ticks_second as u64)) / 1_000_000u64; + let us_64: u64 = ns.into(); + let clock = (us_64 * (self.ticks_second as u64)) / 1_000_000_000u64; while mcycle::read64().wrapping_sub(t0) <= clock {} - } + } } From 9d9cb77579e4e22709642dcb86fe1b2d98f440a0 Mon Sep 17 00:00:00 2001 From: Aaron Gowatch Date: Wed, 29 Nov 2023 21:53:04 -0700 Subject: [PATCH 03/11] Remove crate pinning --- riscv/Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/Cargo.toml b/riscv/Cargo.toml index bdae8024..821ba0e5 100644 --- a/riscv/Cargo.toml +++ b/riscv/Cargo.toml @@ -24,4 +24,4 @@ critical-section-single-hart = ["critical-section/restore-state-bool"] [dependencies] critical-section = "1.1.2" -embedded-hal = "=1.0.0-rc.1" +embedded-hal = "1.0.0-rc.1" From b74b90bd5840ed1cba2a47f819c588d7d9dce36a Mon Sep 17 00:00:00 2001 From: Aaron Gowatch Date: Wed, 29 Nov 2023 21:57:32 -0700 Subject: [PATCH 04/11] Update variable name --- riscv/src/delay.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv/src/delay.rs b/riscv/src/delay.rs index bcdfa7ac..6641e6dd 100644 --- a/riscv/src/delay.rs +++ b/riscv/src/delay.rs @@ -28,8 +28,8 @@ impl DelayNs for McycleDelay { #[inline] fn delay_ns(&mut self, ns: u32) { let t0 = mcycle::read64(); - let us_64: u64 = ns.into(); - let clock = (us_64 * (self.ticks_second as u64)) / 1_000_000_000u64; + let ns_64: u64 = ns.into(); + let clock = (ns_64 * (self.ticks_second as u64)) / 1_000_000_000u64; while mcycle::read64().wrapping_sub(t0) <= clock {} } } From 4a2bf51b62a1df1c37a5299180d8200814741549 Mon Sep 17 00:00:00 2001 From: Aaron Gowatch Date: Thu, 30 Nov 2023 08:00:25 -0700 Subject: [PATCH 05/11] Update embedded-hal --- riscv/Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/Cargo.toml b/riscv/Cargo.toml index 821ba0e5..5eab8ac9 100644 --- a/riscv/Cargo.toml +++ b/riscv/Cargo.toml @@ -24,4 +24,4 @@ critical-section-single-hart = ["critical-section/restore-state-bool"] [dependencies] critical-section = "1.1.2" -embedded-hal = "1.0.0-rc.1" +embedded-hal = "1.0.0-rc.2" From 67dfbdc82619c805dd43974a98935a36f218d800 Mon Sep 17 00:00:00 2001 From: Aaron Gowatch Date: Thu, 30 Nov 2023 08:01:17 -0700 Subject: [PATCH 06/11] Use default implementation of delay_us --- riscv/src/delay.rs | 5 ----- 1 file changed, 5 deletions(-) diff --git a/riscv/src/delay.rs b/riscv/src/delay.rs index 6641e6dd..bff17d55 100644 --- a/riscv/src/delay.rs +++ b/riscv/src/delay.rs @@ -21,11 +21,6 @@ impl McycleDelay { impl DelayNs for McycleDelay { #[inline] - fn delay_us(&mut self, us: u32) { - self.delay_ns(us * 1000) - } - - #[inline] fn delay_ns(&mut self, ns: u32) { let t0 = mcycle::read64(); let ns_64: u64 = ns.into(); From a4184cfca81464b5785892c1f4fe2bcab465d009 Mon Sep 17 00:00:00 2001 From: Aaron Gowatch Date: Thu, 30 Nov 2023 08:03:29 -0700 Subject: [PATCH 07/11] Fix formatting --- riscv/src/delay.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv/src/delay.rs b/riscv/src/delay.rs index bff17d55..ee501f08 100644 --- a/riscv/src/delay.rs +++ b/riscv/src/delay.rs @@ -21,10 +21,10 @@ impl McycleDelay { impl DelayNs for McycleDelay { #[inline] - fn delay_ns(&mut self, ns: u32) { + fn delay_ns(&mut self, ns: u32) { let t0 = mcycle::read64(); let ns_64: u64 = ns.into(); let clock = (ns_64 * (self.ticks_second as u64)) / 1_000_000_000u64; while mcycle::read64().wrapping_sub(t0) <= clock {} - } + } } From 0a30be94115b4ddb987cf39d214f0f05a6e3ba1b Mon Sep 17 00:00:00 2001 From: Aaron Gowatch Date: Thu, 30 Nov 2023 08:13:00 -0700 Subject: [PATCH 08/11] Update CHANGELOG.md to reflect embedded-hal v1.0.0-rc.2 --- riscv/CHANGELOG.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md index e9ae972d..ab12ce7b 100644 --- a/riscv/CHANGELOG.md +++ b/riscv/CHANGELOG.md @@ -21,7 +21,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Changed - Cargo workspace for riscv and riscv-rt -- Update `embedded-hal` dependency to v1.0 (bumps MSRV to 1.60) +- Update `embedded-hal` dependency to v1.0.0-rc.2 (bumps MSRV to 1.60) - `misa::MXL` renamed to `misa::XLEN` - Removed `bit_field` dependency - CI actions updated. They now use `checkout@v3` and `dtolnay/rust-toolchain`. From ce6e680419a8514380ea2dd7894514aa4686dcce Mon Sep 17 00:00:00 2001 From: Aaron Gowatch Date: Thu, 30 Nov 2023 08:51:56 -0700 Subject: [PATCH 09/11] Upgrade rust-version to 1.60 --- riscv-rt/CHANGELOG.md | 1 + riscv-rt/Cargo.toml | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md index bcd96239..e9bd775f 100644 --- a/riscv-rt/CHANGELOG.md +++ b/riscv-rt/CHANGELOG.md @@ -16,6 +16,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Changed +- Upgrade rust-version to 1.60 - Cargo workspace for riscv and riscv-rt - Use inline assembly instead of pre-compiled blobs - Removed bors in favor of GitHub Merge Queue diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml index a368c68f..01c7a9af 100644 --- a/riscv-rt/Cargo.toml +++ b/riscv-rt/Cargo.toml @@ -1,7 +1,7 @@ [package] name = "riscv-rt" version = "0.11.0" -rust-version = "1.59" +rust-version = "1.60" repository = "https://github.com/rust-embedded/riscv" authors = ["The RISC-V Team "] categories = ["embedded", "no-std"] From 1e2f9862ef900eca80dd6d6f99295c12e165945d Mon Sep 17 00:00:00 2001 From: Aaron Gowatch Date: Thu, 30 Nov 2023 08:55:41 -0700 Subject: [PATCH 10/11] Additional updates to Rust 1.60.0 --- .github/workflows/riscv-rt.yaml | 6 +++--- .github/workflows/riscv.yaml | 6 +++--- riscv-rt/README.md | 2 +- riscv-rt/src/lib.rs | 6 +++--- riscv/Cargo.toml | 2 +- riscv/src/lib.rs | 2 +- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/.github/workflows/riscv-rt.yaml b/.github/workflows/riscv-rt.yaml index b1aeff5a..9662a4c9 100644 --- a/.github/workflows/riscv-rt.yaml +++ b/.github/workflows/riscv-rt.yaml @@ -10,8 +10,8 @@ jobs: build: strategy: matrix: - # All generated code should be running on stable now, MRSV is 1.59.0 - toolchain: [ stable, nightly, 1.59.0 ] + # All generated code should be running on stable now, MRSV is 1.60.0 + toolchain: [ stable, nightly, 1.60.0 ] target: - riscv32i-unknown-none-elf - riscv32imc-unknown-none-elf @@ -41,7 +41,7 @@ jobs: run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=single-hart - name: Build example (all features) run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --all-features - + # Job to check that all the builds succeeded build-check: needs: diff --git a/.github/workflows/riscv.yaml b/.github/workflows/riscv.yaml index ec3984dc..e2156dfe 100644 --- a/.github/workflows/riscv.yaml +++ b/.github/workflows/riscv.yaml @@ -11,7 +11,7 @@ jobs: build-riscv: strategy: matrix: - # All generated code should be running on stable now, MRSV is 1.59.0 + # All generated code should be running on stable now, MRSV is 1.60.0 toolchain: [ stable, nightly, 1.60.0 ] target: - riscv32i-unknown-none-elf @@ -35,7 +35,7 @@ jobs: run: cargo build --package riscv --target ${{ matrix.target }} - name: Build (all features) run: cargo build --package riscv --target ${{ matrix.target }} --all-features - + # On MacOS, Ubuntu, and Windows, we at least make sure that the crate builds and links. build-others: strategy: @@ -49,7 +49,7 @@ jobs: run: cargo build --package riscv - name: Build (all features) run: cargo build --package riscv --all-features - + # Job to check that all the builds succeeded build-check: needs: diff --git a/riscv-rt/README.md b/riscv-rt/README.md index 0f7ed012..74cdfeea 100644 --- a/riscv-rt/README.md +++ b/riscv-rt/README.md @@ -11,7 +11,7 @@ This project is developed and maintained by the [RISC-V team][team]. ## Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.59 and up. It *might* +This crate is guaranteed to compile on stable Rust 1.60 and up. It *might* compile with older versions but that may change in any new patch release. ## License diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs index 54e5c01c..fcc77f9f 100644 --- a/riscv-rt/src/lib.rs +++ b/riscv-rt/src/lib.rs @@ -2,7 +2,7 @@ //! //! # Minimum Supported Rust Version (MSRV) //! -//! This crate is guaranteed to compile on stable Rust 1.59 and up. It *might* +//! This crate is guaranteed to compile on stable Rust 1.60 and up. It *might* //! compile with older versions but that may change in any new patch release. //! //! # Features @@ -483,14 +483,14 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! { sd {a},0({start}) addi {start},{start},8 bltu {start},{end},1b - + 2: // .data zero registers li {a},0 li {input},0 la {start},_sbss la {end},_ebss - + bgeu {start},{end},4f 3: // .bss main loop diff --git a/riscv/Cargo.toml b/riscv/Cargo.toml index 5eab8ac9..8e126fe7 100644 --- a/riscv/Cargo.toml +++ b/riscv/Cargo.toml @@ -2,7 +2,7 @@ name = "riscv" version = "0.10.1" edition = "2021" -rust-version = "1.59" +rust-version = "1.60" repository = "https://github.com/rust-embedded/riscv" authors = ["The RISC-V Team "] categories = ["embedded", "hardware-support", "no-std"] diff --git a/riscv/src/lib.rs b/riscv/src/lib.rs index e5d1f281..8128fd81 100644 --- a/riscv/src/lib.rs +++ b/riscv/src/lib.rs @@ -2,7 +2,7 @@ //! //! # Minimum Supported Rust Version (MSRV) //! -//! This crate is guaranteed to compile on stable Rust 1.59 and up. It *might* +//! This crate is guaranteed to compile on stable Rust 1.60 and up. It *might* //! compile with older versions but that may change in any new patch release. //! //! # Features From 43ace8750f56229388e3e5bbaed1c5f037416254 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= Date: Sat, 2 Dec 2023 10:59:37 +0100 Subject: [PATCH 11/11] Remove riscv-target --- riscv-rt/CHANGELOG.md | 1 + riscv-rt/Cargo.toml | 3 --- riscv-rt/build.rs | 43 ++++++++++++++++++++++++++++++++++++------- 3 files changed, 37 insertions(+), 10 deletions(-) diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md index bcd96239..f9c6e965 100644 --- a/riscv-rt/CHANGELOG.md +++ b/riscv-rt/CHANGELOG.md @@ -16,6 +16,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Changed +- Removed riscv-target dependency for build - Cargo workspace for riscv and riscv-rt - Use inline assembly instead of pre-compiled blobs - Removed bors in favor of GitHub Merge Queue diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml index a368c68f..5aff1fa3 100644 --- a/riscv-rt/Cargo.toml +++ b/riscv-rt/Cargo.toml @@ -21,6 +21,3 @@ riscv-rt-macros = { path = "macros", version = "0.2.0" } [dev-dependencies] panic-halt = "0.2.0" - -[build-dependencies] -riscv-target = "0.1.2" diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs index e7c92126..3fbbd397 100644 --- a/riscv-rt/build.rs +++ b/riscv-rt/build.rs @@ -1,7 +1,6 @@ // NOTE: Adapted from cortex-m/build.rs -use riscv_target::Target; -use std::{env, fs, io, path::PathBuf}; +use std::{collections::HashSet, env, fs, io, path::PathBuf}; fn add_linker_script(arch_width: u32) -> io::Result<()> { // Read the file to a string and replace all occurrences of ${ARCH_WIDTH} with the arch width @@ -18,6 +17,35 @@ fn add_linker_script(arch_width: u32) -> io::Result<()> { Ok(()) } +/// Parse the target RISC-V architecture and returns its bit width and the extension set +fn parse_target(target: &str) -> (u32, HashSet) { + // isolate bit width and extensions from the rest of the target information + let arch = target + .trim_start_matches("riscv") + .split('-') + .next() + .unwrap(); + + let bits = arch + .chars() + .take_while(|c| c.is_ascii_digit()) + .collect::() + .parse::() + .unwrap(); + + let mut extensions: HashSet = arch.chars().skip_while(|c| c.is_ascii_digit()).collect(); + // get rid of the 'g' shorthand extension + if extensions.remove(&'g') { + extensions.insert('i'); + extensions.insert('m'); + extensions.insert('a'); + extensions.insert('f'); + extensions.insert('d'); + } + + (bits, extensions) +} + fn main() { let target = env::var("TARGET").unwrap(); let _name = env::var("CARGO_PKG_NAME").unwrap(); @@ -25,10 +53,11 @@ fn main() { // set configuration flags depending on the target if target.starts_with("riscv") { println!("cargo:rustc-cfg=riscv"); - let target = Target::from_target_str(&target); - // generate the linker script - let arch_width = match target.bits { + let (bits, extensions) = parse_target(&target); + + // generate the linker script and expose the ISA width + let arch_width = match bits { 32 => { println!("cargo:rustc-cfg=riscv32"); 4 @@ -42,8 +71,8 @@ fn main() { add_linker_script(arch_width).unwrap(); // expose the ISA extensions - if target.has_extension('m') { - println!("cargo:rustc-cfg=riscvm"); + for ext in &extensions { + println!("cargo:rustc-cfg=riscv{}", ext); } } }