From a76b09971822e950dad12211731186482ed5fbe9 Mon Sep 17 00:00:00 2001 From: Andrey Zgarbul Date: Sun, 22 Oct 2023 13:24:22 +0300 Subject: [PATCH 1/2] fix docs --- src/generate/generic.rs | 93 ++++++++++++++-------------------------- src/generate/register.rs | 2 +- src/lib.rs | 2 +- src/util.rs | 2 +- 4 files changed, 35 insertions(+), 64 deletions(-) diff --git a/src/generate/generic.rs b/src/generate/generic.rs index 74ae3418..afc7e2fa 100644 --- a/src/generate/generic.rs +++ b/src/generate/generic.rs @@ -457,18 +457,50 @@ impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI> where REG: Writable + RegisterSpec, FI: FieldSpec, + REG::Ux: From, { /// Field width pub const WIDTH: u8 = WI; + + /// Writes raw bits to the field + /// + /// # Safety + /// + /// Passing incorrect value can cause undefined behaviour. See reference manual + #[inline(always)] + pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << OF); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; + self.w + } + /// Writes `variant` to the field + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + unsafe { self.bits(FI::Ux::from(variant)) } + } } impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriterSafe<'a, REG, WI, OF, FI> where REG: Writable + RegisterSpec, FI: FieldSpec, + REG::Ux: From, { /// Field width pub const WIDTH: u8 = WI; + + /// Writes raw bits to the field + #[inline(always)] + pub fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << OF); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; + self.w + } + /// Writes `variant` to the field + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bits(FI::Ux::from(variant)) + } } macro_rules! bit_proxy { @@ -486,17 +518,7 @@ macro_rules! bit_proxy { { /// Field width pub const WIDTH: u8 = 1; - } - }; -} -macro_rules! impl_bit_proxy { - ($writer:ident) => { - impl<'a, REG, const OF: u8, FI> $writer<'a, REG, OF, FI> - where - REG: Writable + RegisterSpec, - bool: From, - { /// Writes bit to the field #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { @@ -521,57 +543,6 @@ bit_proxy!(BitWriter0S, Bit0S); bit_proxy!(BitWriter1T, Bit1T); bit_proxy!(BitWriter0T, Bit0T); -impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, -{ - /// Writes raw bits to the field - /// - /// # Safety - /// - /// Passing incorrect value can cause undefined behaviour. See reference manual - #[inline(always)] - pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { - self.w.bits &= !(REG::Ux::mask::() << OF); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; - self.w - } - /// Writes `variant` to the field - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut W { - unsafe { self.bits(FI::Ux::from(variant)) } - } -} -impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriterSafe<'a, REG, WI, OF, FI> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, -{ - /// Writes raw bits to the field - #[inline(always)] - pub fn bits(self, value: FI::Ux) -> &'a mut W { - self.w.bits &= !(REG::Ux::mask::() << OF); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; - self.w - } - /// Writes `variant` to the field - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut W { - self.bits(FI::Ux::from(variant)) - } -} - -impl_bit_proxy!(BitWriter); -impl_bit_proxy!(BitWriter1S); -impl_bit_proxy!(BitWriter0C); -impl_bit_proxy!(BitWriter1C); -impl_bit_proxy!(BitWriter0S); -impl_bit_proxy!(BitWriter1T); -impl_bit_proxy!(BitWriter0T); - impl<'a, REG, const OF: u8, FI> BitWriter<'a, REG, OF, FI> where REG: Writable + RegisterSpec, diff --git a/src/generate/register.rs b/src/generate/register.rs index 9c9a54a6..8e8aede0 100644 --- a/src/generate/register.rs +++ b/src/generate/register.rs @@ -95,7 +95,7 @@ pub fn render( ); if name_snake_case != "cfg" { alias_doc += format!( - "\n\nFor information about available fields see [`{name_snake_case}`] module" + "\n\nFor information about available fields see [`mod@{name_snake_case}`] module" ) .as_str(); } diff --git a/src/lib.rs b/src/lib.rs index 2fae4718..62cf1948 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -588,7 +588,7 @@ pub fn generate(input: &str, config: &Config) -> Result { }) } -/// Load a [Device] from a string slice with given [config](crate::util::Config). +/// Load a [Device](svd::Device) from a string slice with given [config](crate::util::Config). pub fn load_from(input: &str, config: &crate::util::Config) -> Result { use self::util::SourceType; use svd_parser::ValidateLevel; diff --git a/src/util.rs b/src/util.rs index 4bf6ed07..23cefdc1 100644 --- a/src/util.rs +++ b/src/util.rs @@ -183,7 +183,7 @@ pub enum SourceType { } impl SourceType { - /// Make a new [`Source`] from a given extension. + /// Make a new [`SourceType`] from a given extension. pub fn from_extension(s: &str) -> Option { match s { "svd" | "xml" => Some(Self::Xml), From 5e9a29c353edb291ece6ee271a6c8bfa75598b29 Mon Sep 17 00:00:00 2001 From: Andrey Zgarbul Date: Sun, 22 Oct 2023 13:27:19 +0300 Subject: [PATCH 2/2] release-0.30.2 --- CHANGELOG.md | 6 +++++- Cargo.lock | 2 +- Cargo.toml | 2 +- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 2e13e561..03c8720f 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/). ## [Unreleased] +## [v0.30.2] - 2023-10-22 + +- Fix documentation warnings - Use `ArrayProxy` for memory disjoined register arrays - Use `const fn` where allowed @@ -813,7 +816,8 @@ peripheral.register.write(|w| w.field().set()); - Initial version of the `svd2rust` tool -[Unreleased]: https://github.com/rust-embedded/svd2rust/compare/v0.30.1...HEAD +[Unreleased]: https://github.com/rust-embedded/svd2rust/compare/v0.30.2...HEAD +[v0.30.2]: https://github.com/rust-embedded/svd2rust/compare/v0.30.1...v0.30.2 [v0.30.1]: https://github.com/rust-embedded/svd2rust/compare/v0.30.0...v0.30.1 [v0.30.0]: https://github.com/rust-embedded/svd2rust/compare/v0.29.0...v0.30.0 [v0.29.0]: https://github.com/rust-embedded/svd2rust/compare/v0.28.0...v0.29.0 diff --git a/Cargo.lock b/Cargo.lock index 0a596acd..404c15ca 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -526,7 +526,7 @@ dependencies = [ [[package]] name = "svd2rust" -version = "0.30.1" +version = "0.30.2" dependencies = [ "anyhow", "clap", diff --git a/Cargo.toml b/Cargo.toml index cebb98e9..339672b2 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -23,7 +23,7 @@ keywords = [ license = "MIT OR Apache-2.0" name = "svd2rust" repository = "https://github.com/rust-embedded/svd2rust/" -version = "0.30.1" +version = "0.30.2" readme = "README.md" rust-version = "1.70"