From 4790ff40ec78c2f1855fe18b4fa799c0f97dd946 Mon Sep 17 00:00:00 2001
From: Andrey Zgarbul <zgarbul.andrey@gmail.com>
Date: Tue, 23 Jan 2024 23:41:41 +0300
Subject: [PATCH] write_raw

---
 CHANGELOG.md                      |  1 +
 src/generate/generic.rs           |  2 +-
 src/generate/generic_reg_vcell.rs | 10 ++++++++++
 3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 6fdad6f3..237c4bc6 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/).
 
 ## [Unreleased]
 
+- Add unsafe `write_bits` to all writtable registers
 - Revert #711
 - Add `defmt` impls for `TryFromInterruptError`, riscv interrupt enums
 - Fix calculating `modifiedWriteValues` bitmasks with field arrays
diff --git a/src/generate/generic.rs b/src/generate/generic.rs
index 706b7e12..8b978732 100644
--- a/src/generate/generic.rs
+++ b/src/generate/generic.rs
@@ -478,7 +478,7 @@ macro_rules! bit_proxy {
             pub const fn width(&self) -> u8 {
                 Self::WIDTH
             }
-        
+
             /// Field offset
             #[inline(always)]
             pub const fn offset(&self) -> u8 {
diff --git a/src/generate/generic_reg_vcell.rs b/src/generate/generic_reg_vcell.rs
index b0ca0d5e..ad3ec646 100644
--- a/src/generate/generic_reg_vcell.rs
+++ b/src/generate/generic_reg_vcell.rs
@@ -179,6 +179,16 @@ impl<REG: Writable> Reg<REG> {
 
         result
     }
+
+    /// Writes raw value to register.
+    ///
+    /// # Safety
+    ///
+    /// Unsafe as it passes value without checks.
+    #[inline(always)]
+    pub unsafe fn write_bits(&self, bits: REG::Ux) {
+        self.register.set(bits);
+    }
 }
 
 impl<REG: Readable + Writable> Reg<REG> {