diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi
index b1594dec49f28..3d66be43dca06 100644
--- a/arch/riscv/boot/dts/canaan/k230.dtsi
+++ b/arch/riscv/boot/dts/canaan/k230.dtsi
@@ -401,6 +401,92 @@
 			clock-names = "vglite";
 			status = "okay";
 		};
+
+		display: display-subsystem {
+			compatible = "canaan,display-subsystem";
+			ports = <&vo_out>;
+			status = "okay";
+			power-domains = <&sysctl_power K230_PM_DOMAIN_DISP>;
+		};
+
+		vo: vo@90840000 {
+			compatible = "canaan,k230-vo";
+			reg = <0x0 0x90840000 0x0 0x10000>;
+			interrupts = <133 IRQ_TYPE_LEVEL_HIGH>;
+			status = "okay";
+
+			background = <0xffffff>;
+			vth_line = <11>;
+
+			vo_out: port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		dsi: dsi@90850000 {
+			compatible = "canaan,k230-mipi-dsi";
+			reg = <0x0 0x90850000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+
+			panel@0 {
+				compatible = "canaan,universal";
+				reg = <0>;
+				panel-width-mm = <1080>;
+				panel-height-mm = <1920>;
+				panel-dsi-lane = <4>;
+				dsi_reset-gpios = <&gpio0_ports 9 GPIO_ACTIVE_HIGH>;
+				backlight_gpio-gpios = <&gpio0_ports 31 GPIO_ACTIVE_HIGH>;
+
+				panel-init-sequence = [
+					39 00 04 B9 FF 83 99
+					39 00 02 D2 AA
+					39 00 10 B1 02 04 71 91 01 32 33 11 11 ab 4d 56 73 02 02
+					39 00 10 B2 00 80 80 ae 05 07 5a 11 00 00 10 1e 70 03 d4
+					39 00 2d B4 00 FF 02 C0 02 c0 00 00 08 00 04 06 00 32 04 0a
+					08 21 03 01
+					00 0f b8 8b 02 c0 02 c0 00 00 08 00 04 06 00 32 04 0a 08 01
+					00 0f b8 01
+					39 00 22 D3 00 00 00 00 00 00 06 00 00 10 04 00 04 00 00 00
+					00 00 00 00 00 00 00 01 00 05 05 07 00 00 00 05 40
+					39 00 21 D5 18 18 19 19 18 18 21 20 01 00 07 06 05 04 03 02
+					18 18 18 18 18 18 2f 2f 30 30 31 31 18 18 18 18
+					39 00 21 D6 18 18 19 19 40 40 20 21 02 03 04 05 06 07 00 01
+					40 40 40 40 40 40 2f 2f 30 30 31 31 40 40 40 40
+					39 00 11 D8 a2 aa 02 a0 a2 a8 02 a0 b0 00 00 00 b0 00 00 00
+					39 00 02 BD 01
+					39 00 11 D8 B0 00 00 00 B0 00 00 00 E2 AA 03 F0 E2 AA 03 F0
+					39 00 02 BD 02
+					39 00 09 D8 E2 AA 03 F0 E2 AA 03 F0
+					39 00 02 BD 00
+					39 00 03 B6 8D 8D
+					39 00 02 CC 04
+					39 00 03 C6 FF F9
+					39 00 37 E0 00 12 1f 1a 40 4a 59 55 5e 67 6f 75 7a 82 8b 90
+					95 9f a3 ad a2 b2 B6 5e 5a 65 77 00 12 1f 1a 40 4a 59 55 5e
+					67 6f 75 7a 82 8b 90 95
+					9f a3 ad a2 b2 B6 5e 5a 65 77
+					39 ff 01 11
+					39 ff 01 29
+				];
+
+				display-timings {
+					timing-0 {
+						clock-frequency = <74250000>;
+						hactive = <1080>;
+						vactive = <1920>;
+						hfront-porch = <40>;
+						hback-porch = <20>;
+						hsync-len = <20>;
+						vfront-porch = <206>;
+						vback-porch = <8>;
+						vsync-len = <5>;
+					};
+				};
+			};
+		};
 	};
 };
 #include "k230_clock_provider.dtsi"
diff --git a/arch/riscv/boot/dts/canaan/k230d-canmv.dts b/arch/riscv/boot/dts/canaan/k230d-canmv.dts
index e0c4cde421b9b..1bcac71923b9e 100644
--- a/arch/riscv/boot/dts/canaan/k230d-canmv.dts
+++ b/arch/riscv/boot/dts/canaan/k230d-canmv.dts
@@ -47,3 +47,78 @@
 		interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
 	};
 };
+
+&vo {
+	vth_line = <10>;
+};
+
+&dsi {
+	panel@0 {
+		panel-width-mm = <480>;
+		panel-height-mm = <800>;
+		panel-dsi-lane = <2>;
+		dsi_reset-gpios = <&gpio0_ports 24 GPIO_ACTIVE_HIGH>;
+		backlight_gpio-gpios = <&gpio0_ports 25 GPIO_ACTIVE_HIGH>;
+
+		panel-init-sequence = [
+			39 00 06 ff 77 01 00 00 13
+			39 00 02 ef 08
+			39 00 06 ff 77 01 00 00 10
+			39 00 03 c0 63 00
+			39 00 03 c1 10 02
+			39 00 03 c2 31 02
+			39 00 02 cc 10
+			39 00 11 b0 c0 0c 92 0c 10 05 02 0d 07 21 04 53 11 6a 32 1f
+			39 00 11 b1 c0 87 cf 0c 10 06 00 03 08 1d 06 54 12 e6 ec 0f
+			39 00 06 ff 77 01 00 00 11
+			39 00 02 b0 5d
+			39 00 02 b1 62
+			39 00 02 b2 82
+			39 00 02 b3 80
+			39 00 02 b5 42
+			39 00 02 b7 85
+			39 00 02 b8 20
+			39 00 02 c0 09
+			39 00 02 c1 78
+			39 00 02 c2 78
+			39 00 02 d0 88
+			39 ff 02 ee 42
+			39 00 04 e0 00 00 02
+			39 00 0c e1 04 a0 06 a0 05 a0 07 a0 00 44 44
+			39 00 0d e2 00 00 33 33 01 a0 00 00 01 a0 00 00
+			39 00 05 e3 00 00 33 33
+			39 00 03 e4 44 44
+			39 00 11 e5 0c 30 a0 a0 0e 32 a0 a0 08 2c a0 a0 0a 2e a0 a0
+			39 00 05 e6 00 00 33 33
+			39 00 03 e7 44 44
+			39 00 11 e8 0d 31 a0 a0 0f 33 a0 a0 09 2d a0 a0 0b 2f a0 a0
+			39 00 08 eb 00 01 e4 e4 44 88 00
+			39 00 11 ed ff f5 47 6f 0b a1 a2 bf fb 2a 1a b0 f6 74 5f ff
+			39 00 07 ef 08 08 08 40 3f 64
+			39 00 06 ff 77 01 00 00 13
+			39 00 03 e8 00 0e
+			39 00 06 ff 77 01 00 00 00
+			39 ff 01 11
+			39 00 06 ff 77 01 00 00 13
+			39 ff 03 e8 00 0c
+			39 00 03 e8 00 00
+			39 00 06 ff 77 01 00 00 00
+			39 00 02 3a 50
+			39 ff 01 29
+		];
+
+		display-timings {
+			timing-0 {
+				clock-frequency = <39600000>;
+				hactive = <480>;
+				vactive = <800>;
+				hfront-porch = <80>;
+				hback-porch = <20>;
+				hsync-len = <20>;
+				vfront-porch = <220>;
+				vback-porch = <70>;
+				vsync-len = <10>;
+			};
+		};
+	};
+};
diff --git a/arch/riscv/configs/k230_defconfig b/arch/riscv/configs/k230_defconfig
index 3e7d0cacbbf81..a6c85b75daabf 100644
--- a/arch/riscv/configs/k230_defconfig
+++ b/arch/riscv/configs/k230_defconfig
@@ -278,3 +278,4 @@ CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_EDT_FT5X06=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_GPU_VGLITE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index de1853c07f994..9599d3cfe953f 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -390,6 +390,8 @@ source "drivers/gpu/drm/sprd/Kconfig"
 
 source "drivers/gpu/drm/verisilicon/Kconfig"
 
+source "drivers/gpu/drm/canaan/Kconfig"
+
 config DRM_HYPERV
 	tristate "DRM Support for Hyper-V synthetic video device"
 	depends on DRM && PCI && MMU && HYPERV
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index a0902298f98ff..92906a06447d4 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -199,3 +199,4 @@ obj-y			+= solomon/
 obj-$(CONFIG_DRM_SPRD) += sprd/
 obj-$(CONFIG_DRM_LOONGSON) += loongson/
 obj-$(CONFIG_DRM_VERISILICON) += verisilicon/
+obj-y			+= canaan/
diff --git a/drivers/gpu/drm/canaan/Kconfig b/drivers/gpu/drm/canaan/Kconfig
new file mode 100644
index 0000000000000..60f4899ccabe2
--- /dev/null
+++ b/drivers/gpu/drm/canaan/Kconfig
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config DRM_CANAAN
+	bool "DRM Support for Canaan K230 Display Controller"
+	depends on OF
+	depends on COMMON_CLK
+	select DRM
+	select DRM_KMS_HELPER
+	select DRM_KMS_DMA_HELPER
+	select DRM_GEM_DMA_HELPER
+	select VIDEOMODE_HELPERS
+	default ARCH_CANAAN
+	help
+	  Choose this option if you have a Canaan K230 soc chipset.
+	  This driver provides kernel mode setting and buffer
+	  management to userspace. This driver does not provide
+	  2D or 3D acceleration; acceleration is performed by other
+	  IP found on the SoC.
+
+if DRM_CANAAN
+
+config DRM_CANAAN_DSI
+	bool "Canaan K230 MIPI-DSI Controller Support"
+	select DRM_MIPI_DSI
+	default DRM_CANAAN
+	help
+	  Choose this option if you have a Canaan K230 soc chipset.
+	  This driver provides MIPI-DSI controller for DRM.
+	  This driver does not provide 2D or 3D acceleration;
+	  acceleration is performed by other
+	  IP found on the SoC.
+
+endif
diff --git a/drivers/gpu/drm/canaan/Makefile b/drivers/gpu/drm/canaan/Makefile
new file mode 100644
index 0000000000000..e547cca4c4da1
--- /dev/null
+++ b/drivers/gpu/drm/canaan/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+canaan-drm-y := \
+		canaan_drv.o \
+		canaan_vo.o \
+		canaan_crtc.o \
+		canaan_plane.o \
+		canaan_phy.o
+
+obj-$(CONFIG_DRM_CANAAN) += canaan-drm.o
+obj-$(CONFIG_DRM_CANAAN_DSI) += canaan_dsi.o
diff --git a/drivers/gpu/drm/canaan/canaan_crtc.c b/drivers/gpu/drm/canaan/canaan_crtc.c
new file mode 100644
index 0000000000000..4beb0443edcf6
--- /dev/null
+++ b/drivers/gpu/drm/canaan/canaan_crtc.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022, Canaan Bright Sight Co., Ltd
+ *
+ * All enquiries to https://www.canaan-creative.com/
+ *
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/component.h>
+#include <linux/of_graph.h>
+#include <linux/of_platform.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_vblank.h>
+#include <drm/drm_ioctl.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_print.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_plane.h>
+#include <drm/drm_plane_helper.h>
+#include <drm/drm_probe_helper.h>
+
+#include "canaan_vo.h"
+#include "canaan_crtc.h"
+#include "canaan_plane.h"
+
+static int canaan_crtc_enable_vblank(struct drm_crtc *crtc)
+{
+	struct canaan_crtc *canaan_crtc = to_canaan_crtc(crtc);
+	struct canaan_vo *vo = canaan_crtc->vo;
+
+	DRM_DEBUG_DRIVER("Enable vblank on CRTC:%d\n", crtc->base.id);
+	return canaan_vo_enable_vblank(vo);
+}
+
+static void canaan_crtc_disable_vblank(struct drm_crtc *crtc)
+{
+	struct canaan_crtc *canaan_crtc = to_canaan_crtc(crtc);
+	struct canaan_vo *vo = canaan_crtc->vo;
+
+	DRM_DEBUG_DRIVER("Disable vblank on CRTC:%d\n", crtc->base.id);
+	canaan_vo_disable_vblank(vo);
+}
+
+static void canaan_crtc_atomic_enable(struct drm_crtc *crtc,
+				      struct drm_atomic_state *old_crtc_state)
+{
+	struct canaan_crtc *canaan_crtc = to_canaan_crtc(crtc);
+	struct canaan_vo *vo = canaan_crtc->vo;
+	struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
+
+	DRM_DEBUG_DRIVER("Enable the CRTC:%d\n", crtc->base.id);
+
+	canaan_vo_enable_crtc(vo, canaan_crtc, adjusted_mode);
+	drm_crtc_vblank_on(crtc);
+}
+
+static void canaan_crtc_atomic_disable(struct drm_crtc *crtc,
+				       struct drm_atomic_state *old_crtc_state)
+{
+	struct canaan_crtc *canaan_crtc = to_canaan_crtc(crtc);
+	struct canaan_vo *vo = canaan_crtc->vo;
+
+	DRM_DEBUG_DRIVER("Disable the CRTC:%d\n", crtc->base.id);
+	drm_crtc_vblank_off(crtc);
+	canaan_vo_disable_crtc(vo, canaan_crtc);
+
+	if (crtc->state->event && !crtc->state->active) {
+		spin_lock_irq(&crtc->dev->event_lock);
+		drm_crtc_send_vblank_event(crtc, crtc->state->event);
+		spin_unlock_irq(&crtc->dev->event_lock);
+
+		crtc->state->event = NULL;
+	}
+}
+
+static void canaan_crtc_atomic_flush(struct drm_crtc *crtc,
+				     struct drm_atomic_state *old_crtc_state)
+{
+	struct canaan_crtc *canaan_crtc = to_canaan_crtc(crtc);
+	struct canaan_vo *vo = canaan_crtc->vo;
+	struct drm_pending_vblank_event *event = crtc->state->event;
+
+	DRM_DEBUG_DRIVER("Flush the configuration\n");
+	canaan_vo_flush_config(vo);
+
+	if (event) {
+		WARN_ON(drm_crtc_vblank_get(crtc) != 0);
+
+		spin_lock_irq(&crtc->dev->event_lock);
+		drm_crtc_arm_vblank_event(crtc, event);
+		spin_unlock_irq(&crtc->dev->event_lock);
+		crtc->state->event = NULL;
+	}
+}
+
+static const struct drm_crtc_funcs canaan_crtc_funcs = {
+	.reset = drm_atomic_helper_crtc_reset,
+	.destroy = drm_crtc_cleanup,
+	.set_config = drm_atomic_helper_set_config,
+	.page_flip = drm_atomic_helper_page_flip,
+	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
+	.enable_vblank = canaan_crtc_enable_vblank,
+	.disable_vblank = canaan_crtc_disable_vblank,
+};
+
+static const struct drm_crtc_helper_funcs canaan_crtc_helper_funcs = {
+	.atomic_enable = canaan_crtc_atomic_enable,
+	.atomic_disable = canaan_crtc_atomic_disable,
+	.atomic_flush = canaan_crtc_atomic_flush,
+};
+
+struct canaan_crtc *canaan_crtc_create(struct drm_device *drm_dev,
+				       struct drm_plane *primary,
+				       struct drm_plane *cursor,
+				       struct canaan_vo *vo)
+{
+	int ret = 0;
+	struct canaan_crtc *canaan_crtc = NULL;
+	struct drm_crtc *crtc = NULL;
+	struct device *dev = vo->dev;
+
+	canaan_crtc = devm_kzalloc(dev, sizeof(struct canaan_crtc), GFP_KERNEL);
+	if (!canaan_crtc)
+		return ERR_PTR(-ENOMEM);
+	canaan_crtc->vo = vo;
+	crtc = &canaan_crtc->base;
+
+	ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
+					&canaan_crtc_funcs, "canaan_crtc");
+	if (ret) {
+		return ERR_PTR(ret);
+		DRM_DEV_ERROR(dev, "Failed to init CRTC\n");
+	}
+
+	drm_crtc_helper_add(crtc, &canaan_crtc_helper_funcs);
+
+	drm_mode_crtc_set_gamma_size(crtc, 256);
+	drm_crtc_enable_color_mgmt(crtc, 0, false, 256);
+	DRM_DEBUG_DRIVER("Create the CRTC:%d\n", crtc->base.id);
+
+	return canaan_crtc;
+}
diff --git a/drivers/gpu/drm/canaan/canaan_crtc.h b/drivers/gpu/drm/canaan/canaan_crtc.h
new file mode 100644
index 0000000000000..8f6af93309ef7
--- /dev/null
+++ b/drivers/gpu/drm/canaan/canaan_crtc.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2022, Canaan Bright Sight Co., Ltd
+ *
+ * All enquiries to https://www.canaan-creative.com/
+ *
+ */
+
+#ifndef __CANAAN_CRTC_H__
+#define __CANAAN_CRTC_H__
+
+struct canaan_crtc {
+	struct drm_crtc base;
+	struct canaan_vo *vo;
+	struct drm_pending_vblank_event *event;
+};
+
+static inline struct canaan_crtc *to_canaan_crtc(struct drm_crtc *crtc)
+{
+	return container_of(crtc, struct canaan_crtc, base);
+}
+
+struct canaan_crtc *canaan_crtc_create(struct drm_device *drm_dev,
+				       struct drm_plane *primary,
+				       struct drm_plane *cursor,
+				       struct canaan_vo *vo);
+
+#endif /* __CANAAN_CRTC_H__ */
diff --git a/drivers/gpu/drm/canaan/canaan_drv.c b/drivers/gpu/drm/canaan/canaan_drv.c
new file mode 100644
index 0000000000000..019ac99163c53
--- /dev/null
+++ b/drivers/gpu/drm/canaan/canaan_drv.c
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022, Canaan Bright Sight Co., Ltd
+ *
+ * All enquiries to https://www.canaan-creative.com/
+ *
+ */
+
+#include <linux/fs.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/component.h>
+#include <linux/of_graph.h>
+#include <linux/of_platform.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_gem_dma_helper.h>
+#include <drm/drm_fbdev_generic.h>
+#include <drm/drm_vblank.h>
+#include <drm/drm_ioctl.h>
+#include <drm/drm_print.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_probe_helper.h>
+
+#include "canaan_drv.h"
+#include "canaan_vo.h"
+
+static int canaan_drm_open(struct inode *inode, struct file *filp);
+static int canaan_drm_release(struct inode *inode, struct file *filp);
+
+static const struct file_operations canaan_drm_fops = {
+	.owner = THIS_MODULE,
+	.open = canaan_drm_open,
+	.release = canaan_drm_release,
+	.unlocked_ioctl = drm_ioctl,
+	.compat_ioctl = drm_compat_ioctl,
+	.poll = drm_poll,
+	.read = drm_read,
+	.llseek = noop_llseek,
+	.mmap = drm_gem_mmap,
+	DRM_GEM_DMA_UNMAPPED_AREA_FOPS
+};
+
+static struct drm_driver canaan_drm_driver = {
+	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
+	DRM_GEM_DMA_DRIVER_OPS_VMAP,
+	.fops = &canaan_drm_fops,
+	.name = "canaan-drm",
+	.desc = "Canaan K230 DRM driver",
+	.date = "20230501",
+	.major = 1,
+	.minor = 0,
+};
+
+static const struct drm_mode_config_funcs canaan_drm_mode_config_funcs = {
+	.fb_create = drm_gem_fb_create,
+	.atomic_check = drm_atomic_helper_check,
+	.atomic_commit = drm_atomic_helper_commit,
+};
+
+static const struct drm_mode_config_helper_funcs
+	canaan_drm_mode_config_helpers = {
+		.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
+	};
+
+static struct device *disp_dev;
+
+static int canaan_drm_open(struct inode *inode, struct file *filp)
+{
+	int ret;
+
+	pm_runtime_get_sync(disp_dev);
+	ret = drm_open(inode, filp);
+
+	return ret;
+}
+
+static int canaan_drm_release(struct inode *inode, struct file *filp)
+{
+	int ret;
+
+	ret = drm_release(inode, filp);
+	// pm_runtime_put_sync(disp_dev);
+
+	return ret;
+}
+
+static int canaan_drm_bind(struct device *dev)
+{
+	int ret = 0;
+	struct drm_device *drm_dev;
+
+	drm_dev = drm_dev_alloc(&canaan_drm_driver, dev);
+	if (IS_ERR(drm_dev))
+		return PTR_ERR(drm_dev);
+	dev_set_drvdata(dev, drm_dev);
+
+	drm_mode_config_init(drm_dev);
+	drm_dev->mode_config.min_width = 16;
+	drm_dev->mode_config.min_height = 16;
+	drm_dev->mode_config.max_width = 4096;
+	drm_dev->mode_config.max_height = 4096;
+	drm_dev->mode_config.normalize_zpos = true;
+	drm_dev->mode_config.funcs = &canaan_drm_mode_config_funcs;
+	drm_dev->mode_config.helper_private = &canaan_drm_mode_config_helpers;
+
+	ret = component_bind_all(dev, drm_dev);
+	if (ret) {
+		DRM_DEV_ERROR(dev, "Failed to bind all components\n");
+		goto cleanup_mode_config;
+	}
+
+	ret = drm_vblank_init(drm_dev, drm_dev->mode_config.num_crtc);
+	if (ret) {
+		DRM_DEV_ERROR(dev, "Failed to init vblank\n");
+		goto unbind_all;
+	}
+
+	drm_mode_config_reset(drm_dev);
+	drm_kms_helper_poll_init(drm_dev);
+
+	ret = drm_dev_register(drm_dev, 0);
+	if (ret) {
+		DRM_DEV_ERROR(dev, "Failed to register drm device\n");
+		goto finish_poll;
+	}
+
+	drm_fbdev_generic_setup(drm_dev, 32);
+	DRM_DEV_INFO(dev, "Canaan K230 DRM driver register successfully\n");
+
+	return 0;
+
+finish_poll:
+	drm_kms_helper_poll_fini(drm_dev);
+unbind_all:
+	component_unbind_all(dev, drm_dev);
+cleanup_mode_config:
+	drm_mode_config_cleanup(drm_dev);
+
+	dev_set_drvdata(dev, NULL);
+	drm_dev_put(drm_dev);
+	return ret;
+}
+
+static void canaan_drm_unbind(struct device *dev)
+{
+	struct drm_device *drm_dev = dev_get_drvdata(dev);
+
+	drm_dev_unregister(drm_dev);
+	drm_kms_helper_poll_fini(drm_dev);
+	drm_atomic_helper_shutdown(drm_dev);
+	component_unbind_all(dev, drm_dev);
+	drm_mode_config_cleanup(drm_dev);
+	dev_set_drvdata(dev, NULL);
+	drm_dev_put(drm_dev);
+}
+
+static const struct component_master_ops canaan_drm_master_ops = {
+	.bind = canaan_drm_bind,
+	.unbind = canaan_drm_unbind,
+};
+
+static struct platform_driver *const component_drivers[] = {
+	&canaan_vo_driver,
+	&canaan_dsi_driver,
+};
+
+static int compare_dev(struct device *dev, void *data)
+{
+	return dev == (struct device *)data;
+}
+
+static struct component_match *canaan_drm_match_add(struct device *dev)
+{
+	int i = 0;
+	struct component_match *match = NULL;
+
+	for (i = 0; i < ARRAY_SIZE(component_drivers); i++) {
+		struct device_driver *driver = &component_drivers[i]->driver;
+		struct device *p = NULL, *d;
+
+		while ((d = platform_find_device_by_driver(p, driver))) {
+			put_device(p);
+			component_match_add(dev, &match, compare_dev, d);
+			p = d;
+		}
+		put_device(p);
+	}
+
+	return match ?: ERR_PTR(-ENODEV);
+}
+
+static int canaan_drm_platform_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct component_match *match = NULL;
+
+	disp_dev = dev;
+	pm_runtime_enable(disp_dev);
+	match = canaan_drm_match_add(dev);
+	if (IS_ERR(match))
+		return PTR_ERR(match);
+
+	return component_master_add_with_match(dev, &canaan_drm_master_ops,
+					       match);
+}
+
+static int canaan_drm_platform_remove(struct platform_device *pdev)
+{
+	component_master_del(&pdev->dev, &canaan_drm_master_ops);
+
+	return 0;
+}
+
+static const struct of_device_id canaan_drm_of_table[] = {
+	{
+		.compatible = "canaan,display-subsystem",
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, canaan_drm_of_table);
+
+static struct platform_driver canaan_drm_platform_driver = {
+	.probe = canaan_drm_platform_probe,
+	.remove = canaan_drm_platform_remove,
+	.driver = {
+		.name = "canaan-drm",
+		.of_match_table = canaan_drm_of_table,
+	},
+};
+
+static int __init canaan_drm_init(void)
+{
+	int ret = 0;
+
+	ret = platform_register_drivers(component_drivers,
+					ARRAY_SIZE(component_drivers));
+	if (ret)
+		return ret;
+
+	ret = platform_driver_register(&canaan_drm_platform_driver);
+	if (ret)
+		platform_unregister_drivers(component_drivers,
+					    ARRAY_SIZE(component_drivers));
+
+	return ret;
+}
+
+static void __exit canaan_drm_exit(void)
+{
+	platform_unregister_drivers(component_drivers,
+				    ARRAY_SIZE(component_drivers));
+	platform_driver_unregister(&canaan_drm_platform_driver);
+}
+
+module_init(canaan_drm_init);
+module_exit(canaan_drm_exit);
+
+MODULE_DESCRIPTION("Canaan K230 DRM driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/canaan/canaan_drv.h b/drivers/gpu/drm/canaan/canaan_drv.h
new file mode 100644
index 0000000000000..646a25453ec08
--- /dev/null
+++ b/drivers/gpu/drm/canaan/canaan_drv.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2022, Canaan Bright Sight Co., Ltd
+ *
+ * All enquiries to https://www.canaan-creative.com/
+ *
+ */
+
+#ifndef __CANAAN_DRV_H__
+#define __CANAAN_DRV_H__
+
+extern struct platform_driver canaan_vo_driver;
+extern struct platform_driver canaan_dsi_driver;
+
+#endif /* __CANAAN_DRV_H__ */
diff --git a/drivers/gpu/drm/canaan/canaan_dsi.c b/drivers/gpu/drm/canaan/canaan_dsi.c
new file mode 100644
index 0000000000000..582a8d6e305d1
--- /dev/null
+++ b/drivers/gpu/drm/canaan/canaan_dsi.c
@@ -0,0 +1,629 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022, Canaan Bright Sight Co., Ltd
+ *
+ * All enquiries to https://www.canaan-creative.com/
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/crc-ccitt.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy-mipi-dphy.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_print.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_simple_kms_helper.h>
+#include "canaan_dsi.h"
+#include <video/mipi_display.h>
+
+#define DSI_GEN_HDR 0x6c
+#define DSI_GEN_PLD_DATA 0x70
+#define DSI_CMD_PKT_STATUS 0x74
+#define GEN_RD_CMD_BUSY BIT(6)
+#define GEN_PLD_R_FULL BIT(5)
+#define GEN_PLD_R_EMPTY BIT(4)
+#define GEN_PLD_W_FULL BIT(3)
+#define GEN_PLD_W_EMPTY BIT(2)
+#define GEN_CMD_FULL BIT(1)
+#define GEN_CMD_EMPTY BIT(0)
+#define PHY_IF_CFG (0xa4)
+#define CLKMGR_CFG (0x08)
+#define GEN_VCID (0x30)
+#define VID_PKT_SIZE (0x3c)
+#define VID_NUM_CHUNKS (0x40)
+#define VID_NULL_SIZE (0x44)
+#define VID_HSA_TIME (0x48)
+#define VID_HBP_TIME (0x4c)
+#define VID_HLINE_TIME (0x50)
+#define VID_VSA_LINES (0x54)
+#define VID_VBP_LINES (0x58)
+#define VID_VFP_LINES (0x5c)
+#define VID_VACTIVE_LINES (0x60)
+#define DSI_TO_CNT_CFG 0x78
+#define HSTX_TO_CNT(p) (((p)&0xffff) << 16)
+#define LPRX_TO_CNT(p) ((p)&0xffff)
+#define DSI_BTA_TO_CNT 0x8c
+#define MODE_CFG (0x34)
+#define VID_MODE_CFG (0x38)
+#define CMD_MODE_CFG (0x68)
+#define DPI_COLOR_CODING (0x10)
+#define LPCLK_CTRL (0x94)
+#define PCKHDL_CFG (0x2c)
+
+#define CMD_PKT_STATUS_TIMEOUT_US 20000
+
+#define TXPHY_445_5_M (295)
+#define TXPHY_445_5_N (15)
+#define TXPHY_445_5_VOC (0x17)
+#define TXPHY_445_5_HS_FREQ (0x96)
+
+#define TXPHY_891_M (165)
+#define TXPHY_891_N (8)
+#define TXPHY_891_VOC (0x09)
+#define TXPHY_891_HS_FREQ (0x96)
+
+#define TXPHY_475_M (196)
+#define TXPHY_475_N (9)
+#define TXPHY_475_VOC (0x17)
+#define TXPHY_475_HS_FREQ (0xa3)
+
+static inline void dsi_write(struct canaan_dsi *dsi, u32 reg, u32 val)
+{
+	writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct canaan_dsi *dsi, u32 reg)
+{
+	return readl(dsi->base + reg);
+}
+
+static void canaan_dsi_inst_abort(struct canaan_dsi *dsi)
+{
+	// TODO
+}
+
+static int canaan_dsi_inst_wait_for_completion(struct canaan_dsi *dsi)
+{
+	// TODO
+	return 0;
+}
+
+static int dw_mipi_dsi_gen_pkt_hdr_write(struct canaan_dsi *dsi, u32 hdr_val)
+{
+	int ret;
+	u32 val;
+
+	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, val,
+				 !(val & GEN_CMD_FULL), 1000,
+				 CMD_PKT_STATUS_TIMEOUT_US);
+	if (ret) {
+		dev_err(dsi->dev, "failed to get available command FIFO\n");
+		return ret;
+	}
+
+	dsi_write(dsi, DSI_GEN_HDR, hdr_val);
+	return 0;
+}
+
+static int canaan_dsi_dcs_write_short(struct canaan_dsi *dsi,
+				      const struct mipi_dsi_msg *msg)
+{
+	uint32_t hdr_val = 0;
+	uint32_t vcid = msg->channel;
+	__le32 word = 0;
+	const u8 *tx_buf = msg->tx_buf;
+
+	hdr_val = (tx_buf[0] << 8) + (vcid << 6) + 0x5;
+	memcpy(&word, &hdr_val, sizeof(hdr_val));
+	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
+}
+
+static int canaan_dsi_dcs_write_long(struct canaan_dsi *dsi,
+				     const struct mipi_dsi_msg *msg)
+{
+	int ret = 0;
+	uint32_t val;
+	uint32_t hdr_val = 0;
+	uint32_t len = msg->tx_len;
+	uint32_t pld_data_bytes = sizeof(u32);
+	uint32_t vcid = msg->channel;
+	__le32 word;
+	const u8 *tx_buf = msg->tx_buf;
+
+	while (len) {
+		if (len < pld_data_bytes) {
+			word = 0;
+			memcpy(&word, tx_buf, len);
+			dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
+			len = 0;
+		} else {
+			memcpy(&word, tx_buf, pld_data_bytes);
+			dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
+			tx_buf += pld_data_bytes;
+			len -= pld_data_bytes;
+		}
+
+		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, val,
+					 !(val & GEN_PLD_W_FULL), 1000,
+					 CMD_PKT_STATUS_TIMEOUT_US);
+		if (ret) {
+			dev_err(dsi->dev,
+				"failed to get available write payload FIFO\n");
+			return ret;
+		}
+	}
+	word = 0;
+	// set cmd tpye
+	hdr_val = (msg->tx_len << 8) + (vcid << 6) + 0x39;
+	memcpy(&word, &hdr_val, sizeof(hdr_val));
+	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
+}
+
+static int canaan_dsi_dcs_read(struct canaan_dsi *dsi,
+			       const struct mipi_dsi_msg *msg)
+{
+	// TODO
+	return 1;
+}
+
+static void canaan_dsi_set_lan_num(struct canaan_dsi *dsi, int lan_num)
+{
+	switch (lan_num) {
+	case 1:
+		dsi_write(dsi, PHY_IF_CFG, 0x2800);
+		break;
+	case 2:
+		dsi_write(dsi, PHY_IF_CFG, 0x2801);
+		break;
+	case 4:
+		dsi_write(dsi, PHY_IF_CFG, 0x2803);
+		break;
+	default:
+		dev_err(dsi->dev, "dsi lane num only support 1 , 2, 4 lane\n");
+		break;
+	}
+}
+
+static u32 canaan_dsi_get_hcomponent_lbcc(struct canaan_dsi *dsi,
+					  const struct drm_display_mode *mode,
+					  u32 hcomponent)
+{
+	u32 frac, lbcc;
+
+	lbcc = hcomponent * dsi->phy_freq / 8;
+
+	frac = lbcc % mode->clock;
+	lbcc = lbcc / mode->clock;
+	if (frac)
+		lbcc++;
+
+	return lbcc;
+}
+
+static void canaan_dsi_set_dpi_timing(struct canaan_dsi *dsi,
+				      struct drm_display_mode *mode)
+{
+	u32 htotal, hsa, hbp, hact, lbcc, vsa, vbp, vfp, vact;
+
+	htotal = mode->htotal;
+	hsa = mode->hsync_end - mode->hsync_start;
+	hbp = mode->htotal - mode->hsync_end;
+	hact = mode->hdisplay;
+
+	vsa = mode->vsync_end - mode->vsync_start;
+	vbp = mode->vtotal - mode->vsync_end;
+	vact = mode->vdisplay;
+	vfp = mode->vtotal - vsa - vbp - vact;
+
+	dsi_write(dsi, VID_PKT_SIZE, hact);
+	dsi_write(dsi, VID_NUM_CHUNKS, 0);
+	dsi_write(dsi, VID_NULL_SIZE, 0);
+
+	// set hsa
+	lbcc = canaan_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
+	dsi_write(dsi, VID_HSA_TIME, lbcc);
+
+	// set hbp
+	lbcc = canaan_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
+	dsi_write(dsi, VID_HBP_TIME, lbcc);
+
+	// set hline
+	lbcc = canaan_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
+	dsi_write(dsi, VID_HLINE_TIME, lbcc);
+
+	// set vsa
+	dsi_write(dsi, VID_VSA_LINES, vsa);
+	// set vbp
+	dsi_write(dsi, VID_VBP_LINES, vbp);
+	// set vfp
+	dsi_write(dsi, VID_VFP_LINES, vfp);
+	// set vline
+	dsi_write(dsi, VID_VACTIVE_LINES, vact);
+}
+
+void canaan_dsi_lpdt_init(struct canaan_dsi *dsi, struct drm_display_mode *mode)
+{
+	// set lpdt div
+	dsi_write(dsi, CLKMGR_CFG, 0x108);
+	// set vcid
+	dsi_write(dsi, GEN_VCID, 0x303);
+	// stt dpi tinging
+	canaan_dsi_set_dpi_timing(dsi, mode);
+	/*
+	 * TODO dw drv improvements
+	 * compute high speed transmission counter timeout according
+	 * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
+	 */
+	// dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
+	/*
+	 * TODO dw drv improvements
+	 * the Bus-Turn-Around Timeout Counter should be computed
+	 * according to byte lane...
+	 */
+	// dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
+
+	dsi_write(dsi, MODE_CFG, 0x1);
+	dsi_write(dsi, VID_MODE_CFG, 0xbf02);
+	dsi_write(dsi, CMD_MODE_CFG, 0x10f7f01);
+	dsi_write(dsi, PCKHDL_CFG, 0x1c);
+	dsi_write(dsi, 0x4, 0x1);
+}
+
+static void canaan_mipi_dsi_set_dsi_enable(struct canaan_dsi *dsi)
+{
+	dsi_write(dsi, DPI_COLOR_CODING, 0x105);
+	dsi_write(dsi, 0x9c, 0x320068);
+	dsi_write(dsi, 0x98, 0x2e0080);
+	dsi_write(dsi, 0xc4, 0xffffffff);
+	dsi_write(dsi, 0xc8, 0xffffffff);
+	dsi_write(dsi, MODE_CFG, 0x0);
+	dsi_write(dsi, CMD_MODE_CFG, 0x0);
+	dsi_write(dsi, LPCLK_CTRL, 0x3);
+	dsi_write(dsi, LPCLK_CTRL, 0x1);
+}
+
+static void canaan_mipi_dsi_set_test_mode(struct canaan_dsi *dsi)
+{
+	uint32_t reg = 0;
+	//1. set MODE_CFG register to enable Video mode
+
+	//2. Configure the DPI_COLOR_CODING register.
+
+	//3. Configure the frame using the registers
+
+	//4. Configure the pattern generation mode
+	reg = dsi_read(dsi, VID_MODE_CFG);
+	reg = (reg & ~(BIT_MASK(20))) | (1 << 20);
+	reg = (reg & ~(BIT_MASK(24))) | (1 << 24);
+	reg = (reg & ~(BIT_MASK(16))) | (1 << 16);
+	dsi_write(dsi, VID_MODE_CFG, reg);
+}
+
+static void canaan_dsi_encoder_enable(struct drm_encoder *encoder)
+{
+	struct canaan_dsi *dsi = encoder_to_canaan_dsi(encoder);
+	struct drm_display_mode *adjusted_mode =
+		&encoder->crtc->state->adjusted_mode;
+	struct mipi_dsi_device *device = dsi->device;
+	int dsi_test_en = 0;
+
+	DRM_DEBUG_DRIVER("Enabling DSI output\n");
+
+	dev_vdbg(dsi->dev, "DSI encoder enable %u\n", adjusted_mode->clock);
+	switch (adjusted_mode->clock) {
+	case 74250:
+		// 74.25M
+		k230_dsi_config_4lan_phy(dsi, TXPHY_445_5_M, TXPHY_445_5_N,
+					 TXPHY_445_5_VOC, TXPHY_445_5_HS_FREQ);
+		// set clk todo
+		dsi->phy_freq = 445500;
+		dsi->clk_freq = 74250;
+		break;
+	case 148500:
+		// 144.5M
+		k230_dsi_config_4lan_phy(dsi, TXPHY_891_M, TXPHY_891_N,
+					 TXPHY_891_VOC, TXPHY_891_HS_FREQ);
+		// set clk todo
+		dsi->phy_freq = 890666;
+		dsi->clk_freq = 14850;
+		break;
+	case 39600: {
+		void *dis_clk = ioremap(0x91100000, 0x1000);
+		u32 reg = 0;
+		u32 div = 14;
+
+		reg = readl(dis_clk + 0x78);
+		reg = (reg & ~(GENMASK(10, 3))) |
+		      (div << 3); //  8M =    pll1(2376) / 4 / 66
+		reg = reg | (1 << 31);
+		writel(reg, dis_clk + 0x78);
+		// 475.5M
+		k230_dsi_config_4lan_phy(dsi, TXPHY_475_M, TXPHY_475_N,
+					 TXPHY_475_VOC, TXPHY_475_HS_FREQ);
+		// set clk todo
+		dsi->phy_freq = 475200;
+		dsi->clk_freq = 39600;
+		break;
+	}
+	default:
+		dev_err(dsi->dev, "MIPI clock not support\n");
+		break;
+	}
+	// set dsi lan num
+	canaan_dsi_set_lan_num(dsi, device->lanes);
+	// set lpdt
+	canaan_dsi_lpdt_init(dsi, adjusted_mode);
+
+	/*
+	 * Enable the DSI block.
+	 */
+
+	if (dsi->panel)
+		drm_panel_prepare(dsi->panel);
+
+	/*
+	 * FIXME: This should be moved after the switch to HS mode.
+	 *
+	 * Unfortunately, once in HS mode, it seems like we're not
+	 * able to send DCS commands anymore, which would prevent any
+	 * panel to send any DCS command as part as their enable
+	 * method, which is quite common.
+	 *
+	 * I haven't seen any artifact due to that sub-optimal
+	 * ordering on the panels I've tested it with, so I guess this
+	 * will do for now, until that IP is better understood.
+	 */
+	if (dsi->panel)
+		drm_panel_enable(dsi->panel);
+
+	//dsi enable
+	canaan_mipi_dsi_set_dsi_enable(dsi);
+
+	if (dsi_test_en == 1)
+		canaan_mipi_dsi_set_test_mode(dsi);
+}
+
+static void canaan_dsi_encoder_disable(struct drm_encoder *encoder)
+{
+	struct canaan_dsi *dsi = encoder_to_canaan_dsi(encoder);
+
+	DRM_DEBUG_DRIVER("Disabling DSI output\n");
+
+	if (dsi->panel) {
+		drm_panel_disable(dsi->panel);
+		drm_panel_unprepare(dsi->panel);
+	}
+}
+
+static int canaan_dsi_get_modes(struct drm_connector *connector)
+{
+	struct canaan_dsi *dsi = connector_to_canaan_dsi(connector);
+
+	return drm_panel_get_modes(dsi->panel, connector);
+}
+
+static const struct drm_connector_helper_funcs
+	canaan_dsi_connector_helper_funcs = {
+		.get_modes = canaan_dsi_get_modes,
+	};
+
+static enum drm_connector_status
+canaan_dsi_connector_detect(struct drm_connector *connector, bool force)
+{
+	struct canaan_dsi *dsi = connector_to_canaan_dsi(connector);
+
+	return dsi->panel ? connector_status_connected :
+			    connector_status_disconnected;
+}
+
+static const struct drm_connector_funcs canaan_dsi_connector_funcs = {
+	.detect = canaan_dsi_connector_detect,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.destroy = drm_connector_cleanup,
+	.reset = drm_atomic_helper_connector_reset,
+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static const struct drm_encoder_helper_funcs canaan_dsi_enc_helper_funcs = {
+	.disable = canaan_dsi_encoder_disable,
+	.enable = canaan_dsi_encoder_enable,
+};
+
+static int canaan_dsi_attach(struct mipi_dsi_host *host,
+			     struct mipi_dsi_device *device)
+{
+	struct canaan_dsi *dsi = host_to_canaan_dsi(host);
+	struct drm_panel *panel = of_drm_find_panel(device->dev.of_node);
+
+	if (IS_ERR(panel))
+		return PTR_ERR(panel);
+
+	dsi->connector.status = connector_status_connected;
+	dsi->panel = panel;
+	dsi->device = device;
+
+	dev_info(host->dev, "Attached device %s\n", device->name);
+
+	return 0;
+}
+
+static int canaan_dsi_detach(struct mipi_dsi_host *host,
+			     struct mipi_dsi_device *device)
+{
+	struct canaan_dsi *dsi = host_to_canaan_dsi(host);
+
+	dsi->panel = NULL;
+	dsi->device = NULL;
+
+	return 0;
+}
+
+static ssize_t canaan_dsi_transfer(struct mipi_dsi_host *host,
+				   const struct mipi_dsi_msg *msg)
+{
+	struct canaan_dsi *dsi = host_to_canaan_dsi(host);
+	int ret;
+
+	ret = canaan_dsi_inst_wait_for_completion(dsi);
+	if (ret < 0)
+		canaan_dsi_inst_abort(dsi);
+
+	switch (msg->type) {
+	case MIPI_DSI_DCS_SHORT_WRITE:
+		ret = canaan_dsi_dcs_write_short(dsi, msg);
+		break;
+	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
+	case MIPI_DSI_DCS_LONG_WRITE:
+	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
+		ret = canaan_dsi_dcs_write_long(dsi, msg);
+		break;
+
+	case MIPI_DSI_DCS_READ:
+		if (msg->rx_len == 1) {
+			ret = canaan_dsi_dcs_read(dsi, msg);
+			break;
+		}
+		fallthrough;
+	default:
+		ret = -EINVAL;
+	}
+	return ret;
+}
+
+static const struct mipi_dsi_host_ops canaan_dsi_host_ops = {
+	.attach = canaan_dsi_attach,
+	.detach = canaan_dsi_detach,
+	.transfer = canaan_dsi_transfer,
+};
+
+static int canaan_dsi_bind(struct device *dev, struct device *master,
+			   void *data)
+{
+	struct drm_device *drm = data;
+	struct canaan_dsi *dsi = dev_get_drvdata(dev);
+	int ret;
+
+	drm_encoder_helper_add(&dsi->encoder, &canaan_dsi_enc_helper_funcs);
+	ret = drm_simple_encoder_init(drm, &dsi->encoder, DRM_MODE_ENCODER_DSI);
+	if (ret) {
+		dev_err(dsi->dev, "Couldn't initialise the DSI encoder\n");
+		return ret;
+	}
+	dsi->encoder.possible_crtcs = BIT(0);
+
+	drm_connector_helper_add(&dsi->connector,
+				 &canaan_dsi_connector_helper_funcs);
+	ret = drm_connector_init(drm, &dsi->connector,
+				 &canaan_dsi_connector_funcs,
+				 DRM_MODE_CONNECTOR_DSI);
+	if (ret) {
+		dev_err(dsi->dev, "Couldn't initialise the DSI connector\n");
+		goto err_cleanup_connector;
+	}
+
+	drm_connector_attach_encoder(&dsi->connector, &dsi->encoder);
+
+	dsi->drm = drm;
+
+	return 0;
+
+err_cleanup_connector:
+	drm_encoder_cleanup(&dsi->encoder);
+	return ret;
+}
+
+static void canaan_dsi_unbind(struct device *dev, struct device *master,
+			      void *data)
+{
+	struct canaan_dsi *dsi = dev_get_drvdata(dev);
+
+	dsi->drm = NULL;
+}
+
+static const struct component_ops canaan_dsi_ops = {
+	.bind = canaan_dsi_bind,
+	.unbind = canaan_dsi_unbind,
+};
+
+static int canaan_dsi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct canaan_dsi *dsi;
+	struct resource *res;
+	int ret;
+
+	dev_info(&pdev->dev, "probe\n");
+	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
+	if (!dsi)
+		return -ENOMEM;
+	dev_set_drvdata(dev, dsi);
+	dsi->dev = dev;
+	dsi->host.ops = &canaan_dsi_host_ops;
+	dsi->host.dev = dev;
+
+	// DSI Device Tree Read..
+	// get dsi base addr
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dsi->base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(dsi->base)) {
+		dev_err(dev, "Couldn't map the DSI encoder registers\n");
+		return PTR_ERR(dsi->base);
+	}
+
+	ret = mipi_dsi_host_register(&dsi->host);
+	if (ret) {
+		dev_err(dev, "Couldn't register MIPI-DSI host\n");
+		goto err_unprotect_clk;
+	}
+
+	ret = component_add(&pdev->dev, &canaan_dsi_ops);
+	if (ret) {
+		dev_err(dev, "Couldn't register our component\n");
+		goto err_remove_dsi_host;
+	}
+
+	return 0;
+
+err_remove_dsi_host:
+	mipi_dsi_host_unregister(&dsi->host);
+err_unprotect_clk:
+	clk_rate_exclusive_put(dsi->mod_clk);
+	return ret;
+}
+
+static int canaan_dsi_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static const struct of_device_id canaan_dsi_of_table[] = {
+	{ .compatible = "canaan,k230-mipi-dsi" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, canaan_dsi_of_table);
+
+struct platform_driver canaan_dsi_driver = {
+	.probe		= canaan_dsi_probe,
+	.remove		= canaan_dsi_remove,
+	.driver		= {
+		.name		= "canaan-mipi-dsi",
+		.of_match_table	= canaan_dsi_of_table,
+	},
+};
+
+MODULE_AUTHOR("");
+MODULE_DESCRIPTION("Canaan K230 DSI Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/canaan/canaan_dsi.h b/drivers/gpu/drm/canaan/canaan_dsi.h
new file mode 100644
index 0000000000000..6f91ab36d98bb
--- /dev/null
+++ b/drivers/gpu/drm/canaan/canaan_dsi.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2022, Canaan Bright Sight Co., Ltd
+ *
+ * All enquiries to https://www.canaan-creative.com/
+ *
+ */
+
+#ifndef _CANAAN_DSI_H_
+#define _CANAAN_DSI_H_
+
+#include <drm/drm_connector.h>
+#include <drm/drm_encoder.h>
+#include <drm/drm_mipi_dsi.h>
+
+struct canaan_dsi {
+	struct drm_connector connector;
+	struct drm_encoder encoder;
+	struct mipi_dsi_host host;
+
+	struct clk *bus_clk;
+	struct clk *mod_clk;
+	struct regmap *regs;
+	struct regulator *regulator;
+	struct reset_control *reset;
+	struct phy *dphy;
+
+	struct device *dev;
+	struct mipi_dsi_device *device;
+	struct drm_device *drm;
+	struct drm_panel *panel;
+
+	void __iomem *base;
+	u32 phy_freq;
+	u32 clk_freq;
+};
+
+static inline struct canaan_dsi *host_to_canaan_dsi(struct mipi_dsi_host *host)
+{
+	return container_of(host, struct canaan_dsi, host);
+};
+
+static inline struct canaan_dsi *
+connector_to_canaan_dsi(struct drm_connector *connector)
+{
+	return container_of(connector, struct canaan_dsi, connector);
+};
+
+static inline struct canaan_dsi *
+encoder_to_canaan_dsi(const struct drm_encoder *encoder)
+{
+	return container_of(encoder, struct canaan_dsi, encoder);
+};
+
+void k230_dsi_config_4lan_phy(struct canaan_dsi *dsi, uint32_t m, uint32_t n,
+			      uint8_t vco, uint8_t hsfreq);
+
+#endif /* _CANAAN_DSI_H_ */
diff --git a/drivers/gpu/drm/canaan/canaan_phy.c b/drivers/gpu/drm/canaan/canaan_phy.c
new file mode 100644
index 0000000000000..f96c74af3f5ea
--- /dev/null
+++ b/drivers/gpu/drm/canaan/canaan_phy.c
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022, Canaan Bright Sight Co., Ltd
+ *
+ * All enquiries to https://www.canaan-creative.com/
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/crc-ccitt.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy-mipi-dphy.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_print.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_simple_kms_helper.h>
+#include "canaan_dsi.h"
+#include "linux/export.h"
+#include <video/mipi_display.h>
+
+#define TXDPHY_PLL_CFG1 0x10
+#define TXDPHY_PLL_CFG0 0x08
+#define PHY_TST_CTRL0 0xb4
+#define PHY_TST_CTRL1 0xb8
+#define TXDPHY_CFG1 0x4
+#define PHY_RSTZ 0xa0
+#define TXDPHY_CFG0 0x0
+#define PHY_STATUS (0xb0)
+#define LPCLK_CTRL (0x94)
+
+static void k230_dsi_write_phy_reg(struct canaan_dsi *dsi, uint8_t addr,
+				   uint8_t val)
+{
+	uint32_t reg = 0;
+
+	reg = 0x10000 + addr;
+	writel(reg, PHY_TST_CTRL1 + dsi->base);
+	writel(0x2, PHY_TST_CTRL0 + dsi->base);
+	writel(0x0, PHY_TST_CTRL0 + dsi->base);
+
+	reg = val;
+	writel(reg, PHY_TST_CTRL1 + dsi->base);
+	writel(0x2, PHY_TST_CTRL0 + dsi->base);
+	writel(0x0, PHY_TST_CTRL0 + dsi->base);
+}
+
+static void k230_dsi_phy_pll_config(struct canaan_dsi *dsi, uint32_t m,
+				    uint32_t n, uint8_t vco)
+{
+	uint32_t reg = 0;
+
+	reg = readl(dsi->base + 0x400 + TXDPHY_PLL_CFG1);
+	reg = (reg & ~(BIT_MASK(9))) | (1 << 9); // shadow_clear field
+	writel(reg, dsi->base + 0x400 + TXDPHY_PLL_CFG1);
+	reg = (reg & ~(BIT_MASK(9))) | (0 << 9); // shadow_clear field
+	writel(reg, dsi->base + 0x400 + TXDPHY_PLL_CFG1);
+
+	reg = readl(dsi->base + 0x400 + TXDPHY_PLL_CFG1);
+	reg = (reg & ~(GENMASK(1, 0))) | (0x1 << 0); // clksel
+	writel(reg, dsi->base + 0x400 + TXDPHY_PLL_CFG1);
+
+	reg = readl(dsi->base + 0x400 + TXDPHY_PLL_CFG0); // TODO case by case
+	reg = (reg & ~(GENMASK(26, 17))) | (m << 17); // M=m+2   M=125
+	reg = (reg & ~(GENMASK(30, 27))) | (n << 27); // N=n+1   N=6
+	writel(reg,
+	       dsi->base + 0x400 +
+		       TXDPHY_PLL_CFG0); // expect fout = 125 = (1M/4N)*24;  m=125,n=6
+
+	reg = readl(dsi->base + 0x400 + TXDPHY_PLL_CFG1);
+	reg = (reg & ~(GENMASK(16, 11))) | (vco << 11); // vco_cntrl
+	writel(reg, dsi->base + 0x400 + TXDPHY_PLL_CFG1);
+
+	reg = readl(dsi->base + 0x400 + TXDPHY_PLL_CFG0);
+	reg = (reg & ~(GENMASK(6, 0))) | (0x10 << 0); // cpbias_cntrl
+	writel(reg, dsi->base + 0x400 + TXDPHY_PLL_CFG0);
+
+	reg = readl(dsi->base + 0x400 + TXDPHY_PLL_CFG0);
+	reg = (reg & ~(GENMASK(9, 8))) | (0x00 << 8); // gmp_cntrl
+	writel(reg, dsi->base + 0x400 + TXDPHY_PLL_CFG0);
+
+	reg = readl(dsi->base + 0x400 + TXDPHY_PLL_CFG0);
+	reg = (reg & ~(GENMASK(16, 11))) | (0x00 << 11); // int_cntrl
+	writel(reg, dsi->base + 0x400 + TXDPHY_PLL_CFG0);
+
+	reg = readl(dsi->base + 0x400 + TXDPHY_PLL_CFG1);
+	reg = (reg & ~(GENMASK(8, 3))) | (0x8 << 3); // prop_cntrl
+	writel(reg, dsi->base + 0x400 + TXDPHY_PLL_CFG1);
+
+	k230_dsi_write_phy_reg(dsi, 0x14, 0x2); // pll1_th1
+	k230_dsi_write_phy_reg(dsi, 0x15, 0x60); // pll1_th2
+	k230_dsi_write_phy_reg(dsi, 0x16, 0x3); // pll1_th3
+	k230_dsi_write_phy_reg(dsi, 0x1D, 0x1); // pll_lock_sel
+
+	reg = readl(dsi->base + 0x400 + TXDPHY_PLL_CFG1);
+	reg = (reg & ~(BIT_MASK(10))) | (1 << 10);
+	writel(reg, dsi->base + 0x400 + TXDPHY_PLL_CFG1);
+
+	msleep(20);
+
+	reg = (reg & ~(BIT_MASK(10))) | (0 << 10);
+	writel(reg, dsi->base + 0x400 + TXDPHY_PLL_CFG1);
+}
+
+static void k230_dsi_phy0_config(struct canaan_dsi *dsi, uint32_t m, uint32_t n,
+				 uint8_t vco, uint8_t hsfreq)
+{
+	uint32_t reg = 0;
+
+	// select phy0
+	writel(0x0, dsi->base + 0x400 + TXDPHY_CFG1);
+	// set rstz
+	writel(0xc, dsi->base + PHY_RSTZ);
+	// Set test clr to 1
+	writel(0x1, dsi->base + PHY_TST_CTRL0);
+	// Set test clr to 0
+	writel(0x0, dsi->base + PHY_TST_CTRL0);
+	// set mastermacro=1, prototyping_env =1 ??
+	k230_dsi_write_phy_reg(dsi, 0x0c, 0x03);
+	//set hsfreqrange
+	// k230_dsi_write_phy_reg(0x44, 0x96);
+	k230_dsi_write_phy_reg(dsi, 0x44, hsfreq); // set 445.5  hsfreqrange = 0010110
+	// for < 1.5Gbps data rate set Slew
+	k230_dsi_write_phy_reg(
+		dsi, 0xa0,
+		0x40); // set Slew rate vs DDL sr_range      *TODO case by case
+	k230_dsi_write_phy_reg(
+		dsi, 0xa4,
+		0x11); // set Slew sr_osc_freq_target[6:0]   *TODO case by case
+	k230_dsi_write_phy_reg(
+		dsi, 0xa4,
+		0x85); // set Slew sr_osc_freq_target[11:7]  *TODO case by case
+	k230_dsi_write_phy_reg(
+		dsi, 0xa3,
+		0x1); // enable Slew rate calibration  (sr_sel_tester)
+
+	k230_dsi_write_phy_reg(dsi, 0x1f, 0x1); // mpll_prog[0] = 1'b1
+	k230_dsi_write_phy_reg(dsi, 0x4a, 0x40); // prg_on_lane0 = 1'b1
+
+	reg = readl(dsi->base + 0x400 + TXDPHY_CFG0);
+	reg = (reg & ~(GENMASK(7, 2))) |
+	      (0x28 << 2); //phy0 cfgclkfreqrange     6'b101000;
+	reg = (reg & ~(GENMASK(13, 8))) |
+	      (0x28 << 8); //phy1 cfgclkfreqrange      6'b101000;
+	writel(reg, dsi->base + 0x400 + TXDPHY_CFG0);
+
+	// config pll
+	// k230_dsi_phy_pll_config(295, 15, 0x17);                  // 222.75 M   phy clk = pll x 2
+	k230_dsi_phy_pll_config(dsi, m, n, vco); // 222.75 M   phy clk = pll x 2
+
+	writel(0x28a0, dsi->base + 0x400 + TXDPHY_CFG0);
+	writel(0xc, dsi->base + PHY_RSTZ);
+}
+
+void k230_dsi_phy1_config(struct canaan_dsi *dsi, uint8_t hsfreq)
+{
+	uint32_t reg = 0;
+	unsigned int count = 0;
+
+	// select1
+	writel(0x400000, dsi->base + 0x400 + TXDPHY_CFG1);
+
+	writel(0x1, dsi->base + PHY_TST_CTRL0);
+	msleep(20);
+	writel(0x0, dsi->base + PHY_TST_CTRL0);
+
+	// SET TEST CLR TO LOW
+	k230_dsi_write_phy_reg(dsi, 0xc, 0x0);
+
+	// select1
+	writel(0x400000, dsi->base + 0x400 + TXDPHY_CFG1);
+
+	//set hsfreqrange 445.5Mbps
+	// k230_dsi_write_phy_reg(0x44, 0x96);
+	k230_dsi_write_phy_reg(dsi, 0x44, hsfreq); // set 445.5  hsfreqrange = 0010110
+
+	// try slave phy hs clk lane
+	k230_dsi_write_phy_reg(dsi, 0x30, 0xff);
+
+	// for < 1.5Gbps data rate set Slew
+	k230_dsi_write_phy_reg(
+		dsi, 0xa0,
+		0x40); // set Slew rate vs DDL sr_range      *TODO case by cas
+
+	k230_dsi_write_phy_reg(
+		dsi, 0xa4,
+		0x11); // set Slew sr_osc_freq_target[6:0]   *TODO case by case
+
+	k230_dsi_write_phy_reg(
+		dsi, 0xa4,
+		0x85); // set Slew sr_osc_freq_target[11:7]  *TODO case by case
+	k230_dsi_write_phy_reg(
+		dsi, 0xa3,
+		0x1); // enable Slew rate calibration  (sr_sel_tester)
+	k230_dsi_write_phy_reg(dsi, 0x1f, 0x1); // mpll_prog[0] = 1'b1
+
+	k230_dsi_write_phy_reg(dsi, 0x4a, 0x40); // prg_on_lane0 = 1'b1
+
+	reg = readl(dsi->base + 0x400 + TXDPHY_CFG0);
+	reg = (reg & ~(GENMASK(7, 2))) |
+	      (0x28 << 2); //phy0 cfgclkfreqrange     6'b101000;
+	reg = (reg & ~(GENMASK(13, 8))) |
+	      (0x28 << 8); //phy1 cfgclkfreqrange      6'b101000;
+	writel(reg, dsi->base + 0x400 + TXDPHY_CFG0);
+
+	reg = readl(dsi->base + 0x400 + TXDPHY_CFG0);
+	reg = (reg & ~(BIT_MASK(1))) | (0 << 1);
+	writel(reg, dsi->base + 0x400 + TXDPHY_CFG0); //phy1 basedir
+
+	writel(0x4, dsi->base + PHY_RSTZ); //phy enableclk
+	writel(0xd, dsi->base + PHY_RSTZ); // redundant
+	writel(0xf, dsi->base + PHY_RSTZ);
+
+	k230_dsi_write_phy_reg(dsi, 0x3, 0x80); // monitor phy fsm
+
+	while (readl(dsi->base + PHY_TST_CTRL1) != 0x580) { //0x580
+		k230_dsi_write_phy_reg(dsi, 0x03, 0x80);
+		msleep(20);
+		count += 1;
+		if (count >= 1000)
+			break;
+	}
+
+}
+
+void k230_dsi_config_4lan_phy(struct canaan_dsi *dsi, uint32_t m, uint32_t n,
+			      uint8_t vco, uint8_t hsfreq)
+{
+	uint32_t reg = 0;
+
+	k230_dsi_phy0_config(dsi, m, n, vco, hsfreq);
+	k230_dsi_phy1_config(dsi, hsfreq);
+
+	reg = readl(dsi->base + 0x400 + TXDPHY_CFG1); // rdata = 0x0
+	writel(0x0, dsi->base + 0x400 + TXDPHY_CFG1);
+	writel(0xd, dsi->base + PHY_RSTZ);
+	writel(0xf, dsi->base + PHY_RSTZ);
+
+	while (readl(dsi->base + PHY_STATUS) != 0x1fbd)
+		;
+
+	msleep(20);
+	/* To postpone HS request,
+	 * for MIPI spec: First STOP_STATE time should be greater than T_INIT time at least 100us
+	 */
+	writel(0x1, dsi->base + LPCLK_CTRL);
+
+	//-------- display_dut_cfg_seq_dsi::wait_for_PHY1_PWRUP() -------//
+	reg = readl(dsi->base + 0x400 + TXDPHY_CFG1); // rdata = 0x0
+	writel(0x400000, dsi->base + 0x400 + TXDPHY_CFG1);
+
+	while (readl(dsi->base + PHY_STATUS) != 0x1fbd)
+		;
+
+	reg = readl(dsi->base + PHY_STATUS); // rdata = 0x1fbd
+}
diff --git a/drivers/gpu/drm/canaan/canaan_plane.c b/drivers/gpu/drm/canaan/canaan_plane.c
new file mode 100644
index 0000000000000..6a159365cc9c4
--- /dev/null
+++ b/drivers/gpu/drm/canaan/canaan_plane.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022, Canaan Bright Sight Co., Ltd
+ *
+ * All enquiries to https://www.canaan-creative.com/
+ *
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/component.h>
+#include <linux/of_graph.h>
+#include <linux/of_platform.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_vblank.h>
+#include <drm/drm_ioctl.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_print.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_plane.h>
+#include <drm/drm_plane_helper.h>
+#include <drm/drm_probe_helper.h>
+
+#include "canaan_vo.h"
+#include "canaan_crtc.h"
+#include "canaan_plane.h"
+
+static int canaan_plane_atomic_check(struct drm_plane *plane,
+				     struct drm_atomic_state *state)
+{
+	struct drm_plane_state *plane_state =
+		drm_atomic_get_new_plane_state(state, plane);
+	struct canaan_plane *canaan_plane = to_canaan_plane(plane);
+	struct canaan_vo *vo = canaan_plane->vo;
+
+	if (!plane_state->crtc || !plane_state->fb) {
+		DRM_DEBUG_DRIVER("crtc or fb NULL\n");
+		return 0;
+	}
+
+	DRM_DEBUG_DRIVER("Check plane:%d\n", plane->base.id);
+	DRM_DEBUG_DRIVER("(%d,%d)@(%d,%d) -> (%d,%d)@(%d,%d)\n",
+			 plane_state->src_w >> 16, plane_state->src_h >> 16,
+			 plane_state->src_x >> 16, plane_state->src_y >> 16,
+			 plane_state->crtc_w, plane_state->crtc_h,
+			 plane_state->crtc_x, plane_state->crtc_y);
+
+	return canaan_vo_check_plane(vo, canaan_plane, plane_state);
+}
+
+static void canaan_plane_atomic_update(struct drm_plane *plane,
+				       struct drm_atomic_state *state)
+{
+	struct drm_plane_state *plane_state = plane->state;
+	struct canaan_plane *canaan_plane = to_canaan_plane(plane);
+	struct canaan_vo *vo = canaan_plane->vo;
+
+	if (!plane_state->crtc || !plane_state->fb) {
+		DRM_DEBUG_DRIVER("crtc or fb NULL\n");
+		return;
+	}
+
+	DRM_DEBUG_DRIVER("Update plane:%d\n", plane->base.id);
+	canaan_vo_update_plane(vo, canaan_plane, plane_state);
+}
+
+static void canaan_plane_atomic_disable(struct drm_plane *plane,
+					struct drm_atomic_state *state)
+{
+	struct canaan_plane *canaan_plane = to_canaan_plane(plane);
+	struct canaan_vo *vo = canaan_plane->vo;
+
+	DRM_DEBUG_DRIVER("Disable plane:%d\n", plane->base.id);
+	canaan_vo_disable_plane(vo, canaan_plane);
+}
+
+static const struct drm_plane_funcs canaan_plane_funcs = {
+	.reset = drm_atomic_helper_plane_reset,
+	.destroy = drm_plane_cleanup,
+	.update_plane = drm_atomic_helper_update_plane,
+	.disable_plane = drm_atomic_helper_disable_plane,
+	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+};
+
+static const struct drm_plane_helper_funcs canaan_plane_helper_funcs = {
+	.atomic_check = canaan_plane_atomic_check,
+	.atomic_update = canaan_plane_atomic_update,
+	.atomic_disable = canaan_plane_atomic_disable,
+};
+
+struct canaan_plane *canaan_plane_create(struct drm_device *drm_dev,
+					 struct canaan_plane_config *config,
+					 struct canaan_vo *vo)
+{
+	int ret = 0;
+	struct canaan_plane *canaan_plane = NULL;
+	struct drm_plane *plane = NULL;
+	struct device *dev = vo->dev;
+
+	canaan_plane = devm_kzalloc(dev, sizeof(*canaan_plane), GFP_KERNEL);
+	if (!canaan_plane)
+		return ERR_PTR(-ENOMEM);
+	plane = &canaan_plane->base;
+
+	ret = drm_universal_plane_init(drm_dev, plane, config->possible_crtcs,
+				       &canaan_plane_funcs, config->formats,
+				       config->num_formats, NULL,
+				       config->plane_type, NULL);
+	if (ret) {
+		DRM_DEV_ERROR(dev, "Failed to init Plane\n");
+		return ERR_PTR(ret);
+	}
+
+	drm_plane_helper_add(plane, &canaan_plane_helper_funcs);
+	canaan_plane->id = config->id;
+	canaan_plane->config = config;
+	canaan_plane->vo = vo;
+	DRM_DEBUG_DRIVER("Create plane:%d\n", plane->base.id);
+
+	return canaan_plane;
+}
diff --git a/drivers/gpu/drm/canaan/canaan_plane.h b/drivers/gpu/drm/canaan/canaan_plane.h
new file mode 100644
index 0000000000000..3c07fe6f42f44
--- /dev/null
+++ b/drivers/gpu/drm/canaan/canaan_plane.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2022, Canaan Bright Sight Co., Ltd
+ *
+ * All enquiries to https://www.canaan-creative.com/
+ *
+ */
+
+#ifndef __CANAAN_PLANE_H__
+#define __CANAAN_PLANE_H__
+
+struct canaan_plane_config {
+	char *name;
+	uint32_t id;
+	uint32_t possible_crtcs;
+	uint32_t num_formats;
+	const uint32_t *formats;
+	enum drm_plane_type plane_type;
+
+	uint32_t plane_offset;
+	uint32_t plane_enable_bit;
+	uint32_t xctl_reg_offset;
+	uint32_t yctl_reg_offset;
+};
+
+struct canaan_plane {
+	struct drm_plane base;
+	struct canaan_vo *vo;
+	struct canaan_plane_config *config;
+	uint32_t id;
+};
+
+static inline struct canaan_plane *to_canaan_plane(struct drm_plane *plane)
+{
+	return container_of(plane, struct canaan_plane, base);
+}
+
+struct canaan_plane *canaan_plane_create(struct drm_device *drm_dev,
+					 struct canaan_plane_config *config,
+					 struct canaan_vo *vo);
+#endif /* __CANAAN_PLANE_H__ */
diff --git a/drivers/gpu/drm/canaan/canaan_vo.c b/drivers/gpu/drm/canaan/canaan_vo.c
new file mode 100644
index 0000000000000..604442435c0fc
--- /dev/null
+++ b/drivers/gpu/drm/canaan/canaan_vo.c
@@ -0,0 +1,687 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022, Canaan Bright Sight Co., Ltd
+ *
+ * All enquiries to https://www.canaan-creative.com/
+ *
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/component.h>
+#include <linux/of_graph.h>
+#include <linux/of_platform.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_framebuffer.h>
+#include <drm/drm_gem_dma_helper.h>
+#include <drm/drm_fb_dma_helper.h>
+#include <drm/drm_vblank.h>
+#include <drm/drm_ioctl.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_print.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_plane.h>
+#include <drm/drm_plane_helper.h>
+#include <drm/drm_probe_helper.h>
+
+#include "canaan_vo.h"
+#include "canaan_vo_regs.h"
+#include "canaan_vo_table.h"
+#include "canaan_crtc.h"
+#include "canaan_plane.h"
+
+static inline void canaan_vo_write(struct canaan_vo *vo, u32 reg, u32 val)
+{
+	writel(val, vo->reg_base + reg);
+}
+
+static inline u32 canaan_vo_read(struct canaan_vo *vo, u32 reg)
+{
+	return readl(vo->reg_base + reg);
+}
+
+static void canaan_vo_update_video(struct canaan_vo *vo,
+				   struct canaan_plane *canaan_plane,
+				   struct drm_display_mode *adj_mode)
+{
+	uint32_t reg_val = 0x00;
+	struct drm_plane_state *plane_state = canaan_plane->base.state;
+	struct drm_framebuffer *fb = plane_state->fb;
+	struct drm_gem_dma_object *cma_obj = drm_fb_dma_get_gem_obj(fb, 0);
+	struct canaan_plane_config *config = canaan_plane->config;
+	uint32_t plane_offset = config->plane_offset;
+	uint32_t plane_enable_bit = config->plane_enable_bit;
+	uint32_t xctl_reg_offset = config->xctl_reg_offset;
+	uint32_t yctl_reg_offset = config->yctl_reg_offset;
+	uint32_t actual_w, start_w, offset_w;
+	uint32_t actual_h, start_h, offset_h;
+	uint32_t y_addr, uv_addr;
+	uint32_t stride = 0x00;
+	uint32_t disp_en = 0x00;
+
+	switch (fb->format->format) {
+	case DRM_FORMAT_NV12:
+		reg_val = 1 + (1 << 8) + (1 << 12) + (3 << 16) + (0 << 28);
+		break;
+	case DRM_FORMAT_NV21:
+		reg_val = 1 + (1 << 8) + (1 << 12) + (2 << 16) + (0 << 28);
+		break;
+	case DRM_FORMAT_NV16:
+		reg_val = 1 + (1 << 4) + (1 << 12) + (3 << 16) + (0 << 28);
+		break;
+	case DRM_FORMAT_NV61:
+		reg_val = 1 + (1 << 4) + (1 << 12) + (2 << 16) + (0 << 28);
+		break;
+	default:
+		DRM_DEV_ERROR(vo->dev, "Invalid pixel format %d\n",
+			      fb->format->format);
+		return;
+	}
+	writel(reg_val,
+	       vo->reg_base + plane_offset + VO_LAYER2_3_CTL_REG_OFFSET);
+
+	actual_w = plane_state->src_w >> 16;
+	actual_h = plane_state->src_h >> 16;
+	reg_val = (actual_w - 1) | (actual_h << 16);
+	writel(reg_val,
+	       vo->reg_base + plane_offset + VO_LAYER2_3_ACT_SIZE_REG_OFFSET);
+
+	offset_w = plane_state->crtc_x;
+	start_w = readl(vo->reg_base + VO_DISP_XZONE_CTL) & 0x1fff;
+	reg_val = ((start_w + offset_w + actual_w - 1) << 16) +
+		  (start_w + offset_w);
+	writel(reg_val, vo->reg_base + xctl_reg_offset);
+
+	offset_h = plane_state->crtc_y;
+	start_h = readl(vo->reg_base + VO_DISP_YZONE_CTL) & 0x1fff;
+	reg_val = ((start_h + offset_h + actual_h - 1) << 16) +
+		  (start_h + offset_h);
+	writel(reg_val, vo->reg_base + yctl_reg_offset);
+
+	y_addr = cma_obj->dma_addr;
+	writel(y_addr,
+	       vo->reg_base + plane_offset + VO_LAYER2_3_Y_ADDR0_REG_OFFSET);
+	writel(y_addr,
+	       vo->reg_base + plane_offset + VO_LAYER2_3_Y_ADDR1_REG_OFFSET);
+
+	uv_addr = cma_obj->dma_addr + fb->offsets[1];
+	writel(uv_addr,
+	       vo->reg_base + plane_offset + VO_LAYER2_3_UV_ADDR0_REG_OFFSET);
+	writel(uv_addr,
+	       vo->reg_base + plane_offset + VO_LAYER2_3_UV_ADDR1_REG_OFFSET);
+
+	stride = (actual_w / 8 - 1) | (actual_h << 16);
+	writel(stride,
+	       vo->reg_base + plane_offset + VO_LAYER2_3_STRIDE_REG_OFFSET);
+
+	writel(0x00, vo->reg_base + plane_offset +
+			     VO_LAYER2_3_IMG_IN_OFFSET_REG_OFFSET);
+	writel(0x0f,
+	       vo->reg_base + plane_offset + VO_LAYER2_3_BLENTH_REG_OFFSET);
+	writel(0x11, vo->reg_base + plane_offset +
+			     VO_LAYER2_3_ADDR_SEL_MODE_REG_OFFSET);
+
+	disp_en = readl(vo->reg_base + VO_DISP_ENABLE);
+	disp_en |= 1 << plane_enable_bit;
+	writel(disp_en, vo->reg_base + VO_DISP_ENABLE);
+
+	DRM_DEBUG_DRIVER("VIDEO_CTL_REG: 0x%02x\n",
+			 readl(vo->reg_base + plane_offset +
+			       VO_LAYER2_3_CTL_REG_OFFSET));
+	DRM_DEBUG_DRIVER("VIDEO_ACT_SIZE_REG: 0x%02x\n",
+			 readl(vo->reg_base + plane_offset +
+			       VO_LAYER2_3_ACT_SIZE_REG_OFFSET));
+	DRM_DEBUG_DRIVER("VIDEO_Y_ADDR0_REG: 0x%02x\n",
+			 readl(vo->reg_base + plane_offset +
+			       VO_LAYER2_3_Y_ADDR0_REG_OFFSET));
+	DRM_DEBUG_DRIVER("VIDEO_UV_ADDR0_REG: 0x%02x\n",
+			 readl(vo->reg_base + plane_offset +
+			       VO_LAYER2_3_UV_ADDR0_REG_OFFSET));
+	DRM_DEBUG_DRIVER("VIDEO_STRIDE_REG: 0x%02x\n",
+			 readl(vo->reg_base + plane_offset +
+			       VO_LAYER2_3_STRIDE_REG_OFFSET));
+}
+
+static void canaan_vo_update_osd(struct canaan_vo *vo,
+				 struct canaan_plane *canaan_plane,
+				 struct drm_display_mode *adj_mode)
+{
+	uint32_t reg_val = 0x00;
+	struct drm_plane_state *plane_state = canaan_plane->base.state;
+	struct drm_framebuffer *fb = plane_state->fb;
+	struct drm_gem_dma_object *cma_obj = drm_fb_dma_get_gem_obj(fb, 0);
+	struct canaan_plane_config *config = canaan_plane->config;
+	uint32_t plane_offset = config->plane_offset;
+	uint32_t plane_enable_bit = config->plane_enable_bit;
+	uint32_t xctl_reg_offset = config->xctl_reg_offset;
+	uint32_t yctl_reg_offset = config->yctl_reg_offset;
+	uint32_t actual_w, start_w, offset_w;
+	uint32_t actual_h, start_h, offset_h;
+	dma_addr_t paddr = 0x00;
+	uint32_t stride = 0x00;
+	uint32_t disp_en = 0x00;
+
+	switch (fb->format->format) {
+	case DRM_FORMAT_ARGB8888:
+		reg_val = 0x53;
+		break;
+	case DRM_FORMAT_ARGB4444:
+		reg_val = 0x54;
+		break;
+	case DRM_FORMAT_ARGB1555:
+		reg_val = 0x55;
+		break;
+	case DRM_FORMAT_RGB888:
+		reg_val = 0x00;
+		break;
+	case DRM_FORMAT_RGB565:
+		reg_val = 0x02;
+		break;
+	default:
+		DRM_DEV_ERROR(vo->dev, "Invalid pixel format %d\n",
+			      fb->format->format);
+		return;
+	}
+	writel(reg_val,
+	       vo->reg_base + plane_offset + VO_OSD0_7_INFO_REG_OFFSET);
+
+	actual_w = plane_state->src_w >> 16;
+	actual_h = plane_state->src_h >> 16;
+	reg_val = actual_w | actual_h << 16;
+	writel(reg_val,
+	       vo->reg_base + plane_offset + VO_OSD0_7_SIZE_REG_OFFSET);
+
+	offset_w = plane_state->crtc_x;
+	start_w = readl(vo->reg_base + VO_DISP_XZONE_CTL) & 0x1fff;
+	reg_val = ((start_w + offset_w + actual_w - 1) << 16) +
+		  (start_w + offset_w);
+	writel(reg_val, vo->reg_base + xctl_reg_offset);
+
+	offset_h = plane_state->crtc_y;
+	start_h = readl(vo->reg_base + VO_DISP_YZONE_CTL) & 0x1fff;
+	reg_val = ((start_h + offset_h + actual_h - 1) << 16) +
+		  (start_h + offset_h);
+	writel(reg_val, vo->reg_base + yctl_reg_offset);
+
+	paddr = cma_obj->dma_addr;
+	writel(paddr,
+	       vo->reg_base + plane_offset + VO_OSD0_7_VLU_ADDR0_REG_OFFSET);
+	writel(paddr,
+	       vo->reg_base + plane_offset + VO_OSD0_7_ALP_ADDR0_REG_OFFSET);
+	writel(paddr,
+	       vo->reg_base + plane_offset + VO_OSD0_7_VLU_ADDR1_REG_OFFSET);
+	writel(paddr,
+	       vo->reg_base + plane_offset + VO_OSD0_7_ALP_ADDR1_REG_OFFSET);
+
+	stride = fb->pitches[0] / 8;
+	writel(stride,
+	       vo->reg_base + plane_offset + VO_OSD0_7_STRIDE_REG_OFFSET);
+
+	writel(0x4F,
+	       vo->reg_base + plane_offset + VO_OSD0_7_DMA_CTRL_REG_OFFSET);
+	writel(0x100, vo->reg_base + plane_offset +
+			      VO_OSD0_7_ADDR_SEL_MODE_REG_OFFSET);
+
+	disp_en = readl(vo->reg_base + VO_DISP_ENABLE);
+	disp_en |= 1 << plane_enable_bit;
+	writel(disp_en, vo->reg_base + VO_DISP_ENABLE);
+
+	DRM_DEBUG_DRIVER(
+		"OSD_INFO_REG: 0x%02x\n",
+		readl(vo->reg_base + plane_offset + VO_OSD0_7_INFO_REG_OFFSET));
+	DRM_DEBUG_DRIVER(
+		"OSD_SIZE_REG: 0x%02x\n",
+		readl(vo->reg_base + plane_offset + VO_OSD0_7_SIZE_REG_OFFSET));
+	DRM_DEBUG_DRIVER("OSD_VLU_ADDR0_REG: 0x%02x\n",
+			 readl(vo->reg_base + plane_offset +
+			       VO_OSD0_7_VLU_ADDR0_REG_OFFSET));
+	DRM_DEBUG_DRIVER("OSD_ALP_ADDR0_REG: 0x%02x\n",
+			 readl(vo->reg_base + plane_offset +
+			       VO_OSD0_7_ALP_ADDR0_REG_OFFSET));
+	DRM_DEBUG_DRIVER("OSD_STRIDE_REG: 0x%02x\n",
+			 readl(vo->reg_base + plane_offset +
+			       VO_OSD0_7_STRIDE_REG_OFFSET));
+}
+
+int canaan_vo_check_plane(struct canaan_vo *vo,
+			  struct canaan_plane *canaan_plane,
+			  struct drm_plane_state *plane_state)
+{
+	int ret = 0;
+	struct drm_crtc_state *crtc_state = NULL;
+
+	crtc_state = drm_atomic_get_crtc_state(plane_state->state,
+					       plane_state->crtc);
+	if (IS_ERR(crtc_state)) {
+		DRM_DEV_ERROR(vo->dev, "Failed to get crtc_state\n");
+		return PTR_ERR(crtc_state);
+	}
+
+	ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,
+						  DRM_PLANE_NO_SCALING,
+						  DRM_PLANE_NO_SCALING, true,
+						  true);
+	if (ret) {
+		DRM_DEV_ERROR(vo->dev, "Failed to check plane_state\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+void canaan_vo_update_plane(struct canaan_vo *vo,
+			    struct canaan_plane *canaan_plane,
+			    struct drm_plane_state *plane_state)
+{
+	struct drm_crtc_state *crtc_state = plane_state->crtc->state;
+	struct drm_display_mode *adj_mode = &crtc_state->adjusted_mode;
+
+	if (vo->canaan_plane[0]->id == canaan_plane->id)
+		canaan_vo_update_video(vo, canaan_plane, adj_mode);
+	else
+		canaan_vo_update_osd(vo, canaan_plane, adj_mode);
+}
+
+void canaan_vo_disable_plane(struct canaan_vo *vo,
+			     struct canaan_plane *canaan_plane)
+{
+	struct canaan_plane_config *config = canaan_plane->config;
+	uint32_t plane_enable_bit = config->plane_enable_bit;
+	uint32_t disp_en = 0x00;
+
+	disp_en = readl(vo->reg_base + VO_DISP_ENABLE);
+	disp_en &= ~(1 << plane_enable_bit);
+	writel(disp_en, vo->reg_base + VO_DISP_ENABLE);
+}
+
+static irqreturn_t canaan_vo_irq_handler(int irq, void *dev_id)
+{
+	struct canaan_vo *vo = dev_id;
+	struct canaan_crtc *canaan_crtc = vo->canaan_crtc;
+
+	canaan_vo_write(vo, VO_DISP_IRQ_STATUS, 0xffffffff);
+
+	// printk("canaan_vo_irq_handler---------------\n");
+	if (atomic_read(&vo->vsync_enabled))
+		drm_crtc_handle_vblank(&canaan_crtc->base);
+
+	return IRQ_HANDLED;
+}
+
+static void canaan_vo_set_vtth_intr(struct canaan_vo *vo, bool status, u32 vpos)
+{
+	u32 reg = 0;
+
+	reg = (reg & ~(BIT_MASK(20))) | (status << 20);
+	if (status != 0)
+		reg = (reg & ~(GENMASK(12, 0))) | (vpos << 0);
+
+	canaan_vo_write(vo, VO_DISP_IRQ1_CTL, reg);
+}
+
+int canaan_vo_enable_vblank(struct canaan_vo *vo)
+{
+	atomic_set(&vo->vsync_enabled, 1);
+
+	canaan_vo_set_vtth_intr(vo, 1, vo->vth_line);
+	// canaan_vo_write(vo, VO_REG_LOAD_CTL, 0x11);
+	return 0;
+}
+
+void canaan_vo_disable_vblank(struct canaan_vo *vo)
+{
+	atomic_set(&vo->vsync_enabled, 0);
+
+	canaan_vo_set_vtth_intr(vo, 0, vo->vth_line);
+	// canaan_vo_write(vo, VO_REG_LOAD_CTL, 0x11);
+}
+
+static void canaan_vo_init(struct canaan_vo *vo)
+{
+	int i = 0;
+	u32 reg = 0;
+
+	canaan_vo_write(vo, VO_DMA_SW_CTL, 0x11);
+	canaan_vo_write(vo, VO_DMA_RD_CTL_OUT, 0x88);
+	canaan_vo_write(vo, VO_DMA_ARB_MODE, 0x0);
+
+	for (i = 0; i < 8; i++)
+		canaan_vo_write(vo, 0x14 + (4 * i), 0x1010101);
+
+	canaan_vo_write(vo, 0x34, 0x76543210);
+	canaan_vo_write(vo, 0x3c, 0x76543210);
+	canaan_vo_write(vo, 0x44, 0x76543210);
+	canaan_vo_write(vo, VO_DMA_ID_RD_0, 0x76543210);
+
+	canaan_vo_write(vo, 0x38, 0xfedcba98);
+	canaan_vo_write(vo, 0x40, 0xfedcba98);
+	canaan_vo_write(vo, 0x48, 0xfedcba98);
+	canaan_vo_write(vo, 0x50, 0xfedcba98);
+
+	for (i = 0; i < 10; i++)
+		canaan_vo_write(vo, VO_LAYER0_LINE0_BD_CTL + (4 * i), 0x701);
+
+	canaan_vo_write(vo, 0x800, 0x701);
+	canaan_vo_write(vo, 0x804, 0x701);
+	canaan_vo_write(vo, 0x808, 0x701);
+	canaan_vo_write(vo, 0x80c, 0x701);
+	canaan_vo_write(vo, 0x810, 0x701);
+
+	canaan_vo_write(vo, VO_DISP_ENABLE, 0x0);
+
+	canaan_vo_write(vo, VO_DISP_MIX_LAYER_GLB_EN, 0x7f);
+	canaan_vo_write(vo, VO_DISP_MIX_LAYER_GLB_ALPHA0, 0xffffffff);
+	canaan_vo_write(vo, VO_DISP_MIX_LAYER_GLB_ALPHA1, 0xffffffff);
+	canaan_vo_write(vo, 0x940, 0xffffffff);
+
+	reg = 0 + (1 << 4) + (2 << 8) + (3 << 12);
+	canaan_vo_write(vo, VO_DISP_MIX_SEL, reg);
+
+	reg = 4UL + (5UL << 4) + (6UL << 8) + (7UL << 12) + (8UL << 16) +
+	      (9UL << 20) + (10UL << 24) + (11UL << 28);
+	canaan_vo_write(vo, 0x950, reg);
+
+	canaan_vo_write(vo, VO_DISP_YUV2RGB_CTL, 0x1);
+	canaan_vo_write(vo, VO_DISP_CLUT_CTL, 0x0);
+	canaan_vo_write(vo, VO_DISP_DITH_CTL, 0x1);
+	canaan_vo_write(vo, VO_OSD_RGB2YUV_CTL, 0x11111111);
+	canaan_vo_write(vo, VO_DISP_MIX_LAYER_GLB_EN, 0xff);
+
+	//close vo irq
+	canaan_vo_write(vo, VO_DISP_IRQ0_CTL, 0x0);
+	canaan_vo_write(vo, VO_DISP_IRQ1_CTL, 0x0);
+	canaan_vo_write(vo, VO_DISP_IRQ2_CTL, 0x0);
+
+	for (i = 0; i < 64; i++) {
+		canaan_vo_write(vo, VO_VSCALE_BASE + ((i * 2) << 2),
+				V_Coef[i * 2]);
+		canaan_vo_write(vo, VO_VSCALE_BASE + ((i * 2 + 1) << 2),
+				V_Coef[i * 2 + 1]);
+	}
+
+	// init HSCALE
+	for (i = 0; i < 64; i++) {
+		canaan_vo_write(vo, VO_HSCALE_BASE + ((i * 4) << 2),
+				H_Coef[i * 3]);
+		canaan_vo_write(vo, VO_HSCALE_BASE + ((i * 4 + 1) << 2),
+				H_Coef[i * 3 + 1]);
+		canaan_vo_write(vo, VO_HSCALE_BASE + ((i * 4 + 2) << 2),
+				H_Coef[i * 3 + 2]);
+	}
+
+	// // set vline irq
+	// canaan_vo_set_vtth_intr(vo, 1, 11);
+}
+
+static void canaan_vo_set_timing(struct canaan_vo *vo,
+				 struct drm_display_mode *mode)
+{
+	u32 htotal, hsa, hbp, hact, vsa, vbp, vfp, vact, vtotal;
+	u32 reg = 0;
+
+	htotal = mode->htotal;
+	hsa = mode->hsync_end - mode->hsync_start;
+	hbp = mode->htotal - mode->hsync_end;
+	hact = mode->hdisplay;
+
+	vsa = mode->vsync_end - mode->vsync_start;
+	vbp = mode->vtotal - mode->vsync_end;
+	vact = mode->vdisplay;
+	vfp = mode->vtotal - vsa - vbp - vact;
+	vtotal = mode->vtotal;
+
+	// 0 - 12 start ; 16 - 28 end
+	reg = (0x2 << 16) + 0x1;
+	canaan_vo_write(vo, VO_DISP_HSYNC_CTL, reg);
+
+	reg = (0x6 << 16) + 0x5;
+	canaan_vo_write(vo, VO_DISP_HSYNC1_CTL, reg);
+
+	reg = (0x5 << 16) + 0x1;
+	canaan_vo_write(vo, VO_DISP_HSYNC2_CTL, reg);
+
+	reg = (0x1 << 16) + 0x1;
+	canaan_vo_write(vo, VO_DISP_VSYNC1_CTL, reg);
+
+	reg = (0x1 << 16) + 0x1;
+	canaan_vo_write(vo, VO_DISP_VSYNC2_CTL, reg);
+
+	reg = (5 + hsa + hbp + 1) + (((hact + (5 + hsa + hbp + 1)) - 1) << 16);
+	canaan_vo_write(vo, VO_DISP_XZONE_CTL, reg);
+
+	// set yzone
+	reg = 0;
+	reg = (vbp + 1) + (((vact + (vbp + 1)) - 1) << 16);
+	canaan_vo_write(vo, VO_DISP_YZONE_CTL, reg);
+
+	// set total size
+	reg = 0;
+	reg = (htotal) + ((vtotal) << 16);
+	canaan_vo_write(vo, VO_DISP_TOTAL_SIZE, reg);
+
+	// set draw
+	reg = 0;
+	reg = (hact - 1) + ((vact - 1) << 16) + (0x1 << 15);
+	canaan_vo_write(vo, 0x780, reg); // enalbe remap  0x77f8437
+}
+
+void canaan_vo_enable_crtc(struct canaan_vo *vo,
+			   struct canaan_crtc *canaan_crtc,
+			   struct drm_display_mode *adjusted_mode)
+{
+	canaan_vo_init(vo);
+	// set timing
+	canaan_vo_set_timing(vo, adjusted_mode);
+	// set background
+	canaan_vo_write(vo, VO_DISP_BACKGROUND,
+			0xffffff); // enalbe remap  0x77f8437
+	// enable vo
+	canaan_vo_write(vo, VO_REG_LOAD_CTL, 0x11);
+}
+
+void canaan_vo_disable_crtc(struct canaan_vo *vo,
+			    struct canaan_crtc *canaan_crtc)
+{
+	// canaan_vo_write(vo, VO_REG_LOAD_CTL, 0x0);
+}
+
+void canaan_vo_flush_config(struct canaan_vo *vo)
+{
+	writel(0x11, vo->reg_base + VO_REG_LOAD_CTL);
+}
+
+static const uint32_t video_plane_formats[] = {
+	DRM_FORMAT_NV12,
+	DRM_FORMAT_NV21,
+	DRM_FORMAT_NV16,
+	DRM_FORMAT_NV61,
+};
+
+static const uint32_t osd_plane_formats[] = {
+	DRM_FORMAT_ARGB8888, DRM_FORMAT_ARGB4444, DRM_FORMAT_ARGB1555,
+	DRM_FORMAT_RGB888,   DRM_FORMAT_RGB565,
+};
+
+static struct canaan_plane_config
+	canaan_plane_configurations[CANAAN_PLANE_NUMBER] = {
+		{
+			.id = 0,
+			.name = "video_3",
+			.formats = video_plane_formats,
+			.num_formats = ARRAY_SIZE(video_plane_formats),
+			.plane_type = DRM_PLANE_TYPE_OVERLAY,
+			.plane_offset = VO_LAYER3_OFFSET,
+			.plane_enable_bit = 3,
+			.xctl_reg_offset = VO_DISP_LAYER3_XCTL,
+			.yctl_reg_offset = VO_DISP_LAYER3_YCTL,
+		},
+		{
+			.id = 1,
+			.name = "OSD4",
+			.formats = osd_plane_formats,
+			.num_formats = ARRAY_SIZE(osd_plane_formats),
+			.plane_type = DRM_PLANE_TYPE_PRIMARY,
+			.plane_offset = VO_OSD4_OFFSET,
+			.plane_enable_bit = 8,
+			.xctl_reg_offset = VO_DISP_OSD4_XCTL,
+			.yctl_reg_offset = VO_DISP_OSD4_YCTL,
+		},
+		{
+			.id = 2,
+			.name = "OSD5",
+			.formats = osd_plane_formats,
+			.num_formats = ARRAY_SIZE(osd_plane_formats),
+			.plane_type = DRM_PLANE_TYPE_CURSOR,
+			.plane_offset = VO_OSD5_OFFSET,
+			.plane_enable_bit = 9,
+			.xctl_reg_offset = VO_DISP_OSD5_XCTL,
+			.yctl_reg_offset = VO_DISP_OSD5_YCTL,
+		},
+		{
+			.id = 3,
+			.name = "OSD6",
+			.formats = osd_plane_formats,
+			.num_formats = ARRAY_SIZE(osd_plane_formats),
+			.plane_type = DRM_PLANE_TYPE_OVERLAY,
+			.plane_offset = VO_OSD6_OFFSET,
+			.plane_enable_bit = 10,
+			.xctl_reg_offset = VO_DISP_OSD6_XCTL,
+			.yctl_reg_offset = VO_DISP_OSD6_YCTL,
+		},
+		{
+			.id = 4,
+			.name = "OSD7",
+			.formats = osd_plane_formats,
+			.num_formats = ARRAY_SIZE(osd_plane_formats),
+			.plane_type = DRM_PLANE_TYPE_OVERLAY,
+			.plane_offset = VO_OSD7_OFFSET,
+			.plane_enable_bit = 11,
+			.xctl_reg_offset = VO_DISP_OSD7_XCTL,
+			.yctl_reg_offset = VO_DISP_OSD7_YCTL,
+		},
+	};
+
+static int canaan_vo_bind(struct device *dev, struct device *master, void *data)
+{
+	int i = 0;
+	int ret = 0;
+	struct canaan_vo *vo = NULL;
+	struct drm_device *drm_dev = data;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct resource *res = NULL;
+	struct canaan_plane_config *config;
+	struct device_node *np = dev->of_node;
+	struct drm_plane *primary;
+	struct drm_plane *cursor;
+
+	vo = devm_kzalloc(dev, sizeof(*vo), GFP_KERNEL);
+	vo->dev = dev;
+	vo->drm_dev = drm_dev;
+	dev_set_drvdata(dev, vo);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		DRM_DEV_ERROR(dev, "Failed to get register resource\n");
+		return -ENXIO;
+	}
+
+	vo->reg_base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(vo->reg_base)) {
+		DRM_DEV_ERROR(dev, "Failed to map register resource\n");
+		return PTR_ERR(vo->reg_base);
+	}
+
+	of_property_read_u32(np, "background", &vo->background);
+	of_property_read_u32(np, "vth_line", &vo->vth_line);
+
+	dev_info(vo->dev, "background color is %x\n", vo->background);
+	dev_info(vo->dev, "vth_line line is %x\n", vo->vth_line);
+
+	atomic_set(&vo->vsync_enabled, 0);
+	vo->irq = platform_get_irq(pdev, 0);
+	if (vo->irq < 0) {
+		DRM_DEV_ERROR(dev, "Failed to get vsync irq\n");
+		return vo->irq;
+	}
+
+	ret = devm_request_irq(dev, vo->irq, canaan_vo_irq_handler, 0,
+			       dev_name(dev), vo);
+	if (ret) {
+		DRM_DEV_ERROR(dev, "Failed to request vsync irq\n");
+		return ret;
+	}
+
+	for (i = 0; i < CANAAN_PLANE_NUMBER; i++) {
+		config = &canaan_plane_configurations[i];
+		config->possible_crtcs = 1 << drm_dev->mode_config.num_crtc;
+		vo->canaan_plane[i] = canaan_plane_create(drm_dev, config, vo);
+		if (IS_ERR(vo->canaan_plane[i])) {
+			DRM_DEV_ERROR(dev, "Failed to create canaan_plane\n");
+			return PTR_ERR(vo->canaan_plane[i]);
+		}
+	}
+
+	primary = &vo->canaan_plane[1]->base;
+	cursor = &vo->canaan_plane[2]->base;
+	vo->canaan_crtc = canaan_crtc_create(drm_dev, primary, cursor, vo);
+	if (IS_ERR(vo->canaan_crtc)) {
+		DRM_DEV_ERROR(dev, "Failed to create canaan_crtc\n");
+		return PTR_ERR(vo->canaan_crtc);
+	}
+
+	return 0;
+}
+
+static void canaan_vo_unbind(struct device *dev, struct device *master,
+			     void *data)
+{
+}
+
+static const struct component_ops canaan_vo_component_ops = {
+	.bind = canaan_vo_bind,
+	.unbind = canaan_vo_unbind,
+};
+
+static int canaan_vo_probe(struct platform_device *pdev)
+{
+	dev_info(&pdev->dev, "probe\n");
+	return component_add(&pdev->dev, &canaan_vo_component_ops);
+}
+
+static int canaan_vo_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &canaan_vo_component_ops);
+
+	return 0;
+}
+
+static const struct of_device_id canaan_vo_of_table[] = {
+	{
+		.compatible = "canaan,k230-vo",
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, canaan_vo_of_table);
+
+struct platform_driver canaan_vo_driver = {
+	.probe = canaan_vo_probe,
+	.remove = canaan_vo_remove,
+	.driver = {
+		.name = "canaan-vo",
+		.of_match_table = of_match_ptr(canaan_vo_of_table),
+	},
+};
+
+MODULE_DESCRIPTION("Canaan K230 VO Controller");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/canaan/canaan_vo.h b/drivers/gpu/drm/canaan/canaan_vo.h
new file mode 100644
index 0000000000000..1d723d1ac706d
--- /dev/null
+++ b/drivers/gpu/drm/canaan/canaan_vo.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2022, Canaan Bright Sight Co., Ltd
+ *
+ * All enquiries to https://www.canaan-creative.com/
+ *
+ */
+
+#ifndef __CANAAN_VO_H__
+#define __CANAAN_VO_H__
+
+#define CANAAN_PLANE_NUMBER 5
+
+struct canaan_vo {
+	struct device *dev;
+	struct drm_device *drm_dev;
+
+	void __iomem *reg_base;
+	int irq;
+	atomic_t vsync_enabled;
+
+	struct canaan_crtc *canaan_crtc;
+	struct canaan_plane *canaan_plane[CANAAN_PLANE_NUMBER];
+
+	u32 background;
+	u32 vth_line;
+};
+
+int canaan_vo_check_plane(struct canaan_vo *vo,
+			  struct canaan_plane *canaan_plane,
+			  struct drm_plane_state *plane_state);
+void canaan_vo_update_plane(struct canaan_vo *vo,
+			    struct canaan_plane *canaan_plane,
+			    struct drm_plane_state *plane_state);
+void canaan_vo_disable_plane(struct canaan_vo *vo,
+			     struct canaan_plane *canaan_plane);
+
+int canaan_vo_enable_vblank(struct canaan_vo *vo);
+void canaan_vo_disable_vblank(struct canaan_vo *vo);
+void canaan_vo_enable_crtc(struct canaan_vo *vo,
+			   struct canaan_crtc *canaan_crtc,
+			   struct drm_display_mode *adjusted_mode);
+void canaan_vo_disable_crtc(struct canaan_vo *vo,
+			    struct canaan_crtc *canaan_crtc);
+void canaan_vo_flush_config(struct canaan_vo *vo);
+
+#endif /* __CANAAN_VO_H__ */
diff --git a/drivers/gpu/drm/canaan/canaan_vo_regs.h b/drivers/gpu/drm/canaan/canaan_vo_regs.h
new file mode 100644
index 0000000000000..f10b700d0cb1a
--- /dev/null
+++ b/drivers/gpu/drm/canaan/canaan_vo_regs.h
@@ -0,0 +1,223 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2022, Canaan Bright Sight Co., Ltd
+ *
+ * All enquiries to https://www.canaan-creative.com/
+ *
+ */
+
+#ifndef __CANAAN_VO_REGS_H__
+#define __CANAAN_VO_REGS_H__
+
+#define VO_SOFT_RST_CTL 0x00
+#define VO_REG_LOAD_CTL 0x04
+#define VO_DMA_SW_CTL 0x08
+#define VO_DMA_RD_CTL_OUT 0x0c
+#define VO_DMA_ARB_MODE 0x10
+#define VO_DMA_WEIGHT_RD0 0x24
+#define VO_DMA_WEIGHT_RD1 0x28
+#define VO_DMA_WEIGHT_RD2 0x2c
+#define VO_DMA_WEIGHT_RD3 0x30
+#define VO_DMA_PRIORITY_RD_0 0x3c
+#define VO_DMA_PRIORITY_RD_1 0x40
+#define VO_DMA_ID_RD_0 0x4c
+#define VO_DMA_ID_RD_1 0x50
+
+#define VO_LAYER0_LINE0_BD_CTL 0x80
+#define VO_LAYER0_LINE1_BD_CTL 0x84
+#define VO_LAYER0_LINE2_BD_CTL 0x88
+#define VO_LAYER0_LINE3_BD_CTL 0x8C
+#define VO_LAYER1_BD_CTL 0x90
+#define VO_LAYER2_BD_CTL 0x94
+#define VO_LAYER3_BD_CTL 0x98
+#define VO_OSD0_BD_CTL 0x9c
+#define VO_OSD1_BD_CTL 0xa0
+#define VO_OSD2_BD_CTL 0xa4
+#define VO_OSD3_BD_CTL 0x800
+#define VO_OSD4_BD_CTL 0x804
+#define VO_OSD5_BD_CTL 0x808
+#define VO_OSD6_BD_CTL 0x80c
+#define VO_OSD7_BD_CTL 0x810
+
+#define VO_DISP_IRQ0_CTL 0x3e0
+#define VO_DISP_IRQ1_CTL 0x3e4
+#define VO_DISP_IRQ2_CTL 0x3e8
+#define VO_DISP_IRQ_STATUS 0x3ec
+
+#define VO_DISP_CTL 0x114
+#define VO_DISP_ENABLE 0x118
+
+#define VO_DISP_XZONE_CTL 0x0C0
+#define VO_DISP_YZONE_CTL 0x0C4
+#define VO_DISP_LAYER0_XCTL 0x0C8
+#define VO_DISP_LAYER0_YCTL 0x0CC
+#define VO_DISP_LAYER1_XCTL 0x0D0
+#define VO_DISP_LAYER1_YCTL 0x0D4
+#define VO_DISP_LAYER2_XCTL 0x0D8
+#define VO_DISP_LAYER2_YCTL 0x0DC
+#define VO_DISP_LAYER3_XCTL 0x0E0
+#define VO_DISP_LAYER3_YCTL 0x0E4
+#define VO_DISP_OSD0_XCTL 0x0E8
+#define VO_DISP_OSD0_YCTL 0x0EC
+#define VO_DISP_OSD1_XCTL 0x0F0
+#define VO_DISP_OSD1_YCTL 0x0F4
+#define VO_DISP_OSD2_XCTL 0x0F8
+#define VO_DISP_OSD2_YCTL 0x0FC
+#define VO_DISP_OSD3_XCTL 0x820
+#define VO_DISP_OSD3_YCTL 0x824
+#define VO_DISP_OSD4_XCTL 0x828
+#define VO_DISP_OSD4_YCTL 0x82C
+#define VO_DISP_OSD5_XCTL 0x830
+#define VO_DISP_OSD5_YCTL 0x834
+#define VO_DISP_OSD6_XCTL 0x838
+#define VO_DISP_OSD6_YCTL 0x83C
+#define VO_DISP_OSD7_XCTL 0x840
+#define VO_DISP_OSD7_YCTL 0x844
+
+#define VO_LAYER3_OFFSET 0x240
+#define VO_LAYER3_CTL 0x240
+#define VO_LAYER3_Y_ADDR0 0x244
+#define VO_LAYER3_UV_ADDR0 0x248
+#define VO_LAYER3_Y_ADDR1 0x24C
+#define VO_LAYER3_UV_ADDR1 0x250
+#define VO_LAYER3_IMG_IN_OFFSET 0x254
+#define VO_LAYER3_BLENTH 0x258
+#define VO_LAYER3_STRIDE 0x25C
+#define VO_LAYER3_ACT_SIZE 0x260
+#define VO_LAYER3_ADDR_SEL_MODE 0x264
+
+#define VO_LAYER2_3_CTL_REG_OFFSET 0x00
+#define VO_LAYER2_3_Y_ADDR0_REG_OFFSET 0x04
+#define VO_LAYER2_3_UV_ADDR0_REG_OFFSET 0x08
+#define VO_LAYER2_3_Y_ADDR1_REG_OFFSET 0x0C
+#define VO_LAYER2_3_UV_ADDR1_REG_OFFSET 0x10
+#define VO_LAYER2_3_IMG_IN_OFFSET_REG_OFFSET 0x14
+#define VO_LAYER2_3_BLENTH_REG_OFFSET 0x18
+#define VO_LAYER2_3_STRIDE_REG_OFFSET 0x1C
+#define VO_LAYER2_3_ACT_SIZE_REG_OFFSET 0x20
+#define VO_LAYER2_3_ADDR_SEL_MODE_REG_OFFSET 0x24
+
+#define VO_OSD0_OFFSET 0x280
+#define VO_OSD0_INFO 0x280
+#define VO_OSD0_SIZE 0x284
+#define VO_OSD0_VLU_ADDR0 0x288
+#define VO_OSD0_ALP_ADDR0 0x28C
+#define VO_OSD0_VLU_ADDR1 0x290
+#define VO_OSD0_ALP_ADDR1 0x294
+#define VO_OSD0_DMA_CTRL 0x298
+#define VO_OSD0_STRIDE 0x29C
+#define VO_OSD0_ADDR_SEL_MODE 0x2A0
+
+#define VO_OSD1_OFFSET 0x2C0
+#define VO_OSD1_INFO 0x2C0
+#define VO_OSD1_SIZE 0x2C4
+#define VO_OSD1_VLU_ADDR0 0x2C8
+#define VO_OSD1_ALP_ADDR0 0x2CC
+#define VO_OSD1_VLU_ADDR1 0x2D0
+#define VO_OSD1_ALP_ADDR1 0x2D4
+#define VO_OSD1_DMA_CTRL 0x2D8
+#define VO_OSD1_STRIDE 0x2DC
+#define VO_OSD1_ADDR_SEL_MODE 0x2E0
+
+#define VO_OSD2_OFFSET 0x300
+#define VO_OSD2_INFO 0x300
+#define VO_OSD2_SIZE 0x304
+#define VO_OSD2_VLU_ADDR0 0x308
+#define VO_OSD2_ALP_ADDR0 0x30C
+#define VO_OSD2_VLU_ADDR1 0x310
+#define VO_OSD2_ALP_ADDR1 0x314
+#define VO_OSD2_DMA_CTRL 0x318
+#define VO_OSD2_STRIDE 0x31C
+#define VO_OSD2_ADDR_SEL_MODE 0x320
+
+#define VO_OSD3_OFFSET 0x850
+#define VO_OSD3_INFO 0x850
+#define VO_OSD3_SIZE 0x854
+#define VO_OSD3_VLU_ADDR0 0x858
+#define VO_OSD3_ALP_ADDR0 0x85c
+#define VO_OSD3_VLU_ADDR1 0x860
+#define VO_OSD3_ALP_ADDR1 0x864
+#define VO_OSD3_DMA_CTRL 0x868
+#define VO_OSD3_STRIDE 0x86c
+#define VO_OSD3_ADDR_SEL_MODE 0x870
+
+#define VO_OSD4_OFFSET 0x880
+#define VO_OSD4_INFO 0x880
+#define VO_OSD4_SIZE 0x884
+#define VO_OSD4_VLU_ADDR0 0x888
+#define VO_OSD4_ALP_ADDR0 0x88c
+#define VO_OSD4_VLU_ADDR1 0x890
+#define VO_OSD4_ALP_ADDR1 0x894
+#define VO_OSD4_DMA_CTRL 0x898
+#define VO_OSD4_STRIDE 0x89c
+#define VO_OSD4_ADDR_SEL_MODE 0x8a0
+
+#define VO_OSD5_OFFSET 0x8b0
+#define VO_OSD5_INFO 0x8b0
+#define VO_OSD5_SIZE 0x8b4
+#define VO_OSD5_VLU_ADDR0 0x8b8
+#define VO_OSD5_ALP_ADDR0 0x8bc
+#define VO_OSD5_VLU_ADDR1 0x8c0
+#define VO_OSD5_ALP_ADDR1 0x8c4
+#define VO_OSD5_DMA_CTRL 0x8c8
+#define VO_OSD5_STRIDE 0x8cc
+#define VO_OSD5_ADDR_SEL_MODE 0x8d0
+
+#define VO_OSD6_OFFSET 0x8e0
+#define VO_OSD6_INFO 0x8e0
+#define VO_OSD6_SIZE 0x8e4
+#define VO_OSD6_VLU_ADDR0 0x8e8
+#define VO_OSD6_ALP_ADDR0 0x8ec
+#define VO_OSD6_VLU_ADDR1 0x8f0
+#define VO_OSD6_ALP_ADDR1 0x8f4
+#define VO_OSD6_DMA_CTRL 0x8f8
+#define VO_OSD6_STRIDE 0x8fc
+#define VO_OSD6_ADDR_SEL_MODE 0x900
+
+#define VO_OSD7_OFFSET 0x910
+#define VO_OSD7_INFO 0x910
+#define VO_OSD7_SIZE 0x914
+#define VO_OSD7_VLU_ADDR0 0x918
+#define VO_OSD7_ALP_ADDR0 0x91c
+#define VO_OSD7_VLU_ADDR1 0x920
+#define VO_OSD7_ALP_ADDR1 0x924
+#define VO_OSD7_DMA_CTRL 0x928
+#define VO_OSD7_STRIDE 0x92c
+#define VO_OSD7_ADDR_SEL_MODE 0x930
+
+#define VO_OSD0_7_INFO_REG_OFFSET 0x00
+#define VO_OSD0_7_SIZE_REG_OFFSET 0x04
+#define VO_OSD0_7_VLU_ADDR0_REG_OFFSET 0x08
+#define VO_OSD0_7_ALP_ADDR0_REG_OFFSET 0x0C
+#define VO_OSD0_7_VLU_ADDR1_REG_OFFSET 0x10
+#define VO_OSD0_7_ALP_ADDR1_REG_OFFSET 0x14
+#define VO_OSD0_7_DMA_CTRL_REG_OFFSET 0x18
+#define VO_OSD0_7_STRIDE_REG_OFFSET 0x1C
+#define VO_OSD0_7_ADDR_SEL_MODE_REG_OFFSET 0x20
+
+#define VO_CONFIG_LINE_BASE 0x0600
+#define VO_HSCALE_BASE 0x8000
+#define VO_VSCALE_BASE 0x8C00
+#define VO_GAMMA_BASE 0xC000
+
+#define VO_DISP_BACKGROUND 0x3D0
+#define VO_DISP_MIX_LAYER_GLB_EN 0x3c0
+#define VO_DISP_MIX_LAYER_GLB_ALPHA0 0x3c4
+#define VO_DISP_MIX_LAYER_GLB_ALPHA1 0x3c8
+#define VO_DISP_MIX_SEL 0x3cc
+
+#define VO_DISP_YUV2RGB_CTL 0x380
+#define VO_DISP_CLUT_CTL 0x3d8
+#define VO_DISP_DITH_CTL 0x3d4
+#define VO_OSD_RGB2YUV_CTL 0x340
+
+#define VO_DISP_HSYNC_CTL 0x100
+#define VO_DISP_HSYNC1_CTL 0x104
+#define VO_DISP_VSYNC1_CTL 0x108
+#define VO_DISP_VSYNC2_CTL 0x110
+#define VO_DISP_HSYNC2_CTL 0x10c
+#define VO_DISP_TOTAL_SIZE 0x11C
+#define VO_DISP_XZONE_CTL 0x0C0
+#define VO_DISP_YZONE_CTL 0x0C4
+
+#endif /* __CANAAN_VO_REGS_H__ */
diff --git a/drivers/gpu/drm/canaan/canaan_vo_table.h b/drivers/gpu/drm/canaan/canaan_vo_table.h
new file mode 100644
index 0000000000000..eb44801ba9465
--- /dev/null
+++ b/drivers/gpu/drm/canaan/canaan_vo_table.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2022, Canaan Bright Sight Co., Ltd
+ *
+ * All enquiries to https://www.canaan-creative.com/
+ *
+ */
+
+#ifndef __CANAAN_VO_TABLE_H__
+#define __CANAAN_VO_TABLE_H__
+
+/*
+ * v scale coeff
+ */
+int V_Coef[128] = {
+	0x400000, 0x000000, 0x3ffff8, 0xfff008, 0x3fdff0, 0xfff011, 0x3fafea,
+	0xffe01c, 0x3f6fe3, 0xffe027, 0x3f1fde, 0xffd033, 0x3eafd8, 0xffb040,
+	0x3e3fd3, 0xffa04e, 0x3dbfcf, 0xff905d, 0x3d1fca, 0xff706c, 0x3c7fc7,
+	0xff507c, 0x3bcfc3, 0xff308c, 0x3b0fc0, 0xff109d, 0x3a3fbd, 0xfef0af,
+	0x395fbb, 0xfec0c1, 0x387fb9, 0xfea0d4, 0x378fb8, 0xfe80e8, 0x368fb6,
+	0xfe50fb, 0x357fb5, 0xfe210f, 0x346fb4, 0xfe0124, 0x334fb4, 0xfdd139,
+	0x322fb4, 0xfda14e, 0x30ffb4, 0xfd8163, 0x2fcfb4, 0xfd5179, 0x2e9fb5,
+	0xfd318f, 0x2d4fb5, 0xfd01a4, 0x2c0fb6, 0xfcd1bb, 0x2abfb7, 0xfcb1d1,
+	0x296fb9, 0xfc81e7, 0x281fba, 0xfc61fd, 0x26bfbc, 0xfc4213, 0x255fbe,
+	0xfc2229, 0x240fc0, 0xfc0240, 0x229fc2, 0xfbe255, 0x213fc4, 0xfbc26b,
+	0x1fdfc6, 0xfba281, 0x1e7fc8, 0xfb9296, 0x1d1fcb, 0xfb72ab, 0x1bbfcd,
+	0xfb62c0, 0x1a4fd0, 0xfb52d4, 0x18ffd3, 0xfb52e9, 0x179fd5, 0xfb42fc,
+	0x163fd8, 0xfb430f, 0x14efda, 0xfb4322, 0x139fdd, 0xfb4334, 0x124fe0,
+	0xfb4346, 0x10ffe2, 0xfb5357, 0x0fbfe5, 0xfb6368, 0x0e8fe8, 0xfb8378,
+	0x0d4fea, 0xfb9387, 0x0c1fec, 0xfbb395, 0x0affef, 0xfbd3a3, 0x09dff1,
+	0xfc03b0, 0x08cff3, 0xfc33bc, 0x07cff5, 0xfc73c7, 0x06cff7, 0xfca3d1,
+	0x05dff9, 0xfcf3db, 0x04effa, 0xfd33e3, 0x040ffb, 0xfd83ea, 0x033ffd,
+	0xfde3f1, 0x027ffe, 0xfe33f6, 0x01cffe, 0xfea3fa, 0x011fff, 0xff03fd,
+	0x008fff, 0xff83ff
+};
+
+/*
+ * h scale coeff
+ */
+int H_Coef[192] = {
+	0x00000000, 0x00004000, 0x00000000, 0xf8000000, 0xf0083fff, 0x000000ff,
+	0xf0000000, 0xf0113fdf, 0x000000ff, 0xea000000, 0xe01c3faf, 0x000000ff,
+	0xe3000000, 0xe0273f6f, 0x000000ff, 0xde000000, 0xd0333f1f, 0x000000ff,
+	0xd8000000, 0xb0403eaf, 0x000000ff, 0xd3000000, 0xa04e3e3f, 0x000000ff,
+	0xcf000000, 0x905d3dbf, 0x000000ff, 0xca000000, 0x706c3d1f, 0x000000ff,
+	0xc7000000, 0x507c3c7f, 0x000000ff, 0xc3000000, 0x308c3bcf, 0x000000ff,
+	0xc0000000, 0x109d3b0f, 0x000000ff, 0xbd000000, 0xf0af3a3f, 0x000000fe,
+	0xbb000000, 0xc0c1395f, 0x000000fe, 0xb9000000, 0xa0d4387f, 0x000000fe,
+	0xb8000000, 0x80e8378f, 0x000000fe, 0xb6000000, 0x50fb368f, 0x000000fe,
+	0xb5000000, 0x210f357f, 0x000000fe, 0xb4000000, 0x0124346f, 0x000000fe,
+	0xb4000000, 0xd139334f, 0x000000fd, 0xb4000000, 0xa14e322f, 0x000000fd,
+	0xb4000000, 0x816330ff, 0x000000fd, 0xb4000000, 0x51792fcf, 0x000000fd,
+	0xb5000000, 0x318f2e9f, 0x000000fd, 0xb5000000, 0x01a42d4f, 0x000000fd,
+	0xb6000000, 0xd1bb2c0f, 0x000000fc, 0xb7000000, 0xb1d12abf, 0x000000fc,
+	0xb9000000, 0x81e7296f, 0x000000fc, 0xba000000, 0x61fd281f, 0x000000fc,
+	0xbc000000, 0x421326bf, 0x000000fc, 0xbe000000, 0x2229255f, 0x000000fc,
+	0xc0000000, 0x0240240f, 0x000000fc, 0xc2000000, 0xe255229f, 0x000000fb,
+	0xc4000000, 0xc26b213f, 0x000000fb, 0xc6000000, 0xa2811fdf, 0x000000fb,
+	0xc8000000, 0x92961e7f, 0x000000fb, 0xcb000000, 0x72ab1d1f, 0x000000fb,
+	0xcd000000, 0x62c01bbf, 0x000000fb, 0xd0000000, 0x52d41a4f, 0x000000fb,
+	0xd3000000, 0x52e918ff, 0x000000fb, 0xd5000000, 0x42fc179f, 0x000000fb,
+	0xd8000000, 0x430f163f, 0x000000fb, 0xda000000, 0x432214ef, 0x000000fb,
+	0xdd000000, 0x4334139f, 0x000000fb, 0xe0000000, 0x4346124f, 0x000000fb,
+	0xe2000000, 0x535710ff, 0x000000fb, 0xe5000000, 0x63680fbf, 0x000000fb,
+	0xe8000000, 0x83780e8f, 0x000000fb, 0xea000000, 0x93870d4f, 0x000000fb,
+	0xec000000, 0xb3950c1f, 0x000000fb, 0xef000000, 0xd3a30aff, 0x000000fb,
+	0xf1000000, 0x03b009df, 0x000000fc, 0xf3000000, 0x33bc08cf, 0x000000fc,
+	0xf5000000, 0x73c707cf, 0x000000fc, 0xf7000000, 0xa3d106cf, 0x000000fc,
+	0xf9000000, 0xf3db05df, 0x000000fc, 0xfa000000, 0x33e304ef, 0x000000fd,
+	0xfb000000, 0x83ea040f, 0x000000fd, 0xfd000000, 0xe3f1033f, 0x000000fd,
+	0xfe000000, 0x33f6027f, 0x000000fe, 0xfe000000, 0xa3fa01cf, 0x000000fe,
+	0xff000000, 0x03fd011f, 0x000000ff, 0xff000000, 0x83ff008f, 0x000000ff
+};
+/*
+ * gamma coeff
+ */
+int GammaCoef[256] = {
+	0b00000000, 0b00000001, 0b00000010, 0b00000011, 0b00000100, 0b00000101,
+	0b00000110, 0b00000111, 0b00001000, 0b00001001, 0b00001010, 0b00001011,
+	0b00001100, 0b00001101, 0b00001110, 0b00001111, 0b00010000, 0b00010001,
+	0b00010010, 0b00010011, 0b00010100, 0b00010101, 0b00010110, 0b00010111,
+	0b00011000, 0b00011001, 0b00011010, 0b00011011, 0b00011100, 0b00011101,
+	0b00011110, 0b00011111, 0b00100000, 0b00100001, 0b00100010, 0b00100011,
+	0b00100100, 0b00100101, 0b00100110, 0b00100111, 0b00101000, 0b00101001,
+	0b00101010, 0b00101011, 0b00101100, 0b00101101, 0b00101110, 0b00101111,
+	0b00110000, 0b00110001, 0b00110010, 0b00110011, 0b00110100, 0b00110101,
+	0b00110110, 0b00110111, 0b00111000, 0b00111001, 0b00111010, 0b00111011,
+	0b00111100, 0b00111101, 0b00111110, 0b00111111, 0b01000000, 0b01000001,
+	0b01000010, 0b01000011, 0b01000100, 0b01000101, 0b01000110, 0b01000111,
+	0b01001000, 0b01001001, 0b01001010, 0b01001011, 0b01001100, 0b01001101,
+	0b01001110, 0b01001111, 0b01010000, 0b01010001, 0b01010010, 0b01010011,
+	0b01010100, 0b01010101, 0b01010110, 0b01010111, 0b01011000, 0b01011001,
+	0b01011010, 0b01011011, 0b01011100, 0b01011101, 0b01011110, 0b01011111,
+	0b01100000, 0b01100001, 0b01100010, 0b01100011, 0b01100100, 0b01100101,
+	0b01100110, 0b01100111, 0b01101000, 0b01101001, 0b01101010, 0b01101011,
+	0b01101100, 0b01101101, 0b01101110, 0b01101111, 0b01110000, 0b01110001,
+	0b01110010, 0b01110011, 0b01110100, 0b01110101, 0b01110110, 0b01110111,
+	0b01111000, 0b01111001, 0b01111010, 0b01111011, 0b01111100, 0b01111101,
+	0b01111110, 0b01111111, 0b10000000, 0b10000001, 0b10000010, 0b10000011,
+	0b10000100, 0b10000101, 0b10000110, 0b10000111, 0b10001000, 0b10001001,
+	0b10001010, 0b10001011, 0b10001100, 0b10001101, 0b10001110, 0b10001111,
+	0b10010000, 0b10010001, 0b10010010, 0b10010011, 0b10010100, 0b10010101,
+	0b10010110, 0b10010111, 0b10011000, 0b10011001, 0b10011010, 0b10011011,
+	0b10011100, 0b10011101, 0b10011110, 0b10011111, 0b10100000, 0b10100001,
+	0b10100010, 0b10100011, 0b10100100, 0b10100101, 0b10100110, 0b10100111,
+	0b10101000, 0b10101001, 0b10101010, 0b10101011, 0b10101100, 0b10101101,
+	0b10101110, 0b10101111, 0b10110000, 0b10110001, 0b10110010, 0b10110011,
+	0b10110100, 0b10110101, 0b10110110, 0b10110111, 0b10111000, 0b10111001,
+	0b10111010, 0b10111011, 0b10111100, 0b10111101, 0b10111110, 0b10111111,
+	0b11000000, 0b11000001, 0b11000010, 0b11000011, 0b11000100, 0b11000101,
+	0b11000110, 0b11000111, 0b11001000, 0b11001001, 0b11001010, 0b11001011,
+	0b11001100, 0b11001101, 0b11001110, 0b11001111, 0b11010000, 0b11010001,
+	0b11010010, 0b11010011, 0b11010100, 0b11010101, 0b11010110, 0b11010111,
+	0b11011000, 0b11011001, 0b11011010, 0b11011011, 0b11011100, 0b11011101,
+	0b11011110, 0b11011111, 0b11100000, 0b11100001, 0b11100010, 0b11100011,
+	0b11100100, 0b11100101, 0b11100110, 0b11100111, 0b11101000, 0b11101001,
+	0b11101010, 0b11101011, 0b11101100, 0b11101101, 0b11101110, 0b11101111,
+	0b11110000, 0b11110001, 0b11110010, 0b11110011, 0b11110100, 0b11110101,
+	0b11110110, 0b11110111, 0b11111000, 0b11111001, 0b11111010, 0b11111011,
+	0b11111100, 0b11111101, 0b11111110, 0b11111111
+};
+
+#endif /* __CANAAN_TABLE_H__ */
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 3a2f4a9f1d466..6daa8f80aaf84 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -835,4 +835,16 @@ config DRM_PANEL_XINPENG_XPP055C272
 	  Say Y here if you want to enable support for the Xinpeng
 	  XPP055C272 controller for 720x1280 LCD panels with MIPI/RGB/SPI
 	  system interfaces.
+
+config DRM_PANEL_CANAAN_UNIVERSAL
+	tristate "Canaan universal panel driver"
+	default ARCH_CANAAN
+	depends on OF
+	depends on DRM_MIPI_DSI
+	depends on BACKLIGHT_CLASS_DEVICE
+	help
+	Say Y here if you want to enable support for the Canaan K230
+	  universal panel controller with MIPI DSI system interfaces.
+	  See Documents/devicetree/bindings/display/panel/canaan,universal.yaml
+	  for detail.
 endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 433e93d57949c..4dd8d83895c34 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -85,3 +85,4 @@ obj-$(CONFIG_DRM_PANEL_VISIONOX_VTDR6130) += panel-visionox-vtdr6130.o
 obj-$(CONFIG_DRM_PANEL_VISIONOX_R66451) += panel-visionox-r66451.o
 obj-$(CONFIG_DRM_PANEL_WIDECHIPS_WS2401) += panel-widechips-ws2401.o
 obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o
+obj-$(CONFIG_DRM_PANEL_CANAAN_UNIVERSAL) += panel-canaan-universal.o
diff --git a/drivers/gpu/drm/panel/panel-canaan-universal.c b/drivers/gpu/drm/panel/panel-canaan-universal.c
new file mode 100644
index 0000000000000..0043714a1b021
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-canaan-universal.c
@@ -0,0 +1,395 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022, Canaan Bright Sight Co., Ltd
+ *
+ * All enquiries to https://www.canaan-creative.com/
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
+
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+
+#include <video/mipi_display.h>
+#include <video/of_videomode.h>
+#include <video/videomode.h>
+
+struct canaan_panel_instr {
+	char cmd;
+	char data;
+};
+
+struct canaan_panel_desc {
+	const struct canaan_panel_instr *init;
+	const size_t init_length;
+	//const struct drm_display_mode *mode;
+};
+
+struct panel_cmd_header {
+	u8 data_type;
+	u8 delay;
+	u8 payload_length;
+} __packed;
+
+struct panel_cmd_desc {
+	struct panel_cmd_header header;
+	u8 *payload;
+};
+
+struct panel_cmd_seq {
+	struct panel_cmd_desc *cmds;
+	unsigned int cmd_cnt;
+};
+
+struct canaan_panel {
+	struct drm_panel panel;
+	struct mipi_dsi_device *dsi;
+	const struct canaan_panel_desc *desc;
+
+	struct regulator *power;
+	struct gpio_desc *reset;
+	struct gpio_desc *power_on;
+	struct videomode vm;
+	u32 width_mm;
+	u32 height_mm;
+	u32 lan_num;
+	u32 init_set_v1_flag;
+
+	struct panel_cmd_seq *init_seq_v1;
+};
+
+static inline struct canaan_panel *
+panel_to_canaan_panel(struct drm_panel *panel)
+{
+	return container_of(panel, struct canaan_panel, panel);
+}
+
+static void panel_simple_sleep(unsigned int msec)
+{
+	if (msec > 20)
+		msleep(msec);
+	else
+		usleep_range(msec * 1000, (msec + 1) * 1000);
+}
+
+static int panel_simple_xfer_dsi_cmd_seq(struct canaan_panel *panel,
+					 struct panel_cmd_seq *seq)
+{
+	struct device *dev = panel->panel.dev;
+	struct mipi_dsi_device *dsi = panel->dsi;
+	unsigned int i;
+	int err;
+
+	if (!seq)
+		return -EINVAL;
+
+	for (i = 0; i < seq->cmd_cnt; i++) {
+		struct panel_cmd_desc *cmd = &seq->cmds[i];
+
+		switch (cmd->header.data_type) {
+		case MIPI_DSI_DCS_SHORT_WRITE:
+		case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
+			err = mipi_dsi_dcs_write_buffer(
+				dsi, cmd->payload, cmd->header.payload_length);
+			break;
+		case MIPI_DSI_DCS_LONG_WRITE:
+			err = mipi_dsi_dcs_write_buffer(
+				dsi, cmd->payload, cmd->header.payload_length);
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		if (err < 0)
+			dev_err(dev, "failed to write dcs cmd: %d\n", err);
+
+		if (cmd->header.delay)
+			panel_simple_sleep(cmd->header.delay);
+	}
+	return 0;
+}
+
+static int canaan_panel_prepare(struct drm_panel *panel)
+{
+	struct canaan_panel *p = panel_to_canaan_panel(panel);
+
+	// set power on
+	if (!IS_ERR(p->power_on)) {
+		// gpiod_direction_output(p->power_on, 1);
+		// gpiod_set_value_cansleep(p->power_on, 1);
+	}
+	// set rst
+	if (!IS_ERR(p->reset)) {
+		// gpiod_direction_output(p->reset, 1);
+
+		// gpiod_set_value_cansleep(p->reset, 1);
+		// panel_simple_sleep(200);
+		// gpiod_set_value_cansleep(p->reset, 0);
+		// panel_simple_sleep(200);
+		// gpiod_set_value_cansleep(p->reset, 1);
+		// panel_simple_sleep(200);
+	}
+
+	if (p->init_set_v1_flag) {
+		// config screen
+		panel_simple_xfer_dsi_cmd_seq(p, p->init_seq_v1);
+	}
+	return 0;
+}
+
+static int canaan_panel_enable(struct drm_panel *panel)
+{
+	return 0;
+}
+
+static int canaan_panel_disable(struct drm_panel *panel)
+{
+	return 0;
+}
+
+static int canaan_panel_unprepare(struct drm_panel *panel)
+{
+	struct canaan_panel *p = panel_to_canaan_panel(panel);
+	// int err = 0;
+
+	if (p->power_on)
+		gpiod_set_value_cansleep(p->power_on, 0);
+	if (p->reset)
+		gpiod_set_value_cansleep(p->reset, 0);
+
+	panel_simple_sleep(500);
+
+	return 0;
+}
+
+static int canaan_panel_get_modes(struct drm_panel *panel,
+				  struct drm_connector *connector)
+{
+	struct canaan_panel *ctx = panel_to_canaan_panel(panel);
+	struct drm_display_mode *mode;
+
+	mode = drm_mode_create(connector->dev);
+	if (!mode) {
+		dev_err(panel->dev, "failed to create a new display mode\n");
+		return 0;
+	}
+
+	drm_display_mode_from_videomode(&ctx->vm, mode);
+	mode->width_mm = ctx->width_mm;
+	mode->height_mm = ctx->height_mm;
+	connector->display_info.width_mm = mode->width_mm;
+	connector->display_info.height_mm = mode->height_mm;
+
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_probed_add(connector, mode);
+
+	return 1;
+}
+
+static const struct drm_panel_funcs canaan_panel_funcs = {
+	.prepare = canaan_panel_prepare,
+	.unprepare = canaan_panel_unprepare,
+	.enable = canaan_panel_enable,
+	.disable = canaan_panel_disable,
+	.get_modes = canaan_panel_get_modes,
+};
+
+static int panel_simple_parse_cmd_seq(struct device *dev, const u8 *data,
+				      int length, struct panel_cmd_seq *seq)
+{
+	struct panel_cmd_header *header;
+	struct panel_cmd_desc *desc;
+	char *buf, *d;
+	unsigned int i, cnt, len;
+
+	if (!seq)
+		return -EINVAL;
+
+	buf = devm_kmemdup(dev, data, length, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	d = buf;
+	len = length;
+	cnt = 0;
+	while (len > sizeof(*header)) {
+		header = (struct panel_cmd_header *)d;
+
+		d += sizeof(*header);
+		len -= sizeof(*header);
+
+		if (header->payload_length > len)
+			return -EINVAL;
+
+		d += header->payload_length;
+		len -= header->payload_length;
+		cnt++;
+	}
+
+	if (len)
+		return -EINVAL;
+
+	seq->cmd_cnt = cnt;
+	seq->cmds = devm_kcalloc(dev, cnt, sizeof(*desc), GFP_KERNEL);
+	if (!seq->cmds)
+		return -ENOMEM;
+
+	d = buf;
+	len = length;
+	for (i = 0; i < cnt; i++) {
+		header = (struct panel_cmd_header *)d;
+		len -= sizeof(*header);
+		d += sizeof(*header);
+
+		desc = &seq->cmds[i];
+		desc->header = *header;
+		desc->payload = d;
+
+		d += header->payload_length;
+		len -= header->payload_length;
+	}
+
+	return 0;
+}
+
+static int canaan_panel_parse_dt(struct canaan_panel *ctx)
+{
+	struct device *dev = &ctx->dsi->dev;
+	struct device_node *np = dev->of_node;
+	const void *data;
+	int ret, err;
+	int len;
+
+	// get display timing
+	ret = of_get_videomode(np, &ctx->vm, 0);
+	if (ret < 0)
+		return ret;
+
+	// get width && heidth
+	of_property_read_u32(np, "panel-width-mm", &ctx->width_mm);
+	of_property_read_u32(np, "panel-height-mm", &ctx->height_mm);
+	of_property_read_u32(np, "panel-dsi-lane", &ctx->lan_num);
+
+	// get screen data
+	data = of_get_property(np, "panel-init-sequence", &len);
+	if (data) {
+		ctx->init_seq_v1 = devm_kzalloc(dev, sizeof(*ctx->init_seq_v1),
+						GFP_KERNEL);
+		if (!ctx->init_seq_v1)
+			return -ENOMEM;
+
+		err = panel_simple_parse_cmd_seq(dev, data, len,
+						 ctx->init_seq_v1);
+		if (err) {
+			dev_err(dev, "failed to parse init sequence v1\n");
+			return err;
+		}
+		ctx->init_set_v1_flag = 1;
+	}
+
+	return 0;
+}
+
+static int canaan_panel_dsi_probe(struct mipi_dsi_device *dsi)
+{
+	struct canaan_panel *ctx;
+	int ret;
+
+	ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+
+	ctx->init_set_v1_flag = 0;
+
+	mipi_dsi_set_drvdata(dsi, ctx);
+
+	ctx->reset = devm_gpiod_get(&dsi->dev, "dsi_reset", GPIOD_OUT_LOW);
+	if (IS_ERR(ctx->reset)) {
+		dev_err(&dsi->dev, "Couldn't get our reset GPIO, error: %ld\n",
+			PTR_ERR(ctx->reset));
+		// return PTR_ERR(ctx->reset);
+	} else {
+		gpiod_direction_output(ctx->reset, 1);
+		panel_simple_sleep(200);
+		gpiod_set_value_cansleep(ctx->reset, 0);
+		panel_simple_sleep(200);
+		gpiod_set_value_cansleep(ctx->reset, 1);
+	}
+
+	ctx->power_on =
+		devm_gpiod_get(&dsi->dev, "backlight_gpio", GPIOD_OUT_LOW);
+	if (IS_ERR(ctx->power_on)) {
+		dev_err(&dsi->dev,
+			"Couldn't get our backlight_gpio GPIO, error: %ld\n",
+			PTR_ERR(ctx->power_on));
+		// return PTR_ERR(ctx->power_on);
+	} else {
+		gpiod_direction_output(ctx->power_on, 1);
+	}
+
+	ctx->dsi = dsi;
+	ctx->desc = of_device_get_match_data(&dsi->dev);
+
+	ret = canaan_panel_parse_dt(ctx);
+	if (ret < 0)
+		return ret;
+
+	// Panel Device Tree Read..
+
+	dsi->mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+	dsi->format = MIPI_DSI_FMT_RGB888;
+	dsi->lanes = ctx->lan_num;
+
+	drm_panel_init(&ctx->panel, &dsi->dev, &canaan_panel_funcs,
+		       DRM_MODE_CONNECTOR_DSI);
+
+	drm_panel_add(&ctx->panel);
+
+	ret = mipi_dsi_attach(dsi);
+	if (ret)
+		drm_panel_remove(&ctx->panel);
+
+	return ret;
+}
+
+static void canaan_panel_dsi_remove(struct mipi_dsi_device *dsi)
+{
+	struct canaan_panel *ctx = mipi_dsi_get_drvdata(dsi);
+
+	mipi_dsi_detach(dsi);
+	drm_panel_remove(&ctx->panel);
+}
+
+static const struct of_device_id canaan_panel_of_match[] = {
+	{
+		.compatible = "canaan,universal",
+	},
+	{}
+};
+MODULE_DEVICE_TABLE(of, canaan_panel_of_match);
+
+static struct mipi_dsi_driver canaan_panel_driver = {
+	.probe		= canaan_panel_dsi_probe,
+	.remove		= canaan_panel_dsi_remove,
+	.driver = {
+		.name		= "canaan-panel-dsi",
+		.of_match_table	= canaan_panel_of_match,
+	},
+};
+module_mipi_dsi_driver(canaan_panel_driver);
+
+MODULE_AUTHOR("");
+MODULE_DESCRIPTION("Canaan K230 Panel Driver");
+MODULE_LICENSE("GPL");