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chap3-elf32abi.sgml
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<!-- Author(s): See <authorgroup> in book-elfabi.sgml -->
<!-- Copyright (c) 2011, 2012, Power.org -->
<!-- Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3; with
no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
Texts. A copy of the license is available in the COPYING.txt file. -->
<chapter id="LOW-LEVEL"><title>Low Level System Information</title>
<para></para>
<sect1 id="MACHINE"><title>Machine Interface</title>
<para></para>
<sect2 id="PROCESSOR"><title>Processor Architecture</title>
<para>This Application Binary Interface (ABI) is not explicitly predicated on a minimum Power ISA version.</para>
<para>All nonoptional instructions that are defined by the <trademark class="REGISTERED">Power Architecture</trademark>
can be assumed to be implemented and work as specified. ABI conforming implementations
must provide these instructions through software emulation if they are not provided by the
processor.</para>
<note><title>note</title><para>Note: The exceptions to this rule are the <emphasis>Fixed-point Load and Store Multiple</emphasis> and
<emphasis>Fixed-point Move Assist</emphasis> instructions which are not available in little-endian implementations because they
would cause alignment exceptions.</para></note>
<para>Processors may support additional instructions beyond the published Instruction Set
Architecture (ISA) and the Power Architecture optional ones, through <emphasis>Auxiliary
Processing Units</emphasis> (APUs). This ABI provides a method for describing the additional
instructions in section information (see <emphasis><xref linkend="SPECIAL-SECTIONS"></emphasis>
and <emphasis><xref linkend="APU-INFORMATION-SECTION"></emphasis>) but does not address these
additional instructions directly and executing them may result in undefined behavior.</para>
<para>This ABI does not explicitly impose any performance constraints on systems.</para>
</sect2>
<sect2 id="DATA-REP"><title>Data Representation</title>
<sect3 id="BYTEORDER"><title>Byte Ordering</title>
<para>The following standard data formats are recognized:</para>
<itemizedlist>
<listitem>
<para> 8-bit byte</para>
</listitem>
<listitem>
<para> 16-bit halfword</para>
</listitem>
<listitem>
<para> 32-bit word</para>
</listitem>
<listitem>
<para> 64-bit doubleword</para>
</listitem>
<listitem>
<para> 128-bit quadword</para>
</listitem>
</itemizedlist>
<para>In big-endian byte ordering, the most significant byte is
located in the lowest addressed byte position in memory (byte 0).
This byte ordering is alternately referred to as <emphasis>Most Significant Byte</emphasis> (MSB)
ordering.</para>
<para>In little-endian byte ordering, the least significant byte is
located in the lowest addressed byte position in memory (byte 0). This byte ordering
is alternately referred to as <emphasis>Least Significant Byte</emphasis> (LSB)
ordering.</para>
<para> A specific processor implementation must state which type of byte ordering is
to be used.</para>
<note CONDITION="ATR-SPE || ATR-EABI">
<title>Note</title>
<para>Although it is possible on some processors to map some pages as little-endian, and other pages
as big-endian in the same application, such an application does not conform to
the ABI.</para>
</note>
<para><emphasis><xref linkend="BIT-AND-BYTE-IN-HALFWORDS"></emphasis>, <emphasis><xref
linkend="BIT-AND-BYTE-IN-WORDS">, </emphasis><emphasis><xref
linkend="BIT-AND-BYTE-IN-DOUBLEWORDS"></emphasis>, and <emphasis><xref
linkend="BIT-AND-BYTE-IN-QUADWORDS"></emphasis> show the conventions being assumed in big-endian
and little-endian byte ordering at the bit and byte levels. These conventions are applied to
integer and floating-point data types. Byte numbers are indicated in the upper corners, and bit
numbers in the lower corners. Little-endian byte numbers are indicated on the right side;
big-endian byte numbers are indicated on the left side.</para>
<table id="BIT-AND-BYTE-IN-HALFWORDS" frame="all"><title>Bit and Byte Numbering in Halfwords</title>
<tgroup cols='4' colsep='0' rowsep='0'>
<colspec colwidth="25" colname='c1' align="left">
<colspec colwidth="25" colname='c2' align="right" colsep='1'>
<colspec colwidth="25" colname='c3' align="left">
<colspec colwidth="25" colname='c4' align="right">
<tbody>
<row>
<entry namest="c1">0</entry>
<entry namest="c2">1</entry>
<entry namest="c3">1</entry>
<entry namest="c4">0</entry>
</row>
<row>
<entry namest="c1" nameend="c2" align="center" colsep='1'>msb</entry>
<entry namest="c3" nameend="c4" align="center">lsb</entry>
</row>
<row>
<entry namest="c1">0</entry>
<entry namest="c2">7</entry>
<entry namest="c3">8</entry>
<entry namest="c4">15</entry>
</row>
</tbody>
</tgroup>
</table>
<table id="BIT-AND-BYTE-IN-WORDS" frame="all"><title>Bit and Byte Numbering in Words</title>
<tgroup cols='8' colsep='0' rowsep='0'>
<colspec colwidth="25" colname='c1' align="left">
<colspec colwidth="25" colname='c2' align="right" colsep='1'>
<colspec colwidth="25" colname='c3' align="left">
<colspec colwidth="25" colname='c4' align="right" colsep='1'>
<colspec colwidth="25" colname='c5' align="left">
<colspec colwidth="25" colname='c6' align="right" colsep='1'>
<colspec colwidth="25" colname='c7' align="left">
<colspec colwidth="25" colname='c8' align="right">
<tbody>
<row>
<entry namest="c1">0</entry>
<entry namest="c2">3</entry>
<entry namest="c3">1</entry>
<entry namest="c4">2</entry>
<entry namest="c5">2</entry>
<entry namest="c6">1</entry>
<entry namest="c7">3</entry>
<entry namest="c8">0</entry>
</row>
<row>
<entry namest="c1" nameend="c2" align="center" colsep='1'>msb</entry>
<entry namest="c3" nameend="c4" align="center" colsep='1'></entry>
<entry namest="c5" nameend="c6" align="center" colsep='1'></entry>
<entry namest="c7" nameend="c8" align="center">lsb</entry>
</row>
<row>
<entry namest="c1">0</entry>
<entry namest="c2">7</entry>
<entry namest="c3">8</entry>
<entry namest="c4">15</entry>
<entry namest="c5">16</entry>
<entry namest="c6">23</entry>
<entry namest="c7">24</entry>
<entry namest="c8">31</entry>
</row>
</tbody>
</tgroup>
</table>
<table id="BIT-AND-BYTE-IN-DOUBLEWORDS" frame="all"><title>Bit and Byte Numbering in Doublewords</title>
<tgroup cols='8' colsep='0' rowsep='0'>
<colspec colwidth="25" colname='c1' align="left">
<colspec colwidth="25" colname='c2' align="right" colsep='1'>
<colspec colwidth="25" colname='c3' align="left">
<colspec colwidth="25" colname='c4' align="right" colsep='1'>
<colspec colwidth="25" colname='c5' align="left">
<colspec colwidth="25" colname='c6' align="right" colsep='1'>
<colspec colwidth="25" colname='c7' align="left">
<colspec colwidth="25" colname='c8' align="right">
<tbody>
<row>
<entry namest="c1">0</entry>
<entry namest="c2">7</entry>
<entry namest="c3">1</entry>
<entry namest="c4">6</entry>
<entry namest="c5">2</entry>
<entry namest="c6">5</entry>
<entry namest="c7">3</entry>
<entry namest="c8">4</entry>
</row>
<row>
<entry namest="c1" nameend="c2" align="center" colsep='1'>msb</entry>
<entry namest="c3" nameend="c4" align="center" colsep='1'></entry>
<entry namest="c5" nameend="c6" align="center" colsep='1'></entry>
<entry namest="c7" nameend="c8" align="center"></entry>
</row>
<row rowsep='1'>
<entry namest="c1">0</entry>
<entry namest="c2">7</entry>
<entry namest="c3">8</entry>
<entry namest="c4">15</entry>
<entry namest="c5">16</entry>
<entry namest="c6">23</entry>
<entry namest="c7">24</entry>
<entry namest="c8">31</entry>
</row>
<row>
<entry namest="c1">4</entry>
<entry namest="c2">3</entry>
<entry namest="c3">5</entry>
<entry namest="c4">2</entry>
<entry namest="c5">6</entry>
<entry namest="c6">1</entry>
<entry namest="c7">7</entry>
<entry namest="c8">0</entry>
</row>
<row>
<entry namest="c1" nameend="c2" align="center" colsep='1'></entry>
<entry namest="c3" nameend="c4" align="center" colsep='1'></entry>
<entry namest="c5" nameend="c6" align="center" colsep='1'></entry>
<entry namest="c7" nameend="c8" align="center">lsb</entry>
</row>
<row>
<entry namest="c1">32</entry>
<entry namest="c2">39</entry>
<entry namest="c3">40</entry>
<entry namest="c4">47</entry>
<entry namest="c5">48</entry>
<entry namest="c6">55</entry>
<entry namest="c7">56</entry>
<entry namest="c8">63</entry>
</row>
</tbody>
</tgroup>
</table>
<table id="BIT-AND-BYTE-IN-QUADWORDS" frame="all"><title>Bit and Byte Numbering in Quadwords</title>
<tgroup cols='8' colsep='0' rowsep='0'>
<colspec colwidth="25" colname='c1' align="left">
<colspec colwidth="25" colname='c2' align="right" colsep='1'>
<colspec colwidth="25" colname='c3' align="left">
<colspec colwidth="25" colname='c4' align="right" colsep='1'>
<colspec colwidth="25" colname='c5' align="left">
<colspec colwidth="25" colname='c6' align="right" colsep='1'>
<colspec colwidth="25" colname='c7' align="left">
<colspec colwidth="25" colname='c8' align="right">
<tbody>
<row>
<entry namest="c1">0</entry>
<entry namest="c2">15</entry>
<entry namest="c3">1</entry>
<entry namest="c4">14</entry>
<entry namest="c5">2</entry>
<entry namest="c6">13</entry>
<entry namest="c7">3</entry>
<entry namest="c8">12</entry>
</row>
<row>
<entry namest="c1" nameend="c2" align="center" colsep='1'>msb</entry>
<entry namest="c3" nameend="c4" align="center" colsep='1'></entry>
<entry namest="c5" nameend="c6" align="center" colsep='1'></entry>
<entry namest="c7" nameend="c8" align="center"></entry>
</row>
<row rowsep='1'>
<entry namest="c1">0</entry>
<entry namest="c2">7</entry>
<entry namest="c3">8</entry>
<entry namest="c4">15</entry>
<entry namest="c5">16</entry>
<entry namest="c6">23</entry>
<entry namest="c7">24</entry>
<entry namest="c8">31</entry>
</row>
<row>
<entry namest="c1">4</entry>
<entry namest="c2">11</entry>
<entry namest="c3">5</entry>
<entry namest="c4">10</entry>
<entry namest="c5">6</entry>
<entry namest="c6">9</entry>
<entry namest="c7">7</entry>
<entry namest="c8">8</entry>
</row>
<row>
<entry namest="c1" nameend="c2" align="center" colsep='1'></entry>
<entry namest="c3" nameend="c4" align="center" colsep='1'></entry>
<entry namest="c5" nameend="c6" align="center" colsep='1'></entry>
<entry namest="c7" nameend="c8" align="center"></entry>
</row>
<row rowsep='1'>
<entry namest="c1">32</entry>
<entry namest="c2">39</entry>
<entry namest="c3">40</entry>
<entry namest="c4">47</entry>
<entry namest="c5">48</entry>
<entry namest="c6">55</entry>
<entry namest="c7">56</entry>
<entry namest="c8">63</entry>
</row>
<row>
<entry namest="c1">8</entry>
<entry namest="c2">7</entry>
<entry namest="c3">9</entry>
<entry namest="c4">6</entry>
<entry namest="c5">10</entry>
<entry namest="c6">5</entry>
<entry namest="c7">11</entry>
<entry namest="c8">4</entry>
</row>
<row>
<entry namest="c1" nameend="c2" align="center" colsep='1'></entry>
<entry namest="c3" nameend="c4" align="center" colsep='1'></entry>
<entry namest="c5" nameend="c6" align="center" colsep='1'></entry>
<entry namest="c7" nameend="c8" align="center"></entry>
</row>
<row rowsep='1'>
<entry namest="c1">64</entry>
<entry namest="c2">71</entry>
<entry namest="c3">72</entry>
<entry namest="c4">79</entry>
<entry namest="c5">80</entry>
<entry namest="c6">87</entry>
<entry namest="c7">88</entry>
<entry namest="c8">95</entry>
</row>
<row>
<entry namest="c1">12</entry>
<entry namest="c2">3</entry>
<entry namest="c3">13</entry>
<entry namest="c4">2</entry>
<entry namest="c5">14</entry>
<entry namest="c6">1</entry>
<entry namest="c7">15</entry>
<entry namest="c8">0</entry>
</row>
<row>
<entry namest="c1" nameend="c2" align="center" colsep='1'></entry>
<entry namest="c3" nameend="c4" align="center" colsep='1'></entry>
<entry namest="c5" nameend="c6" align="center" colsep='1'></entry>
<entry namest="c7" nameend="c8" align="center">lsb</entry>
</row>
<row>
<entry namest="c1">96</entry>
<entry namest="c2">103</entry>
<entry namest="c3">104</entry>
<entry namest="c4">111</entry>
<entry namest="c5">112</entry>
<entry namest="c6">119</entry>
<entry namest="c7">120</entry>
<entry namest="c8">127</entry>
</row>
</tbody>
</tgroup>
</table>
<note>
<title>Note</title>
<para>Note: In the Power ISA,
the figures are generally only shown in big-endian byte order. The
bits in these data format specification are numbered from left to
right (MSB to LSB).</para>
</note>
<note CONDITION="ATR-SPE">
<title>Note</title>
<para>Note: SPE documentation uses 64-bit numbering throughout,
including for registers such as the CR that only contain 32 bits. This numbering
can lead to some confusion. For example, although the CR bits are now
numbered from 32 to 63, the same assembly instructions still work:
<varname>crxor 6,6,6</varname> operates on bit 32 + 6, that is, CR[38]. When discussing
register contents, the bits are numbered 0 : 63 for 64-bit registers
and 32 : 63 for 32-bit registers. When discussing memory contents, the
bits are numbered naturally (for example, 0 : 7 for bits within one
byte and 0 : 15 for bits within halfwords).</para>
</note>
<para>The bit numbering in the Power ISA is all 64-bit except for the following registers indicated in Power ISA section 1.4:</para>
<itemizedlist>
<listitem>
<para>Opcodes marking 0-31</para>
</listitem>
<listitem CONDITION="ATR-VECTOR">
<para>Vector registers and the VSCR (see <emphasis><xref linkend="REG"></emphasis>).</para>
</listitem>
<listitem CONDITION="ATR-CLASSIC-FLOAT">
<para>As of Power ISA version 2.05 the FPSCR has been extended from 32-bits to 64-bits.
The fields of the original 32-bit FPSCR are now held in bits 32-63 of the 64-bit
FPSCR. The assembly instructions which operate upon the 64-bit FPSCR have
either had a <emphasis>W Instruction Field</emphasis> added to select the
operative word for the instruction, e.g., <varname>mtfsfi</varname>, or the
instruction has been extended to operate upon the entire 64-bit FPSCR, e.g.,
<varname>mffs</varname>. Reference to fields of the FPSCR, representing 1 or
more bits, is done by field number with an indication of the operative word
rather than by bit-number.</para> <para>If the Power ISA version 2.05 DFP category is
not needed by an implementation the FPSCR may continue to be referenced as a
32-bit register using the old forms of the instructions to support binary
compatibility of ELF files built against an older Power ISA version. See <emphasis><xref linkend="REG"></emphasis> for more information on the
FPSCR.</para>
</listitem>
</itemizedlist>
</sect3>
<sect3 id="FUNDAMENTAL-TYPES"><title>Fundamental Types</title>
<para>The following tables map the data format specifications described
in the Power ISA to ISO C scalar types. Each scalar type has a
required alignment, which is indicated in the alignment column. Usage
of these types in data structures must follow the alignment specified in
the order encountered to ensure consistent mapping. When using variables
individually, more strict alignment may be imposed if it has
optimization benefits.</para>
<table id="FUNDAMENTAL-TYPES-TABLE" frame="none"><title>Fundamental Types</title>
<tgroup cols='5' colsep='0' rowsep='0'>
<colspec colwidth='60' colname='c1' align="left">
<colspec colwidth='95' colname='c2' align="left">
<colspec colwidth='40' colname='c3' align="left">
<colspec colwidth='60' colname='c4' align="left">
<colspec colwidth='130' colname='c5' align="left">
<thead>
<row rowsep="1">
<entry namest="c1" rowsep='1'>Type</entry>
<entry namest="c2" rowsep='1'>ISO C Types</entry>
<entry namest="c3" rowsep='1'>sizeof</entry>
<entry namest="c4" rowsep='1'>Alignment</entry>
<entry namest="c5" rowsep='1'>Description</entry>
</row>
</thead>
<tbody>
<row>
<entry namest="c1" rowsep='1'>Boolean</entry>
<entry namest="c2" rowsep='1'>_Bool</entry>
<entry namest="c3" rowsep='1'>1</entry>
<entry namest="c4" rowsep='1'>byte</entry>
<entry namest="c5" rowsep='1'>boolean</entry>
</row>
<row>
<entry namest="c1" rowsep='0'>Character</entry>
<entry namest="c2" rowsep='0'>char</entry>
<entry namest="c3" rowsep='0'>1</entry>
<entry namest="c4" rowsep='0'>byte</entry>
<entry namest="c5" rowsep='0'>unsigned byte</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>unsigned char</entry>
<entry namest="c3" rowsep='1'></entry>
<entry namest="c4" rowsep='1'></entry>
<entry namest="c5" rowsep='1'></entry>
</row>
<row>
<entry namest="c2" rowsep='1'>signed char</entry>
<entry namest="c3" rowsep='1'>1</entry>
<entry namest="c4" rowsep='1'>byte</entry>
<entry namest="c5" rowsep='1'>signed byte</entry>
</row>
<row>
<entry namest="c2" rowsep='0'>short</entry>
<entry namest="c3" rowsep='0'>2</entry>
<entry namest="c4" rowsep='0'>halfword</entry>
<entry namest="c5" rowsep='0'>signed halfword</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>signed short</entry>
<entry namest="c3" rowsep='1'></entry>
<entry namest="c4" rowsep='1'></entry>
<entry namest="c5" rowsep='1'></entry>
</row>
<row>
<entry namest="c1" rowsep='1'></entry>
<entry namest="c2" rowsep='1'>unsigned short</entry>
<entry namest="c3" rowsep='1'>2</entry>
<entry namest="c4" rowsep='1'>halfword</entry>
<entry namest="c5" rowsep='1'>unsigned halfword</entry>
</row>
<row>
<entry namest="c1" rowsep='0'>Enumeration</entry>
<entry namest="c2" rowsep='1'>signed enum</entry>
<entry namest="c3" rowsep='1'>4</entry>
<entry namest="c4" rowsep='1'>word</entry>
<entry namest="c5" rowsep='1'>signed word</entry>
</row>
<row>
<entry namest="c1" rowsep='1'></entry>
<entry namest="c2" rowsep='1'>unsigned enum</entry>
<entry namest="c3" rowsep='1'>4</entry>
<entry namest="c4" rowsep='1'>word</entry>
<entry namest="c5" rowsep='1'>unsigned word</entry>
</row>
<row>
<entry namest="c1" rowsep='0'>Integral</entry>
<entry namest="c2" rowsep='0'>int</entry>
<entry namest="c3" rowsep='0'>4</entry>
<entry namest="c4" rowsep='0'>word</entry>
<entry namest="c5" rowsep='0'>signed word</entry>
</row>
<row>
<entry namest="c2" rowsep='0'>signed int</entry>
<entry namest="c3" rowsep='0'></entry>
<entry namest="c4" rowsep='0'></entry>
<entry namest="c5" rowsep='0'></entry>
</row>
<row>
<entry namest="c2" rowsep='0'>long int</entry>
<entry namest="c3" rowsep='0'></entry>
<entry namest="c4" rowsep='0'></entry>
<entry namest="c5" rowsep='0'></entry>
</row>
<row>
<entry namest="c2" rowsep='1'>signed long</entry>
<entry namest="c3" rowsep='1'></entry>
<entry namest="c4" rowsep='1'></entry>
<entry namest="c5" rowsep='1'></entry>
</row>
<row>
<entry namest="c2" rowsep='0'>unsigned int</entry>
<entry namest="c3" rowsep='0'>4</entry>
<entry namest="c4" rowsep='0'>word</entry>
<entry namest="c5" rowsep='0'>unsigned word</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>unsigned long</entry>
<entry namest="c3" rowsep='1'></entry>
<entry namest="c4" rowsep='1'></entry>
<entry namest="c5" rowsep='1'></entry>
</row>
<row>
<entry namest="c2" rowsep='0'>long long</entry>
<entry namest="c3" rowsep='0'>8</entry>
<entry namest="c4" rowsep='0'>doubleword</entry>
<entry namest="c5" rowsep='0'>signed doubleword</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>signed long long</entry>
<entry namest="c3" rowsep='1'></entry>
<entry namest="c4" rowsep='1'></entry>
<entry namest="c5" rowsep='1'></entry>
</row>
<row>
<entry namest="c1" rowsep='1'></entry>
<entry namest="c2" rowsep='1'>unsigned long long</entry>
<entry namest="c3" rowsep='1'>8</entry>
<entry namest="c4" rowsep='1'>doubleword</entry>
<entry namest="c5" rowsep='1'>unsigned doubleword</entry>
</row>
<row>
<entry namest="c1" rowsep='0'>Pointer</entry>
<entry namest="c2" rowsep='0'>any *</entry>
<entry namest="c3" rowsep='0'>4</entry>
<entry namest="c4" rowsep='0'>word</entry>
<entry namest="c5" rowsep='0'>unsigned word</entry>
</row>
<row>
<entry namest="c1" rowsep='1'></entry>
<entry namest="c2" rowsep='1'>any (*) ()</entry>
<entry namest="c3" rowsep='1'></entry>
<entry namest="c4" rowsep='1'></entry>
<entry namest="c5" rowsep='1'></entry>
</row>
<row>
<entry namest="c1" rowsep='0'>Floating</entry>
<entry namest="c2" rowsep='1'>float</entry>
<entry namest="c3" rowsep='1'>4</entry>
<entry namest="c4" rowsep='1'>word</entry>
<entry namest="c5" rowsep='1'>single-precision float</entry>
</row>
<row>
<entry namest="c1" rowsep='0'></entry>
<entry namest="c2">double</entry>
<entry namest="c3">8</entry>
<entry namest="c4">doubleword</entry>
<entry namest="c5">double-precision float</entry>
</row>
</tbody>
</tgroup>
</table>
<important><para>A NULL pointer has all bits zero.</para></important>
<note><title>Note</title><para>Note: A boolean value is represented as a byte
with value 0 or 1. If a byte with a value other than 0 or 1 is
evaluated as a boolean value (for example, through the use of unions),
the behavior is undefined.</para></note>
<note><title>Note</title><para>Note: If an enumerated type contains a
negative value, it is compatible with and has the same representation
and alignment as int; otherwise it is compatible with and has the same
representation and alignment as unsigned int.</para></note>
<note><title>Note</title><para>Note: For each real floating-point type
there is a corresponding complex type. This has the same alignment as
the real type and twice the size; the representation is the real part
followed by the imaginary part.</para></note>
<table id="SPE-TYPES-TABLE" frame="none" CONDITION="ATR-SPE"><title>SPE Types</title>
<tgroup cols='5' colsep='0' rowsep='0'>
<colspec colwidth='50' colname='c1' align="left">
<colspec colwidth='105' colname='c2' align="left">
<colspec colwidth='40' colname='c3' align="left">
<colspec colwidth='60' colname='c4' align="left">
<colspec colwidth='130' colname='c5' align="left">
<thead>
<row rowsep="1">
<entry namest="c1">Type</entry>
<entry namest="c2">SPEPIM C Types</entry>
<entry namest="c3">sizeof</entry>
<entry namest="c4">Alignment</entry>
<entry namest="c5">Description</entry>
</row>
</thead>
<tbody>
<row>
<entry namest="c1" rowsep='0'>vector-64</entry>
<entry namest="c2" rowsep='1'>__ev64_u16__</entry>
<entry namest="c3" rowsep='1'>8</entry>
<entry namest="c4" rowsep='1'>doubleword</entry>
<entry namest="c5" rowsep='1'>vector of four unsigned halfwords</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>__ev64_s16__</entry>
<entry namest="c3" rowsep='1'>8</entry>
<entry namest="c4" rowsep='1'>doubleword</entry>
<entry namest="c5" rowsep='1'>vector of four signed halfwords</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>__ev64_u32__</entry>
<entry namest="c3" rowsep='1'>8</entry>
<entry namest="c4" rowsep='1'>doubleword</entry>
<entry namest="c5" rowsep='1'>vector of two unsigned words</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>__ev64_s32__</entry>
<entry namest="c3" rowsep='1'>8</entry>
<entry namest="c4" rowsep='1'>doubleword</entry>
<entry namest="c5" rowsep='1'>vector of two signed words</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>__ev64_fs__</entry>
<entry namest="c3" rowsep='1'>8</entry>
<entry namest="c4" rowsep='1'>doubleword</entry>
<entry namest="c5" rowsep='1'>vector of two single-precision floats</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>__ev64_u64__</entry>
<entry namest="c3" rowsep='1'>8</entry>
<entry namest="c4" rowsep='1'>doubleword</entry>
<entry namest="c5" rowsep='1'>1 unsigned doubleword</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>__ev64_s64__</entry>
<entry namest="c3" rowsep='1'>8</entry>
<entry namest="c4" rowsep='1'>doubleword</entry>
<entry namest="c5" rowsep='1'>1 signed doubleword</entry>
</row>
<row rowsep='0'>
<entry namest="c1"></entry>
<entry namest="c2">__ev64_opaque__</entry>
<entry namest="c3">8</entry>
<entry namest="c4">doubleword</entry>
<entry namest="c5">any of the above</entry>
</row>
</tbody>
</tgroup>
</table>
<table id="VECTOR-TYPES-TABLE" frame="none" CONDITION="ATR-VECTOR"><title>Vector Types</title>
<tgroup cols='5' colsep='0' rowsep='0'>
<colspec colwidth='60' colname='c1' align="left">
<colspec colwidth='95' colname='c2' align="left">
<colspec colwidth='40' colname='c3' align="left">
<colspec colwidth='60' colname='c4' align="left">
<colspec colwidth='130' colname='c5' align="left">
<thead>
<row rowsep="1">
<entry namest="c1">Type</entry>
<entry namest="c2">ALTIVECPIM C Types</entry>
<entry namest="c3">sizeof</entry>
<entry namest="c4">Alignment</entry>
<entry namest="c5">Description</entry>
</row>
</thead>
<tbody>
<row>
<entry namest="c1" rowsep='0'>vector-128</entry>
<entry namest="c2" rowsep='1'>vector unsigned char</entry>
<entry namest="c3" rowsep='1'>16</entry>
<entry namest="c4" rowsep='1'>quadword</entry>
<entry namest="c5" rowsep='1'>vector of sixteen unsigned bytes</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>vector signed char</entry>
<entry namest="c3" rowsep='1'>16</entry>
<entry namest="c4" rowsep='1'>quadword</entry>
<entry namest="c5" rowsep='1'>vector of sixteen signed bytes</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>vector unsigned short</entry>
<entry namest="c3" rowsep='1'>16</entry>
<entry namest="c4" rowsep='1'>quadword</entry>
<entry namest="c5" rowsep='1'>vector of eight unsigned halfwords</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>vector signed short</entry>
<entry namest="c3" rowsep='1'>16</entry>
<entry namest="c4" rowsep='1'>quadword</entry>
<entry namest="c5" rowsep='1'>vector of eight signed halfwords</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>vector unsigned int</entry>
<entry namest="c3" rowsep='1'>16</entry>
<entry namest="c4" rowsep='1'>quadword</entry>
<entry namest="c5" rowsep='1'>vector of four unsigned words</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>vector signed int</entry>
<entry namest="c3" rowsep='1'>16</entry>
<entry namest="c4" rowsep='1'>quadword</entry>
<entry namest="c5" rowsep='1'>vector of four signed words</entry>
</row>
<row rowsep='0'>
<entry namest="c1"></entry>
<entry namest="c2">vector float</entry>
<entry namest="c3">16</entry>
<entry namest="c4">quadword</entry>
<entry namest="c5">vector of four single-precision floats</entry>
</row>
</tbody>
</tgroup>
</table>
<note CONDITION="ATR-SPE && ATR-VECTOR">
<title>Note</title>
<para>Note: Availability of Vector
data types is subject to conformance to a Power ISA category where the
categories “Vector” and “SPE” are mutually exclusive.</para></note>
<table id="DFP-TYPES-TABLE" frame="none" CONDITION="ATR-DFP"><title>Decimal Floating-Point Types</title>
<tgroup cols='5' colsep='0' rowsep='0'>
<colspec colwidth='60' colname='c1' align="left">
<colspec colwidth='95' colname='c2' align="left">
<colspec colwidth='40' colname='c3' align="left">
<colspec colwidth='60' colname='c4' align="left">
<colspec colwidth='130' colname='c5' align="left">
<thead>
<row rowsep="1">
<entry namest="c1">Type</entry>
<entry namest="c2">ISO TR 24732 C Types</entry>
<entry namest="c3">sizeof</entry>
<entry namest="c4">Alignment</entry>
<entry namest="c5">Description</entry>
</row>
</thead>
<tbody>
<row rowsep="1">
<entry namest="c1" rowsep='0'>Decimal Floating</entry>
<entry namest="c2" rowsep='1'>_Decimal32</entry>
<entry namest="c3" rowsep='1'>4</entry>
<entry namest="c4" rowsep='1'>word</entry>
<entry namest="c5" rowsep='1'>single-precision decimal float</entry>
</row>
<row>
<entry namest="c2" rowsep='1'>_Decimal64</entry>
<entry namest="c3" rowsep='1'>8</entry>
<entry namest="c4" rowsep='1'>doubleword</entry>
<entry namest="c5" rowsep='1'>double-precision decimal float</entry>
</row>
<row rowsep='0'>
<entry namest="c2">_Decimal128</entry>
<entry namest="c3">16</entry>
<entry namest="c4">quadword</entry>
<entry namest="c5">quad-precision decimal float</entry>
</row>
</tbody>
</tgroup>
</table>
<table id="LONG-DOUBLE-IS-IBM-TYPES-TABLE" frame="none" CONDITION="ATR-LONG-DOUBLE-IBM"><title><trademark class="REGISTERED">IBM</trademark> <trademark class="registered">AIX</trademark> Long Double 128 Type</title>
<tgroup cols='5' colsep='0' rowsep='0'>
<colspec colwidth='60' colname='c1' align="left">
<colspec colwidth='95' colname='c2' align="left">
<colspec colwidth='40' colname='c3' align="left">
<colspec colwidth='60' colname='c4' align="left">
<colspec colwidth='130' colname='c5' align="left">
<thead>
<row rowsep="1">
<entry namest="c1">Type</entry>
<entry namest="c2">ISO C Types</entry>
<entry namest="c3">sizeof</entry>
<entry namest="c4">Alignment</entry>
<entry namest="c5">Description</entry>
</row>
</thead>
<tbody>
<row rowsep="0">
<entry namest="c1">IBM AIX long double</entry>
<entry namest="c2">long double</entry>
<entry namest="c3">16</entry>
<entry namest="c4">quadword</entry>
<entry namest="c5">two double-precision floats</entry>
</row>
</tbody>
</tgroup>
</table>
<table id="LONG-DOUBLE-IS-DOUBLE-TYPES-TABLE" frame="none" CONDITION="ATR-LONG-DOUBLE-IS-DOUBLE"><title>Long Double Is Double Type</title>
<tgroup cols='5' colsep='0' rowsep='0'>
<colspec colwidth='60' colname='c1' align="left">
<colspec colwidth='95' colname='c2' align="left">
<colspec colwidth='40' colname='c3' align="left">
<colspec colwidth='60' colname='c4' align="left">
<colspec colwidth='130' colname='c5' align="left">
<thead>
<row rowsep="1">
<entry namest="c1">Type</entry>
<entry namest="c2">ISO C Types</entry>
<entry namest="c3">sizeof</entry>
<entry namest="c4">Alignment</entry>
<entry namest="c5">Description</entry>
</row>
</thead>
<tbody>
<row rowsep='0'>
<entry namest="c1">long double is double</entry>
<entry namest="c2">long double</entry>
<entry namest="c3">8</entry>
<entry namest="c4">doubleword</entry>
<entry namest="c5">double-precision float</entry>
</row>
</tbody>
</tgroup>
</table>
<note CONDITION="ATR-LONG-DOUBLE-IBM && ATR-LONG-DOUBLE-IS-DOUBLE">
<title>Note</title>
<para>Note: Availability of the long
double data type is subject to conformance to a long double standard
where the IBM AIX 128-bit
Long Double format and the <emphasis>Long Double is Double</emphasis> format are mutually
exclusive.</para>
</note>
<note CONDITION="ATR-LONG-DOUBLE-IS-DOUBLE || ATR-LONG-DOUBLE-IBM">
<title>Note</title>
<para> This ABI provides the following choices for implementation of
long double in compilers and systems:</para>
<itemizedlist>
<listitem CONDITION="ATR-LONG-DOUBLE-IS-DOUBLE">
<para>Do not support any floating-point types with greater
precision than double. In this case, long doubles and doubles have the same
size and precision. </para>
</listitem>
<listitem CONDITION="ATR-LONG-DOUBLE-IBM">
<para> Provide support for the IBM AIX 128-bit Long Double format. In
this format, double precision numbers with different magnitudes
that do not overlap, provide an effective precision of 106-bits.
The high-order double-precision value (the one that comes first in
storage) must have the larger magnitude. The high-order double-precision value must equal the sum of the two values, rounded to
nearest double.</para>
<itemizedlist>
<listitem>
<para>Extended precision provides the same range of double-precision (about 10<superscript>−308</superscript> to 10<superscript>308</superscript> but more precision (a variable amount, about 31 decimal digits or more).
</para>
</listitem>
<listitem>
<para> As the absolute value of the magnitude decreases (near the denormal range), the
precision available in the low-order double also decreases. </para>
</listitem>
<listitem>
<para> When the value represented is in the denormal range, this representation
provides no more precision than 64-bit (double) floating-point.</para>
</listitem>
<listitem>
<para> The actual number of bits of precision can vary. If the low-order part is much
less then 1 unit of least precision (ULP) of the high-order part, significant bits (either all 0s or all 1s)
are implied between the significands of high-order and low-order numbers. Some
algorithms that rely on having a fixed number of bits in the significand can fail when
using extended-precision.</para>
</listitem>
</itemizedlist>
<para> This implementation differs from the IEEE 754 Standard in the following ways:</para>
<itemizedlist>
<listitem>
<para> The software support is restricted to round-to-nearest mode. Programs that use
extended-precision must ensure that this rounding mode is in effect when
extended-precision calculations are performed.</para>
</listitem>
<listitem>
<para> Does not fully support the IEEE special numbers NaN and INF. These values are
encoded in the high-order double value only. The low-order
value is not significant, but the low-order value of an
infinity must be positive or negative zero.
</para>
</listitem>
<listitem>
<para> Does not support the IEEE status flags for overflow, underflow, and other
conditions. These flags have no meaning in this format.</para>
</listitem>
</itemizedlist>
</listitem>
</itemizedlist>
</note>
</sect3>
<sect3 id="AGG-UNION"><title>Aggregates and Unions</title>
<para>The following are the rules for aggregates (structures and arrays)
and unions that apply to their alignment and size.</para>
<itemizedlist>
<listitem>
<para>The entire aggregate or union must be aligned to its most strictly aligned
member, which corresponds to the member with the largest alignment, including flexible array members.</para>
</listitem>
<listitem>
<para>Each member is assigned the lowest available offset that meets the alignment
requirements of the member. Depending on the previous member, internal padding can be
required.</para>
</listitem>
<listitem>
<para>The entire aggregate or union must have a size that is a multiple of its
alignment. Depending on the last member, tail padding can be required.</para>
</listitem>
</itemizedlist>
<para>For the following figures, the big-endian byte offsets are located in the upper left
corners, and the little-endian byte offsets are located in the upper right corners.</para>
<figure><title>Structure Smaller Than a Word</title>
<programlisting>
struct {
char c;
};
</programlisting>
<synopsis>byte aligned, sizeof is 1</synopsis>
</figure>
<informaltable frame="all">
<tgroup cols='2' colsep='0' rowsep='0'>
<colspec colwidth="15" colname='c1' align="left">
<colspec colwidth="15" colname='c2' align="right">
<tbody>
<row>
<entry namest="c1">0</entry>
<entry namest="c2">0</entry>
</row>
<row>
<entry namest="c1" nameend="c2" align="center">c</entry>
</row>
</tbody>
</tgroup>
</informaltable>
<figure><title>Structure With No Padding</title>
<programlisting>
struct {
char c;
char d;
short s;
int n;
};
</programlisting>
<synopsis>word-aligned, sizeof is 8</synopsis>
</figure>
<para>little-endian</para>
<informaltable frame="all">
<tgroup cols='8' colsep='0' rowsep='0'>
<colspec colwidth='15' colname='c1' align="left">
<colspec colwidth='15' colname='c2' align="right">
<colspec colwidth='15' colname='c3' align="left">
<colspec colwidth='15' colname='c4' align="right">
<colspec colwidth='15' colname='c5' align="left">
<colspec colwidth='15' colname='c6' align="right">
<colspec colwidth='15' colname='c7' align="left">
<colspec colwidth='15' colname='c8' align="right">
<tbody>
<row>
<entry namest="c1" nameend="c4" align="right" colsep="1">2</entry>
<entry namest="c5" nameend="c6" align="right" colsep="1">1</entry>
<entry namest="c7" nameend="c8" align="right">0</entry>
</row>
<row rowsep="1">
<entry namest="c1" nameend="c4" colsep="1" align="center">s</entry>
<entry namest="c5" nameend="c6" colsep="1" align="center">d</entry>
<entry namest="c7" nameend="c8" align="center">c</entry>
</row>
<row>
<entry namest="c1" nameend="c8" align="right">4</entry>
</row>
<row>
<entry namest="c1" nameend="c8" align="center">n</entry>
</row>
</tbody>
</tgroup>
</informaltable>
<para>big-endian</para>
<informaltable frame="all">
<tgroup cols='8' colsep='0' rowsep='0'>
<colspec colwidth='15' colname='c1' align="left">
<colspec colwidth='15' colname='c2' align="right">