From 1d8cca9f00677fd294aefcbf4523d67d0a03d86f Mon Sep 17 00:00:00 2001 From: shawntsai0312 Date: Tue, 17 Dec 2024 12:40:42 +0800 Subject: [PATCH] update all readme --- Lab1/README.md | 41 ++++- Lab2/README.md | 96 +++++++++++- .../{rs232 old.py => rs232_python2.py} | 0 Lab2/{ => src}/rsa_qsys/rsa_qsys.bsf | 0 Lab2/{ => src}/rsa_qsys/rsa_qsys.cmp | 0 Lab2/{ => src}/rsa_qsys/rsa_qsys.html | 0 Lab2/{ => src}/rsa_qsys/rsa_qsys.xml | 0 Lab2/{ => src}/rsa_qsys/rsa_qsys_bb.v | 0 .../rsa_qsys/rsa_qsys_generation.rpt | 0 Lab2/{ => src}/rsa_qsys/rsa_qsys_inst.v | 0 Lab2/{ => src}/rsa_qsys/rsa_qsys_inst.vhd | 0 .../rsa_qsys/synthesis/rsa_qsys.debuginfo.xml | 0 .../{ => src}/rsa_qsys/synthesis/rsa_qsys.qip | 0 Lab2/{ => src}/rsa_qsys/synthesis/rsa_qsys.v | 0 .../synthesis/submodules/Rsa256Core.sv | 0 .../synthesis/submodules/Rsa256Wrapper.sv | 0 .../altera_merlin_master_translator.sv | 0 .../altera_merlin_slave_translator.sv | 0 .../submodules/altera_reset_controller.sdc | 0 .../submodules/altera_reset_controller.v | 0 .../submodules/altera_reset_synchronizer.v | 0 .../synthesis/submodules/rsa_qsys_altpll_0.v | 0 .../submodules/rsa_qsys_mm_interconnect_0.v | 0 .../synthesis/submodules/rsa_qsys_uart_0.v | 0 Lab3/README.md | 144 +++++++++++++++++- Lab3/{ => src}/Altpll/Altpll.bsf | 0 Lab3/{ => src}/Altpll/Altpll.cmp | 0 Lab3/{ => src}/Altpll/Altpll.html | 0 Lab3/{ => src}/Altpll/Altpll.xml | 0 Lab3/{ => src}/Altpll/Altpll_bb.v | 0 Lab3/{ => src}/Altpll/Altpll_generation.rpt | 0 Lab3/{ => src}/Altpll/Altpll_inst.v | 0 Lab3/{ => src}/Altpll/Altpll_inst.vhd | 0 .../Altpll/synthesis/Altpll.debuginfo.xml | 0 Lab3/{ => src}/Altpll/synthesis/Altpll.qip | 0 Lab3/{ => src}/Altpll/synthesis/Altpll.v | 0 .../synthesis/submodules/Altpll_altpll_0.v | 0 .../submodules/altera_reset_controller.sdc | 0 .../submodules/altera_reset_controller.v | 0 .../submodules/altera_reset_synchronizer.v | 0 40 files changed, 278 insertions(+), 3 deletions(-) rename Lab2/src/pc_python/{rs232 old.py => rs232_python2.py} (100%) rename Lab2/{ => src}/rsa_qsys/rsa_qsys.bsf (100%) rename Lab2/{ => src}/rsa_qsys/rsa_qsys.cmp (100%) rename Lab2/{ => src}/rsa_qsys/rsa_qsys.html (100%) rename Lab2/{ => src}/rsa_qsys/rsa_qsys.xml (100%) rename Lab2/{ => src}/rsa_qsys/rsa_qsys_bb.v (100%) rename Lab2/{ => src}/rsa_qsys/rsa_qsys_generation.rpt (100%) rename Lab2/{ => src}/rsa_qsys/rsa_qsys_inst.v (100%) rename Lab2/{ => src}/rsa_qsys/rsa_qsys_inst.vhd (100%) rename Lab2/{ => src}/rsa_qsys/synthesis/rsa_qsys.debuginfo.xml (100%) rename Lab2/{ => src}/rsa_qsys/synthesis/rsa_qsys.qip (100%) rename Lab2/{ => src}/rsa_qsys/synthesis/rsa_qsys.v (100%) rename Lab2/{ => src}/rsa_qsys/synthesis/submodules/Rsa256Core.sv (100%) rename Lab2/{ => src}/rsa_qsys/synthesis/submodules/Rsa256Wrapper.sv (100%) rename Lab2/{ => src}/rsa_qsys/synthesis/submodules/altera_merlin_master_translator.sv (100%) rename Lab2/{ => src}/rsa_qsys/synthesis/submodules/altera_merlin_slave_translator.sv (100%) rename Lab2/{ => src}/rsa_qsys/synthesis/submodules/altera_reset_controller.sdc (100%) rename Lab2/{ => src}/rsa_qsys/synthesis/submodules/altera_reset_controller.v (100%) rename Lab2/{ => src}/rsa_qsys/synthesis/submodules/altera_reset_synchronizer.v (100%) rename Lab2/{ => src}/rsa_qsys/synthesis/submodules/rsa_qsys_altpll_0.v (100%) rename Lab2/{ => src}/rsa_qsys/synthesis/submodules/rsa_qsys_mm_interconnect_0.v (100%) rename Lab2/{ => src}/rsa_qsys/synthesis/submodules/rsa_qsys_uart_0.v (100%) rename Lab3/{ => src}/Altpll/Altpll.bsf (100%) rename Lab3/{ => src}/Altpll/Altpll.cmp (100%) rename Lab3/{ => src}/Altpll/Altpll.html (100%) rename Lab3/{ => src}/Altpll/Altpll.xml (100%) rename Lab3/{ => src}/Altpll/Altpll_bb.v (100%) rename Lab3/{ => src}/Altpll/Altpll_generation.rpt (100%) rename Lab3/{ => src}/Altpll/Altpll_inst.v (100%) rename Lab3/{ => src}/Altpll/Altpll_inst.vhd (100%) rename Lab3/{ => src}/Altpll/synthesis/Altpll.debuginfo.xml (100%) rename Lab3/{ => src}/Altpll/synthesis/Altpll.qip (100%) rename Lab3/{ => src}/Altpll/synthesis/Altpll.v (100%) rename Lab3/{ => src}/Altpll/synthesis/submodules/Altpll_altpll_0.v (100%) rename Lab3/{ => src}/Altpll/synthesis/submodules/altera_reset_controller.sdc (100%) rename Lab3/{ => src}/Altpll/synthesis/submodules/altera_reset_controller.v (100%) rename Lab3/{ => src}/Altpll/synthesis/submodules/altera_reset_synchronizer.v (100%) diff --git a/Lab1/README.md b/Lab1/README.md index c87d37e..1bae84b 100644 --- a/Lab1/README.md +++ b/Lab1/README.md @@ -1,6 +1,45 @@ # Lab 1 亂數產生器 -### Before Running +### File Structures + +``` +. +├── Guideline.md +├── README.md +├── doc +│ ├── Lab1_lecture.pdf +│ ├── Lab1_quartus.pdf +│ ├── architecture.drawio +│ ├── machine.drawio +│ ├── state.drawio +│ ├── state.png +│ └── team04_lab1_report.pdf +├── include +│ └── LAB1_include.sv +├── lint +│ └── Makefile +├── sim +│ ├── Top_test.py +│ ├── Top_test.sv +│ ├── run.sh +│ ├── seven.py +│ ├── tb_Top.sv +│ └── tool.sh +└── src + ├── DE2_115 + │ ├── DE2_115.qsf + │ ├── DE2_115.sdc + │ ├── DE2_115.sv + │ ├── Debounce.sv + │ └── SevenHexDecoder.sv + └── Top.sv +``` + +### How To Run on DE2-115 with QuartusII + + - [Tutorial Video](https://youtu.be/d8w0doN23KI) + +### Before Simulation ```shell cd Lab1/sim/ diff --git a/Lab2/README.md b/Lab2/README.md index c1b679d..03fb92a 100644 --- a/Lab2/README.md +++ b/Lab2/README.md @@ -1,6 +1,100 @@ # Lab 2 RSA256 解密機 -### Before Running +### File Structures + +``` +. +├── Guideline.md +├── README.md +├── doc +│ ├── Lab2_lecture.pdf +│ ├── Lab2_qsys_tuto1.pdf +│ ├── core state.drawio +│ ├── core state.png +│ ├── prep mont state.drawio +│ ├── prep mont state.png +│ ├── team04_lab2_report.pdf +│ ├── wrapper state.drawio +│ └── wrapper state.png +└── src + ├── DE2_115 + │ ├── DE2_115.qsf + │ ├── DE2_115.sdc + │ └── DE2_115.sv + ├── Rsa256Core.sv + ├── Rsa256Wrapper.sv + ├── pc_python + │ ├── enc.bin + │ ├── enc.txt + │ ├── golden + │ │ ├── core.log + │ │ ├── core.py + │ │ ├── core.sh + │ │ ├── dec1.txt + │ │ ├── dec2.txt + │ │ ├── dec3.txt + │ │ ├── enc1.bin + │ │ ├── enc1.txt + │ │ ├── enc2.bin + │ │ ├── enc2.txt + │ │ ├── enc3.bin + │ │ ├── enc3.txt + │ │ ├── key.bin + │ │ ├── key.txt + │ │ ├── key_ascii.txt + │ │ ├── mont.log + │ │ ├── mont.py + │ │ ├── mont.sh + │ │ ├── prep.log + │ │ ├── prep.py + │ │ ├── prep.sh + │ │ └── rsa.py + │ ├── key.bin + │ ├── key.txt + │ ├── rs232_python2.py + │ ├── rs232.cpp + │ └── rs232.py + ├── rsa_qsys + │ ├── rsa_qsys.bsf + │ ├── rsa_qsys.cmp + │ ├── rsa_qsys.html + │ ├── rsa_qsys.xml + │ ├── rsa_qsys_bb.v + │ ├── rsa_qsys_generation.rpt + │ ├── rsa_qsys_inst.v + │ ├── rsa_qsys_inst.vhd + │ └── synthesis + │ ├── rsa_qsys.debuginfo.xml + │ ├── rsa_qsys.qip + │ ├── rsa_qsys.v + │ └── submodules + │ ├── Rsa256Core.sv + │ ├── Rsa256Wrapper.sv + │ ├── altera_merlin_master_translator.sv + │ ├── altera_merlin_slave_translator.sv + │ ├── altera_reset_controller.sdc + │ ├── altera_reset_controller.v + │ ├── altera_reset_synchronizer.v + │ ├── rsa_qsys_altpll_0.v + │ ├── rsa_qsys_mm_interconnect_0.v + │ └── rsa_qsys_uart_0.v + └── tb_verilog + ├── PipelineCtrl.v + ├── PipelineTb.v + ├── core.sh + ├── tb.sv + ├── test_wrapper.sv + ├── tool.sh + ├── wrapper.sh + ├── wrapper_input.txt + └── wrapper_output.txt +``` + +### How To Run on DE2-115 with QuartusII + + - [Tutorial Video](https://youtu.be/MsHFpBeLLhE) + +### Before Simulation ```shell cd Lab2/src/tb_verilog diff --git a/Lab2/src/pc_python/rs232 old.py b/Lab2/src/pc_python/rs232_python2.py similarity index 100% rename from Lab2/src/pc_python/rs232 old.py rename to Lab2/src/pc_python/rs232_python2.py diff --git a/Lab2/rsa_qsys/rsa_qsys.bsf b/Lab2/src/rsa_qsys/rsa_qsys.bsf similarity index 100% rename from Lab2/rsa_qsys/rsa_qsys.bsf rename to Lab2/src/rsa_qsys/rsa_qsys.bsf diff --git a/Lab2/rsa_qsys/rsa_qsys.cmp b/Lab2/src/rsa_qsys/rsa_qsys.cmp similarity index 100% rename from Lab2/rsa_qsys/rsa_qsys.cmp rename to Lab2/src/rsa_qsys/rsa_qsys.cmp diff --git a/Lab2/rsa_qsys/rsa_qsys.html b/Lab2/src/rsa_qsys/rsa_qsys.html similarity index 100% rename from Lab2/rsa_qsys/rsa_qsys.html rename to Lab2/src/rsa_qsys/rsa_qsys.html diff --git a/Lab2/rsa_qsys/rsa_qsys.xml b/Lab2/src/rsa_qsys/rsa_qsys.xml similarity index 100% rename from Lab2/rsa_qsys/rsa_qsys.xml rename to Lab2/src/rsa_qsys/rsa_qsys.xml diff --git a/Lab2/rsa_qsys/rsa_qsys_bb.v b/Lab2/src/rsa_qsys/rsa_qsys_bb.v similarity index 100% rename from Lab2/rsa_qsys/rsa_qsys_bb.v rename to Lab2/src/rsa_qsys/rsa_qsys_bb.v diff --git a/Lab2/rsa_qsys/rsa_qsys_generation.rpt b/Lab2/src/rsa_qsys/rsa_qsys_generation.rpt similarity index 100% rename from Lab2/rsa_qsys/rsa_qsys_generation.rpt rename to Lab2/src/rsa_qsys/rsa_qsys_generation.rpt diff --git a/Lab2/rsa_qsys/rsa_qsys_inst.v b/Lab2/src/rsa_qsys/rsa_qsys_inst.v similarity index 100% rename from Lab2/rsa_qsys/rsa_qsys_inst.v rename to Lab2/src/rsa_qsys/rsa_qsys_inst.v diff --git a/Lab2/rsa_qsys/rsa_qsys_inst.vhd b/Lab2/src/rsa_qsys/rsa_qsys_inst.vhd similarity index 100% rename from Lab2/rsa_qsys/rsa_qsys_inst.vhd rename to Lab2/src/rsa_qsys/rsa_qsys_inst.vhd diff --git a/Lab2/rsa_qsys/synthesis/rsa_qsys.debuginfo.xml b/Lab2/src/rsa_qsys/synthesis/rsa_qsys.debuginfo.xml similarity index 100% rename from Lab2/rsa_qsys/synthesis/rsa_qsys.debuginfo.xml rename to Lab2/src/rsa_qsys/synthesis/rsa_qsys.debuginfo.xml diff --git a/Lab2/rsa_qsys/synthesis/rsa_qsys.qip b/Lab2/src/rsa_qsys/synthesis/rsa_qsys.qip similarity index 100% rename from Lab2/rsa_qsys/synthesis/rsa_qsys.qip rename to Lab2/src/rsa_qsys/synthesis/rsa_qsys.qip diff --git a/Lab2/rsa_qsys/synthesis/rsa_qsys.v b/Lab2/src/rsa_qsys/synthesis/rsa_qsys.v similarity index 100% rename from Lab2/rsa_qsys/synthesis/rsa_qsys.v rename to Lab2/src/rsa_qsys/synthesis/rsa_qsys.v diff --git a/Lab2/rsa_qsys/synthesis/submodules/Rsa256Core.sv b/Lab2/src/rsa_qsys/synthesis/submodules/Rsa256Core.sv similarity index 100% rename from Lab2/rsa_qsys/synthesis/submodules/Rsa256Core.sv rename to Lab2/src/rsa_qsys/synthesis/submodules/Rsa256Core.sv diff --git a/Lab2/rsa_qsys/synthesis/submodules/Rsa256Wrapper.sv b/Lab2/src/rsa_qsys/synthesis/submodules/Rsa256Wrapper.sv similarity index 100% rename from Lab2/rsa_qsys/synthesis/submodules/Rsa256Wrapper.sv rename to Lab2/src/rsa_qsys/synthesis/submodules/Rsa256Wrapper.sv diff --git a/Lab2/rsa_qsys/synthesis/submodules/altera_merlin_master_translator.sv b/Lab2/src/rsa_qsys/synthesis/submodules/altera_merlin_master_translator.sv similarity index 100% rename from Lab2/rsa_qsys/synthesis/submodules/altera_merlin_master_translator.sv rename to Lab2/src/rsa_qsys/synthesis/submodules/altera_merlin_master_translator.sv diff --git a/Lab2/rsa_qsys/synthesis/submodules/altera_merlin_slave_translator.sv b/Lab2/src/rsa_qsys/synthesis/submodules/altera_merlin_slave_translator.sv similarity index 100% rename from Lab2/rsa_qsys/synthesis/submodules/altera_merlin_slave_translator.sv rename to Lab2/src/rsa_qsys/synthesis/submodules/altera_merlin_slave_translator.sv diff --git a/Lab2/rsa_qsys/synthesis/submodules/altera_reset_controller.sdc b/Lab2/src/rsa_qsys/synthesis/submodules/altera_reset_controller.sdc similarity index 100% rename from Lab2/rsa_qsys/synthesis/submodules/altera_reset_controller.sdc rename to Lab2/src/rsa_qsys/synthesis/submodules/altera_reset_controller.sdc diff --git a/Lab2/rsa_qsys/synthesis/submodules/altera_reset_controller.v b/Lab2/src/rsa_qsys/synthesis/submodules/altera_reset_controller.v similarity index 100% rename from Lab2/rsa_qsys/synthesis/submodules/altera_reset_controller.v rename to Lab2/src/rsa_qsys/synthesis/submodules/altera_reset_controller.v diff --git a/Lab2/rsa_qsys/synthesis/submodules/altera_reset_synchronizer.v b/Lab2/src/rsa_qsys/synthesis/submodules/altera_reset_synchronizer.v similarity index 100% rename from Lab2/rsa_qsys/synthesis/submodules/altera_reset_synchronizer.v rename to Lab2/src/rsa_qsys/synthesis/submodules/altera_reset_synchronizer.v diff --git a/Lab2/rsa_qsys/synthesis/submodules/rsa_qsys_altpll_0.v b/Lab2/src/rsa_qsys/synthesis/submodules/rsa_qsys_altpll_0.v similarity index 100% rename from Lab2/rsa_qsys/synthesis/submodules/rsa_qsys_altpll_0.v rename to Lab2/src/rsa_qsys/synthesis/submodules/rsa_qsys_altpll_0.v diff --git a/Lab2/rsa_qsys/synthesis/submodules/rsa_qsys_mm_interconnect_0.v b/Lab2/src/rsa_qsys/synthesis/submodules/rsa_qsys_mm_interconnect_0.v similarity index 100% rename from Lab2/rsa_qsys/synthesis/submodules/rsa_qsys_mm_interconnect_0.v rename to Lab2/src/rsa_qsys/synthesis/submodules/rsa_qsys_mm_interconnect_0.v diff --git a/Lab2/rsa_qsys/synthesis/submodules/rsa_qsys_uart_0.v b/Lab2/src/rsa_qsys/synthesis/submodules/rsa_qsys_uart_0.v similarity index 100% rename from Lab2/rsa_qsys/synthesis/submodules/rsa_qsys_uart_0.v rename to Lab2/src/rsa_qsys/synthesis/submodules/rsa_qsys_uart_0.v diff --git a/Lab3/README.md b/Lab3/README.md index 1276b1c..4ab524c 100644 --- a/Lab3/README.md +++ b/Lab3/README.md @@ -1,6 +1,148 @@ # Lab 3 數位錄音機 -### Before Running +### File Structures + +``` +. +├── Guideline.md +├── README.md +├── doc +│ ├── Lab3_lecture.pdf +│ ├── Lab3_sup1_audiocodec.pdf +│ ├── Lab3_sup2_mem.pdf +│ ├── Lab3_sup3_lcd.pdf +│ ├── Lab3_sup4_ctrlpanel.pdf +│ ├── auddsp.drawio +│ ├── audplayer.drawio +│ ├── audrecorder.drawio +│ ├── i2c.drawio +│ ├── structure.drawio +│ ├── team04_lab3.pdf +│ └── top state.drawio +├── sim +│ ├── sh +│ │ ├── AudDSP +│ │ │ └── run.sh +│ │ ├── AudPlayer +│ │ │ └── run.sh +│ │ ├── AudRecorder +│ │ │ └── run.sh +│ │ ├── I2cInitializer +│ │ │ └── run.sh +│ │ ├── Top +│ │ │ └── run.sh +│ │ └── tool.sh +│ └── tb +│ ├── AudDSP +│ │ ├── data.py +│ │ ├── golden +│ │ │ ├── constant +│ │ │ │ ├── constant_2.txt +│ │ │ │ ├── constant_3.txt +│ │ │ │ ├── constant_4.txt +│ │ │ │ ├── constant_5.txt +│ │ │ │ ├── constant_6.txt +│ │ │ │ ├── constant_7.txt +│ │ │ │ └── constant_8.txt +│ │ │ ├── fast +│ │ │ │ ├── fast_2.txt +│ │ │ │ ├── fast_3.txt +│ │ │ │ ├── fast_4.txt +│ │ │ │ ├── fast_5.txt +│ │ │ │ ├── fast_6.txt +│ │ │ │ ├── fast_7.txt +│ │ │ │ └── fast_8.txt +│ │ │ ├── linear +│ │ │ │ ├── linear_2.txt +│ │ │ │ ├── linear_3.txt +│ │ │ │ ├── linear_4.txt +│ │ │ │ ├── linear_5.txt +│ │ │ │ ├── linear_6.txt +│ │ │ │ ├── linear_7.txt +│ │ │ │ └── linear_8.txt +│ │ │ ├── mem.txt +│ │ │ └── normal.txt +│ │ └── tb.sv +│ ├── AudPlayer +│ │ ├── golden.txt +│ │ └── tb.sv +│ ├── AudRecorder +│ │ ├── data.py +│ │ ├── golden.txt +│ │ └── tb.sv +│ ├── I2cInitializer +│ │ ├── golden.txt +│ │ ├── tb.sv +│ │ └── tb_raw.sv +│ └── Top +│ ├── data.py +│ ├── golden +│ │ ├── constant +│ │ │ ├── constant_2.txt +│ │ │ ├── constant_3.txt +│ │ │ ├── constant_4.txt +│ │ │ ├── constant_5.txt +│ │ │ ├── constant_6.txt +│ │ │ ├── constant_7.txt +│ │ │ └── constant_8.txt +│ │ ├── fast +│ │ │ ├── fast_2.txt +│ │ │ ├── fast_3.txt +│ │ │ ├── fast_4.txt +│ │ │ ├── fast_5.txt +│ │ │ ├── fast_6.txt +│ │ │ ├── fast_7.txt +│ │ │ └── fast_8.txt +│ │ ├── linear +│ │ │ ├── linear_2.txt +│ │ │ ├── linear_3.txt +│ │ │ ├── linear_4.txt +│ │ │ ├── linear_5.txt +│ │ │ ├── linear_6.txt +│ │ │ ├── linear_7.txt +│ │ │ └── linear_8.txt +│ │ ├── mem.txt +│ │ └── normal.txt +│ └── tb.sv +└── src + ├── Altpll + │ ├── Altpll.bsf + │ ├── Altpll.cmp + │ ├── Altpll.html + │ ├── Altpll.xml + │ ├── Altpll_bb.v + │ ├── Altpll_generation.rpt + │ ├── Altpll_inst.v + │ ├── Altpll_inst.vhd + │ └── synthesis + │ ├── Altpll.debuginfo.xml + │ ├── Altpll.qip + │ ├── Altpll.v + │ └── submodules + │ ├── Altpll_altpll_0.v + │ ├── altera_reset_controller.sdc + │ ├── altera_reset_controller.v + │ └── altera_reset_synchronizer.v + ├── AudDSP.sv + ├── AudPlayer.sv + ├── AudRecorder.sv + ├── DE2_115 + │ ├── DE2_115.qsf + │ ├── DE2_115.sdc + │ ├── DE2_115.sv + │ ├── Debounce.sv + │ ├── FastSlow.sv + │ └── SevenHexDecoder.sv + ├── I2cInitializer.sv + └── Top.sv +``` + +### How To Run on DE2-115 with QuartusII + + - [Tutorial Video 1](https://youtu.be/lxQ1CqLxdgA) + - [Tutorial Video 2](https://youtu.be/XZyHApFdQvU) + +### Before Simulation ```shell cd Lab3/sim/ diff --git a/Lab3/Altpll/Altpll.bsf b/Lab3/src/Altpll/Altpll.bsf similarity index 100% rename from Lab3/Altpll/Altpll.bsf rename to Lab3/src/Altpll/Altpll.bsf diff --git a/Lab3/Altpll/Altpll.cmp b/Lab3/src/Altpll/Altpll.cmp similarity index 100% rename from Lab3/Altpll/Altpll.cmp rename to Lab3/src/Altpll/Altpll.cmp diff --git a/Lab3/Altpll/Altpll.html b/Lab3/src/Altpll/Altpll.html similarity index 100% rename from Lab3/Altpll/Altpll.html rename to Lab3/src/Altpll/Altpll.html diff --git a/Lab3/Altpll/Altpll.xml b/Lab3/src/Altpll/Altpll.xml similarity index 100% rename from Lab3/Altpll/Altpll.xml rename to Lab3/src/Altpll/Altpll.xml diff --git a/Lab3/Altpll/Altpll_bb.v b/Lab3/src/Altpll/Altpll_bb.v similarity index 100% rename from Lab3/Altpll/Altpll_bb.v rename to Lab3/src/Altpll/Altpll_bb.v diff --git a/Lab3/Altpll/Altpll_generation.rpt b/Lab3/src/Altpll/Altpll_generation.rpt similarity index 100% rename from Lab3/Altpll/Altpll_generation.rpt rename to Lab3/src/Altpll/Altpll_generation.rpt diff --git a/Lab3/Altpll/Altpll_inst.v b/Lab3/src/Altpll/Altpll_inst.v similarity index 100% rename from Lab3/Altpll/Altpll_inst.v rename to Lab3/src/Altpll/Altpll_inst.v diff --git a/Lab3/Altpll/Altpll_inst.vhd b/Lab3/src/Altpll/Altpll_inst.vhd similarity index 100% rename from Lab3/Altpll/Altpll_inst.vhd rename to Lab3/src/Altpll/Altpll_inst.vhd diff --git a/Lab3/Altpll/synthesis/Altpll.debuginfo.xml b/Lab3/src/Altpll/synthesis/Altpll.debuginfo.xml similarity index 100% rename from Lab3/Altpll/synthesis/Altpll.debuginfo.xml rename to Lab3/src/Altpll/synthesis/Altpll.debuginfo.xml diff --git a/Lab3/Altpll/synthesis/Altpll.qip b/Lab3/src/Altpll/synthesis/Altpll.qip similarity index 100% rename from Lab3/Altpll/synthesis/Altpll.qip rename to Lab3/src/Altpll/synthesis/Altpll.qip diff --git a/Lab3/Altpll/synthesis/Altpll.v b/Lab3/src/Altpll/synthesis/Altpll.v similarity index 100% rename from Lab3/Altpll/synthesis/Altpll.v rename to Lab3/src/Altpll/synthesis/Altpll.v diff --git a/Lab3/Altpll/synthesis/submodules/Altpll_altpll_0.v b/Lab3/src/Altpll/synthesis/submodules/Altpll_altpll_0.v similarity index 100% rename from Lab3/Altpll/synthesis/submodules/Altpll_altpll_0.v rename to Lab3/src/Altpll/synthesis/submodules/Altpll_altpll_0.v diff --git a/Lab3/Altpll/synthesis/submodules/altera_reset_controller.sdc b/Lab3/src/Altpll/synthesis/submodules/altera_reset_controller.sdc similarity index 100% rename from Lab3/Altpll/synthesis/submodules/altera_reset_controller.sdc rename to Lab3/src/Altpll/synthesis/submodules/altera_reset_controller.sdc diff --git a/Lab3/Altpll/synthesis/submodules/altera_reset_controller.v b/Lab3/src/Altpll/synthesis/submodules/altera_reset_controller.v similarity index 100% rename from Lab3/Altpll/synthesis/submodules/altera_reset_controller.v rename to Lab3/src/Altpll/synthesis/submodules/altera_reset_controller.v diff --git a/Lab3/Altpll/synthesis/submodules/altera_reset_synchronizer.v b/Lab3/src/Altpll/synthesis/submodules/altera_reset_synchronizer.v similarity index 100% rename from Lab3/Altpll/synthesis/submodules/altera_reset_synchronizer.v rename to Lab3/src/Altpll/synthesis/submodules/altera_reset_synchronizer.v