diff --git a/base/general/rtl/RstPipelineVector.vhd b/base/general/rtl/RstPipelineVector.vhd
new file mode 100644
index 0000000000..c68c4a334d
--- /dev/null
+++ b/base/general/rtl/RstPipelineVector.vhd
@@ -0,0 +1,58 @@
+-------------------------------------------------------------------------------
+-- File : RstPipelineVector.vhd
+-- Company : SLAC National Accelerator Laboratory
+-- Created : 2018-05-03
+-- Last update: 2018-05-03
+-------------------------------------------------------------------------------
+-- Description: Wrapper for multiple RstPipeline modules
+-------------------------------------------------------------------------------
+-- This file is part of 'SLAC Firmware Standard Library'.
+-- It is subject to the license terms in the LICENSE.txt file found in the
+-- top-level directory of this distribution and at:
+-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+-- No part of 'SLAC Firmware Standard Library', including this file,
+-- may be copied, modified, propagated, or distributed except according to
+-- the terms contained in the LICENSE.txt file.
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.StdRtlPkg.all;
+
+entity RstPipelineVector is
+ generic (
+ TPD_G : time := 1 ns;
+ INV_RST_G : boolean := false;
+ PIPE_STAGES_G : positive := 3;
+ MAX_FANOUT_G : positive := 16384;
+ INIT_G : slv := "1";
+ WIDTH_G : positive := 16);
+ port (
+ clk : in sl;
+ rstIn : in slv(WIDTH_G-1 downto 0);
+ rstOut : out slv(WIDTH_G-1 downto 0));
+end RstPipelineVector;
+
+architecture mapping of RstPipelineVector is
+
+begin
+
+ GEN_VEC :
+ for i in (WIDTH_G-1) downto 0 generate
+
+ U_RstPipeline : entity work.RstPipeline
+ generic map (
+ TPD_G => TPD_G,
+ INV_RST_G => INV_RST_G,
+ PIPE_STAGES_G => PIPE_STAGES_G,
+ MAX_FANOUT_G => MAX_FANOUT_G,
+ INIT_G => INIT_G)
+ port map (
+ clk => clk,
+ rstIn => rstIn(i),
+ rstOut => rstOut(i));
+
+ end generate GEN_VEC;
+
+end architecture mapping;
diff --git a/devices/transceivers/cxp/rtl/AxiI2cCxpCore.vhd b/devices/transceivers/cxp/rtl/AxiI2cCxpCore.vhd
deleted file mode 100644
index 2de2d44501..0000000000
--- a/devices/transceivers/cxp/rtl/AxiI2cCxpCore.vhd
+++ /dev/null
@@ -1,136 +0,0 @@
--------------------------------------------------------------------------------
--- File : AxiI2cCxpCore.vhd
--- Company : SLAC National Accelerator Laboratory
--- Created : 2014-10-21
--- Last update: 2018-01-08
--------------------------------------------------------------------------------
--- Description: AXI-Lite interface to CXP
--------------------------------------------------------------------------------
--- This file is part of 'SLAC Firmware Standard Library'.
--- It is subject to the license terms in the LICENSE.txt file found in the
--- top-level directory of this distribution and at:
--- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
--- No part of 'SLAC Firmware Standard Library', including this file,
--- may be copied, modified, propagated, or distributed except according to
--- the terms contained in the LICENSE.txt file.
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.StdRtlPkg.all;
-use work.AxiLitePkg.all;
-use work.I2cPkg.all;
-use work.AxiI2cCxpPkg.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
-entity AxiI2cCxpCore is
- generic (
- TPD_G : time := 1 ns;
- AXI_CLK_FREQ_G : real := 200.0E+6; -- units of Hz
- I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz
- I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds
- STATUS_CNT_WIDTH_G : natural range 1 to 32 := 32);
- port (
- -- CXP Ports
- cxpIn : in AxiI2cCxpInType;
- cxpInOut : inout AxiI2cCxpInOutType;
- -- AXI-Lite Register Interface
- axiReadMaster : in AxiLiteReadMasterType;
- axiReadSlave : out AxiLiteReadSlaveType;
- axiWriteMaster : in AxiLiteWriteMasterType;
- axiWriteSlave : out AxiLiteWriteSlaveType;
- -- Clocks and Resets
- axiClk : in sl;
- axiRst : in sl);
-end AxiI2cCxpCore;
-
-architecture mapping of AxiI2cCxpCore is
-
- -- Note: PRESCALE_G = (clk_freq / (5 * i2c_freq)) - 1
- -- FILTER_G = (min_pulse_time / clk_period) + 1
- constant I2C_SCL_5xFREQ_C : real := 5.0 * I2C_SCL_FREQ_G;
- constant PRESCALE_C : natural := (getTimeRatio(AXI_CLK_FREQ_G, I2C_SCL_5xFREQ_C)) - 1;
- constant FILTER_C : natural := natural(AXI_CLK_FREQ_G * I2C_MIN_PULSE_G) + 1;
-
- signal i2cRegMasterIn : I2cRegMasterInType;
- signal i2cRegMasterOut : I2cRegMasterOutType;
-
- signal i2ci : i2c_in_type;
- signal i2co : i2c_out_type;
-
- signal status : AxiI2cCxpStatusType;
- signal config : AxiI2cCxpConfigType;
-
- signal irqRstL : sl;
- signal oeL : sl;
-
-begin
-
- IOBUF_SCL : IOBUF
- port map (
- O => i2ci.scl, -- Buffer output
- IO => cxpInOut.scl, -- Buffer inout port (connect directly to top-level port)
- I => i2co.scl, -- Buffer input
- T => i2co.scloen); -- 3-state enable input, high=input, low=output
-
- IOBUF_SDA : IOBUF
- port map (
- O => i2ci.sda, -- Buffer output
- IO => cxpInOut.sda, -- Buffer inout port (connect directly to top-level port)
- I => i2co.sda, -- Buffer input
- T => i2co.sdaoen); -- 3-state enable input, high=input, low=output
-
- IOBUF_RST : IOBUF
- port map (
- O => irqRstL, -- Buffer output
- IO => cxpInOut.irqRstL, -- Buffer inout port (connect directly to top-level port)
- I => '0', -- Buffer input
- T => oeL); -- 3-state enable input, high=input, low=output
-
- oeL <= not(config.rst);
-
- status.irq <= not(irqRstL);
- status.moduleDet <= not(cxpIn.moduleDetL);
-
- AxiI2cCxpReg_Inst : entity work.AxiI2cCxpReg
- generic map(
- TPD_G => TPD_G,
- STATUS_CNT_WIDTH_G => STATUS_CNT_WIDTH_G)
- port map(
- -- I2C Register Interface
- i2cRegMasterIn => i2cRegMasterIn,
- i2cRegMasterOut => i2cRegMasterOut,
- -- AXI-Lite Register Interface
- axiReadMaster => axiReadMaster,
- axiReadSlave => axiReadSlave,
- axiWriteMaster => axiWriteMaster,
- axiWriteSlave => axiWriteSlave,
- -- Register Inputs/Outputs
- status => status,
- config => config,
- -- Clock and Reset
- axiClk => axiClk,
- axiRst => axiRst);
-
- I2cRegMaster_Inst : entity work.I2cRegMaster
- generic map(
- TPD_G => TPD_G,
- OUTPUT_EN_POLARITY_G => 0,
- FILTER_G => FILTER_C,
- PRESCALE_G => PRESCALE_C)
- port map (
- -- I2C Port Interface
- i2ci => i2ci,
- i2co => i2co,
- -- I2C Register Interface
- regIn => i2cRegMasterIn,
- regOut => i2cRegMasterOut,
- -- Clock and Reset
- clk => axiClk,
- srst => axiRst);
-
-end mapping;
diff --git a/devices/transceivers/cxp/rtl/AxiI2cCxpPkg.vhd b/devices/transceivers/cxp/rtl/AxiI2cCxpPkg.vhd
deleted file mode 100644
index 8050c82391..0000000000
--- a/devices/transceivers/cxp/rtl/AxiI2cCxpPkg.vhd
+++ /dev/null
@@ -1,59 +0,0 @@
--------------------------------------------------------------------------------
--- File : AxiI2cCxpPkg.vhd
--- Company : SLAC National Accelerator Laboratory
--- Created : 2014-10-21
--- Last update: 2016-09-20
--------------------------------------------------------------------------------
--- Description: AxiI2cCxp Package File
--------------------------------------------------------------------------------
--- This file is part of 'SLAC Firmware Standard Library'.
--- It is subject to the license terms in the LICENSE.txt file found in the
--- top-level directory of this distribution and at:
--- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
--- No part of 'SLAC Firmware Standard Library', including this file,
--- may be copied, modified, propagated, or distributed except according to
--- the terms contained in the LICENSE.txt file.
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-use work.StdRtlPkg.all;
-
-package AxiI2cCxpPkg is
-
- type AxiI2cCxpInType is record
- moduleDetL : sl; -- Module Present = PRSNT_L
- end record;
- type AxiI2cCxpInArray is array (natural range <>) of AxiI2cCxpInType;
- type AxiI2cCxpInVectorArray is array (integer range<>, integer range<>)of AxiI2cCxpInType;
- constant AXI_SFP_IN_INIT_C : AxiI2cCxpInType := (
- moduleDetL => '1');
-
- type AxiI2cCxpInOutType is record
- irqRstL : sl; -- Interrupt / Reset = Int_L/Reset_L
- scl : sl; -- Two-wire serial interface clock
- sda : sl; -- Two-wire serial interface data
- end record;
- type AxiI2cCxpInOutArray is array (natural range <>) of AxiI2cCxpInOutType;
- type AxiI2cCxpInOutVectorArray is array (integer range<>, integer range<>)of AxiI2cCxpInOutType;
- constant AXI_SFP_IN_OUT_INIT_C : AxiI2cCxpInOutType := (
- irqRstL => 'Z',
- scl => 'Z',
- sda => 'Z');
-
- type AxiI2cCxpStatusType is record
- irq : sl;
- moduleDet : sl;
- end record;
- constant AXI_SFP_STATUS_INIT_C : AxiI2cCxpStatusType := (
- irq => '0',
- moduleDet => '0');
-
- type AxiI2cCxpConfigType is record
- rst : sl;
- end record;
- constant AXI_SFP_CONFIG_INIT_C : AxiI2cCxpConfigType := (
- rst => '0');
-
-end package;
diff --git a/devices/transceivers/cxp/rtl/AxiI2cCxpReg.vhd b/devices/transceivers/cxp/rtl/AxiI2cCxpReg.vhd
deleted file mode 100644
index 842cadd70e..0000000000
--- a/devices/transceivers/cxp/rtl/AxiI2cCxpReg.vhd
+++ /dev/null
@@ -1,149 +0,0 @@
--------------------------------------------------------------------------------
--- File : AxiI2cCxpReg.vhd
--- Company : SLAC National Accelerator Laboratory
--- Created : 2014-10-21
--- Last update: 2018-01-08
--------------------------------------------------------------------------------
--- Description: AXI-Lite Register Access Module
--------------------------------------------------------------------------------
--- This file is part of 'SLAC Firmware Standard Library'.
--- It is subject to the license terms in the LICENSE.txt file found in the
--- top-level directory of this distribution and at:
--- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
--- No part of 'SLAC Firmware Standard Library', including this file,
--- may be copied, modified, propagated, or distributed except according to
--- the terms contained in the LICENSE.txt file.
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-use work.StdRtlPkg.all;
-use work.AxiLitePkg.all;
-use work.AxiI2cCxpPkg.all;
-use work.I2cPkg.all;
-
-entity AxiI2cCxpReg is
- generic (
- TPD_G : time := 1 ns;
- STATUS_CNT_WIDTH_G : natural range 1 to 32 := 32);
- port (
- -- I2C Register Interface
- i2cRegMasterIn : out I2cRegMasterInType;
- i2cRegMasterOut : in I2cRegMasterOutType;
- -- AXI-Lite Register Interface
- axiReadMaster : in AxiLiteReadMasterType;
- axiReadSlave : out AxiLiteReadSlaveType;
- axiWriteMaster : in AxiLiteWriteMasterType;
- axiWriteSlave : out AxiLiteWriteSlaveType;
- -- Register Inputs/Outputs
- status : in AxiI2cCxpStatusType;
- config : out AxiI2cCxpConfigType;
- -- Global Signals
- axiClk : in sl;
- axiRst : in sl);
-end AxiI2cCxpReg;
-
-architecture rtl of AxiI2cCxpReg is
-
- constant TX_INDEX_C : natural := 0;
- constant RX_INDEX_C : natural := 1;
-
- constant DEVICE_MAP_C : I2cAxiLiteDevArray(0 to 1) := (
- TX_INDEX_C => MakeI2cAxiLiteDevType(
- i2cAddress => "1010000", -- TX Memory Map
- dataSize => 8, -- in units of bits
- addrSize => 8, -- in units of bits
- endianness => '1'), -- Big Endian
- RX_INDEX_C => MakeI2cAxiLiteDevType(
- i2cAddress => "1010100", -- RX Memory Map
- dataSize => 8, -- in units of bits
- addrSize => 8, -- in units of bits
- endianness => '1')); -- Big Endian
-
- constant NUM_WRITE_REG_C : positive := 3;
- constant STATUS_SIZE_C : positive := 2;
- constant NUM_READ_REG_C : positive := (STATUS_SIZE_C+1);
-
- constant WRITE_REG_INIT_C : Slv32Array(0 to NUM_WRITE_REG_C-1) := (
- 0 => x"00000000", -- config.rst
- 1 => x"00000000", -- rollOverEn
- 2 => x"00000000"); -- cntRst
-
- signal cntRst : sl;
- signal rollOverEn : slv(STATUS_SIZE_C-1 downto 0);
- signal cntOut : SlVectorArray(STATUS_SIZE_C-1 downto 0, STATUS_CNT_WIDTH_G-1 downto 0);
-
- signal regIn : AxiI2cCxpStatusType;
-
- signal readRegister : Slv32Array(0 to NUM_READ_REG_C-1) := (others => x"00000000");
- signal writeRegister : Slv32Array(0 to NUM_WRITE_REG_C-1) := (others => x"00000000");
-
-begin
-
- I2cRegMasterAxiBridge_Inst : entity work.I2cRegMasterAxiBridge
- generic map (
- TPD_G => TPD_G,
- DEVICE_MAP_G => DEVICE_MAP_C,
- EN_USER_REG_G => true,
- NUM_WRITE_REG_G => (NUM_WRITE_REG_C-1),
- NUM_READ_REG_G => (NUM_READ_REG_C-1))
- port map (
- -- I2C Interface
- i2cRegMasterIn => i2cRegMasterIn,
- i2cRegMasterOut => i2cRegMasterOut,
- -- AXI-Lite Register Interface
- axiReadMaster => axiReadMaster,
- axiReadSlave => axiReadSlave,
- axiWriteMaster => axiWriteMaster,
- axiWriteSlave => axiWriteSlave,
- -- Optional User Read/Write Register Interface
- readRegister => readRegister,
- writeRegisterInit => WRITE_REG_INIT_C,
- writeRegister => writeRegister,
- -- Clock and Reset
- axiClk => axiClk,
- axiRst => axiRst);
-
- -------------------------------
- -- Synchronization: Outputs
- -------------------------------
- config.rst <= writeRegister(0)(0);
- rollOverEn <= writeRegister(1)(STATUS_SIZE_C-1 downto 0);
- cntRst <= writeRegister(2)(0);
-
- -------------------------------
- -- Synchronization: Inputs
- -------------------------------
- SyncStatusVec_Inst : entity work.SyncStatusVector
- generic map (
- TPD_G => TPD_G,
- OUT_POLARITY_G => '1',
- CNT_RST_EDGE_G => true,
- COMMON_CLK_G => true,
- CNT_WIDTH_G => STATUS_CNT_WIDTH_G,
- WIDTH_G => STATUS_SIZE_C)
- port map (
- -- Input Status bit Signals (wrClk domain)
- statusIn(1) => status.irq,
- statusIn(0) => status.moduleDet,
- -- Output Status bit Signals (rdClk domain)
- statusOut(1) => regIn.irq,
- statusOut(0) => regIn.moduleDet,
- -- Status Bit Counters Signals (rdClk domain)
- cntRstIn => cntRst,
- rollOverEnIn => rollOverEn,
- cntOut => cntOut,
- -- Clocks and Reset Ports
- wrClk => axiClk,
- rdClk => axiClk);
-
- readRegister(2)(1) <= regIn.irq;
- readRegister(2)(0) <= regIn.moduleDet;
-
- readRegister(1)(STATUS_CNT_WIDTH_G-1 downto 0) <= muxSlVectorArray(cntOut, 1); -- irqCnt
- readRegister(0)(STATUS_CNT_WIDTH_G-1 downto 0) <= muxSlVectorArray(cntOut, 0); -- moduleDetCnt
-
-end rtl;
diff --git a/devices/transceivers/cxp/ruckus.tcl b/devices/transceivers/cxp/ruckus.tcl
deleted file mode 100644
index 6fa215e9f8..0000000000
--- a/devices/transceivers/cxp/ruckus.tcl
+++ /dev/null
@@ -1,5 +0,0 @@
-# Load RUCKUS library
-source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
-
-# Load Source Code
-loadSource -dir "$::DIR_PATH/rtl/"
diff --git a/devices/transceivers/qsfp/rtl/AxiI2cQsfpCore.vhd b/devices/transceivers/qsfp/rtl/AxiI2cQsfpCore.vhd
deleted file mode 100644
index 177bd3d3c5..0000000000
--- a/devices/transceivers/qsfp/rtl/AxiI2cQsfpCore.vhd
+++ /dev/null
@@ -1,129 +0,0 @@
--------------------------------------------------------------------------------
--- File : AxiI2cQsfpCore.vhd
--- Company : SLAC National Accelerator Laboratory
--- Created : 2014-04-24
--- Last update: 2018-01-08
--------------------------------------------------------------------------------
--- Description: AXI-Lite interface to QSFP
--------------------------------------------------------------------------------
--- This file is part of 'SLAC Firmware Standard Library'.
--- It is subject to the license terms in the LICENSE.txt file found in the
--- top-level directory of this distribution and at:
--- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
--- No part of 'SLAC Firmware Standard Library', including this file,
--- may be copied, modified, propagated, or distributed except according to
--- the terms contained in the LICENSE.txt file.
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.StdRtlPkg.all;
-use work.AxiLitePkg.all;
-use work.I2cPkg.all;
-use work.AxiI2cQsfpPkg.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
-entity AxiI2cQsfpCore is
- generic (
- TPD_G : time := 1 ns;
- AXI_CLK_FREQ_G : real := 200.0E+6; -- units of Hz
- I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz
- I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds
- STATUS_CNT_WIDTH_G : natural range 1 to 32 := 32);
- port (
- -- QSFP Ports
- qsfpIn : in AxiI2cQsfpInType;
- qsfpInOut : inout AxiI2cQsfpInOutType;
- qsfpOut : out AxiI2cQsfpOutType;
- -- AXI-Lite Register Interface
- axiReadMaster : in AxiLiteReadMasterType;
- axiReadSlave : out AxiLiteReadSlaveType;
- axiWriteMaster : in AxiLiteWriteMasterType;
- axiWriteSlave : out AxiLiteWriteSlaveType;
- -- Clocks and Resets
- axiClk : in sl;
- axiRst : in sl);
-end AxiI2cQsfpCore;
-
-architecture mapping of AxiI2cQsfpCore is
-
- -- Note: PRESCALE_G = (clk_freq / (5 * i2c_freq)) - 1
- -- FILTER_G = (min_pulse_time / clk_period) + 1
- constant I2C_SCL_5xFREQ_C : real := 5.0 * I2C_SCL_FREQ_G;
- constant PRESCALE_C : natural := (getTimeRatio(AXI_CLK_FREQ_G, I2C_SCL_5xFREQ_C)) - 1;
- constant FILTER_C : natural := natural(AXI_CLK_FREQ_G * I2C_MIN_PULSE_G) + 1;
-
- signal i2cRegMasterIn : I2cRegMasterInType;
- signal i2cRegMasterOut : I2cRegMasterOutType;
-
- signal i2ci : i2c_in_type;
- signal i2co : i2c_out_type;
-
- signal status : AxiI2cQsfpStatusType;
- signal config : AxiI2cQsfpConfigType;
-
-begin
-
- IOBUF_SCL : IOBUF
- port map (
- O => i2ci.scl, -- Buffer output
- IO => qsfpInOut.scl, -- Buffer inout port (connect directly to top-level port)
- I => i2co.scl, -- Buffer input
- T => i2co.scloen); -- 3-state enable input, high=input, low=output
-
- IOBUF_SDA : IOBUF
- port map (
- O => i2ci.sda, -- Buffer output
- IO => qsfpInOut.sda, -- Buffer inout port (connect directly to top-level port)
- I => i2co.sda, -- Buffer input
- T => i2co.sdaoen); -- 3-state enable input, high=input, low=output
-
- qsfpOut.modSelL <= not(config.modSel);
- qsfpOut.rstL <= not(config.rst);
- qsfpOut.lpMode <= config.lpMode;
-
- status.modPrst <= not(qsfpIn.modPrstL);
- status.interrupt <= not(qsfpIn.intL);
-
- AxiI2cQsfpReg_Inst : entity work.AxiI2cQsfpReg
- generic map(
- TPD_G => TPD_G,
- STATUS_CNT_WIDTH_G => STATUS_CNT_WIDTH_G)
- port map(
- -- I2C Register Interface
- i2cRegMasterIn => i2cRegMasterIn,
- i2cRegMasterOut => i2cRegMasterOut,
- -- AXI-Lite Register Interface
- axiReadMaster => axiReadMaster,
- axiReadSlave => axiReadSlave,
- axiWriteMaster => axiWriteMaster,
- axiWriteSlave => axiWriteSlave,
- -- Register Inputs/Outputs
- status => status,
- config => config,
- -- Clock and Reset
- axiClk => axiClk,
- axiRst => axiRst);
-
- I2cRegMaster_Inst : entity work.I2cRegMaster
- generic map(
- TPD_G => TPD_G,
- OUTPUT_EN_POLARITY_G => 0,
- FILTER_G => FILTER_C,
- PRESCALE_G => PRESCALE_C)
- port map (
- -- I2C Port Interface
- i2ci => i2ci,
- i2co => i2co,
- -- I2C Register Interface
- regIn => i2cRegMasterIn,
- regOut => i2cRegMasterOut,
- -- Clock and Reset
- clk => axiClk,
- srst => axiRst);
-
-end mapping;
diff --git a/devices/transceivers/qsfp/rtl/AxiI2cQsfpPkg.vhd b/devices/transceivers/qsfp/rtl/AxiI2cQsfpPkg.vhd
deleted file mode 100644
index 4ae3cd8e87..0000000000
--- a/devices/transceivers/qsfp/rtl/AxiI2cQsfpPkg.vhd
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- File : AxiI2cQsfpPkg.vhd
--- Company : SLAC National Accelerator Laboratory
--- Created : 2014-10-21
--- Last update: 2017-05-02
--------------------------------------------------------------------------------
--- Description: AxiI2cQsfp Package File
--------------------------------------------------------------------------------
--- This file is part of 'SLAC Firmware Standard Library'.
--- It is subject to the license terms in the LICENSE.txt file found in the
--- top-level directory of this distribution and at:
--- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
--- No part of 'SLAC Firmware Standard Library', including this file,
--- may be copied, modified, propagated, or distributed except according to
--- the terms contained in the LICENSE.txt file.
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-use work.StdRtlPkg.all;
-
-package AxiI2cQsfpPkg is
-
- type AxiI2cQsfpInType is record
- modPrstL : sl; -- Module Present
- -- ModPrsL is pulled up to Vcc_Host on the host board and
- -- grounded in the module. The ModPrsL is asserted "Low"
- -- when module is inserted into the host connector, and
- -- deasserted "High" when the module is physically absent
- -- from the host connector.
- intL : sl; -- Interrupt
- -- IntL is an output signal. When "Low", it indicates a possible module operational fault or a status critical to the
- -- host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL signal is an
- -- open collector output and must be pulled to host supply
- -- voltage on the host board. A corresponding soft status
- -- IntL signal is also available in the transceiver memory
- -- page 0 address 2 bit 1.
- end record;
- type AxiI2cQsfpInArray is array (natural range <>) of AxiI2cQsfpInType;
- type AxiI2cQsfpInVectorArray is array (integer range<>, integer range<>)of AxiI2cQsfpInType;
- constant AXI_QSFP_IN_INIT_C : AxiI2cQsfpInType := (
- '1',
- '1');
-
- type AxiI2cQsfpInOutType is record
- scl : sl; -- 2-wire serial interface clock (SCL)
- sda : sl; -- 2-wire serial interface data (SDA)
- end record;
- type AxiI2cQsfpInOutArray is array (natural range <>) of AxiI2cQsfpInOutType;
- type AxiI2cQsfpInOutVectorArray is array (integer range<>, integer range<>)of AxiI2cQsfpInOutType;
- constant AXI_QSFP_IN_OUT_INIT_C : AxiI2cQsfpInOutType := (
- 'Z',
- 'Z');
-
- type AxiI2cQsfpOutType is record
- modSelL : sl; -- Module Select
- -- The ModSelL is an input signal. When held low by the
- -- host, the module responds to 2-wire serial communication commands. The ModSelL allows the use of multiple
- -- QSFP+ modules on a single 2-wire interface bus. When
- -- the ModSelL is "High", the module will not respond to or
- -- acknowledge any 2-wire interface communication from
- -- the host. ModSelL signal input node is biased to the "High"
- -- state in the module. In order to avoid conflicts, the host
- -- system shall not attempt 2-wire interface communications within the ModSelL de-assert time after any QSFP+
- -- module is deselected. Similarly, the host must wait at least
- -- for the period of the ModSelL assert time before communicating with the newly selected module. The assertion and
- -- de-assertion periods of different modules may overlap as
- -- long as the above timing requirements are met.
- rstL : sl; -- Module Reset
- -- The ResetL signal is pulled to Vcc in the QSFP+ module.
- -- A low level on the ResetL signal for longer than the
- -- minimum pulse length (t_Reset_init) initiates a complete
- -- module reset, returning all user module settings to their
- -- default state. Module Reset Assert Time (t_init) starts on
- -- the rising edge after the low level on the ResetL pin is
- -- released. During the execution of a reset (t_init) the host
- -- shall disregard all status bits until the module indicates a
- -- completion of the reset interrupt. The module indicates
- -- this by posting an IntL signal with the Data_Not_Ready bit
- -- negated. Note that on power up (including hot insertion)
- -- the module will post this completion of reset interrupt
- -- without requiring a reset.
- lpMode : sl; -- Low Power Mode
- -- Low power mode. When held high by host, the module
- -- is held at low power mode. When held low by host, the
- -- module operates in the normal mode. For class 1 power
- -- level modules (1.5W), low power mode has no effect.
- end record;
- type AxiI2cQsfpOutArray is array (natural range <>) of AxiI2cQsfpOutType;
- type AxiI2cQsfpOutVectorArray is array (integer range<>, integer range<>)of AxiI2cQsfpOutType;
- constant AXI_QSFP_OUT_INIT_C : AxiI2cQsfpOutType := (
- '1',
- '1',
- '0');
-
- type AxiI2cQsfpStatusType is record
- modPrst : sl;
- interrupt : sl;
- end record;
- constant AXI_QSFP_STATUS_INIT_C : AxiI2cQsfpStatusType := (
- '1',
- '1');
-
- type AxiI2cQsfpConfigType is record
- modSel : sl;
- rst : sl;
- lpMode : sl;
- end record;
- constant AXI_QSFP_CONFIG_INIT_C : AxiI2cQsfpConfigType := (
- '1',
- '1',
- '0');
-
-end package;
diff --git a/devices/transceivers/qsfp/rtl/AxiI2cQsfpReg.vhd b/devices/transceivers/qsfp/rtl/AxiI2cQsfpReg.vhd
deleted file mode 100644
index d64d94a221..0000000000
--- a/devices/transceivers/qsfp/rtl/AxiI2cQsfpReg.vhd
+++ /dev/null
@@ -1,142 +0,0 @@
--------------------------------------------------------------------------------
--- File : AxiI2cQsfpReg.vhd
--- Company : SLAC National Accelerator Laboratory
--- Created : 2014-04-24
--- Last update: 2018-01-08
--------------------------------------------------------------------------------
--- Description: AXI-Lite Register Access Module
--------------------------------------------------------------------------------
--- This file is part of 'SLAC Firmware Standard Library'.
--- It is subject to the license terms in the LICENSE.txt file found in the
--- top-level directory of this distribution and at:
--- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
--- No part of 'SLAC Firmware Standard Library', including this file,
--- may be copied, modified, propagated, or distributed except according to
--- the terms contained in the LICENSE.txt file.
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-use work.StdRtlPkg.all;
-use work.AxiLitePkg.all;
-use work.AxiI2cQsfpPkg.all;
-use work.I2cPkg.all;
-
-entity AxiI2cQsfpReg is
- generic (
- TPD_G : time := 1 ns;
- STATUS_CNT_WIDTH_G : natural range 1 to 32 := 32);
- port (
- -- I2C Register Interface
- i2cRegMasterIn : out I2cRegMasterInType;
- i2cRegMasterOut : in I2cRegMasterOutType;
- -- AXI-Lite Register Interface
- axiReadMaster : in AxiLiteReadMasterType;
- axiReadSlave : out AxiLiteReadSlaveType;
- axiWriteMaster : in AxiLiteWriteMasterType;
- axiWriteSlave : out AxiLiteWriteSlaveType;
- -- Register Inputs/Outputs
- status : in AxiI2cQsfpStatusType;
- config : out AxiI2cQsfpConfigType;
- -- Global Signals
- axiClk : in sl;
- axiRst : in sl);
-end AxiI2cQsfpReg;
-
-architecture rtl of AxiI2cQsfpReg is
-
- constant DEVICE_MAP_C : I2cAxiLiteDevArray(0 to 1) := (
- 0 => MakeI2cAxiLiteDevType(
- i2cAddress => "1010000", -- Configuration PROM
- dataSize => 8, -- in units of bits
- addrSize => 8, -- in units of bits
- endianness => '1'), -- Big endian
- 1 => MakeI2cAxiLiteDevType(
- i2cAddress => "1010001", -- Diagnostic Monitoring
- dataSize => 8, -- in units of bits
- addrSize => 8, -- in units of bits
- endianness => '1')); -- Big endian
-
- constant NUM_WRITE_REG_C : positive := 5;
- constant STATUS_SIZE_C : positive := 2;
- constant NUM_READ_REG_C : positive := (STATUS_SIZE_C+1);
-
- signal cntRst : sl;
- signal rollOverEn : slv(STATUS_SIZE_C-1 downto 0);
- signal cntOut : SlVectorArray(STATUS_SIZE_C-1 downto 0, STATUS_CNT_WIDTH_G-1 downto 0);
-
- signal regIn : AxiI2cQsfpStatusType;
-
- signal readRegister : Slv32Array(0 to NUM_READ_REG_C-1) := (others => x"00000000");
- signal writeRegister : Slv32Array(0 to NUM_WRITE_REG_C-1) := (others => x"00000000");
-
-begin
-
- I2cRegMasterAxiBridge_Inst : entity work.I2cRegMasterAxiBridge
- generic map (
- TPD_G => TPD_G,
- DEVICE_MAP_G => DEVICE_MAP_C,
- EN_USER_REG_G => true,
- NUM_WRITE_REG_G => NUM_WRITE_REG_C-1,
- NUM_READ_REG_G => NUM_READ_REG_C-1)
- port map (
- -- I2C Interface
- i2cRegMasterIn => i2cRegMasterIn,
- i2cRegMasterOut => i2cRegMasterOut,
- -- AXI-Lite Register Interface
- axiReadMaster => axiReadMaster,
- axiReadSlave => axiReadSlave,
- axiWriteMaster => axiWriteMaster,
- axiWriteSlave => axiWriteSlave,
- -- Optional User Read/Write Register Interface
- readRegister => readRegister,
- writeRegister => writeRegister,
- -- Clock and Reset
- axiClk => axiClk,
- axiRst => axiRst);
-
- -------------------------------
- -- Synchronization: Outputs
- -------------------------------
- config.modSel <= writeRegister(0)(0);
- config.rst <= writeRegister(1)(0);
- config.lpMode <= writeRegister(2)(0);
- rollOverEn <= writeRegister(3)(STATUS_SIZE_C-1 downto 0);
- cntRst <= writeRegister(4)(0);
-
- -------------------------------
- -- Synchronization: Inputs
- -------------------------------
- SyncStatusVec_Inst : entity work.SyncStatusVector
- generic map (
- TPD_G => TPD_G,
- OUT_POLARITY_G => '1',
- CNT_RST_EDGE_G => true,
- COMMON_CLK_G => true,
- CNT_WIDTH_G => STATUS_CNT_WIDTH_G,
- WIDTH_G => STATUS_SIZE_C)
- port map (
- -- Input Status bit Signals (wrClk domain)
- statusIn(1) => status.modPrst,
- statusIn(0) => status.interrupt,
- -- Output Status bit Signals (rdClk domain)
- statusOut(1) => regIn.modPrst,
- statusOut(0) => regIn.interrupt,
- -- Status Bit Counters Signals (rdClk domain)
- cntRstIn => cntRst,
- rollOverEnIn => rollOverEn,
- cntOut => cntOut,
- -- Clocks and Reset Ports
- wrClk => axiClk,
- rdClk => axiClk);
-
- readRegister(2)(1) <= regIn.modPrst;
- readRegister(2)(0) <= regIn.interrupt;
-
- readRegister(1)(STATUS_CNT_WIDTH_G-1 downto 0) <= muxSlVectorArray(cntOut, 1); -- modPrstCnt
- readRegister(0)(STATUS_CNT_WIDTH_G-1 downto 0) <= muxSlVectorArray(cntOut, 0); -- interruptCnt
-
-end rtl;
diff --git a/devices/transceivers/qsfp/ruckus.tcl b/devices/transceivers/qsfp/ruckus.tcl
deleted file mode 100644
index 6fa215e9f8..0000000000
--- a/devices/transceivers/qsfp/ruckus.tcl
+++ /dev/null
@@ -1,5 +0,0 @@
-# Load RUCKUS library
-source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
-
-# Load Source Code
-loadSource -dir "$::DIR_PATH/rtl/"
diff --git a/devices/transceivers/rtl/Sff8472.vhd b/devices/transceivers/rtl/Sff8472.vhd
new file mode 100644
index 0000000000..f3d5828905
--- /dev/null
+++ b/devices/transceivers/rtl/Sff8472.vhd
@@ -0,0 +1,85 @@
+-------------------------------------------------------------------------------
+-- File : Sff8472.vhd
+-- Company : SLAC National Accelerator Laboratory
+-- Created : 2018-05-07
+-- Last update: 2018-05-07
+-------------------------------------------------------------------------------
+-- Description: Optical Module SFF-8472 Wrapper (I2C for SFP, QSFP, etc)
+-------------------------------------------------------------------------------
+-- This file is part of 'SLAC Firmware Standard Library'.
+-- It is subject to the license terms in the LICENSE.txt file found in the
+-- top-level directory of this distribution and at:
+-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+-- No part of 'SLAC Firmware Standard Library', including this file,
+-- may be copied, modified, propagated, or distributed except according to
+-- the terms contained in the LICENSE.txt file.
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+use work.StdRtlPkg.all;
+use work.AxiLitePkg.all;
+use work.I2cPkg.all;
+
+entity Sff8472 is
+ generic (
+ TPD_G : time := 1 ns;
+ I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz
+ I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds
+ AXI_CLK_FREQ_G : real := 156.25E+6); -- units of Hz
+ port (
+ -- I2C Ports
+ scl : inout sl;
+ sda : inout sl;
+ -- AXI-Lite Register Interface
+ axilReadMaster : in AxiLiteReadMasterType;
+ axilReadSlave : out AxiLiteReadSlaveType;
+ axilWriteMaster : in AxiLiteWriteMasterType;
+ axilWriteSlave : out AxiLiteWriteSlaveType;
+ -- Clocks and Resets
+ axilClk : in sl;
+ axilRst : in sl);
+end Sff8472;
+
+architecture mapping of Sff8472 is
+
+ constant DEVICE_MAP_C : I2cAxiLiteDevArray(0 to 1) := (
+ 0 => MakeI2cAxiLiteDevType(
+ i2cAddress => "1010000", -- Configuration PROM
+ dataSize => 8, -- in units of bits
+ addrSize => 8, -- in units of bits
+ endianness => '0', -- Little endian
+ repeatStart => '0'), -- Repeat start
+ 1 => MakeI2cAxiLiteDevType( -- Enhanced interface
+ i2cAddress => "1010001", -- Diagnostic Monitoring
+ dataSize => 8, -- in units of bits
+ addrSize => 8, -- in units of bits
+ endianness => '0', -- Little endian
+ repeatStart => '0')); -- Repeat Start
+
+begin
+
+ U_AxiI2C : entity work.AxiI2cRegMaster
+ generic map (
+ TPD_G => TPD_G,
+ DEVICE_MAP_G => DEVICE_MAP_C,
+ I2C_SCL_FREQ_G => I2C_SCL_FREQ_G,
+ I2C_MIN_PULSE_G => I2C_MIN_PULSE_G,
+ AXI_CLK_FREQ_G => AXI_CLK_FREQ_G)
+ port map (
+ -- I2C Ports
+ scl => scl,
+ sda => sda,
+ -- AXI-Lite Register Interface
+ axiReadMaster => axilReadMaster,
+ axiReadSlave => axilReadSlave,
+ axiWriteMaster => axilWriteMaster,
+ axiWriteSlave => axilWriteSlave,
+ -- Clocks and Resets
+ axiClk => axilClk,
+ axiRst => axilRst);
+
+end mapping;
diff --git a/devices/transceivers/ruckus.tcl b/devices/transceivers/ruckus.tcl
index e9c1ccd1c9..12c89db2b5 100644
--- a/devices/transceivers/ruckus.tcl
+++ b/devices/transceivers/ruckus.tcl
@@ -1,7 +1,5 @@
# Load RUCKUS environment and library
source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
-# Load ruckus files
-loadRuckusTcl "$::DIR_PATH/cxp"
-loadRuckusTcl "$::DIR_PATH/qsfp"
-loadRuckusTcl "$::DIR_PATH/sfp"
+# Load Source Code
+loadSource -dir "$::DIR_PATH/rtl"
diff --git a/devices/transceivers/sfp/rtl/AxiI2cSfpCore.vhd b/devices/transceivers/sfp/rtl/AxiI2cSfpCore.vhd
deleted file mode 100644
index 14ee584db2..0000000000
--- a/devices/transceivers/sfp/rtl/AxiI2cSfpCore.vhd
+++ /dev/null
@@ -1,144 +0,0 @@
--------------------------------------------------------------------------------
--- File : AxiI2cSfpCore.vhd
--- Company : SLAC National Accelerator Laboratory
--- Created : 2014-04-18
--- Last update: 2018-01-08
--------------------------------------------------------------------------------
--- Description: AXI-Lite interface to SFP
--------------------------------------------------------------------------------
--- This file is part of 'SLAC Firmware Standard Library'.
--- It is subject to the license terms in the LICENSE.txt file found in the
--- top-level directory of this distribution and at:
--- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
--- No part of 'SLAC Firmware Standard Library', including this file,
--- may be copied, modified, propagated, or distributed except according to
--- the terms contained in the LICENSE.txt file.
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.StdRtlPkg.all;
-use work.AxiLitePkg.all;
-use work.I2cPkg.all;
-use work.AxiI2cSfpPkg.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
-entity AxiI2cSfpCore is
- generic (
- TPD_G : time := 1 ns;
- AXI_CLK_FREQ_G : real := 200.0E+6; -- units of Hz
- I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz
- I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds
- STATUS_CNT_WIDTH_G : natural range 1 to 32 := 32;
- ALLOW_TX_DISABLE_G : boolean := false);
- port (
- -- SFP Ports
- sfpIn : in AxiI2cSfpInType;
- sfpInOut : inout AxiI2cSfpInOutType;
- sfpOut : out AxiI2cSfpOutType;
- -- AXI-Lite Register Interface
- axiReadMaster : in AxiLiteReadMasterType;
- axiReadSlave : out AxiLiteReadSlaveType;
- axiWriteMaster : in AxiLiteWriteMasterType;
- axiWriteSlave : out AxiLiteWriteSlaveType;
- -- Clocks and Resets
- axiClk : in sl;
- axiRst : in sl);
-end AxiI2cSfpCore;
-
-architecture mapping of AxiI2cSfpCore is
-
- -- Note: PRESCALE_G = (clk_freq / (5 * i2c_freq)) - 1
- -- FILTER_G = (min_pulse_time / clk_period) + 1
- constant I2C_SCL_5xFREQ_C : real := 5.0 * I2C_SCL_FREQ_G;
- constant PRESCALE_C : natural := (getTimeRatio(AXI_CLK_FREQ_G, I2C_SCL_5xFREQ_C)) - 1;
- constant FILTER_C : natural := natural(AXI_CLK_FREQ_G * I2C_MIN_PULSE_G) + 1;
-
- signal i2cRegMasterIn : I2cRegMasterInType;
- signal i2cRegMasterOut : I2cRegMasterOutType;
-
- signal i2ci : i2c_in_type;
- signal i2co : i2c_out_type;
-
- signal status : AxiI2cSfpStatusType;
- signal config : AxiI2cSfpConfigType;
-
-begin
-
- IOBUF_SCL : IOBUF
- port map (
- O => i2ci.scl, -- Buffer output
- IO => sfpInOut.scl, -- Buffer inout port (connect directly to top-level port)
- I => i2co.scl, -- Buffer input
- T => i2co.scloen); -- 3-state enable input, high=input, low=output
-
- IOBUF_SDA : IOBUF
- port map (
- O => i2ci.sda, -- Buffer output
- IO => sfpInOut.sda, -- Buffer inout port (connect directly to top-level port)
- I => i2co.sda, -- Buffer input
- T => i2co.sdaoen); -- 3-state enable input, high=input, low=output
-
- IOBUF_RATE0 : IOBUF
- port map (
- O => open, -- Buffer output
- IO => sfpInOut.rateSel(0), -- Buffer inout port (connect directly to top-level port)
- I => config.rateSel(0), -- Buffer input
- T => '0'); -- 3-state enable input, high=input, low=output
-
- IOBUF_RATE1 : IOBUF -- Reserved for future use
- port map (
- O => open, -- Buffer output
- IO => sfpInOut.rateSel(1), -- Buffer inout port (connect directly to top-level port)
- I => '0', -- Buffer input
- T => '1'); -- 3-state enable input, high=input, low=output
-
- sfpOut.txDisable <= config.txDisable;
-
- status.rxLoss <= sfpIn.rxLoss;
- status.moduleDetL <= sfpIn.moduleDetL;
- status.txFault <= sfpIn.txFault;
-
- AxiI2cSfpReg_Inst : entity work.AxiI2cSfpReg
- generic map(
- TPD_G => TPD_G,
- STATUS_CNT_WIDTH_G => STATUS_CNT_WIDTH_G,
- ALLOW_TX_DISABLE_G => ALLOW_TX_DISABLE_G)
- port map(
- -- I2C Register Interface
- i2cRegMasterIn => i2cRegMasterIn,
- i2cRegMasterOut => i2cRegMasterOut,
- -- AXI-Lite Register Interface
- axiReadMaster => axiReadMaster,
- axiReadSlave => axiReadSlave,
- axiWriteMaster => axiWriteMaster,
- axiWriteSlave => axiWriteSlave,
- -- Register Inputs/Outputs
- status => status,
- config => config,
- -- Clock and Reset
- axiClk => axiClk,
- axiRst => axiRst);
-
- I2cRegMaster_Inst : entity work.I2cRegMaster
- generic map(
- TPD_G => TPD_G,
- OUTPUT_EN_POLARITY_G => 0,
- FILTER_G => FILTER_C,
- PRESCALE_G => PRESCALE_C)
- port map (
- -- I2C Port Interface
- i2ci => i2ci,
- i2co => i2co,
- -- I2C Register Interface
- regIn => i2cRegMasterIn,
- regOut => i2cRegMasterOut,
- -- Clock and Reset
- clk => axiClk,
- srst => axiRst);
-
-end mapping;
diff --git a/devices/transceivers/sfp/rtl/AxiI2cSfpPkg.vhd b/devices/transceivers/sfp/rtl/AxiI2cSfpPkg.vhd
deleted file mode 100644
index ecef32eb86..0000000000
--- a/devices/transceivers/sfp/rtl/AxiI2cSfpPkg.vhd
+++ /dev/null
@@ -1,74 +0,0 @@
--------------------------------------------------------------------------------
--- File : AxiI2cSfpPkg.vhd
--- Company : SLAC National Accelerator Laboratory
--- Created : 2014-04-18
--- Last update: 2017-05-02
--------------------------------------------------------------------------------
--- Description: AxiI2cSfp Package File
--------------------------------------------------------------------------------
--- This file is part of 'SLAC Firmware Standard Library'.
--- It is subject to the license terms in the LICENSE.txt file found in the
--- top-level directory of this distribution and at:
--- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
--- No part of 'SLAC Firmware Standard Library', including this file,
--- may be copied, modified, propagated, or distributed except according to
--- the terms contained in the LICENSE.txt file.
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-use work.StdRtlPkg.all;
-
-package AxiI2cSfpPkg is
-
- type AxiI2cSfpInType is record
- rxLoss : sl; -- Loss of Signal - High indicates loss of received optical signal
- moduleDetL : sl; -- Module Definition 0 (MOD-DEF0) - Grounded in module (module present indicator)
- txFault : sl; -- Transmitter Fault Indication - High indicates a fault condition
- end record;
- type AxiI2cSfpInArray is array (natural range <>) of AxiI2cSfpInType;
- type AxiI2cSfpInVectorArray is array (integer range<>, integer range<>)of AxiI2cSfpInType;
- constant AXI_SFP_IN_INIT_C : AxiI2cSfpInType := (
- '0',
- '0',
- '0');
-
- type AxiI2cSfpInOutType is record
- rateSel : slv(1 downto 0); -- Bit Rate Parametric Optimization
- scl : sl; -- Module Definition 1 (MOD-DEF1) - Two wire serial ID interface clock line (SCL)
- sda : sl; -- Module Definition 2 (MOD-DEF2) - Two wire serial ID interface data line (SDA)
- end record;
- type AxiI2cSfpInOutArray is array (natural range <>) of AxiI2cSfpInOutType;
- type AxiI2cSfpInOutVectorArray is array (integer range<>, integer range<>)of AxiI2cSfpInOutType;
- constant AXI_SFP_IN_OUT_INIT_C : AxiI2cSfpInOutType := (
- (others => 'Z'),
- 'Z',
- 'Z');
-
- type AxiI2cSfpOutType is record
- txDisable : sl; -- Transmitter Disable - Module electrical input disables on high or open
- end record;
- type AxiI2cSfpOutArray is array (natural range <>) of AxiI2cSfpOutType;
- type AxiI2cSfpOutVectorArray is array (integer range<>, integer range<>)of AxiI2cSfpOutType;
- constant AXI_SFP_OUT_INIT_C : AxiI2cSfpOutType := (txDisable => '0');
-
- type AxiI2cSfpStatusType is record
- rxLoss : sl;
- moduleDetL : sl;
- txFault : sl;
- end record;
- constant AXI_SFP_STATUS_INIT_C : AxiI2cSfpStatusType := (
- '0',
- '0',
- '0');
-
- type AxiI2cSfpConfigType is record
- rateSel : slv(1 downto 0);
- txDisable : sl;
- end record;
- constant AXI_SFP_CONFIG_INIT_C : AxiI2cSfpConfigType := (
- (others => '1'),
- '0');
-
-end package;
diff --git a/devices/transceivers/sfp/rtl/AxiI2cSfpReg.vhd b/devices/transceivers/sfp/rtl/AxiI2cSfpReg.vhd
deleted file mode 100644
index 68e01b103a..0000000000
--- a/devices/transceivers/sfp/rtl/AxiI2cSfpReg.vhd
+++ /dev/null
@@ -1,153 +0,0 @@
--------------------------------------------------------------------------------
--- File : AxiI2cSfpReg.vhd
--- Company : SLAC National Accelerator Laboratory
--- Created : 2014-04-18
--- Last update: 2018-01-08
--------------------------------------------------------------------------------
--- Description: AXI-Lite Register Acess Module
--------------------------------------------------------------------------------
--- This file is part of 'SLAC Firmware Standard Library'.
--- It is subject to the license terms in the LICENSE.txt file found in the
--- top-level directory of this distribution and at:
--- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
--- No part of 'SLAC Firmware Standard Library', including this file,
--- may be copied, modified, propagated, or distributed except according to
--- the terms contained in the LICENSE.txt file.
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-use work.StdRtlPkg.all;
-use work.AxiLitePkg.all;
-use work.AxiI2cSfpPkg.all;
-use work.I2cPkg.all;
-
-entity AxiI2cSfpReg is
- generic (
- TPD_G : time := 1 ns;
- STATUS_CNT_WIDTH_G : natural range 1 to 32 := 32;
- ALLOW_TX_DISABLE_G : boolean := false);
- port (
- -- I2C Register Interface
- i2cRegMasterIn : out I2cRegMasterInType;
- i2cRegMasterOut : in I2cRegMasterOutType;
- -- AXI-Lite Register Interface
- axiReadMaster : in AxiLiteReadMasterType;
- axiReadSlave : out AxiLiteReadSlaveType;
- axiWriteMaster : in AxiLiteWriteMasterType;
- axiWriteSlave : out AxiLiteWriteSlaveType;
- -- Register Inputs/Outputs
- status : in AxiI2cSfpStatusType;
- config : out AxiI2cSfpConfigType;
- -- Global Signals
- axiClk : in sl;
- axiRst : in sl);
-end AxiI2cSfpReg;
-
-architecture rtl of AxiI2cSfpReg is
-
- constant DEVICE_MAP_C : I2cAxiLiteDevArray(0 to 1) := (
- 0 => MakeI2cAxiLiteDevType(
- i2cAddress => "1010000", -- Configuration PROM
- dataSize => 8, -- in units of bits
- addrSize => 8, -- in units of bits
- endianness => '1'), -- Big endian
- 1 => MakeI2cAxiLiteDevType(
- i2cAddress => "1010001", -- Diagnostic Monitoring
- dataSize => 8, -- in units of bits
- addrSize => 8, -- in units of bits
- endianness => '1')); -- Big endian
-
- constant NUM_WRITE_REG_C : positive := 4;
- constant STATUS_SIZE_C : positive := 3;
- constant NUM_READ_REG_C : positive := (STATUS_SIZE_C+1);
-
- constant WRITE_REG_INIT_C : Slv32Array(0 to NUM_WRITE_REG_C-1) := (
- 0 => x"00000000", -- config.txDisable
- 1 => x"00000003", -- config.rateSel
- 2 => x"00000000", -- rollOverEn
- 3 => x"00000000"); -- cntRst
-
- signal cntRst : sl;
- signal rollOverEn : slv(STATUS_SIZE_C-1 downto 0);
- signal cntOut : SlVectorArray(STATUS_SIZE_C-1 downto 0, STATUS_CNT_WIDTH_G-1 downto 0);
-
- signal regIn : AxiI2cSfpStatusType;
-
- signal readRegister : Slv32Array(0 to NUM_READ_REG_C-1) := (others => x"00000000");
- signal writeRegister : Slv32Array(0 to NUM_WRITE_REG_C-1) := (others => x"00000000");
-
-begin
-
- I2cRegMasterAxiBridge_Inst : entity work.I2cRegMasterAxiBridge
- generic map (
- TPD_G => TPD_G,
- DEVICE_MAP_G => DEVICE_MAP_C,
- EN_USER_REG_G => true,
- NUM_WRITE_REG_G => NUM_WRITE_REG_C-1,
- NUM_READ_REG_G => NUM_READ_REG_C-1)
- port map (
- -- I2C Interface
- i2cRegMasterIn => i2cRegMasterIn,
- i2cRegMasterOut => i2cRegMasterOut,
- -- AXI-Lite Register Interface
- axiReadMaster => axiReadMaster,
- axiReadSlave => axiReadSlave,
- axiWriteMaster => axiWriteMaster,
- axiWriteSlave => axiWriteSlave,
- -- Optional User Read/Write Register Interface
- readRegister => readRegister,
- writeRegisterInit => WRITE_REG_INIT_C,
- writeRegister => writeRegister,
- -- Clock and Reset
- axiClk => axiClk,
- axiRst => axiRst);
-
- -------------------------------
- -- Synchronization: Outputs
- -------------------------------
- config.txDisable <= writeRegister(0)(0) when(ALLOW_TX_DISABLE_G = true) else '0';
- config.rateSel <= writeRegister(1)(1 downto 0);
- rollOverEn <= writeRegister(2)(STATUS_SIZE_C-1 downto 0);
- cntRst <= writeRegister(3)(0);
-
- -------------------------------
- -- Synchronization: Inputs
- -------------------------------
- SyncStatusVec_Inst : entity work.SyncStatusVector
- generic map (
- TPD_G => TPD_G,
- OUT_POLARITY_G => '1',
- CNT_RST_EDGE_G => true,
- COMMON_CLK_G => true,
- CNT_WIDTH_G => STATUS_CNT_WIDTH_G,
- WIDTH_G => STATUS_SIZE_C)
- port map (
- -- Input Status bit Signals (wrClk domain)
- statusIn(2) => status.txFault,
- statusIn(1) => status.moduleDetL,
- statusIn(0) => status.rxLoss,
- -- Output Status bit Signals (rdClk domain)
- statusOut(2) => regIn.txFault,
- statusOut(1) => regIn.moduleDetL,
- statusOut(0) => regIn.rxLoss,
- -- Status Bit Counters Signals (rdClk domain)
- cntRstIn => cntRst,
- rollOverEnIn => rollOverEn,
- cntOut => cntOut,
- -- Clocks and Reset Ports
- wrClk => axiClk,
- rdClk => axiClk);
-
- readRegister(3)(2) <= regIn.txFault;
- readRegister(3)(1) <= regIn.moduleDetL;
- readRegister(3)(0) <= regIn.rxLoss;
-
- readRegister(2)(STATUS_CNT_WIDTH_G-1 downto 0) <= muxSlVectorArray(cntOut, 2); -- txFaultCnt
- readRegister(1)(STATUS_CNT_WIDTH_G-1 downto 0) <= muxSlVectorArray(cntOut, 1); -- moduleDetCnt
- readRegister(0)(STATUS_CNT_WIDTH_G-1 downto 0) <= muxSlVectorArray(cntOut, 0); -- rxLossCnt
-
-end rtl;
diff --git a/devices/transceivers/sfp/ruckus.tcl b/devices/transceivers/sfp/ruckus.tcl
deleted file mode 100644
index 6fa215e9f8..0000000000
--- a/devices/transceivers/sfp/ruckus.tcl
+++ /dev/null
@@ -1,5 +0,0 @@
-# Load RUCKUS library
-source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
-
-# Load Source Code
-loadSource -dir "$::DIR_PATH/rtl/"
diff --git a/protocols/jesd204b/rtl/Jesd204bPkg.vhd b/protocols/jesd204b/rtl/Jesd204bPkg.vhd
index 409554b8d3..2028d42b35 100644
--- a/protocols/jesd204b/rtl/Jesd204bPkg.vhd
+++ b/protocols/jesd204b/rtl/Jesd204bPkg.vhd
@@ -394,8 +394,8 @@ package body Jesd204bPkg is
vSlv := (others => '0');
- for I in (SAMPLES_IN_WORD_C-1) downto 0 loop
- vSlv(I*8*F_int+8*F_int-1) := '1';
+ for i in (SAMPLES_IN_WORD_C-1) downto 0 loop
+ vSlv(i*8*F_int+8*F_int-1) := '1';
end loop;
return vSlv;
@@ -418,8 +418,8 @@ package body Jesd204bPkg is
vSlv := data;
- for I in (SAMPLES_IN_WORD_C-1) downto 0 loop
- vSlv(I*8*F_int+8*F_int-1 downto I*8*F_int) := invSigned(vSlv(I*8*F_int+8*F_int-1 downto I*8*F_int));
+ for i in (SAMPLES_IN_WORD_C-1) downto 0 loop
+ vSlv(i*8*F_int+8*F_int-1 downto i*8*F_int) := invSigned(vSlv(i*8*F_int+8*F_int-1 downto i*8*F_int));
end loop;
return vSlv;
diff --git a/protocols/jesd204b/rtl/Jesd204bRx.vhd b/protocols/jesd204b/rtl/Jesd204bRx.vhd
index 94cd6e463f..7522cae413 100644
--- a/protocols/jesd204b/rtl/Jesd204bRx.vhd
+++ b/protocols/jesd204b/rtl/Jesd204bRx.vhd
@@ -2,7 +2,7 @@
-- File : Jesd204bRx.vhd
-- Company : SLAC National Accelerator Laboratory
-- Created : 2015-04-14
--- Last update: 2018-01-08
+-- Last update: 2018-05-03
-------------------------------------------------------------------------------
-- Description: JESD204b multi-lane receiver module
-- Receiver JESD204b module.
@@ -94,14 +94,15 @@ entity Jesd204bRx is
r_jesdGtRxArr : in jesdGtRxLaneTypeArray(L_G-1 downto 0);
gtRxReset_o : out slv(L_G-1 downto 0);
- rxPolarity : out slv(L_G-1 downto 0);
-
+ rxPowerDown : out slv(L_G-1 downto 0);
+ rxPolarity : out slv(L_G-1 downto 0);
+
-- Synchronization output combined from all receivers
nSync_o : out sl;
-
+
-- Debug signals
pulse_o : out slv(L_G-1 downto 0);
- leds_o : out slv(1 downto 0)
+ leds_o : out slv(1 downto 0)
);
end Jesd204bRx;
@@ -138,12 +139,12 @@ architecture rtl of Jesd204bRx is
signal s_enableRx : slv(L_G-1 downto 0);
signal s_replEnable : sl;
signal s_scrEnable : sl;
- signal s_invertData : slv(L_G-1 downto 0);
-
+ signal s_invertData : slv(L_G-1 downto 0);
+
-- JESD subclass selection (from AXI lite register)
- signal s_subClass : sl;
+ signal s_subClass : sl;
-- User reset (from AXI lite register)
- signal s_gtReset : sl;
+ signal s_gtReset : sl;
signal s_invertSync : sl;
signal s_clearErr : sl;
@@ -156,7 +157,7 @@ architecture rtl of Jesd204bRx is
signal s_alignTxArr : alignTxArray(L_G-1 downto 0);
- signal s_sampleDataArr : sampleDataArray(L_G-1 downto 0);
+ signal s_sampleDataArr : sampleDataArray(L_G-1 downto 0);
-- Sysref conditioning
signal s_sysrefSync : sl;
@@ -177,21 +178,21 @@ begin
assert (F_G = 1 or F_G = 2 or (F_G = 4 and GT_WORD_SIZE_C = 4)) report "F_G setting must be 1,2,or 4*" severity failure;
-- Legacy Interface that we will remove in the future
- rxAxisMasterArr_o <= (others => AXI_STREAM_MASTER_INIT_C);
-
+ rxAxisMasterArr_o <= (others => AXI_STREAM_MASTER_INIT_C);
+
-----------------------------------------------------------
-- AXI Lite AXI clock domain crossed
-----------------------------------------------------------
-
- GEN_rawData : for I in L_G-1 downto 0 generate
- s_rawData(I) <= s_jesdGtRxArr(I).data;
+
+ GEN_rawData : for i in L_G-1 downto 0 generate
+ s_rawData(i) <= s_jesdGtRxArr(i).data;
end generate GEN_rawData;
-
+
-- axiLite register interface
U_Reg : entity work.JesdRxReg
generic map (
- TPD_G => TPD_G,
- L_G => L_G)
+ TPD_G => TPD_G,
+ L_G => L_G)
port map (
axiClk_i => axiClk,
axiRst_i => axiRst,
@@ -203,6 +204,7 @@ begin
-- DevClk domain
devClk_i => devClk_i,
devRst_i => devRst_i,
+ sysrefRe_i => s_sysrefRe,
statusRxArr_i => s_statusRxArr,
rawData_i => s_rawData,
linkErrMask_o => s_linkErrMask,
@@ -216,9 +218,10 @@ begin
gtReset_o => s_gtReset,
clearErr_o => s_clearErr,
invertSync_o => s_invertSync,
- invertData_o => s_invertData,
+ invertData_o => s_invertData,
thresoldHighArr_o => s_thresoldHighArr,
thresoldLowArr_o => s_thresoldLowArr,
+ rxPowerDown => rxPowerDown,
rxPolarity => rxPolarity);
-----------------------------------------------------------
@@ -229,19 +232,19 @@ begin
-- Generate TX test core if TEST_G=true is selected
TEST_GEN : if TEST_G = true generate
-----------------------------------------
- TX_LANES_GEN : for I in L_G-1 downto 0 generate
+ TX_LANES_GEN : for i in L_G-1 downto 0 generate
JesdTxTest_INST : entity work.JesdTxTest
generic map (
TPD_G => TPD_G)
port map (
devClk_i => devClk_i,
devRst_i => devRst_i,
- enable_i => s_enableRx(I),
- delay_i => s_dlyTxArr(I),
- align_i => s_alignTxArr(I),
+ enable_i => s_enableRx(i),
+ delay_i => s_dlyTxArr(i),
+ align_i => s_alignTxArr(i),
lmfc_i => s_lmfc,
nSync_i => r.nSyncAnyD1,
- r_jesdGtRx => s_jesdGtRxArr(I),
+ r_jesdGtRx => s_jesdGtRxArr(i),
subClass_i => s_subClass,
txDataValid_o => open);
end generate TX_LANES_GEN;
@@ -310,36 +313,36 @@ begin
-----------------------------------------------------------
-- JESD Receiver modules (one module per Lane)
- generateRxLanes : for I in L_G-1 downto 0 generate
+ generateRxLanes : for i in L_G-1 downto 0 generate
JesdRx_INST : entity work.JesdRxLane
generic map (
TPD_G => TPD_G,
F_G => F_G,
K_G => K_G)
port map (
- devClk_i => devClk_i,
- devRst_i => devRst_i,
- sysRef_i => s_sysrefRe, -- Rising-edge of SYSREF
- enable_i => s_enableRx(I),
- clearErr_i => s_clearErr,
- linkErrMask_i=> s_linkErrMask,
- replEnable_i => s_replEnable,
- scrEnable_i => s_scrEnable,
- inv_i => s_invertData(I),
- status_o => s_statusRxArr(I),
- r_jesdGtRx => s_jesdGtRxArr(I),
- lmfc_i => s_lmfc,
- nSyncAnyD1_i => r.nSyncAnyD1,
- nSyncAny_i => s_nSyncAny,
- nSync_o => s_nSyncVec(I),
- dataValid_o => s_dataValidVec(I),
- sampleData_o => s_sampleDataArr(I),
- subClass_i => s_subClass
+ devClk_i => devClk_i,
+ devRst_i => devRst_i,
+ sysRef_i => s_sysrefRe, -- Rising-edge of SYSREF
+ enable_i => s_enableRx(i),
+ clearErr_i => s_clearErr,
+ linkErrMask_i => s_linkErrMask,
+ replEnable_i => s_replEnable,
+ scrEnable_i => s_scrEnable,
+ inv_i => s_invertData(i),
+ status_o => s_statusRxArr(i),
+ r_jesdGtRx => s_jesdGtRxArr(i),
+ lmfc_i => s_lmfc,
+ nSyncAnyD1_i => r.nSyncAnyD1,
+ nSyncAny_i => s_nSyncAny,
+ nSync_o => s_nSyncVec(i),
+ dataValid_o => s_dataValidVec(i),
+ sampleData_o => s_sampleDataArr(i),
+ subClass_i => s_subClass
);
end generate;
-- Test signal generator
- generatePulserLanes : for I in L_G-1 downto 0 generate
+ generatePulserLanes : for i in L_G-1 downto 0 generate
Pulser_INST : entity work.JesdTestSigGen
generic map (
TPD_G => TPD_G,
@@ -347,23 +350,23 @@ begin
port map (
clk => devClk_i,
rst => devRst_i,
- enable_i => s_dataValidVec(I),
- thresoldLow_i => s_thresoldLowArr(I),
- thresoldHigh_i => s_thresoldHighArr(I),
- sampleData_i => s_sampleDataArr(I),
- testSig_o => pulse_o(I));
+ enable_i => s_dataValidVec(i),
+ thresoldLow_i => s_thresoldLowArr(i),
+ thresoldHigh_i => s_thresoldHighArr(i),
+ sampleData_i => s_sampleDataArr(i),
+ testSig_o => pulse_o(i));
end generate;
-- Put sync output in 'z' if not enabled
- syncVectEn : for I in L_G-1 downto 0 generate
- s_nSyncVecEn(I) <= s_nSyncVec(I) or not s_enableRx(I);
+ syncVectEn : for i in L_G-1 downto 0 generate
+ s_nSyncVecEn(i) <= s_nSyncVec(i) or not s_enableRx(i);
end generate syncVectEn;
-- Combine nSync signals from all receivers
s_nSyncAny <= '0' when allBits (s_enableRx, '0') else uAnd(s_nSyncVecEn);
-- DFF
- comb : process (r, devRst_i, s_nSyncAll, s_nSyncAny) is
+ comb : process (devRst_i, s_nSyncAny) is
variable v : RegType;
begin
v.nSyncAnyD1 := s_nSyncAny;
diff --git a/protocols/jesd204b/rtl/Jesd204bTx.vhd b/protocols/jesd204b/rtl/Jesd204bTx.vhd
index 334c529938..ab158ebc5e 100644
--- a/protocols/jesd204b/rtl/Jesd204bTx.vhd
+++ b/protocols/jesd204b/rtl/Jesd204bTx.vhd
@@ -41,16 +41,16 @@ use work.Jesd204bPkg.all;
entity Jesd204bTx is
generic (
- TPD_G : time := 1 ns;
+ TPD_G : time := 1 ns;
-- Register sample data at input and/or output
- INPUT_REG_G : boolean := false;
- OUTPUT_REG_G : boolean := false;
+ INPUT_REG_G : boolean := false;
+ OUTPUT_REG_G : boolean := false;
-- Number of bytes in a frame
- F_G : positive := 2;
+ F_G : positive := 2;
-- Number of frames in a multi frame
- K_G : positive := 32;
+ K_G : positive := 32;
-- Number of TX lanes (1 to 32)
- L_G : positive range 1 to 32 := 2);
+ L_G : positive range 1 to 32 := 2);
port (
-- AXI interface
-- Clocks and Resets
@@ -87,15 +87,16 @@ entity Jesd204bTx is
-- Data and character inputs from GT (transceivers)
r_jesdGtTxArr : out jesdGtTxLaneTypeArray(L_G-1 downto 0);
-
+
-- TX Configurable Driver Ports
- txDiffCtrl : out Slv8Array(L_G-1 downto 0);
- txPostCursor : out Slv8Array(L_G-1 downto 0);
- txPreCursor : out Slv8Array(L_G-1 downto 0);
- txPolarity : out slv(L_G-1 downto 0);
- loopback : out slv(L_G-1 downto 0);
- txEnable : out slv(L_G-1 downto 0);
- txEnableL : out slv(L_G-1 downto 0);
+ txDiffCtrl : out Slv8Array(L_G-1 downto 0);
+ txPostCursor : out Slv8Array(L_G-1 downto 0);
+ txPreCursor : out Slv8Array(L_G-1 downto 0);
+ txPowerDown : out slv(L_G-1 downto 0);
+ txPolarity : out slv(L_G-1 downto 0);
+ loopback : out slv(L_G-1 downto 0);
+ txEnable : out slv(L_G-1 downto 0);
+ txEnableL : out slv(L_G-1 downto 0);
-- Debug signals
pulse_o : out slv(L_G-1 downto 0);
@@ -161,16 +162,16 @@ begin
-- Legacy Interface that we will remove in the future
txAxisSlaveArr_o <= (others => AXI_STREAM_SLAVE_FORCE_C);
-
+
----------------------
-- Input data register
----------------------
GEN_REG_I : if (INPUT_REG_G = true) generate
- GEN_LANE : for I in L_G-1 downto 0 generate
+ GEN_LANE : for i in L_G-1 downto 0 generate
process(devClk_i)
begin
if rising_edge(devClk_i) then
- s_regSampleDataIn(I) <= extSampleDataArray_i(I) after TPD_G;
+ s_regSampleDataIn(i) <= extSampleDataArray_i(i) after TPD_G;
end if;
end process;
end generate GEN_LANE;
@@ -180,59 +181,61 @@ begin
s_regSampleDataIn <= extSampleDataArray_i;
end generate GEN_N_REG_I;
- GEN_VALID : for I in L_G-1 downto 0 generate
- s_dataValid(I) <= s_statusTxArr(I)(1);
+ GEN_VALID : for i in L_G-1 downto 0 generate
+ s_dataValid(i) <= s_statusTxArr(i)(1);
end generate GEN_VALID;
txEnable <= s_enableTx;
txEnableL <= not(s_enableTx);
-
+
---------------------
-- AXI-Lite registers
---------------------
U_Reg : entity work.JesdTxReg
generic map (
- TPD_G => TPD_G,
- L_G => L_G,
- F_G => F_G)
+ TPD_G => TPD_G,
+ L_G => L_G,
+ F_G => F_G)
port map (
- axiClk_i => axiClk,
- axiRst_i => axiRst,
- axilReadMaster => axilReadMaster,
- axilReadSlave => axilReadSlave,
- axilWriteMaster => axilWriteMaster,
- axilWriteSlave => axilWriteSlave,
+ axiClk_i => axiClk,
+ axiRst_i => axiRst,
+ axilReadMaster => axilReadMaster,
+ axilReadSlave => axilReadSlave,
+ axilWriteMaster => axilWriteMaster,
+ axilWriteSlave => axilWriteSlave,
-- DevClk domain
- devClk_i => devClk_i,
- devRst_i => devRst_i,
- statusTxArr_i => s_statusTxArr,
- muxOutSelArr_o => s_muxOutSelArr,
- sysrefDlyTx_o => s_sysrefDlyTx,
- enableTx_o => s_enableTx,
- replEnable_o => s_replEnable,
- scrEnable_o => s_scrEnable,
- invertData_o => s_invertData,
- subClass_o => s_subClass,
- gtReset_o => s_gtReset,
- clearErr_o => s_clearErr,
- sigTypeArr_o => s_sigTypeArr,
- posAmplitude_o => s_posAmplitude,
- negAmplitude_o => s_negAmplitude,
- rampStep_o => s_rampStep,
- squarePeriod_o => s_squarePeriod,
- enableTestSig_o => s_enableTestSig,
- invertSync_o => s_invertSync,
+ devClk_i => devClk_i,
+ devRst_i => devRst_i,
+ sysrefRe_i => s_sysrefRe,
+ statusTxArr_i => s_statusTxArr,
+ muxOutSelArr_o => s_muxOutSelArr,
+ sysrefDlyTx_o => s_sysrefDlyTx,
+ enableTx_o => s_enableTx,
+ replEnable_o => s_replEnable,
+ scrEnable_o => s_scrEnable,
+ invertData_o => s_invertData,
+ subClass_o => s_subClass,
+ gtReset_o => s_gtReset,
+ clearErr_o => s_clearErr,
+ sigTypeArr_o => s_sigTypeArr,
+ posAmplitude_o => s_posAmplitude,
+ negAmplitude_o => s_negAmplitude,
+ rampStep_o => s_rampStep,
+ squarePeriod_o => s_squarePeriod,
+ enableTestSig_o => s_enableTestSig,
+ invertSync_o => s_invertSync,
-- TX Configurable Driver Ports
- txDiffCtrl => txDiffCtrl,
- txPostCursor => txPostCursor,
- txPreCursor => txPreCursor,
- txPolarity => txPolarity,
- loopback => loopback);
-
- GEN_TEST : for I in L_G-1 downto 0 generate
+ txDiffCtrl => txDiffCtrl,
+ txPostCursor => txPostCursor,
+ txPreCursor => txPreCursor,
+ txPowerDown => txPowerDown,
+ txPolarity => txPolarity,
+ loopback => loopback);
+
+ GEN_TEST : for i in L_G-1 downto 0 generate
-- Check the test pattern enable bit
- s_testEn(I) <= s_dataValid(I) and s_enableTestSig;
+ s_testEn(i) <= s_dataValid(i) and s_enableTestSig;
U_TestStream : entity work.JesdTestStreamTx
generic map (
@@ -241,35 +244,35 @@ begin
port map (
clk => devClk_i,
rst => devRst_i,
- enable_i => s_testEn(I),
+ enable_i => s_testEn(i),
rampStep_i => s_rampStep,
squarePeriod_i => s_squarePeriod,
posAmplitude_i => s_posAmplitude,
negAmplitude_i => s_negAmplitude,
- type_i => s_sigTypeArr(I),
- pulse_o => pulse_o(I),
- sampleData_o => s_testDataArr(I));
+ type_i => s_sigTypeArr(i),
+ pulse_o => pulse_o(i),
+ sampleData_o => s_testDataArr(i));
end generate GEN_TEST;
-- Sample data mux
- GEN_MUX : for I in L_G-1 downto 0 generate
+ GEN_MUX : for i in L_G-1 downto 0 generate
-- Swap endian (the module is built to use big endian data but the interface is little endian)
- s_extDataArraySwap(I) <= endianSwapSlv(s_regSampleDataIn(I), GT_WORD_SIZE_C);
+ s_extDataArraySwap(i) <= endianSwapSlv(s_regSampleDataIn(i), GT_WORD_SIZE_C);
-- Separate mux for separate lane
process(devClk_i)
begin
if rising_edge(devClk_i) then
- if (s_muxOutSelArr(I) = "000") then
- s_sampleDataArr(I) <= outSampleZero(F_G, GT_WORD_SIZE_C) after TPD_G;
- elsif (s_muxOutSelArr(I) = "001") then
- s_sampleDataArr(I) <= s_extDataArraySwap(I) after TPD_G;
- elsif (s_muxOutSelArr(I) = "010") then
- s_sampleDataArr(I) <= (others => '1') after TPD_G;
+ if (s_muxOutSelArr(i) = "000") then
+ s_sampleDataArr(i) <= outSampleZero(F_G, GT_WORD_SIZE_C) after TPD_G;
+ elsif (s_muxOutSelArr(i) = "001") then
+ s_sampleDataArr(i) <= s_extDataArraySwap(i) after TPD_G;
+ elsif (s_muxOutSelArr(i) = "010") then
+ s_sampleDataArr(i) <= (others => '1') after TPD_G;
else
- s_sampleDataArr(I) <= s_testDataArr(I) after TPD_G;
+ s_sampleDataArr(i) <= s_testDataArr(i) after TPD_G;
end if;
end if;
end process;
@@ -345,7 +348,7 @@ begin
----------------------------
-- Transmitter modules (L_G)
----------------------------
- GEN_TX : for I in L_G-1 downto 0 generate
+ GEN_TX : for i in L_G-1 downto 0 generate
-- JESD Transmitter modules (one module per Lane)
U_JesdTxLane : entity work.JesdTxLane
generic map (
@@ -356,29 +359,29 @@ begin
devClk_i => devClk_i,
devRst_i => devRst_i,
subClass_i => s_subClass, -- From AXI lite
- enable_i => s_enableTx(I), -- From AXI lite
+ enable_i => s_enableTx(i), -- From AXI lite
replEnable_i => s_replEnable, -- From AXI lite
scrEnable_i => s_scrEnable, -- From AXI lite
- inv_i => s_invertData(I), -- From AXI lite
+ inv_i => s_invertData(i), -- From AXI lite
lmfc_i => s_lmfc,
nSync_i => s_nSyncSync,
- gtTxReady_i => gtTxReady_i(I),
+ gtTxReady_i => gtTxReady_i(i),
sysRef_i => s_sysrefRe,
- status_o => s_statusTxArr(I), -- To AXI lite
- sampleData_i => s_sampleDataArr(I),
- r_jesdGtTx => s_jesdGtTxArr(I));
+ status_o => s_statusTxArr(i), -- To AXI lite
+ sampleData_i => s_sampleDataArr(i),
+ r_jesdGtTx => s_jesdGtTxArr(i));
end generate GEN_TX;
------------------
-- Output register
------------------
GEN_REG_O : if (OUTPUT_REG_G = true) generate
- GEN_LANE : for I in L_G-1 downto 0 generate
+ GEN_LANE : for i in L_G-1 downto 0 generate
process(devClk_i)
begin
if rising_edge(devClk_i) then
- r_jesdGtTxArr(I).data <= s_jesdGtTxArr(I).data after TPD_G;
- r_jesdGtTxArr(I).dataK <= s_jesdGtTxArr(I).dataK after TPD_G;
+ r_jesdGtTxArr(i).data <= s_jesdGtTxArr(i).data after TPD_G;
+ r_jesdGtTxArr(i).dataK <= s_jesdGtTxArr(i).dataK after TPD_G;
end if;
end process;
end generate GEN_LANE;
diff --git a/protocols/jesd204b/rtl/JesdAlignChGen.vhd b/protocols/jesd204b/rtl/JesdAlignChGen.vhd
index 810cbb9a12..47e5be3d3f 100644
--- a/protocols/jesd204b/rtl/JesdAlignChGen.vhd
+++ b/protocols/jesd204b/rtl/JesdAlignChGen.vhd
@@ -165,19 +165,19 @@ begin
end if;
-- Replace with F character
- for I in (SAMPLES_IN_WORD_C-1) downto 0 loop
+ for i in (SAMPLES_IN_WORD_C-1) downto 0 loop
if scrEnable_i = '1' then
- if (v_twoWordBuff((I*F_G*8)+7 downto (I*F_G*8)) = F_CHAR_C and
- v_twoCharBuff((I*F_G+F_G)) = '0')
+ if (v_twoWordBuff((i*F_G*8)+7 downto (i*F_G*8)) = F_CHAR_C and
+ v_twoCharBuff((i*F_G+F_G)) = '0')
then
- v_twoCharBuff(I*F_G) := '1';
+ v_twoCharBuff(i*F_G) := '1';
end if;
else
- if (v_twoWordBuff((I*F_G*8)+(F_G*8)+7 downto (I*F_G*8)+(F_G*8)) = v_twoWordBuff((I*F_G*8)+7 downto (I*F_G*8)) and
- v_twoCharBuff((I*F_G+F_G)) = '0')
+ if (v_twoWordBuff((i*F_G*8)+(F_G*8)+7 downto (i*F_G*8)+(F_G*8)) = v_twoWordBuff((i*F_G*8)+7 downto (i*F_G*8)) and
+ v_twoCharBuff((i*F_G+F_G)) = '0')
then
- v_twoWordBuff((I*F_G*8)+7 downto (I*F_G*8)) := F_CHAR_C;
- v_twoCharBuff(I*F_G) := '1';
+ v_twoWordBuff((i*F_G*8)+7 downto (i*F_G*8)) := F_CHAR_C;
+ v_twoCharBuff(i*F_G) := '1';
end if;
end if;
end loop;
diff --git a/protocols/jesd204b/rtl/JesdAlignFrRepCh.vhd b/protocols/jesd204b/rtl/JesdAlignFrRepCh.vhd
index 6146ae7c91..e53fb60960 100644
--- a/protocols/jesd204b/rtl/JesdAlignFrRepCh.vhd
+++ b/protocols/jesd204b/rtl/JesdAlignFrRepCh.vhd
@@ -167,22 +167,22 @@ begin
-- Replace the control characters in the data with valid data
if(replEnable_i = '1' and dataValid_i = '1') then
- for I in (SAMPLES_IN_WORD_C-1) downto 0 loop
+ for i in (SAMPLES_IN_WORD_C-1) downto 0 loop
-- If the A_CHAR_C or F_CHAR_C characters detected in the stream
- if (v_twoCharBuffAl(I*F_G) = '1' and
- (v_twoWordBuffAl((I*F_G*8+7) downto I*F_G*8) = A_CHAR_C or
- v_twoWordBuffAl((I*F_G*8+7) downto I*F_G*8) = F_CHAR_C)
+ if (v_twoCharBuffAl(i*F_G) = '1' and
+ (v_twoWordBuffAl((i*F_G*8+7) downto i*F_G*8) = A_CHAR_C or
+ v_twoWordBuffAl((i*F_G*8+7) downto i*F_G*8) = F_CHAR_C)
) then
-- If scrambling disabled
-- Replace the character in the data with the data value from previous frame
if (scrEnable_i = '0') then
- v_twoWordBuffAl((I*F_G*8+7) downto I*F_G*8) := v_twoWordBuffAl((I*F_G*8+8*F_G)+7 downto (I*F_G*8+8*F_G));
- v_twoCharBuffAl(I*F_G) := '0';
+ v_twoWordBuffAl((i*F_G*8+7) downto i*F_G*8) := v_twoWordBuffAl((i*F_G*8+8*F_G)+7 downto (i*F_G*8+8*F_G));
+ v_twoCharBuffAl(i*F_G) := '0';
-- If scrambling enabled
-- The data value equals char value and only the char flags are cleared
else
v_twoWordBuffAl := v_twoWordBuffAl;
- v_twoCharBuffAl(I*F_G) := '0';
+ v_twoCharBuffAl(i*F_G) := '0';
end if;
end if;
end loop;
@@ -192,8 +192,8 @@ begin
-- The error indicates that the characters in the data are possibly misplaced or wrong characters
-- have been received.
if(replEnable_i = '1' and dataValid_i = '1') then
- for I in (GT_WORD_SIZE_C-1) downto 0 loop
- if (v_twoCharBuffAl(I) = '1') then
+ for i in (GT_WORD_SIZE_C-1) downto 0 loop
+ if (v_twoCharBuffAl(i) = '1') then
v_alignErr := '1';
end if;
end loop;
diff --git a/protocols/jesd204b/rtl/JesdRxLane.vhd b/protocols/jesd204b/rtl/JesdRxLane.vhd
index e32ad40db2..12841231d2 100644
--- a/protocols/jesd204b/rtl/JesdRxLane.vhd
+++ b/protocols/jesd204b/rtl/JesdRxLane.vhd
@@ -2,7 +2,7 @@
-- File : JesdRxLane.vhd
-- Company : SLAC National Accelerator Laboratory
-- Created : 2015-04-14
--- Last update: 2017-11-10
+-- Last update: 2018-05-04
-------------------------------------------------------------------------------
-- Description: JesdRx single lane module
-- Receiver JESD204b standard.
@@ -58,67 +58,49 @@ use work.Jesd204bPkg.all;
entity JesdRxLane is
generic (
- TPD_G : time := 1 ns;
-
+ TPD_G : time := 1 ns;
-- Number of bytes in a frame
- F_G : positive := 2;
-
+ F_G : positive := 2;
-- Number of frames in a multi frame
- K_G : positive := 32
- );
+ K_G : positive := 32);
port (
-
- -- JESD
-- Clocks and Resets
- devClk_i : in sl;
- devRst_i : in sl;
-
+ devClk_i : in sl;
+ devRst_i : in sl;
-- JESD subclass selection: '0' or '1'(default)
- subClass_i : in sl;
-
+ subClass_i : in sl;
-- SYSREF for subclass 1 fixed latency
- sysRef_i : in sl;
-
+ sysRef_i : in sl;
-- Clear registered errors
- clearErr_i : in sl;
-
+ clearErr_i : in sl;
-- Control register
- enable_i : in sl;
- replEnable_i : in sl;
- scrEnable_i : in sl;
- status_o : out slv((RX_STAT_WIDTH_C)-1 downto 0);
-
+ enable_i : in sl;
+ replEnable_i : in sl;
+ scrEnable_i : in sl;
+ status_o : out slv((RX_STAT_WIDTH_C)-1 downto 0);
-- Data and character inputs from GT (transceivers)
- r_jesdGtRx : in jesdGtRxLaneType;
-
+ r_jesdGtRx : in jesdGtRxLaneType;
-- Local multi frame clock
- lmfc_i : in sl;
-
+ lmfc_i : in sl;
-- Error mask
- linkErrMask_i : in slv(5 downto 0) := (others => '1');
-
+ linkErrMask_i : in slv(5 downto 0) := (others => '1');
-- One or more RX modules requested synchronization
- nSyncAny_i : in sl;
- nSyncAnyD1_i : in sl;
-
+ nSyncAny_i : in sl;
+ nSyncAnyD1_i : in sl;
-- Invert ADC data
- inv_i : in sl := '0';
-
+ inv_i : in sl := '0';
-- Synchronization request output
- nSync_o : out sl;
-
+ nSync_o : out sl;
-- Synchronization process is complete and data is valid
- dataValid_o : out sl;
- sampleData_o : out slv((GT_WORD_SIZE_C*8)-1 downto 0)
- );
+ dataValid_o : out sl;
+ sampleData_o : out slv((GT_WORD_SIZE_C*8)-1 downto 0));
end JesdRxLane;
-
architecture rtl of JesdRxLane is
constant ERR_REG_WIDTH_C : positive := 4+2*GT_WORD_SIZE_C;
--- Register
+
type RegType is record
bufWeD1 : sl;
errReg : slv(ERR_REG_WIDTH_C-1 downto 0);
@@ -126,40 +108,40 @@ architecture rtl of JesdRxLane is
sampleDataValid : sl;
jesdGtRx : jesdGtRxLaneType;
end record RegType;
-
constant REG_INIT_C : RegType := (
bufWeD1 => '0',
errReg => (others => '0'),
sampleData => (others => '0'),
sampleDataValid => '0',
- jesdGtRx => JESD_GT_RX_LANE_INIT_C
- );
+ jesdGtRx => JESD_GT_RX_LANE_INIT_C);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
- -- Internal signals
-- Control signals from FSM
- signal s_nSync : sl;
- signal s_readBuff : sl;
- signal s_alignFrame : sl;
- signal s_alignFrameDly : sl;
- signal s_ila : sl;
- signal s_dataValid : sl;
- signal s_dataValidDly : sl;
+ signal s_nSync : sl;
+ signal s_readBuff : sl;
+ signal s_alignFrame : sl;
+ signal s_alignFrameDly1 : sl;
+ signal s_alignFrameDly0 : sl;
+ signal s_ila : sl;
+ signal s_dataValid : sl;
+ signal s_dataValidDly1 : sl;
+ signal s_dataValidDly0 : sl;
-- Buffer control
signal s_bufRst : sl;
signal s_bufWe : sl;
signal s_bufRe : sl;
- -- Datapath
- signal s_charAndData : slv(((GT_WORD_SIZE_C*8)+GT_WORD_SIZE_C)-1 downto 0);
- signal s_charAndDataBuff : slv(s_charAndData'range);
- signal s_charAndDataBuffDly : slv(s_charAndData'range);
- signal s_sampleData : slv(sampleData_o'range);
- signal s_sampleDataValid : sl;
+ -- Data path
+ signal s_charAndData : slv(((GT_WORD_SIZE_C*8)+GT_WORD_SIZE_C)-1 downto 0);
+ signal s_charAndDataBuff : slv(s_charAndData'range);
+ signal s_charAndDataBuffDly1 : slv(s_charAndData'range);
+ signal s_charAndDataBuffDly0 : slv(s_charAndData'range);
+ signal s_sampleData : slv(sampleData_o'range);
+ signal s_sampleDataValid : sl;
-- Statuses
signal s_bufOvf : sl;
@@ -178,13 +160,16 @@ begin
s_charAndData <= r.jesdGtRx.dataK & r.jesdGtRx.data;
+ -----------------
-- Buffer control
+ -----------------
s_bufRst <= devRst_i or not s_nSync or not enable_i;
s_bufWe <= not s_bufRst and not s_bufFull;
s_bufRe <= r.bufWeD1 and s_readBuff;
- -- Buffer samples between first data and LMFC
- -- Min size one LMFC period
+ -----------------------------------------------------------------------
+ -- Buffer samples between first data and LMFC Min size one LMFC period
+ -----------------------------------------------------------------------
RX_buffer_fifo_INST : entity work.FifoSync
generic map (
TPD_G => TPD_G,
@@ -203,27 +188,20 @@ begin
FULL_THRES_G => 1,
EMPTY_THRES_G => 1)
port map (
- rst => s_bufRst,
- clk => devClk_i,
- wr_en => s_bufWe, -- Always write when enabled
- rd_en => s_bufRe, -- Hold read while sync not in sync with LMFC
- din => s_charAndData,
- dout => s_charAndDataBuff,
- data_count => s_buffLatency,
- wr_ack => open,
- valid => open,
- overflow => s_bufOvf,
- underflow => s_bufUnf,
- prog_full => open,
- prog_empty => open,
- almost_full => open,
- almost_empty => open,
- full => s_bufFull,
- not_full => open,
- empty => open
- );
-
+ rst => s_bufRst,
+ clk => devClk_i,
+ wr_en => s_bufWe, -- Always write when enabled
+ rd_en => s_bufRe, -- Hold read while sync not in sync with LMFC
+ din => s_charAndData,
+ dout => s_charAndDataBuff,
+ data_count => s_buffLatency,
+ overflow => s_bufOvf,
+ underflow => s_bufUnf,
+ full => s_bufFull);
+
+ ----------------------
-- Synchronization FSM
+ ----------------------
syncFSM_INST : entity work.JesdSyncFsmRx
generic map (
TPD_G => TPD_G,
@@ -243,16 +221,16 @@ begin
linkErr_i => s_linkErr,
nSync_o => s_nSync,
readBuff_o => s_readBuff,
- -- buffLatency_o => s_buffLatency,
alignFrame_o => s_alignFrame,
ila_o => s_ila,
kDetected_o => s_kDetected,
sysref_o => s_refDetected,
dataValid_o => s_dataValid,
- subClass_i => subClass_i
- );
+ subClass_i => subClass_i);
- -- Align the rx data within the GT word and replace the characters.
+ ------------------------------------------------------------------
+ -- Align the rx data within the GT word and replace the characters
+ ------------------------------------------------------------------
alignFrRepCh_INST : entity work.JesdAlignFrRepCh
generic map (
TPD_G => TPD_G,
@@ -262,24 +240,28 @@ begin
rst => devRst_i,
replEnable_i => replenable_i,
scrEnable_i => scrEnable_i,
- alignFrame_i => s_alignFrameDly,
- dataValid_i => s_dataValidDly,
- dataRx_i => s_charAndDataBuffDly((GT_WORD_SIZE_C*8)-1 downto 0),
- chariskRx_i => s_charAndDataBuffDly(((GT_WORD_SIZE_C*8)+GT_WORD_SIZE_C)-1 downto (GT_WORD_SIZE_C*8)),
+ alignFrame_i => s_alignFrameDly1,
+ dataValid_i => s_dataValidDly1,
+ dataRx_i => s_charAndDataBuffDly1((GT_WORD_SIZE_C*8)-1 downto 0),
+ chariskRx_i => s_charAndDataBuffDly1(((GT_WORD_SIZE_C*8)+GT_WORD_SIZE_C)-1 downto (GT_WORD_SIZE_C*8)),
sampleDataValid_o => s_sampleDataValid,
sampleData_o => s_sampleData,
alignErr_o => s_alignErr,
- positionErr_o => s_positionErr
- );
+ positionErr_o => s_positionErr);
process(devClk_i)
begin
if rising_edge(devClk_i) then
-- Register to help with timing
- s_alignFrameDly <= s_alignFrame after TPD_G;
- s_dataValidDly <= s_dataValid after TPD_G;
- s_charAndDataBuffDly <= s_charAndDataBuff after TPD_G;
+ s_alignFrameDly1 <= s_alignFrameDly0 after TPD_G;
+ s_dataValidDly1 <= s_dataValidDly0 after TPD_G;
+ s_charAndDataBuffDly1 <= s_charAndDataBuffDly0 after TPD_G;
+
+ -- Register to help with timing
+ s_alignFrameDly0 <= s_alignFrame after TPD_G;
+ s_dataValidDly0 <= s_dataValid after TPD_G;
+ s_charAndDataBuffDly0 <= s_charAndDataBuff after TPD_G;
-- Link error masked by the mask from register and ORed
s_linkErrVec <= s_positionErr & s_bufOvf & s_bufUnf & uOr(r.jesdGtRx.dispErr) & uOr(r.jesdGtRx.decErr) & s_alignErr after TPD_G;
@@ -291,27 +273,23 @@ begin
end if;
end process;
- -- Synchronous process function:
- -- - Registering of errors
- -- - Delay the s_bufWe to use it for s_bufRe
- -- - Inverting ADC data
- -------------------------------------------------------------------------------
- -------------------------------------------------------------------------------
- comb : process (clearErr_i, devRst_i, enable_i, inv_i, r, r_jesdGtRx,
- s_bufWe, s_errComb, s_nSync, s_sampleData,
- s_sampleDataValid) is
+ comb : process (clearErr_i, enable_i, inv_i, r, r_jesdGtRx, s_bufWe,
+ s_buffLatency, s_dataValidDly1, s_errComb, s_kDetected,
+ s_nSync, s_refDetected, s_sampleData, s_sampleDataValid) is
variable v : RegType;
begin
+ -- Latch the current value
v := r;
+ -- Keep a delayed copy
v.jesdGtRx := r_jesdGtRx;
v.bufWeD1 := s_bufWe;
-- Register errors (store until reset)
if (r.jesdGtRx.rstDone = '1' and s_nSync = '1') then
- for I in 0 to(ERR_REG_WIDTH_C-1) loop
- if (s_errComb(I) = '1') and (enable_i = '1') then
- v.errReg(I) := '1';
+ for i in 0 to(ERR_REG_WIDTH_C-1) loop
+ if (s_errComb(i) = '1') and (enable_i = '1') then
+ v.errReg(i) := '1';
end if;
end loop;
end if;
@@ -324,6 +302,7 @@ begin
-- Invert sample data
v.sampleDataValid := s_sampleDataValid;
+ -- Check if inverting the data
if (inv_i = '1') then
-- Invert sample data
v.sampleData := invData(s_sampleData, F_G, GT_WORD_SIZE_C);
@@ -331,12 +310,15 @@ begin
v.sampleData := s_sampleData;
end if;
- -- Reset registers
- if (devRst_i = '1') then
- v := REG_INIT_C;
- end if;
-
+ -- Register the variable for next clock cycle
rin <= v;
+
+ -- Output assignment
+ nSync_o <= s_nSync;
+ dataValid_o <= r.sampleDataValid;
+ sampleData_o <= endianSwapSlv(r.sampleData, GT_WORD_SIZE_C);
+ status_o <= r.jesdGtRx.cdrStable & s_buffLatency & r.errReg(r.errReg'high downto 4) & s_kDetected & s_refDetected & enable_i & r.errReg(2 downto 0) & s_nSync & r.errReg(3) & s_dataValidDly1 & r.jesdGtRx.rstDone;
+
end process comb;
seq : process (devClk_i) is
@@ -346,10 +328,4 @@ begin
end if;
end process seq;
- -- Output assignment
- nSync_o <= s_nSync;
- dataValid_o <= r.sampleDataValid;
- sampleData_o <= endianSwapSlv(r.sampleData, GT_WORD_SIZE_C);
- status_o <= r.jesdGtRx.cdrStable & s_buffLatency & r.errReg(r.errReg'high downto 4) & s_kDetected & s_refDetected & enable_i & r.errReg(2 downto 0) & s_nSync & r.errReg(3) & s_dataValidDly & r.jesdGtRx.rstDone;
------------------------------------------------------------------------------------------
end rtl;
diff --git a/protocols/jesd204b/rtl/JesdRxReg.vhd b/protocols/jesd204b/rtl/JesdRxReg.vhd
index 3c057df5fe..17c7cc959c 100644
--- a/protocols/jesd204b/rtl/JesdRxReg.vhd
+++ b/protocols/jesd204b/rtl/JesdRxReg.vhd
@@ -2,7 +2,7 @@
-- File : JesdRxReg.vhd
-- Company : SLAC National Accelerator Laboratory
-- Created : 2015-04-15
--- Last update: 2018-01-08
+-- Last update: 2018-05-08
-------------------------------------------------------------------------------
-- Description: AXI-Lite interface for register access
-------------------------------------------------------------------------------
@@ -27,11 +27,11 @@ use work.Jesd204bPkg.all;
entity JesdRxReg is
generic (
-- General Configurations
- TPD_G : time := 1 ns;
- AXI_ADDR_WIDTH_G : positive := 10;
+ TPD_G : time := 1 ns;
+ AXI_ADDR_WIDTH_G : positive := 10;
-- JESD
-- Number of RX lanes (1 to 32)
- L_G : positive range 1 to 32 := 2);
+ L_G : positive range 1 to 32 := 2);
port (
-- AXI Clk
axiClk_i : in sl;
@@ -49,25 +49,27 @@ entity JesdRxReg is
-- JESD registers
-- Status
+ sysrefRe_i : in sl;
statusRxArr_i : in rxStatuRegisterArray(L_G-1 downto 0);
rawData_i : in slv32Array(L_G-1 downto 0);
-
+
-- Control
sysrefDlyRx_o : out slv(SYSRF_DLY_WIDTH_C-1 downto 0);
enableRx_o : out slv(L_G-1 downto 0);
replEnable_o : out sl;
scrEnable_o : out sl;
- invertData_o : out slv(L_G-1 downto 0);
- dlyTxArr_o : out Slv4Array(L_G-1 downto 0); -- 1 to 16 clock cycles
+ invertData_o : out slv(L_G-1 downto 0);
+ dlyTxArr_o : out Slv4Array(L_G-1 downto 0); -- 1 to 16 clock cycles
alignTxArr_o : out alignTxArray(L_G-1 downto 0); -- 0001, 0010, 0100, 1000
- thresoldLowArr_o : out Slv16Array(L_G-1 downto 0); -- Test signal threshold low
- thresoldHighArr_o : out Slv16Array(L_G-1 downto 0); -- Test signal threshold high
+ thresoldLowArr_o : out Slv16Array(L_G-1 downto 0); -- Test signal threshold low
+ thresoldHighArr_o : out Slv16Array(L_G-1 downto 0); -- Test signal threshold high
subClass_o : out sl;
gtReset_o : out sl;
clearErr_o : out sl;
invertSync_o : out sl;
linkErrMask_o : out slv(5 downto 0);
- rxPolarity : out slv(L_G-1 downto 0));
+ rxPowerDown : out slv(L_G-1 downto 0);
+ rxPolarity : out slv(L_G-1 downto 0));
end JesdRxReg;
architecture rtl of JesdRxReg is
@@ -75,31 +77,31 @@ architecture rtl of JesdRxReg is
type RegType is record
-- JESD Control (RW)
enableRx : slv(L_G-1 downto 0);
- invertData : slv(L_G-1 downto 0);
+ invertData : slv(L_G-1 downto 0);
commonCtrl : slv(5 downto 0);
linkErrMask : slv(5 downto 0);
sysrefDlyRx : slv(SYSRF_DLY_WIDTH_C-1 downto 0);
testTXItf : Slv16Array(L_G-1 downto 0);
testSigThr : Slv32Array(L_G-1 downto 0);
rxPolarity : slv(L_G-1 downto 0);
-
-
+ rxPowerDown : slv(L_G-1 downto 0);
-- AXI lite
axilReadSlave : AxiLiteReadSlaveType;
axilWriteSlave : AxiLiteWriteSlaveType;
end record;
constant REG_INIT_C : RegType := (
+ -- JESD Control (RW)
enableRx => (others => '0'),
- invertData => (others => '0'),
+ invertData => (others => '0'),
commonCtrl => "010111",
linkErrMask => "111111",
sysrefDlyRx => (others => '0'),
testTXItf => (others => x"0000"),
testSigThr => (others => x"A000_5000"),
- rxPolarity => (others => '0'),
-
-
+ rxPolarity => (others => '0'),
+ rxPowerDown => (others => '0'),
+ -- AXI lite
axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C,
axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C);
@@ -115,15 +117,45 @@ architecture rtl of JesdRxReg is
signal s_rawData : slv32Array(L_G-1 downto 0);
signal s_statusCnt : SlVectorArray(L_G-1 downto 0, 31 downto 0);
signal s_adcValids : slv(L_G-1 downto 0);
-
+
+ signal sysrefDlyRx : slv(SYSRF_DLY_WIDTH_C-1 downto 0);
+ signal enableRx : slv(L_G-1 downto 0);
+ signal replEnable : sl;
+ signal scrEnable : sl;
+ signal invertData : slv(L_G-1 downto 0);
+ signal dlyTxArr : Slv4Array(L_G-1 downto 0);
+ signal alignTxArr : alignTxArray(L_G-1 downto 0);
+ signal thresoldLowArr : Slv16Array(L_G-1 downto 0);
+ signal thresoldHighArr : Slv16Array(L_G-1 downto 0);
+ signal subClass : sl;
+ signal gtReset : sl;
+ signal clearErr : sl;
+ signal invertSync : sl;
+ signal linkErrMask : slv(5 downto 0);
+
+ signal sysRefPeriodmin : slv(15 downto 0);
+ signal sysRefPeriodmax : slv(15 downto 0);
begin
+ U_JesdSysrefMon : entity work.JesdSysrefMon
+ generic map (
+ TPD_G => TPD_G)
+ port map (
+ -- SYSREF Edge detection (devClk domain)
+ devClk => devClk_i,
+ sysrefEdgeDet_i => sysrefRe_i,
+ -- Max/Min measurements (axilClk domain)
+ axilClk => axiClk_i,
+ statClr => r.commonCtrl(3),
+ sysRefPeriodmin => sysRefPeriodmin,
+ sysRefPeriodmax => sysRefPeriodmax);
+
----------------------------------------------------------------------------------------------
-- Data Valid Status Counter
----------------------------------------------------------------------------------------------
- GEN_LANES : for I in L_G-1 downto 0 generate
- s_adcValids(I) <= statusRxArr_i(I)(1);
+ GEN_LANES : for i in L_G-1 downto 0 generate
+ s_adcValids(i) <= statusRxArr_i(i)(1);
end generate GEN_LANES;
@@ -151,7 +183,8 @@ begin
s_WrAddr <= slvToInt(axilWriteMaster.awaddr(AXI_ADDR_WIDTH_G-1 downto 2));
comb : process (axiRst_i, axilReadMaster, axilWriteMaster, r, s_RdAddr,
- s_WrAddr, s_statusRxArr, s_statusCnt, s_rawData) is
+ s_WrAddr, s_rawData, s_statusCnt, s_statusRxArr,
+ sysRefPeriodmax, sysRefPeriodmin) is
variable v : RegType;
variable axilStatus : AxiLiteStatusType;
variable axilWriteResp : slv(1 downto 0);
@@ -179,19 +212,21 @@ begin
when 16#05# => -- ADDR (0x14)
v.linkErrMask := axilWriteMaster.wdata(5 downto 0);
when 16#06# => -- ADDR (0x18)
- v.invertData := axilWriteMaster.wdata(L_G-1 downto 0);
+ v.invertData := axilWriteMaster.wdata(L_G-1 downto 0);
+ when 16#09# => -- ADDR (0x24)
+ v.axilReadSlave.rdata(L_G-1 downto 0) := r.rxPowerDown;
when 16#20# to 16#2F# =>
- for I in (L_G-1) downto 0 loop
- if (axilWriteMaster.awaddr(5 downto 2) = I) then
- v.testTXItf(I) := axilWriteMaster.wdata(15 downto 0);
+ for i in (L_G-1) downto 0 loop
+ if (axilWriteMaster.awaddr(5 downto 2) = i) then
+ v.testTXItf(i) := axilWriteMaster.wdata(15 downto 0);
end if;
end loop;
when 16#30# to 16#3F# =>
- for I in (L_G-1) downto 0 loop
- if (axilWriteMaster.awaddr(5 downto 2) = I) then
- v.testSigThr(I) := axilWriteMaster.wdata(31 downto 0);
+ for i in (L_G-1) downto 0 loop
+ if (axilWriteMaster.awaddr(5 downto 2) = i) then
+ v.testSigThr(i) := axilWriteMaster.wdata(31 downto 0);
end if;
- end loop;
+ end loop;
when others =>
axilWriteResp := AXI_RESP_DECERR_C;
end case;
@@ -214,36 +249,41 @@ begin
v.axilReadSlave.rdata(5 downto 0) := r.linkErrMask;
when 16#06# => -- ADDR (0x18)
v.axilReadSlave.rdata(L_G-1 downto 0) := r.invertData;
+ when 16#09# => -- ADDR (0x24)
+ v.rxPowerDown := axilWriteMaster.wdata(L_G-1 downto 0);
+ when 16#0A# => -- ADDR (0x28)
+ v.axilReadSlave.rdata(15 downto 0) := sysRefPeriodmin;
+ v.axilReadSlave.rdata(31 downto 16) := sysRefPeriodmax;
when 16#10# to 16#1F# =>
- for I in (L_G-1) downto 0 loop
- if (axilReadMaster.araddr(5 downto 2) = I) then
- v.axilReadSlave.rdata(RX_STAT_WIDTH_C-1 downto 0) := s_statusRxArr(I);
+ for i in (L_G-1) downto 0 loop
+ if (axilReadMaster.araddr(5 downto 2) = i) then
+ v.axilReadSlave.rdata(RX_STAT_WIDTH_C-1 downto 0) := s_statusRxArr(i);
end if;
end loop;
when 16#20# to 16#2F# =>
- for I in (L_G-1) downto 0 loop
- if (axilReadMaster.araddr(5 downto 2) = I) then
- v.axilReadSlave.rdata(15 downto 0) := r.testTXItf(I);
+ for i in (L_G-1) downto 0 loop
+ if (axilReadMaster.araddr(5 downto 2) = i) then
+ v.axilReadSlave.rdata(15 downto 0) := r.testTXItf(i);
end if;
end loop;
when 16#30# to 16#3F# =>
- for I in (L_G-1) downto 0 loop
- if (axilReadMaster.araddr(5 downto 2) = I) then
- v.axilReadSlave.rdata(31 downto 0) := r.testSigThr(I);
+ for i in (L_G-1) downto 0 loop
+ if (axilReadMaster.araddr(5 downto 2) = i) then
+ v.axilReadSlave.rdata(31 downto 0) := r.testSigThr(i);
end if;
end loop;
when 16#40# to 16#4F# =>
- for I in (L_G-1) downto 0 loop
- if (axilReadMaster.araddr(5 downto 2) = I) then
- for J in 31 downto 0 loop
- v.axilReadSlave.rdata(J) := s_statusCnt(I, J);
+ for i in (L_G-1) downto 0 loop
+ if (axilReadMaster.araddr(5 downto 2) = i) then
+ for j in 31 downto 0 loop
+ v.axilReadSlave.rdata(J) := s_statusCnt(i, j);
end loop;
end if;
end loop;
when 16#50# to 16#5F# =>
- for I in (L_G-1) downto 0 loop
- if (axilReadMaster.araddr(5 downto 2) = I) then
- v.axilReadSlave.rdata := s_rawData(I);
+ for i in (L_G-1) downto 0 loop
+ if (axilReadMaster.araddr(5 downto 2) = i) then
+ v.axilReadSlave.rdata := s_rawData(i);
end if;
end loop;
when others =>
@@ -263,6 +303,7 @@ begin
-- Outputs
axilReadSlave <= r.axilReadSlave;
axilWriteSlave <= r.axilWriteSlave;
+ rxPowerDown <= r.rxPowerDown;
rxPolarity <= r.rxPolarity;
end process comb;
@@ -275,202 +316,300 @@ begin
end process seq;
-- Input assignment and synchronization
- GEN_0 : for I in L_G-1 downto 0 generate
- SyncFifo_IN0 : entity work.SynchronizerFifo
+ GEN_0 : for i in L_G-1 downto 0 generate
+ U_statusRxArr : entity work.SynchronizerVector
generic map (
- TPD_G => TPD_G,
- DATA_WIDTH_G => RX_STAT_WIDTH_C
- )
+ TPD_G => TPD_G,
+ WIDTH_G => RX_STAT_WIDTH_C)
port map (
- wr_clk => devClk_i,
- din => statusRxArr_i(I),
- rd_clk => axiClk_i,
- dout => s_statusRxArr(I)
- );
-
- SyncFifo_IN1 : entity work.SynchronizerFifo
+ clk => axiClk_i,
+ dataIn => statusRxArr_i(i),
+ dataOut => s_statusRxArr(i));
+
+ U_rawData : entity work.SynchronizerFifo
generic map (
TPD_G => TPD_G,
- DATA_WIDTH_G => 32
- )
+ DATA_WIDTH_G => 32)
port map (
wr_clk => devClk_i,
- din => rawData_i(I),
+ din => rawData_i(i),
rd_clk => axiClk_i,
- dout => s_rawData(I)
- );
+ dout => s_rawData(i));
end generate GEN_0;
-
+
-- Output assignment and synchronization
- SyncFifo_OUT0 : entity work.SynchronizerFifo
+ U_sysrefDlyRx : entity work.SynchronizerVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => SYSRF_DLY_WIDTH_C
- )
+ TPD_G => TPD_G,
+ WIDTH_G => SYSRF_DLY_WIDTH_C)
port map (
- wr_clk => axiClk_i,
- din => r.sysrefDlyRx,
- rd_clk => devClk_i,
- dout => sysrefDlyRx_o
- );
+ clk => devClk_i,
+ dataIn => r.sysrefDlyRx,
+ dataOut => sysrefDlyRx);
- SyncFifo_OUT1 : entity work.SynchronizerFifo
+ U_sysrefDlyRx_Pipeline : entity work.RstPipelineVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => L_G
- )
+ TPD_G => TPD_G,
+ WIDTH_G => SYSRF_DLY_WIDTH_C)
port map (
- wr_clk => axiClk_i,
- din => r.enableRx,
- rd_clk => devClk_i,
- dout => enableRx_o
- );
+ clk => devClk_i,
+ rstIn => sysrefDlyRx,
+ rstOut => sysrefDlyRx_o);
+
+ ------------------------------------------------------------
- Sync_OUT3 : entity work.Synchronizer
+ U_enableRx : entity work.SynchronizerVector
generic map (
- TPD_G => TPD_G
- )
+ TPD_G => TPD_G,
+ WIDTH_G => L_G)
+ port map (
+ clk => devClk_i,
+ dataIn => r.enableRx,
+ dataOut => enableRx);
+
+ U_enableRx_Pipeline : entity work.RstPipelineVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => L_G)
+ port map (
+ clk => devClk_i,
+ rstIn => enableRx,
+ rstOut => enableRx_o);
+
+ ------------------------------------------------------------
+
+ U_subClass : entity work.Synchronizer
+ generic map (
+ TPD_G => TPD_G)
port map (
clk => devClk_i,
- rst => devRst_i,
dataIn => r.commonCtrl(0),
- dataOut => subClass_o
- );
+ dataOut => subClass);
- Sync_OUT4 : entity work.Synchronizer
+ U_subClass_Pipeline : entity work.RstPipeline
generic map (
- TPD_G => TPD_G
- )
+ TPD_G => TPD_G)
+ port map (
+ clk => devClk_i,
+ rstIn => subClass,
+ rstOut => subClass_o);
+
+ ------------------------------------------------------------
+
+ U_replEnable : entity work.Synchronizer
+ generic map (
+ TPD_G => TPD_G)
port map (
clk => devClk_i,
- rst => devRst_i,
dataIn => r.commonCtrl(1),
- dataOut => replEnable_o
- );
+ dataOut => replEnable);
- Sync_OUT5 : entity work.Synchronizer
+ U_replEnable_Pipeline : entity work.RstPipeline
generic map (
- TPD_G => TPD_G
- )
+ TPD_G => TPD_G)
+ port map (
+ clk => devClk_i,
+ rstIn => replEnable,
+ rstOut => replEnable_o);
+
+ ------------------------------------------------------------
+
+ U_gtReset : entity work.Synchronizer
+ generic map (
+ TPD_G => TPD_G)
port map (
clk => devClk_i,
- rst => devRst_i,
dataIn => r.commonCtrl(2),
- dataOut => gtReset_o
- );
+ dataOut => gtReset);
+
+ U_gtReset_Pipeline : entity work.RstPipeline
+ generic map (
+ TPD_G => TPD_G)
+ port map (
+ clk => devClk_i,
+ rstIn => gtReset,
+ rstOut => gtReset_o);
- Sync_OUT6 : entity work.Synchronizer
+ ------------------------------------------------------------
+
+ U_clearErr : entity work.Synchronizer
generic map (
- TPD_G => TPD_G
- )
+ TPD_G => TPD_G)
port map (
clk => devClk_i,
- rst => devRst_i,
dataIn => r.commonCtrl(3),
- dataOut => clearErr_o
- );
+ dataOut => clearErr);
+
+ U_clearErr_Pipeline : entity work.RstPipeline
+ generic map (
+ TPD_G => TPD_G)
+ port map (
+ clk => devClk_i,
+ rstIn => clearErr,
+ rstOut => clearErr_o);
+
+ ------------------------------------------------------------
- Sync_OUT7 : entity work.Synchronizer
+ U_invertSync : entity work.Synchronizer
generic map (
- TPD_G => TPD_G
- )
+ TPD_G => TPD_G)
port map (
clk => devClk_i,
- rst => devRst_i,
dataIn => r.commonCtrl(4),
- dataOut => invertSync_o
- );
+ dataOut => invertSync);
- Sync_OUT8 : entity work.Synchronizer
+ U_invertSync_Pipeline : entity work.RstPipeline
generic map (
- TPD_G => TPD_G
- )
+ TPD_G => TPD_G)
+ port map (
+ clk => devClk_i,
+ rstIn => invertSync,
+ rstOut => invertSync_o);
+
+ ------------------------------------------------------------
+
+ U_scrEnable : entity work.Synchronizer
+ generic map (
+ TPD_G => TPD_G)
port map (
clk => devClk_i,
- rst => devRst_i,
dataIn => r.commonCtrl(5),
- dataOut => scrEnable_o
- );
-
- Sync_OUT9 : entity work.SynchronizerVector
+ dataOut => scrEnable);
+
+ U_scrEnable_Pipeline : entity work.RstPipeline
generic map (
- TPD_G => TPD_G,
- WIDTH_G => 6
- )
+ TPD_G => TPD_G)
+ port map (
+ clk => devClk_i,
+ rstIn => scrEnable,
+ rstOut => scrEnable_o);
+
+ ------------------------------------------------------------
+
+ U_linkErrMask : entity work.SynchronizerVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => 6)
port map (
clk => devClk_i,
- rst => devRst_i,
dataIn => r.linkErrMask,
- dataOut => linkErrMask_o
- );
+ dataOut => linkErrMask);
+
+ U_linkErrMask_Pipeline : entity work.RstPipelineVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => 6)
+ port map (
+ clk => devClk_i,
+ rstIn => linkErrMask,
+ rstOut => linkErrMask_o);
+
+ ------------------------------------------------------------
+
+ U_invertData : entity work.SynchronizerVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => L_G)
+ port map (
+ clk => devClk_i,
+ dataIn => r.invertData,
+ dataOut => invertData);
- SyncFifo_OUT9 : entity work.SynchronizerFifo
+ U_invertData_Pipeline : entity work.RstPipelineVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => L_G
- )
+ TPD_G => TPD_G,
+ WIDTH_G => L_G)
port map (
- wr_clk => axiClk_i,
- din => r.invertData,
- rd_clk => devClk_i,
- dout => invertData_o
- );
-
- GEN_1 : for I in L_G-1 downto 0 generate
- SyncFifo_OUT0 : entity work.SynchronizerFifo
+ clk => devClk_i,
+ rstIn => invertData,
+ rstOut => invertData_o);
+
+ ------------------------------------------------------------
+
+ GEN_1 : for i in L_G-1 downto 0 generate
+
+ ------------------------------------------------------------
+
+ U_dlyTxArr : entity work.SynchronizerVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => 4
- )
+ TPD_G => TPD_G,
+ WIDTH_G => 4)
port map (
- wr_clk => axiClk_i,
- din => r.testTXItf(I) (11 downto 8),
- rd_clk => devClk_i,
- dout => dlyTxArr_o(I)
- );
+ clk => devClk_i,
+ dataIn => r.testTXItf(i)(11 downto 8),
+ dataOut => dlyTxArr(i));
- SyncFifo_OUT1 : entity work.SynchronizerFifo
+ U_dlyTxArr_Pipeline : entity work.RstPipelineVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => GT_WORD_SIZE_C
- )
+ TPD_G => TPD_G,
+ WIDTH_G => 4)
port map (
- wr_clk => axiClk_i,
- din => r.testTXItf(I) (GT_WORD_SIZE_C-1 downto 0),
- rd_clk => devClk_i,
- dout => alignTxArr_o(I)
- );
+ clk => devClk_i,
+ rstIn => dlyTxArr(i),
+ rstOut => dlyTxArr_o(i));
+
+ ------------------------------------------------------------
- SyncFifo_OUT2 : entity work.SynchronizerFifo
+ U_alignTxArr : entity work.SynchronizerVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => 16
- )
+ TPD_G => TPD_G,
+ WIDTH_G => GT_WORD_SIZE_C)
port map (
- wr_clk => axiClk_i,
- din => r.testSigThr(I) (31 downto 16),
- rd_clk => devClk_i,
- dout => thresoldHighArr_o(I)
- );
+ clk => devClk_i,
+ dataIn => r.testTXItf(i) (GT_WORD_SIZE_C-1 downto 0),
+ dataOut => alignTxArr(i));
- SyncFifo_OUT3 : entity work.SynchronizerFifo
+ U_alignTxArr_Pipeline : entity work.RstPipelineVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => 16
- )
+ TPD_G => TPD_G,
+ WIDTH_G => GT_WORD_SIZE_C)
+ port map (
+ clk => devClk_i,
+ rstIn => alignTxArr(i),
+ rstOut => alignTxArr_o(i));
+
+ ------------------------------------------------------------
+
+ U_thresoldLowArr_A : entity work.SynchronizerVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => 16)
+ port map (
+ clk => devClk_i,
+ dataIn => r.testSigThr(i) (31 downto 16),
+ dataOut => thresoldHighArr(i));
+
+ U_thresoldLowArr_A_Pipeline : entity work.RstPipelineVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => 16)
port map (
- wr_clk => axiClk_i,
- din => r.testSigThr(I) (15 downto 0),
- rd_clk => devClk_i,
- dout => thresoldLowArr_o(I)
- );
+ clk => devClk_i,
+ rstIn => thresoldHighArr(i),
+ rstOut => thresoldHighArr_o(i));
+
+ ------------------------------------------------------------
+
+ U_thresoldLowArr_B : entity work.SynchronizerVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => 16)
+ port map (
+ clk => devClk_i,
+ dataIn => r.testSigThr(i) (15 downto 0),
+ dataOut => thresoldLowArr(i));
+
+ U_thresoldLowArr_B_Pipeline : entity work.RstPipelineVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => 16)
+ port map (
+ clk => devClk_i,
+ rstIn => thresoldLowArr(i),
+ rstOut => thresoldLowArr_o(i));
+
+ ------------------------------------------------------------
+
end generate GEN_1;
----------------------------------------------------------------------
+
end rtl;
diff --git a/protocols/jesd204b/rtl/JesdSysrefMon.vhd b/protocols/jesd204b/rtl/JesdSysrefMon.vhd
new file mode 100644
index 0000000000..aa93613d3f
--- /dev/null
+++ b/protocols/jesd204b/rtl/JesdSysrefMon.vhd
@@ -0,0 +1,123 @@
+-------------------------------------------------------------------------------
+-- File : JesdSysrefMon.vhd
+-- Company : SLAC National Accelerator Laboratory
+-- Created : 2018-05-08
+-- Last update: 2018-05-08
+-------------------------------------------------------------------------------
+-- Description: Monitors the time between sysref rising edge detections
+-------------------------------------------------------------------------------
+-- This file is part of 'SLAC Firmware Standard Library'.
+-- It is subject to the license terms in the LICENSE.txt file found in the
+-- top-level directory of this distribution and at:
+-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+-- No part of 'SLAC Firmware Standard Library', including this file,
+-- may be copied, modified, propagated, or distributed except according to
+-- the terms contained in the LICENSE.txt file.
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+use work.StdRtlPkg.all;
+
+entity JesdSysrefMon is
+ generic (
+ TPD_G : time := 1 ns);
+ port (
+ -- SYSREF Edge detection (devClk domain)
+ devClk : in sl;
+ sysrefEdgeDet_i : in sl;
+ -- Max/Min measurements (axilClk domain)
+ axilClk : in sl;
+ statClr : in sl;
+ sysRefPeriodmin : out slv(15 downto 0);
+ sysRefPeriodmax : out slv(15 downto 0));
+end entity JesdSysrefMon;
+
+architecture rtl of JesdSysrefMon is
+
+ type RegType is record
+ cnt : slv(15 downto 0);
+ sysRefPeriodmin : slv(15 downto 0);
+ sysRefPeriodmax : slv(15 downto 0);
+ end record RegType;
+
+ constant REG_INIT_C : RegType := (
+ cnt => x"0000",
+ sysRefPeriodmin => x"FFFF",
+ sysRefPeriodmax => x"0000");
+
+ signal r : RegType := REG_INIT_C;
+ signal rin : RegType;
+
+ signal clr : sl;
+
+begin
+
+ U_RstOneShot : entity work.SynchronizerOneShot
+ generic map (
+ TPD_G => TPD_G)
+ port map (
+ clk => devClk,
+ dataIn => statClr,
+ dataOut => clr);
+
+ comb : process (clr, r, sysrefEdgeDet_i) is
+ variable v : RegType;
+ begin
+ -- Latch the current value
+ v := r;
+
+ -- Increment the counter
+ if (r.cnt /= x"FFFF") then
+ v.cnt := r.cnt + 1;
+ end if;
+
+ -- Wait for sysref edge detection strobe
+ if (sysrefEdgeDet_i = '1') then
+ -- Reset the counter
+ v.cnt := (others => '0');
+ -- Check for max.
+ if (r.cnt > r.sysRefPeriodmax) then
+ v.sysRefPeriodmax := r.cnt;
+ end if;
+ -- Check for min.
+ if (r.cnt < r.sysRefPeriodmin) then
+ v.sysRefPeriodmin := r.cnt;
+ end if;
+ end if;
+
+ -- Check for reseting statistics
+ if (clr = '1') then
+ v := REG_INIT_C;
+ -- Don't change cnt during middle of measurement
+ v.cnt := r.cnt;
+ end if;
+
+ -- Register the variable for next clock cycle
+ rin <= v;
+
+ end process comb;
+
+ seq : process (devClk) is
+ begin
+ if (rising_edge(devClk)) then
+ r <= rin after TPD_G;
+ end if;
+ end process seq;
+
+ U_sync : entity work.SynchronizerFifo
+ generic map (
+ TPD_G => TPD_G,
+ DATA_WIDTH_G => 32)
+ port map (
+ wr_clk => devClk,
+ din(15 downto 0) => r.sysRefPeriodmin,
+ din(31 downto 16) => r.sysRefPeriodmax,
+ rd_clk => axilClk,
+ dout(15 downto 0) => sysRefPeriodmin,
+ dout(31 downto 16) => sysRefPeriodmax);
+
+end rtl;
diff --git a/protocols/jesd204b/rtl/JesdTestStreamTx.vhd b/protocols/jesd204b/rtl/JesdTestStreamTx.vhd
index 85e1bf10da..d2b2f8c93f 100644
--- a/protocols/jesd204b/rtl/JesdTestStreamTx.vhd
+++ b/protocols/jesd204b/rtl/JesdTestStreamTx.vhd
@@ -112,16 +112,16 @@ begin
v.rampCnt := r.rampCnt + slvToInt(rampStep_i)*SAM_IN_WORD_C;
-- Increment samples within the word
- for I in (SAM_IN_WORD_C-1) downto 0 loop
- v.testData((F_G*8*I)+(F_G*8-1) downto F_G*8*I) := std_logic_vector(r.rampCnt(F_G*8-1 downto 0)+((SAM_IN_WORD_C-1)-I)*slvToInt(rampStep_i));
+ for i in (SAM_IN_WORD_C-1) downto 0 loop
+ v.testData((F_G*8*i)+(F_G*8-1) downto F_G*8*i) := std_logic_vector(r.rampCnt(F_G*8-1 downto 0)+((SAM_IN_WORD_C-1)-i)*slvToInt(rampStep_i));
end loop;
else
-- Decrement sample base
v.rampCnt := r.rampCnt - slvToInt(rampStep_i)*SAM_IN_WORD_C;
-- Decrement samples within the word
- for I in (SAM_IN_WORD_C-1) downto 0 loop
- v.testData((F_G*8*I)+(F_G*8-1) downto F_G*8*I) := std_logic_vector(r.rampCnt(F_G*8-1 downto 0)-((SAM_IN_WORD_C-1)-I)*slvToInt(rampStep_i));
+ for i in (SAM_IN_WORD_C-1) downto 0 loop
+ v.testData((F_G*8*i)+(F_G*8-1) downto F_G*8*i) := std_logic_vector(r.rampCnt(F_G*8-1 downto 0)-((SAM_IN_WORD_C-1)-i)*slvToInt(rampStep_i));
end loop;
end if;
@@ -134,12 +134,12 @@ begin
v.squareCnt := (others=>'0');
v.sign := not r.sign;
if (r.sign = '0') then
- for I in (SAM_IN_WORD_C-1) downto 0 loop
- v.testData((F_G*8*I)+(F_G*8-1) downto F_G*8*I) := negAmplitude_i;
+ for i in (SAM_IN_WORD_C-1) downto 0 loop
+ v.testData((F_G*8*i)+(F_G*8-1) downto F_G*8*i) := negAmplitude_i;
end loop;
elsif (r.sign = '1') then
- for I in (SAM_IN_WORD_C-1) downto 0 loop
- v.testData((F_G*8*I)+(F_G*8-1) downto F_G*8*I) := posAmplitude_i;
+ for i in (SAM_IN_WORD_C-1) downto 0 loop
+ v.testData((F_G*8*i)+(F_G*8-1) downto F_G*8*i) := posAmplitude_i;
end loop;
end if;
end if;
diff --git a/protocols/jesd204b/rtl/JesdTxLane.vhd b/protocols/jesd204b/rtl/JesdTxLane.vhd
index 8f543d379e..409ebf1f8f 100644
--- a/protocols/jesd204b/rtl/JesdTxLane.vhd
+++ b/protocols/jesd204b/rtl/JesdTxLane.vhd
@@ -131,9 +131,9 @@ begin
----------------------------------------------------
-- Comma character generation
- COMMA_GEN : for I in GT_WORD_SIZE_C-1 downto 0 generate
- s_commaDataMux(I*8+7 downto I*8) <= K_CHAR_C;
- s_commaKMux(I) <= '1';
+ COMMA_GEN : for i in GT_WORD_SIZE_C-1 downto 0 generate
+ s_commaDataMux(i*8+7 downto i*8) <= K_CHAR_C;
+ s_commaKMux(i) <= '1';
end generate COMMA_GEN;
----------------------------------------------------
diff --git a/protocols/jesd204b/rtl/JesdTxReg.vhd b/protocols/jesd204b/rtl/JesdTxReg.vhd
index ef9ea85cd1..a97864769a 100644
--- a/protocols/jesd204b/rtl/JesdTxReg.vhd
+++ b/protocols/jesd204b/rtl/JesdTxReg.vhd
@@ -2,7 +2,7 @@
-- File : JesdTxReg.vhd
-- Company : SLAC National Accelerator Laboratory
-- Created : 2015-04-15
--- Last update: 2018-01-08
+-- Last update: 2018-05-08
-------------------------------------------------------------------------------
-- Description: AXI-Lite interface for register access
-------------------------------------------------------------------------------
@@ -10,8 +10,8 @@
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
--- No part of 'SLAC Firmware Standard Library', including this file,
--- may be copied, modified, propagated, or distributed except according to
+-- No part of 'SLAC Firmware Standard Library', includataIng this file,
+-- may be copied, modified, propagated, or distributed except accordataIng to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
@@ -27,10 +27,10 @@ use work.Jesd204bPkg.all;
entity JesdTxReg is
generic (
-- General Configurations
- TPD_G : time := 1 ns;
+ TPD_G : time := 1 ns;
-- JESD
- L_G : positive range 1 to 16 := 2;
- F_G : positive := 2);
+ L_G : positive range 1 to 16 := 2;
+ F_G : positive := 2);
port (
-- JESD axiClk
axiClk_i : in sl;
@@ -48,6 +48,7 @@ entity JesdTxReg is
-- JESD registers
-- Status
+ sysrefRe_i : in sl;
statusTxArr_i : in txStatuRegisterArray(L_G-1 downto 0);
-- Control
@@ -57,7 +58,7 @@ entity JesdTxReg is
enableTx_o : out slv(L_G-1 downto 0);
replEnable_o : out sl;
scrEnable_o : out sl;
- invertData_o : out slv(L_G-1 downto 0);
+ invertData_o : out slv(L_G-1 downto 0);
rampStep_o : out slv(PER_STEP_WIDTH_C-1 downto 0);
squarePeriod_o : out slv(PER_STEP_WIDTH_C-1 downto 0);
subClass_o : out sl;
@@ -68,13 +69,14 @@ entity JesdTxReg is
posAmplitude_o : out slv(F_G*8-1 downto 0);
negAmplitude_o : out slv(F_G*8-1 downto 0);
-
+
-- TX Configurable Driver Ports
- txDiffCtrl : out Slv8Array(L_G-1 downto 0);
- txPostCursor : out Slv8Array(L_G-1 downto 0);
- txPreCursor : out Slv8Array(L_G-1 downto 0);
- txPolarity : out slv(L_G-1 downto 0);
- loopback : out slv(L_G-1 downto 0));
+ txDiffCtrl : out Slv8Array(L_G-1 downto 0);
+ txPostCursor : out Slv8Array(L_G-1 downto 0);
+ txPreCursor : out Slv8Array(L_G-1 downto 0);
+ txPowerDown : out slv(L_G-1 downto 0);
+ txPolarity : out slv(L_G-1 downto 0);
+ loopback : out slv(L_G-1 downto 0));
end JesdTxReg;
architecture rtl of JesdTxReg is
@@ -82,7 +84,7 @@ architecture rtl of JesdTxReg is
type RegType is record
-- JESD Control (RW)
enableTx : slv(L_G-1 downto 0);
- invertData : slv(L_G-1 downto 0);
+ invertData : slv(L_G-1 downto 0);
commonCtrl : slv(6 downto 0);
sysrefDlyTx : slv(SYSRF_DLY_WIDTH_C-1 downto 0);
signalSelectArr : Slv8Array(L_G-1 downto 0);
@@ -91,17 +93,18 @@ architecture rtl of JesdTxReg is
negAmplitude : slv(F_G*8-1 downto 0);
txDiffCtrl : Slv8Array(L_G-1 downto 0);
txPostCursor : Slv8Array(L_G-1 downto 0);
- txPreCursor : Slv8Array(L_G-1 downto 0);
- txPolarity : slv(L_G-1 downto 0);
- loopback : slv(L_G-1 downto 0);
+ txPreCursor : Slv8Array(L_G-1 downto 0);
+ txPowerDown : slv(L_G-1 downto 0);
+ txPolarity : slv(L_G-1 downto 0);
+ loopback : slv(L_G-1 downto 0);
-- AXI lite
- axilReadSlave : AxiLiteReadSlaveType;
- axilWriteSlave : AxiLiteWriteSlaveType;
+ axilReadSlave : AxiLiteReadSlaveType;
+ axilWriteSlave : AxiLiteWriteSlaveType;
end record;
constant REG_INIT_C : RegType := (
enableTx => (others => '0'),
- invertData => (others => '0'),
+ invertData => (others => '0'),
commonCtrl => "0110011",
sysrefDlyTx => (others => '0'),
--signalSelectArr=> (others => b"0010_0011"), -- Set to squarewave
@@ -113,12 +116,13 @@ architecture rtl of JesdTxReg is
posAmplitude => (others => '1'),
negAmplitude => (others => '0'),
-
- txDiffCtrl => (others => x"FF"),
- txPostCursor => (others => x"00"),
- txPreCursor => (others => x"00"),
- txPolarity => (others => '0'),
- loopback => (others => '0'),
+
+ txDiffCtrl => (others => x"FF"),
+ txPostCursor => (others => x"00"),
+ txPreCursor => (others => x"00"),
+ txPowerDown => (others => '0'),
+ txPolarity => (others => '0'),
+ loopback => (others => '0'),
axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C,
axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C);
@@ -134,43 +138,76 @@ architecture rtl of JesdTxReg is
signal s_statusTxArr : txStatuRegisterArray(L_G-1 downto 0);
signal s_statusCnt : SlVectorArray(L_G-1 downto 0, 31 downto 0);
signal s_adcValids : slv(L_G-1 downto 0);
-
- signal scrEnable : sl;
-
+
+ signal muxOutSelArr : Slv3Array(L_G-1 downto 0);
+ signal sigTypeArr : Slv2Array(L_G-1 downto 0);
+ signal sysrefDlyTx : slv(SYSRF_DLY_WIDTH_C-1 downto 0);
+ signal enableTx : slv(L_G-1 downto 0);
+ signal replEnable : sl;
+ signal scrEnable : sl;
+ signal invertData : slv(L_G-1 downto 0);
+ signal rampStep : slv(PER_STEP_WIDTH_C-1 downto 0);
+ signal squarePeriod : slv(PER_STEP_WIDTH_C-1 downto 0);
+ signal subClass : sl;
+ signal gtReset : sl;
+ signal clearErr : sl;
+ signal invertSync : sl;
+ signal enableTestSig : sl;
+ signal posAmplitude : slv(F_G*8-1 downto 0);
+ signal negAmplitude : slv(F_G*8-1 downto 0);
+
+ signal sysRefPeriodmin : slv(15 downto 0);
+ signal sysRefPeriodmax : slv(15 downto 0);
+
begin
+ U_JesdSysrefMon : entity work.JesdSysrefMon
+ generic map (
+ TPD_G => TPD_G)
+ port map (
+ -- SYSREF Edge detection (devClk domain)
+ devClk => devClk_i,
+ sysrefEdgeDet_i => sysrefRe_i,
+ -- Max/Min measurements (axilClk domain)
+ axilClk => axiClk_i,
+ statClr => r.commonCtrl(3),
+ sysRefPeriodmin => sysRefPeriodmin,
+ sysRefPeriodmax => sysRefPeriodmax);
+
----------------------------------------------------------------------------------------------
-- Data Valid Status Counter
----------------------------------------------------------------------------------------------
- GEN_LANES : for I in L_G-1 downto 0 generate
- s_adcValids(I) <= statusTxArr_i(I)(1);
+ GEN_LANES : for i in L_G-1 downto 0 generate
+ s_adcValids(i) <= statusTxArr_i(i)(1);
end generate GEN_LANES;
-
-
+
+
U_SyncStatusVector : entity work.SyncStatusVector
- generic map (
- TPD_G => TPD_G,
- OUT_POLARITY_G => '1',
- CNT_RST_EDGE_G => true,
- CNT_WIDTH_G => 32,
- WIDTH_G => L_G)
- port map (
- -- Input Status bit Signals (wrClk domain)
- statusIn => s_adcValids,
- -- Output Status bit Signals (rdClk domain)
- statusOut => open,
- -- Status Bit Counters Signals (rdClk domain)
- cntRstIn => r.commonCtrl(3),
- cntOut => s_statusCnt,
- -- Clocks and Reset Ports
- wrClk => devClk_i,
- rdClk => axiClk_i);
+ generic map (
+ TPD_G => TPD_G,
+ OUT_POLARITY_G => '1',
+ CNT_RST_EDGE_G => true,
+ CNT_WIDTH_G => 32,
+ WIDTH_G => L_G)
+ port map (
+ -- Input Status bit Signals (wrClk domain)
+ statusIn => s_adcValids,
+ -- Output Status bit Signals (rdClk domain)
+ statusOut => open,
+ -- Status Bit Counters Signals (rdClk domain)
+ cntRstIn => r.commonCtrl(3),
+ cntOut => s_statusCnt,
+ -- Clocks and Reset Ports
+ wrClk => devClk_i,
+ rdClk => axiClk_i);
-- Convert address to integer (lower two bits of address are always '0')
s_RdAddr <= slvToInt(axilReadMaster.araddr(9 downto 2));
s_WrAddr <= slvToInt(axilWriteMaster.awaddr(9 downto 2));
- comb : process (axilReadMaster, axilWriteMaster, r, axiRst_i, s_statusTxArr, s_RdAddr, s_WrAddr, s_statusCnt) is
+ comb : process (axiRst_i, axilReadMaster, axilWriteMaster, r, s_RdAddr,
+ s_WrAddr, s_statusCnt, s_statusTxArr, sysRefPeriodmax,
+ sysRefPeriodmin) is
variable v : RegType;
variable axilStatus : AxiLiteStatusType;
variable axilWriteResp : slv(1 downto 0);
@@ -204,21 +241,23 @@ begin
when 16#07# => -- ADDR (0x1C)
v.posAmplitude := axilWriteMaster.wdata(F_G*8-1 downto 0);
when 16#08# => -- ADDR (0x20)
- v.invertData := axilWriteMaster.wdata(L_G-1 downto 0);
+ v.invertData := axilWriteMaster.wdata(L_G-1 downto 0);
+ when 16#09# => -- ADDR (0x24)
+ v.txPowerDown := axilWriteMaster.wdata(L_G-1 downto 0);
when 16#20# to 16#2F# =>
- for I in (L_G-1) downto 0 loop
- if (axilWriteMaster.awaddr(5 downto 2) = I) then
- v.signalSelectArr(I) := axilWriteMaster.wdata(7 downto 0);
+ for i in (L_G-1) downto 0 loop
+ if (axilWriteMaster.awaddr(5 downto 2) = i) then
+ v.signalSelectArr(i) := axilWriteMaster.wdata(7 downto 0);
end if;
end loop;
when 16#80# to 16#9F# =>
- for I in (L_G-1) downto 0 loop
- if (axilWriteMaster.awaddr(6 downto 2) = I) then
- v.txDiffCtrl(I) := axilWriteMaster.wdata(7 downto 0);
- v.txPostCursor(I) := axilWriteMaster.wdata(15 downto 8);
- v.txPreCursor(I) := axilWriteMaster.wdata(23 downto 16);
+ for i in (L_G-1) downto 0 loop
+ if (axilWriteMaster.awaddr(6 downto 2) = i) then
+ v.txDiffCtrl(i) := axilWriteMaster.wdata(7 downto 0);
+ v.txPostCursor(i) := axilWriteMaster.wdata(15 downto 8);
+ v.txPreCursor(i) := axilWriteMaster.wdata(23 downto 16);
end if;
- end loop;
+ end loop;
when others =>
axilWriteResp := AXI_RESP_DECERR_C;
end case;
@@ -247,35 +286,40 @@ begin
v.axilReadSlave.rdata(F_G*8-1 downto 0) := r.posAmplitude;
when 16#08# => -- ADDR (0x20)
v.axilReadSlave.rdata(L_G-1 downto 0) := r.invertData;
+ when 16#09# => -- ADDR (0x24)
+ v.axilReadSlave.rdata(L_G-1 downto 0) := r.txPowerDown;
+ when 16#0A# => -- ADDR (0x28)
+ v.axilReadSlave.rdata(15 downto 0) := sysRefPeriodmin;
+ v.axilReadSlave.rdata(31 downto 16) := sysRefPeriodmax;
when 16#10# to 16#1F# =>
- for I in (L_G-1) downto 0 loop
- if (axilReadMaster.araddr(5 downto 2) = I) then
- v.axilReadSlave.rdata(TX_STAT_WIDTH_C-1 downto 0) := s_statusTxArr(I);
+ for i in (L_G-1) downto 0 loop
+ if (axilReadMaster.araddr(5 downto 2) = i) then
+ v.axilReadSlave.rdata(TX_STAT_WIDTH_C-1 downto 0) := s_statusTxArr(i);
end if;
end loop;
when 16#20# to 16#2F# =>
- for I in (L_G-1) downto 0 loop
- if (axilReadMaster.araddr(5 downto 2) = I) then
- v.axilReadSlave.rdata(7 downto 0) := r.signalSelectArr(I);
+ for i in (L_G-1) downto 0 loop
+ if (axilReadMaster.araddr(5 downto 2) = i) then
+ v.axilReadSlave.rdata(7 downto 0) := r.signalSelectArr(i);
end if;
end loop;
-
+
when 16#40# to 16#4F# =>
- for I in (L_G-1) downto 0 loop
- if (axilReadMaster.araddr(5 downto 2) = I) then
- for J in 31 downto 0 loop
- v.axilReadSlave.rdata(J) := s_statusCnt(I,J);
+ for i in (L_G-1) downto 0 loop
+ if (axilReadMaster.araddr(5 downto 2) = i) then
+ for j in 31 downto 0 loop
+ v.axilReadSlave.rdata(J) := s_statusCnt(i, j);
end loop;
end if;
end loop;
when 16#80# to 16#9F# =>
- for I in (L_G-1) downto 0 loop
- if (axilReadMaster.araddr(6 downto 2) = I) then
- v.axilReadSlave.rdata(7 downto 0) := r.txDiffCtrl(I);
- v.axilReadSlave.rdata(15 downto 8) := r.txPostCursor(I);
- v.axilReadSlave.rdata(23 downto 16) := r.txPreCursor(I);
+ for i in (L_G-1) downto 0 loop
+ if (axilReadMaster.araddr(6 downto 2) = i) then
+ v.axilReadSlave.rdata(7 downto 0) := r.txDiffCtrl(i);
+ v.axilReadSlave.rdata(15 downto 8) := r.txPostCursor(i);
+ v.axilReadSlave.rdata(23 downto 16) := r.txPreCursor(i);
end if;
- end loop;
+ end loop;
when others =>
axilReadResp := AXI_RESP_DECERR_C;
end case;
@@ -295,10 +339,11 @@ begin
axilWriteSlave <= r.axilWriteSlave;
txDiffCtrl <= r.txDiffCtrl;
txPostCursor <= r.txPostCursor;
- txPreCursor <= r.txPreCursor;
- txPolarity <= r.txPolarity;
- loopback <= r.loopback;
-
+ txPreCursor <= r.txPreCursor;
+ txPowerDown <= r.txPowerDown;
+ txPolarity <= r.txPolarity;
+ loopback <= r.loopback;
+
end process comb;
seq : process (axiClk_i) is
@@ -309,192 +354,328 @@ begin
end process seq;
-- Input assignment and synchronization
- GEN_0 : for I in L_G-1 downto 0 generate
- SyncFifo_IN0 : entity work.SynchronizerFifo
+ GEN_0 : for i in L_G-1 downto 0 generate
+ U_statusTxArr : entity work.SynchronizerVector
generic map (
- TPD_G => TPD_G,
- DATA_WIDTH_G => TX_STAT_WIDTH_C)
+ TPD_G => TPD_G,
+ WIDTH_G => TX_STAT_WIDTH_C)
port map (
- wr_clk => devClk_i,
- din => statusTxArr_i(I),
- rd_clk => axiClk_i,
- dout => s_statusTxArr(I));
+ clk => axiClk_i,
+ dataIn => statusTxArr_i(i),
+ dataOut => s_statusTxArr(i));
end generate GEN_0;
-- Output assignment and synchronization
- SyncFifo_OUT0 : entity work.SynchronizerFifo
+ U_sysrefDlyTx : entity work.SynchronizerVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => SYSRF_DLY_WIDTH_C)
+ port map (
+ clk => devClk_i,
+ dataIn => r.sysrefDlyTx,
+ dataOut => sysrefDlyTx);
+
+ U_sysrefDlyTx_Pipeline : entity work.RstPipelineVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => SYSRF_DLY_WIDTH_C)
+ port map (
+ clk => devClk_i,
+ rstIn => sysrefDlyTx,
+ rstOut => sysrefDlyTx_o);
+
+ ------------------------------------------------------------
+
+ U_enableTx : entity work.SynchronizerVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => SYSRF_DLY_WIDTH_C)
+ TPD_G => TPD_G,
+ WIDTH_G => L_G)
port map (
- wr_clk => axiClk_i,
- din => r.sysrefDlyTx,
- rd_clk => devClk_i,
- dout => sysrefDlyTx_o);
+ clk => devClk_i,
+ dataIn => r.enableTx,
+ dataOut => enableTx);
- SyncFifo_OUT1 : entity work.SynchronizerFifo
+ U_enableTx_Pipeline : entity work.RstPipelineVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => L_G)
+ TPD_G => TPD_G,
+ WIDTH_G => L_G)
port map (
- wr_clk => axiClk_i,
- din => r.enableTx,
- rd_clk => devClk_i,
- dout => enableTx_o);
+ clk => devClk_i,
+ rstIn => enableTx,
+ rstOut => enableTx_o);
+
+ ------------------------------------------------------------
- Sync_OUT4 : entity work.Synchronizer
+ U_subClass : entity work.Synchronizer
generic map (
TPD_G => TPD_G)
port map (
clk => devClk_i,
- rst => devRst_i,
dataIn => r.commonCtrl(0),
- dataOut => subClass_o);
+ dataOut => subClass);
- Sync_OUT5 : entity work.Synchronizer
+ U_subClass_Pipeline : entity work.RstPipeline
+ generic map (
+ TPD_G => TPD_G)
+ port map (
+ clk => devClk_i,
+ rstIn => subClass,
+ rstOut => subClass_o);
+
+ ------------------------------------------------------------
+
+ U_replEnable : entity work.Synchronizer
generic map (
TPD_G => TPD_G)
port map (
clk => devClk_i,
- rst => devRst_i,
dataIn => r.commonCtrl(1),
- dataOut => replEnable_o);
+ dataOut => replEnable);
+
+ U_replEnable_Pipeline : entity work.RstPipeline
+ generic map (
+ TPD_G => TPD_G)
+ port map (
+ clk => devClk_i,
+ rstIn => replEnable,
+ rstOut => replEnable_o);
- Sync_OUT6 : entity work.Synchronizer
+ ------------------------------------------------------------
+
+ U_gtReset : entity work.Synchronizer
generic map (
TPD_G => TPD_G)
port map (
clk => devClk_i,
- rst => devRst_i,
dataIn => r.commonCtrl(2),
- dataOut => gtReset_o);
+ dataOut => gtReset);
- Sync_OUT7 : entity work.Synchronizer
+ U_gtReset_Pipeline : entity work.RstPipeline
+ generic map (
+ TPD_G => TPD_G)
+ port map (
+ clk => devClk_i,
+ rstIn => gtReset,
+ rstOut => gtReset_o);
+
+ ------------------------------------------------------------
+
+ U_clearErr : entity work.Synchronizer
generic map (
TPD_G => TPD_G)
port map (
clk => devClk_i,
- rst => devRst_i,
dataIn => r.commonCtrl(3),
- dataOut => clearErr_o);
+ dataOut => clearErr);
- Sync_OUT8 : entity work.Synchronizer
+ U_clearErr_Pipeline : entity work.RstPipeline
+ generic map (
+ TPD_G => TPD_G)
+ port map (
+ clk => devClk_i,
+ rstIn => clearErr,
+ rstOut => clearErr_o);
+
+ ------------------------------------------------------------
+
+ U_invertSync : entity work.Synchronizer
generic map (
TPD_G => TPD_G)
port map (
clk => devClk_i,
- rst => devRst_i,
dataIn => r.commonCtrl(4),
- dataOut => invertSync_o);
+ dataOut => invertSync);
+
+ U_invertSync_Pipeline : entity work.RstPipeline
+ generic map (
+ TPD_G => TPD_G)
+ port map (
+ clk => devClk_i,
+ rstIn => invertSync,
+ rstOut => invertSync_o);
- Sync_OUT9 : entity work.Synchronizer
+ ------------------------------------------------------------
+
+ U_enableTestSig : entity work.Synchronizer
generic map (
TPD_G => TPD_G)
port map (
clk => devClk_i,
- rst => devRst_i,
dataIn => r.commonCtrl(5),
- dataOut => enableTestSig_o);
-
- Sync_OUT10 : entity work.Synchronizer
+ dataOut => enableTestSig);
+
+ U_enableTestSig_Pipeline : entity work.RstPipeline
+ generic map (
+ TPD_G => TPD_G)
+ port map (
+ clk => devClk_i,
+ rstIn => enableTestSig,
+ rstOut => enableTestSig_o);
+
+ ------------------------------------------------------------
+
+ U_scrEnable : entity work.Synchronizer
generic map (
TPD_G => TPD_G)
port map (
clk => devClk_i,
- rst => devRst_i,
dataIn => r.commonCtrl(6),
dataOut => scrEnable);
- -- Help with timing
- U_scrEnable : entity work.RstPipeline
+
+ U_scrEnable_Pipeline : entity work.RstPipeline
generic map (
TPD_G => TPD_G)
port map (
clk => devClk_i,
rstIn => scrEnable,
- rstOut => scrEnable_o);
+ rstOut => scrEnable_o);
+
+ ------------------------------------------------------------
+
+ U_rampStep_A : entity work.SynchronizerVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => PER_STEP_WIDTH_C)
+ port map (
+ clk => devClk_i,
+ dataIn => r.periodStep(PER_STEP_WIDTH_C-1 downto 0),
+ dataOut => rampStep);
+
+ U_rampStep_Pipeline : entity work.RstPipelineVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => PER_STEP_WIDTH_C)
+ port map (
+ clk => devClk_i,
+ rstIn => rampStep,
+ rstOut => rampStep_o);
+
+ ------------------------------------------------------------
- SyncFifo_OUT10 : entity work.SynchronizerFifo
+ U_squarePeriod : entity work.SynchronizerVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => PER_STEP_WIDTH_C)
+ TPD_G => TPD_G,
+ WIDTH_G => PER_STEP_WIDTH_C)
port map (
- wr_clk => axiClk_i,
- din => r.periodStep(PER_STEP_WIDTH_C-1 downto 0),
- rd_clk => devClk_i,
- dout => rampStep_o);
+ clk => devClk_i,
+ dataIn => r.periodStep(16+PER_STEP_WIDTH_C-1 downto 16),
+ dataOut => squarePeriod);
- SyncFifo_OUT11 : entity work.SynchronizerFifo
+ U_squarePeriod_Pipeline : entity work.RstPipelineVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => PER_STEP_WIDTH_C)
+ TPD_G => TPD_G,
+ WIDTH_G => PER_STEP_WIDTH_C)
port map (
- wr_clk => axiClk_i,
- din => r.periodStep(16+PER_STEP_WIDTH_C-1 downto 16),
- rd_clk => devClk_i,
- dout => squarePeriod_o);
+ clk => devClk_i,
+ rstIn => squarePeriod,
+ rstOut => squarePeriod_o);
- SyncFifo_OUT12 : entity work.SynchronizerFifo
+ ------------------------------------------------------------
+
+ U_posAmplitude : entity work.SynchronizerVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => F_G*8)
+ TPD_G => TPD_G,
+ WIDTH_G => F_G*8)
port map (
- wr_clk => axiClk_i,
- din => r.posAmplitude,
- rd_clk => devClk_i,
- dout => posAmplitude_o);
+ clk => devClk_i,
+ dataIn => r.posAmplitude,
+ dataOut => posAmplitude);
- SyncFifo_OUT13 : entity work.SynchronizerFifo
+ U_posAmplitude_Pipeline : entity work.RstPipelineVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => F_G*8)
+ TPD_G => TPD_G,
+ WIDTH_G => F_G*8)
port map (
- wr_clk => axiClk_i,
- din => r.negAmplitude,
- rd_clk => devClk_i,
- dout => negAmplitude_o);
-
- SyncFifo_OUT14 : entity work.SynchronizerFifo
+ clk => devClk_i,
+ rstIn => posAmplitude,
+ rstOut => posAmplitude_o);
+
+ ------------------------------------------------------------
+
+ U_negAmplitude : entity work.SynchronizerVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => L_G)
+ TPD_G => TPD_G,
+ WIDTH_G => F_G*8)
port map (
- wr_clk => axiClk_i,
- din => r.invertData,
- rd_clk => devClk_i,
- dout => invertData_o);
-
- GEN_1 : for I in L_G-1 downto 0 generate
-
- SyncFifo_OUT0 : entity work.SynchronizerFifo
+ clk => devClk_i,
+ dataIn => r.negAmplitude,
+ dataOut => negAmplitude);
+
+ U_negAmplitude_Pipeline : entity work.RstPipelineVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => F_G*8)
+ port map (
+ clk => devClk_i,
+ rstIn => negAmplitude,
+ rstOut => negAmplitude_o);
+
+ ------------------------------------------------------------
+
+ U_invertData : entity work.SynchronizerVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => L_G)
+ port map (
+ clk => devClk_i,
+ dataIn => r.invertData,
+ dataOut => invertData);
+
+ U_invertData_Pipeline : entity work.RstPipelineVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => L_G)
+ port map (
+ clk => devClk_i,
+ rstIn => invertData,
+ rstOut => invertData_o);
+
+ ------------------------------------------------------------
+
+ GEN_1 : for i in L_G-1 downto 0 generate
+
+ ------------------------------------------------------------
+
+ U_muxOutSelArr : entity work.SynchronizerVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => 3)
+ TPD_G => TPD_G,
+ WIDTH_G => 3)
port map (
- wr_clk => axiClk_i,
- din => r.signalSelectArr(I)(2 downto 0),
- rd_clk => devClk_i,
- dout => muxOutSelArr_o(I));
+ clk => devClk_i,
+ dataIn => r.signalSelectArr(i)(2 downto 0),
+ dataOut => muxOutSelArr(i));
- SyncFifo_OUT1 : entity work.SynchronizerFifo
+ U_muxOutSelArr_Pipeline : entity work.RstPipelineVector
generic map (
- TPD_G => TPD_G,
- PIPE_STAGES_G => 1,
- DATA_WIDTH_G => 2
- )
+ TPD_G => TPD_G,
+ WIDTH_G => 3)
port map (
- wr_clk => axiClk_i,
- din => r.signalSelectArr(I)(5 downto 4),
- rd_clk => devClk_i,
- dout => sigTypeArr_o(I));
-
+ clk => devClk_i,
+ rstIn => muxOutSelArr(i),
+ rstOut => muxOutSelArr_o(i));
+
+ ------------------------------------------------------------
+
+ U_sigTypeArr : entity work.SynchronizerVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => 2)
+ port map (
+ clk => devClk_i,
+ dataIn => r.signalSelectArr(i)(5 downto 4),
+ dataOut => sigTypeArr(i));
+
+ U_sigTypeArr_Pipeline : entity work.RstPipelineVector
+ generic map (
+ TPD_G => TPD_G,
+ WIDTH_G => 2)
+ port map (
+ clk => devClk_i,
+ rstIn => sigTypeArr(i),
+ rstOut => sigTypeArr_o(i));
+
+ ------------------------------------------------------------
+
end generate GEN_1;
end rtl;
diff --git a/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp/Pgp3GthUsIp.dcp b/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp/Pgp3GthUsIp.dcp
deleted file mode 100644
index ba2d7866b3..0000000000
--- a/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp/Pgp3GthUsIp.dcp
+++ /dev/null
@@ -1,3 +0,0 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:e16e645a64ac0b090be8d1c7a6969bc0686ccd682e762bd8082ffa5f63c82a39
-size 258213
diff --git a/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp10G/Pgp3GthUsIp10G.dcp b/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp10G/Pgp3GthUsIp10G.dcp
new file mode 100644
index 0000000000..a35e653be8
--- /dev/null
+++ b/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp10G/Pgp3GthUsIp10G.dcp
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:496cd2407ea6fe7e88c4c2bc7a13e2dba492bdef999228383a0e4afd4ccde43c
+size 258033
diff --git a/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp/Pgp3GthUsIp.xci b/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp10G/Pgp3GthUsIp10G.xci
similarity index 99%
rename from protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp/Pgp3GthUsIp.xci
rename to protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp10G/Pgp3GthUsIp10G.xci
index 3a7de7b86d..25d4938055 100644
--- a/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp/Pgp3GthUsIp.xci
+++ b/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp10G/Pgp3GthUsIp10G.xci
@@ -6,7 +6,7 @@
1.0
- Pgp3GthUsIp
+ Pgp3GthUsIp10G
"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000"
@@ -101,7 +101,7 @@
312.5000000
0
X0Y9
- Pgp3GthUsIp
+ Pgp3GthUsIp10G
0
drpaddr_in drpclk_in drpdi_in drpen_in drpwe_in loopback_in rxpolarity_in txdiffctrl_in txpolarity_in txpostcursor_in txprecursor_in drpdo_out drprdy_out
156.25
@@ -649,7 +649,7 @@
-1
-1
-1
- 18
+ 17
0
Aurora_64B66B
5
@@ -1352,10 +1352,10 @@
false
false
kintexu
-
- xcku040
- ffva1156
- VHDL
+ xilinx.com:kcu1500:part0:1.1
+ xcku115
+ flvb2104
+ VERILOG
MIXED
-2
diff --git a/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp6G/Pgp3GthUsIp6G.dcp b/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp6G/Pgp3GthUsIp6G.dcp
new file mode 100644
index 0000000000..6753c77b54
--- /dev/null
+++ b/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp6G/Pgp3GthUsIp6G.dcp
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:9ae9a9071198b0b7101a820ad99c944f0b7583872540bc9e2b1e972d2f66721f
+size 258065
diff --git a/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp6G/Pgp3GthUsIp6G.xci b/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp6G/Pgp3GthUsIp6G.xci
new file mode 100644
index 0000000000..fc6b082155
--- /dev/null
+++ b/protocols/pgp/pgp3/gthUs/ip/Pgp3GthUsIp6G/Pgp3GthUsIp6G.xci
@@ -0,0 +1,1409 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ Pgp3GthUsIp6G
+
+
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+ 1
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+ 0
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+ 64B66B_ASYNC
+ true
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+ -20
+ 6.25
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+ RXPROGDIVCLK
+ QPLL0
+ 0
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+ 0
+ false
+ QPLL0
+ 189.3939394
+ 1
+ ENABLE
+ 64B66B_ASYNC
+ CUSTOM
+ true
+ 32
+ 6.25
+ X0Y9
+ TXPROGDIVCLK
+ QPLL0
+ 0
+ 156.25
+ X0Y9 clk0+2
+ 64
+ false
+ 1
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+ false
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+ kintexu
+ xilinx.com:kcu1500:part0:1.1
+ xcku115
+ flvb2104
+ VERILOG
+
+ MIXED
+ -2
+ E
+ TRUE
+ TRUE
+ IP_Flow
+ 1
+ TRUE
+ .
+
+ .
+ 2017.3
+ OUT_OF_CONTEXT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
diff --git a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd
index c00a448e90..53f27d0787 100644
--- a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd
+++ b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd
@@ -2,7 +2,7 @@
-- File : Pgp3GthUs.vhd
-- Company : SLAC National Accelerator Laboratory
-- Created : 2013-06-29
--- Last update: 2018-04-22
+-- Last update: 2018-05-08
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
@@ -32,6 +32,7 @@ use UNISIM.VCOMPONENTS.all;
entity Pgp3GthUs is
generic (
TPD_G : time := 1 ns;
+ RATE_G : string := "10.3125Gbps"; -- or "6.25Gbps"
----------------------------------------------------------------------------------------------
-- PGP Settings
----------------------------------------------------------------------------------------------
@@ -146,6 +147,10 @@ architecture rtl of Pgp3GthUs is
begin
+ assert ((RATE_G = "6.25Gbps") or (RATE_G = "10.3125Gbps"))
+ report "RATE_G: Must be either 6.25Gbps or 10.3125Gbps"
+ severity error;
+
pgpClk <= pgpTxClkInt;
pgpClkRst <= pgpTxRstInt;
@@ -258,6 +263,7 @@ begin
TPD_G => TPD_G,
TX_POLARITY_G => TX_POLARITY_G,
RX_POLARITY_G => RX_POLARITY_G,
+ RATE_G => RATE_G,
EN_DRP_G => EN_DRP_G)
port map (
stableClk => stableClk, -- [in]
diff --git a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd
index e8020de9b5..f4e2f58bfd 100644
--- a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd
+++ b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd
@@ -2,7 +2,7 @@
-- File : Pgp3GthUsIpWrapper.vhd
-- Company : SLAC National Accelerator Laboratory
-- Created : 2013-06-29
--- Last update: 2018-04-19
+-- Last update: 2018-05-03
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
@@ -24,6 +24,7 @@ entity Pgp3GthUsIpWrapper is
generic (
TPD_G : time := 1 ns;
EN_DRP_G : boolean := true;
+ RATE_G : string := "10.3125Gbps"; -- or "6.25Gbps"
TX_POLARITY_G : sl := '0';
RX_POLARITY_G : sl := '0');
port (
@@ -77,7 +78,68 @@ end entity Pgp3GthUsIpWrapper;
architecture mapping of Pgp3GthUsIpWrapper is
- component Pgp3GthUsIp
+ component Pgp3GthUsIp10G
+ port (
+ gtwiz_userclk_tx_reset_in : in std_logic_vector(0 downto 0);
+ gtwiz_userclk_tx_srcclk_out : out std_logic_vector(0 downto 0);
+ gtwiz_userclk_tx_usrclk_out : out std_logic_vector(0 downto 0);
+ gtwiz_userclk_tx_usrclk2_out : out std_logic_vector(0 downto 0);
+ gtwiz_userclk_tx_active_out : out std_logic_vector(0 downto 0);
+ gtwiz_userclk_rx_reset_in : in std_logic_vector(0 downto 0);
+ gtwiz_userclk_rx_srcclk_out : out std_logic_vector(0 downto 0);
+ gtwiz_userclk_rx_usrclk_out : out std_logic_vector(0 downto 0);
+ gtwiz_userclk_rx_usrclk2_out : out std_logic_vector(0 downto 0);
+ gtwiz_userclk_rx_active_out : out std_logic_vector(0 downto 0);
+ gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0);
+ gtwiz_reset_all_in : in std_logic_vector(0 downto 0);
+ gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0);
+ gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0);
+ gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0);
+ gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0);
+ gtwiz_reset_qpll0lock_in : in std_logic_vector(0 downto 0);
+ gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0);
+ gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0);
+ gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0);
+ gtwiz_reset_qpll0reset_out : out std_logic_vector(0 downto 0);
+ gtwiz_userdata_tx_in : in std_logic_vector(63 downto 0);
+ gtwiz_userdata_rx_out : out std_logic_vector(63 downto 0);
+ drpaddr_in : in std_logic_vector(8 downto 0);
+ drpclk_in : in std_logic_vector(0 downto 0);
+ drpdi_in : in std_logic_vector(15 downto 0);
+ drpen_in : in std_logic_vector(0 downto 0);
+ drpwe_in : in std_logic_vector(0 downto 0);
+ gthrxn_in : in std_logic_vector(0 downto 0);
+ gthrxp_in : in std_logic_vector(0 downto 0);
+ loopback_in : in std_logic_vector(2 downto 0);
+ qpll0clk_in : in std_logic_vector(0 downto 0);
+ qpll0refclk_in : in std_logic_vector(0 downto 0);
+ qpll1clk_in : in std_logic_vector(0 downto 0);
+ qpll1refclk_in : in std_logic_vector(0 downto 0);
+ rxgearboxslip_in : in std_logic_vector(0 downto 0);
+ rxpolarity_in : in std_logic_vector(0 downto 0);
+ txdiffctrl_in : in std_logic_vector(3 downto 0);
+ txheader_in : in std_logic_vector(5 downto 0);
+ txpolarity_in : in std_logic_vector(0 downto 0);
+ txpostcursor_in : in std_logic_vector(4 downto 0);
+ txprecursor_in : in std_logic_vector(4 downto 0);
+ txsequence_in : in std_logic_vector(6 downto 0);
+ drpdo_out : out std_logic_vector(15 downto 0);
+ drprdy_out : out std_logic_vector(0 downto 0);
+ gthtxn_out : out std_logic_vector(0 downto 0);
+ gthtxp_out : out std_logic_vector(0 downto 0);
+ gtpowergood_out : out std_logic_vector(0 downto 0);
+ rxdatavalid_out : out std_logic_vector(1 downto 0);
+ rxheader_out : out std_logic_vector(5 downto 0);
+ rxheadervalid_out : out std_logic_vector(1 downto 0);
+ rxpmaresetdone_out : out std_logic_vector(0 downto 0);
+ rxprgdivresetdone_out : out std_logic_vector(0 downto 0);
+ rxstartofseq_out : out std_logic_vector(1 downto 0);
+ txpmaresetdone_out : out std_logic_vector(0 downto 0);
+ txprgdivresetdone_out : out std_logic_vector(0 downto 0)
+ );
+ end component;
+
+ component Pgp3GthUsIp6G
port (
gtwiz_userclk_tx_reset_in : in std_logic_vector(0 downto 0);
gtwiz_userclk_tx_srcclk_out : out std_logic_vector(0 downto 0);
@@ -183,7 +245,7 @@ begin
clk => txUsrClk2Int, -- [in]
asyncRst => txUsrClkActiveInt, -- [in]
syncRst => txUsrClkRst); -- [out]
- --
+
U_RstSync_RX : entity work.RstSync
generic map (
TPD_G => TPD_G,
@@ -195,67 +257,133 @@ begin
asyncRst => rxUsrClkActiveInt, -- [in]
syncRst => rxUsrClkRst); -- [out]
- U_Pgp3GthUsIp_1 : Pgp3GthUsIp
- port map (
- gtwiz_userclk_tx_reset_in(0) => txReset,
- gtwiz_userclk_tx_srcclk_out(0) => txOutClk,
- gtwiz_userclk_tx_usrclk_out(0) => txUsrClk,
- gtwiz_userclk_tx_usrclk2_out(0) => txUsrClk2Int,
- gtwiz_userclk_tx_active_out(0) => txUsrClkActiveInt,
- gtwiz_userclk_rx_reset_in(0) => rxReset,
- gtwiz_userclk_rx_srcclk_out(0) => rxOutClk,
- gtwiz_userclk_rx_usrclk_out(0) => rxUsrClk,
- gtwiz_userclk_rx_usrclk2_out(0) => rxUsrClk2Int,
- gtwiz_userclk_rx_active_out(0) => rxUsrClkActiveInt,
- gtwiz_reset_clk_freerun_in(0) => stableClk,
- gtwiz_reset_all_in(0) => stableRst,
- gtwiz_reset_tx_pll_and_datapath_in(0) => zeroBit,
- gtwiz_reset_tx_datapath_in(0) => zeroBit,
- gtwiz_reset_rx_pll_and_datapath_in(0) => zeroBit,
- gtwiz_reset_rx_datapath_in(0) => rxReset,
- gtwiz_reset_qpll0lock_in(0) => qpllLock(0),
- gtwiz_reset_rx_cdr_stable_out(0) => dummy5,
- gtwiz_reset_tx_done_out(0) => txResetDone,
- gtwiz_reset_rx_done_out(0) => rxResetDone,
- gtwiz_reset_qpll0reset_out(0) => qpllRst(0),
- gtwiz_userdata_tx_in => txData,
- gtwiz_userdata_rx_out => rxData,
- drpclk_in(0) => stableClk,
- drpaddr_in => drpAddr,
- drpdi_in => drpDi,
- drpen_in(0) => drpEn,
- drpwe_in(0) => drpWe,
- drpdo_out => drpDo,
- drprdy_out(0) => drpRdy,
- gthrxn_in(0) => gtRxN,
- gthrxp_in(0) => gtRxP,
- loopback_in => loopback,
- qpll0clk_in(0) => qpllclk(0),
- qpll0refclk_in(0) => qpllrefclk(0),
- qpll1clk_in(0) => qpllclk(1),
- qpll1refclk_in(0) => qpllrefclk(1),
- rxgearboxslip_in(0) => rxGearboxSlip,
- rxpolarity_in(0) => RX_POLARITY_G,
- txdiffctrl_in => "1111",
- txheader_in => txheader_in,
- txpolarity_in(0) => TX_POLARITY_G,
- txpostcursor_in => "00111",
- txprecursor_in => "00111",
- txsequence_in => txsequence_in,
- gthtxn_out(0) => gtTxN,
- gthtxp_out(0) => gtTxP,
- rxdatavalid_out(0) => rxDataValid,
- rxdatavalid_out(1) => dummy1,
- rxheader_out(1 downto 0) => rxHeader,
- rxheader_out(5 downto 2) => dummy3,
- rxheadervalid_out(0) => rxHeaderValid,
- rxheadervalid_out(1) => dummy4,
- rxpmaresetdone_out(0) => dummy8,
- rxprgdivresetdone_out(0) => dummy9,
- rxstartofseq_out(1) => dummy2,
- rxstartofseq_out(0) => rxStartOfSeq,
- txpmaresetdone_out(0) => dummy10,
- txprgdivresetdone_out(0) => dummy11);
+ GEN_10G : if (RATE_G = "10.3125Gbps") generate
+ U_Pgp3GthUsIp : Pgp3GthUsIp10G
+ port map (
+ gtwiz_userclk_tx_reset_in(0) => txReset,
+ gtwiz_userclk_tx_srcclk_out(0) => txOutClk,
+ gtwiz_userclk_tx_usrclk_out(0) => txUsrClk,
+ gtwiz_userclk_tx_usrclk2_out(0) => txUsrClk2Int,
+ gtwiz_userclk_tx_active_out(0) => txUsrClkActiveInt,
+ gtwiz_userclk_rx_reset_in(0) => rxReset,
+ gtwiz_userclk_rx_srcclk_out(0) => rxOutClk,
+ gtwiz_userclk_rx_usrclk_out(0) => rxUsrClk,
+ gtwiz_userclk_rx_usrclk2_out(0) => rxUsrClk2Int,
+ gtwiz_userclk_rx_active_out(0) => rxUsrClkActiveInt,
+ gtwiz_reset_clk_freerun_in(0) => stableClk,
+ gtwiz_reset_all_in(0) => stableRst,
+ gtwiz_reset_tx_pll_and_datapath_in(0) => zeroBit,
+ gtwiz_reset_tx_datapath_in(0) => zeroBit,
+ gtwiz_reset_rx_pll_and_datapath_in(0) => zeroBit,
+ gtwiz_reset_rx_datapath_in(0) => rxReset,
+ gtwiz_reset_qpll0lock_in(0) => qpllLock(0),
+ gtwiz_reset_rx_cdr_stable_out(0) => dummy5,
+ gtwiz_reset_tx_done_out(0) => txResetDone,
+ gtwiz_reset_rx_done_out(0) => rxResetDone,
+ gtwiz_reset_qpll0reset_out(0) => qpllRst(0),
+ gtwiz_userdata_tx_in => txData,
+ gtwiz_userdata_rx_out => rxData,
+ drpclk_in(0) => stableClk,
+ drpaddr_in => drpAddr,
+ drpdi_in => drpDi,
+ drpen_in(0) => drpEn,
+ drpwe_in(0) => drpWe,
+ drpdo_out => drpDo,
+ drprdy_out(0) => drpRdy,
+ gthrxn_in(0) => gtRxN,
+ gthrxp_in(0) => gtRxP,
+ loopback_in => loopback,
+ qpll0clk_in(0) => qpllclk(0),
+ qpll0refclk_in(0) => qpllrefclk(0),
+ qpll1clk_in(0) => qpllclk(1),
+ qpll1refclk_in(0) => qpllrefclk(1),
+ rxgearboxslip_in(0) => rxGearboxSlip,
+ rxpolarity_in(0) => RX_POLARITY_G,
+ txdiffctrl_in => "1111",
+ txheader_in => txheader_in,
+ txpolarity_in(0) => TX_POLARITY_G,
+ txpostcursor_in => "00111",
+ txprecursor_in => "00111",
+ txsequence_in => txsequence_in,
+ gthtxn_out(0) => gtTxN,
+ gthtxp_out(0) => gtTxP,
+ rxdatavalid_out(0) => rxDataValid,
+ rxdatavalid_out(1) => dummy1,
+ rxheader_out(1 downto 0) => rxHeader,
+ rxheader_out(5 downto 2) => dummy3,
+ rxheadervalid_out(0) => rxHeaderValid,
+ rxheadervalid_out(1) => dummy4,
+ rxpmaresetdone_out(0) => dummy8,
+ rxprgdivresetdone_out(0) => dummy9,
+ rxstartofseq_out(1) => dummy2,
+ rxstartofseq_out(0) => rxStartOfSeq,
+ txpmaresetdone_out(0) => dummy10,
+ txprgdivresetdone_out(0) => dummy11);
+ end generate GEN_10G;
+
+ GEN_6G : if (RATE_G = "6.25Gbps") generate
+ U_Pgp3GthUsIp : Pgp3GthUsIp6G
+ port map (
+ gtwiz_userclk_tx_reset_in(0) => txReset,
+ gtwiz_userclk_tx_srcclk_out(0) => txOutClk,
+ gtwiz_userclk_tx_usrclk_out(0) => txUsrClk,
+ gtwiz_userclk_tx_usrclk2_out(0) => txUsrClk2Int,
+ gtwiz_userclk_tx_active_out(0) => txUsrClkActiveInt,
+ gtwiz_userclk_rx_reset_in(0) => rxReset,
+ gtwiz_userclk_rx_srcclk_out(0) => rxOutClk,
+ gtwiz_userclk_rx_usrclk_out(0) => rxUsrClk,
+ gtwiz_userclk_rx_usrclk2_out(0) => rxUsrClk2Int,
+ gtwiz_userclk_rx_active_out(0) => rxUsrClkActiveInt,
+ gtwiz_reset_clk_freerun_in(0) => stableClk,
+ gtwiz_reset_all_in(0) => stableRst,
+ gtwiz_reset_tx_pll_and_datapath_in(0) => zeroBit,
+ gtwiz_reset_tx_datapath_in(0) => zeroBit,
+ gtwiz_reset_rx_pll_and_datapath_in(0) => zeroBit,
+ gtwiz_reset_rx_datapath_in(0) => rxReset,
+ gtwiz_reset_qpll0lock_in(0) => qpllLock(0),
+ gtwiz_reset_rx_cdr_stable_out(0) => dummy5,
+ gtwiz_reset_tx_done_out(0) => txResetDone,
+ gtwiz_reset_rx_done_out(0) => rxResetDone,
+ gtwiz_reset_qpll0reset_out(0) => qpllRst(0),
+ gtwiz_userdata_tx_in => txData,
+ gtwiz_userdata_rx_out => rxData,
+ drpclk_in(0) => stableClk,
+ drpaddr_in => drpAddr,
+ drpdi_in => drpDi,
+ drpen_in(0) => drpEn,
+ drpwe_in(0) => drpWe,
+ drpdo_out => drpDo,
+ drprdy_out(0) => drpRdy,
+ gthrxn_in(0) => gtRxN,
+ gthrxp_in(0) => gtRxP,
+ loopback_in => loopback,
+ qpll0clk_in(0) => qpllclk(0),
+ qpll0refclk_in(0) => qpllrefclk(0),
+ qpll1clk_in(0) => qpllclk(1),
+ qpll1refclk_in(0) => qpllrefclk(1),
+ rxgearboxslip_in(0) => rxGearboxSlip,
+ rxpolarity_in(0) => RX_POLARITY_G,
+ txdiffctrl_in => "1111",
+ txheader_in => txheader_in,
+ txpolarity_in(0) => TX_POLARITY_G,
+ txpostcursor_in => "00111",
+ txprecursor_in => "00111",
+ txsequence_in => txsequence_in,
+ gthtxn_out(0) => gtTxN,
+ gthtxp_out(0) => gtTxP,
+ rxdatavalid_out(0) => rxDataValid,
+ rxdatavalid_out(1) => dummy1,
+ rxheader_out(1 downto 0) => rxHeader,
+ rxheader_out(5 downto 2) => dummy3,
+ rxheadervalid_out(0) => rxHeaderValid,
+ rxheadervalid_out(1) => dummy4,
+ rxpmaresetdone_out(0) => dummy8,
+ rxprgdivresetdone_out(0) => dummy9,
+ rxstartofseq_out(1) => dummy2,
+ rxstartofseq_out(0) => rxStartOfSeq,
+ txpmaresetdone_out(0) => dummy10,
+ txprgdivresetdone_out(0) => dummy11);
+ end generate GEN_6G;
qpllRst(1) <= '0';
zeroBit <= '0';
diff --git a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd
index ff72699faa..3b1448d2cf 100644
--- a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd
+++ b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd
@@ -2,7 +2,7 @@
-- File : Pgp3GthUsQpll.vhd
-- Company : SLAC National Accelerator Laboratory
-- Created : 2017-10-26
--- Last update: 2018-01-10
+-- Last update: 2018-05-03
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
@@ -28,8 +28,9 @@ use unisim.vcomponents.all;
entity Pgp3GthUsQpll is
generic (
- TPD_G : time := 1 ns;
- EN_DRP_G : boolean := true);
+ TPD_G : time := 1 ns;
+ RATE_G : string := "10.3125Gbps"; -- or "6.25Gbps"
+ EN_DRP_G : boolean := true);
port (
-- Stable Clock and Reset
stableClk : in sl; -- GT needs a stable clock to "boot up"
@@ -51,6 +52,9 @@ end Pgp3GthUsQpll;
architecture mapping of Pgp3GthUsQpll is
+ constant QPLL_CP_C : slv(9 downto 0) := ite((RATE_G = "10.3125Gbps"), "0000011111", "0111111111");
+ constant QPLL_FBDIV_C : positive := ite((RATE_G = "10.3125Gbps"), 66, 80);
+
signal pllRefClk : slv(1 downto 0);
signal pllOutClk : slv(1 downto 0);
signal pllOutRefClk : slv(1 downto 0);
@@ -111,9 +115,9 @@ begin
QPLL_CFG2_G3_G => (others => x"0048"),
QPLL_CFG3_G => (others => x"0120"),
QPLL_CFG4_G => (others => x"0009"),
- QPLL_CP_G => (others => "0000011111"),
+ QPLL_CP_G => (others => QPLL_CP_C),
QPLL_CP_G3_G => (others => "1111111111"),
- QPLL_FBDIV_G => (others => 66),
+ QPLL_FBDIV_G => (others => QPLL_FBDIV_C),
QPLL_FBDIV_G3_G => (others => 80),
QPLL_INIT_CFG0_G => (others => x"02B2"),
QPLL_INIT_CFG1_G => (others => x"00"),
diff --git a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd
index 898ee3fdee..97cfe5ecf7 100644
--- a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd
+++ b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd
@@ -2,7 +2,7 @@
-- File : Pgp3GthUsWrapper.vhd
-- Company : SLAC National Accelerator Laboratory
-- Created : 2017-10-27
--- Last update: 2018-05-02
+-- Last update: 2018-05-03
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
@@ -35,6 +35,7 @@ entity Pgp3GthUsWrapper is
NUM_LANES_G : positive range 1 to 4 := 1;
NUM_VC_G : positive range 1 to 16 := 4;
REFCLK_G : boolean := false; -- FALSE: pgpRefClkP/N, TRUE: pgpRefClkIn
+ RATE_G : string := "10.3125Gbps"; -- or "6.25Gbps"
----------------------------------------------------------------------------------------------
-- PGP Settings
----------------------------------------------------------------------------------------------
@@ -176,6 +177,7 @@ begin
U_QPLL : entity work.Pgp3GthUsQpll
generic map (
TPD_G => TPD_G,
+ RATE_G => RATE_G,
EN_DRP_G => EN_QPLL_DRP_G)
port map (
-- Stable Clock and Reset
@@ -194,7 +196,6 @@ begin
axilWriteMaster => axilWriteMasters(QPLL_AXIL_INDEX_C), -- [in]
axilWriteSlave => axilWriteSlaves(QPLL_AXIL_INDEX_C)); -- [out]
-
-----------
-- PGP Core
-----------
@@ -202,6 +203,7 @@ begin
U_Pgp : entity work.Pgp3GthUs
generic map (
TPD_G => TPD_G,
+ RATE_G => RATE_G,
----------------------------------------------------------------------------------------------
-- PGP Settings
----------------------------------------------------------------------------------------------
diff --git a/protocols/pgp/pgp3/gthUs/ruckus.tcl b/protocols/pgp/pgp3/gthUs/ruckus.tcl
index 858c96c1ca..d6deae2c4a 100644
--- a/protocols/pgp/pgp3/gthUs/ruckus.tcl
+++ b/protocols/pgp/pgp3/gthUs/ruckus.tcl
@@ -7,8 +7,11 @@ if { $::env(VIVADO_VERSION) >= 2017.3 } {
# Load Source Code
loadSource -dir "$::DIR_PATH/rtl/"
- loadSource -path "$::DIR_PATH/ip/Pgp3GthUsIp/Pgp3GthUsIp.dcp"
- # loadIpCore -path "$::DIR_PATH/ip/Pgp3GthUsIp/Pgp3GthUsIp.xci"
+ loadSource -path "$::DIR_PATH/ip/Pgp3GthUsIp10G/Pgp3GthUsIp10G.dcp"
+ # loadIpCore -path "$::DIR_PATH/ip/Pgp3GthUsIp10G/Pgp3GthUsIp10G.xci"
+
+ loadSource -path "$::DIR_PATH/ip/Pgp3GthUsIp6G/Pgp3GthUsIp6G.dcp"
+ # loadIpCore -path "$::DIR_PATH/ip/Pgp3GthUsIp6G/Pgp3GthUsIp6G.xci"
} else {
puts "\n\nWARNING: $::DIR_PATH requires Vivado 2017.3 (or later)\n\n"
diff --git a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7.vhd b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7.vhd
index cd4a1d6e60..831cf689c3 100644
--- a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7.vhd
+++ b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7.vhd
@@ -32,7 +32,7 @@ use UNISIM.VCOMPONENTS.all;
entity Pgp3Gtx7 is
generic (
TPD_G : time := 1 ns;
- RATE_G : boolean := true; -- true = 10.3125 Gbps, false = 6.25 Gbps
+ RATE_G : string := "10.3125Gbps"; -- or "6.25Gbps"
----------------------------------------------------------------------------------------------
-- PGP Settings
----------------------------------------------------------------------------------------------
@@ -155,6 +155,10 @@ architecture rtl of Pgp3Gtx7 is
begin
+ assert ((RATE_G = "6.25Gbps") or (RATE_G = "10.3125Gbps"))
+ report "RATE_G: Must be either 6.25Gbps or 10.3125Gbps"
+ severity error;
+
pgpClk <= pgpTxClkInt;
pgpClkRst <= pgpTxRstInt;
diff --git a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7IpWrapper.vhd b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7IpWrapper.vhd
index ed1c5e8fc8..30b39bad88 100644
--- a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7IpWrapper.vhd
+++ b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7IpWrapper.vhd
@@ -28,7 +28,7 @@ entity Pgp3Gtx7IpWrapper is
generic (
TPD_G : time := 1 ns;
EN_DRP_G : boolean := true;
- RATE_G : boolean := true; -- true = 10.3125 Gbps, false = 6.25 Gbps
+ RATE_G : string := "10.3125Gbps"; -- or "6.25Gbps"
TX_POLARITY_G : sl := '0';
RX_POLARITY_G : sl := '0');
port (
@@ -339,11 +339,11 @@ begin
INPUT_BUFG_G => true,
FB_BUFG_G => false,
NUM_CLOCKS_G => 2,
- CLKIN_PERIOD_G => ite(RATE_G, 3.103, 5.12),
+ CLKIN_PERIOD_G => ite((RATE_G = "10.3125Gbps"), 3.103, 5.12),
DIVCLK_DIVIDE_G => 1,
- CLKFBOUT_MULT_G => ite(RATE_G, 3, 5),
- CLKOUT0_DIVIDE_G => ite(RATE_G, 3, 5),
- CLKOUT1_DIVIDE_G => ite(RATE_G, 6, 10))
+ CLKFBOUT_MULT_G => ite((RATE_G = "10.3125Gbps"), 3, 5),
+ CLKOUT0_DIVIDE_G => ite((RATE_G = "10.3125Gbps"), 3, 5),
+ CLKOUT1_DIVIDE_G => ite((RATE_G = "10.3125Gbps"), 6, 10))
port map(
clkIn => gtRxOutClk,
rstIn => gtRxPllRst,
@@ -367,7 +367,7 @@ begin
end if;
end process;
- GEN_10G : if (RATE_G = true) generate
+ GEN_10G : if (RATE_G = "10.3125Gbps") generate
U_Pgp3Gtx7Ip10G : Pgp3Gtx7Ip10G
port map (
SYSCLK_IN => stableClk,
@@ -474,7 +474,7 @@ begin
GT0_QPLLOUTREFCLK_IN => qpllrefclk);
end generate;
- GEN_6G : if (RATE_G = false) generate
+ GEN_6G : if (RATE_G = "6.25Gbps") generate
U_Pgp3Gtx7Ip6G : Pgp3Gtx7Ip6G
port map (
SYSCLK_IN => stableClk,
diff --git a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Qpll.vhd b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Qpll.vhd
index 88c08330d8..6cb15671de 100644
--- a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Qpll.vhd
+++ b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Qpll.vhd
@@ -32,7 +32,7 @@ entity Pgp3Gtx7Qpll is
TPD_G : time := 1 ns;
EN_DRP_G : boolean := true;
REFCLK_TYPE_G : Pgp3RefClkType := PGP3_REFCLK_312_C;
- RATE_G : boolean := true); -- true = 10.3125 Gbps, false = 6.25 Gbps
+ RATE_G : string := "10.3125Gbps"); -- or "6.25Gbps"
port (
-- Stable Clock and Reset
stableClk : in sl; -- GT needs a stable clock to "boot up"
@@ -58,9 +58,9 @@ architecture mapping of Pgp3Gtx7Qpll is
impure function GenQpllfbdivTop return integer is
begin
-------------------------------
- -- RATE_G = true = 10.3125 Gbps
+ -- RATE_G = 10.3125Gbps
-------------------------------
- if (RATE_G) then
+ if ((RATE_G = "10.3125Gbps")) then
if (REFCLK_TYPE_G = PGP3_REFCLK_312_C) then
return 66;
elsif (REFCLK_TYPE_G = PGP3_REFCLK_156_C) then
@@ -69,7 +69,7 @@ architecture mapping of Pgp3Gtx7Qpll is
return -1;
end if;
-----------------------------
- -- RATE_G = false = 6.25 Gbps
+ -- RATE_G = 6.25Gbps
-----------------------------
else
if (REFCLK_TYPE_G = PGP3_REFCLK_312_C) then
@@ -135,9 +135,9 @@ architecture mapping of Pgp3Gtx7Qpll is
impure function GenRefclkDiv return integer is
begin
-------------------------------
- -- RATE_G = true = 10.3125 Gbps
+ -- RATE_G = 10.3125Gbps
-------------------------------
- if (RATE_G) then
+ if (RATE_G = "10.3125Gbps") then
if (REFCLK_TYPE_G = PGP3_REFCLK_312_C) then
return 2;
elsif (REFCLK_TYPE_G = PGP3_REFCLK_156_C) then
@@ -146,7 +146,7 @@ architecture mapping of Pgp3Gtx7Qpll is
return -1;
end if;
-----------------------------
- -- RATE_G = false = 6.25 Gbps
+ -- RATE_G = 6.25Gbps
-----------------------------
else
if (REFCLK_TYPE_G = PGP3_REFCLK_312_C) then
@@ -163,7 +163,7 @@ architecture mapping of Pgp3Gtx7Qpll is
end if;
end function;
- constant QPLL_CFG_C : bit_vector := ite(RATE_G, x"0680181", x"06801C1");
+ constant QPLL_CFG_C : bit_vector := ite((RATE_G = "10.3125Gbps"), x"0680181", x"06801C1");
constant QPLL_FBDIV_TOP_C : positive := GenQpllfbdivTop;
constant QPLL_FBDIV_C : bit_vector := GenQplFfbdivTop(QPLL_FBDIV_TOP_C);
constant QPLL_FBDIV_RATIO_C : bit := GenQpllFbdivRatio(QPLL_FBDIV_TOP_C);
diff --git a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Wrapper.vhd b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Wrapper.vhd
index 0be21fd49d..3b9100d6e4 100644
--- a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Wrapper.vhd
+++ b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Wrapper.vhd
@@ -34,7 +34,7 @@ entity Pgp3Gtx7Wrapper is
TPD_G : time := 1 ns;
NUM_LANES_G : positive range 1 to 4 := 1;
NUM_VC_G : positive range 1 to 16 := 4;
- RATE_G : boolean := true; -- true = 10.3125 Gbps, false = 6.25 Gbps
+ RATE_G : string := "10.3125Gbps"; -- or "6.25Gbps"
REFCLK_TYPE_G : Pgp3RefClkType := PGP3_REFCLK_312_C;
REFCLK_G : boolean := false; -- FALSE: use pgpRefClkP/N, TRUE: use pgpRefClkIn
----------------------------------------------------------------------------------------------
@@ -310,11 +310,11 @@ begin
INPUT_BUFG_G => true,
FB_BUFG_G => false,
NUM_CLOCKS_G => 2,
- CLKIN_PERIOD_G => ite(RATE_G, 3.103, 5.12),
+ CLKIN_PERIOD_G => ite((RATE_G = "10.3125Gbps"), 3.103, 5.12),
DIVCLK_DIVIDE_G => 1,
- CLKFBOUT_MULT_G => ite(RATE_G, 3, 5),
- CLKOUT0_DIVIDE_G => ite(RATE_G, 3, 5),
- CLKOUT1_DIVIDE_G => ite(RATE_G, 6, 10))
+ CLKFBOUT_MULT_G => ite((RATE_G = "10.3125Gbps"), 3, 5),
+ CLKOUT0_DIVIDE_G => ite((RATE_G = "10.3125Gbps"), 3, 5),
+ CLKOUT1_DIVIDE_G => ite((RATE_G = "10.3125Gbps"), 6, 10))
port map(
clkIn => gtTxOutClk(0),
rstIn => gtTxPllRst(0),
diff --git a/python/surf/devices/linear/_Ltc4151.py b/python/surf/devices/linear/_Ltc4151.py
new file mode 100644
index 0000000000..c368caca84
--- /dev/null
+++ b/python/surf/devices/linear/_Ltc4151.py
@@ -0,0 +1,155 @@
+#!/usr/bin/env python
+#-----------------------------------------------------------------------------
+# Title : PyRogue _Ltc2945 Module
+#-----------------------------------------------------------------------------
+# File : _Ltc2945.py
+# Created : 2017-01-17
+# Last update: 2017-01-17
+#-----------------------------------------------------------------------------
+# Description:
+# PyRogue _Ltc2945 Module
+#-----------------------------------------------------------------------------
+# This file is part of 'SLAC Firmware Standard Library'.
+# It is subject to the license terms in the LICENSE.txt file found in the
+# top-level directory of this distribution and at:
+# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+# No part of 'SLAC Firmware Standard Library', including this file,
+# may be copied, modified, propagated, or distributed except according to
+# the terms contained in the LICENSE.txt file.
+#-----------------------------------------------------------------------------
+
+import pyrogue as pr
+
+class Ltc4151(pr.Device):
+ def __init__(self,
+ name = "Ltc4151",
+ description = "Container for Ltc4151",
+ pollInterval = 1,
+ senseRes = 20.E-3, # Units of Ohms
+ **kwargs):
+ super().__init__(name=name, description=description, **kwargs)
+
+ self.senseRes = senseRes
+
+ self.add(pr.RemoteVariable(
+ name = 'SenseMsb',
+ description = 'Sense MSB Data',
+ offset = (0x0 << 2),
+ bitSize = 8,
+ bitOffset = 0,
+ base = pr.UInt,
+ mode = 'RO',
+ pollInterval = pollInterval,
+ hidden = True,
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'SenseLsb',
+ description = 'Sense LSB Data',
+ offset = (0x1 << 2),
+ bitSize = 4,
+ bitOffset = 4,
+ base = pr.UInt,
+ mode = 'RO',
+ pollInterval = pollInterval,
+ hidden = True,
+ ))
+
+ self.add(pr.LinkVariable(
+ name = 'Iin',
+ description = 'Current Measurment',
+ mode = 'RO',
+ units = 'A',
+ disp = '{:1.3f}',
+ dependencies = [self.SenseMsb,self.SenseLsb],
+ linkedGet = lambda: (int(self.SenseMsb.value()<<4)|int(self.SenseLsb.value()&0xF))*20.0E-6/self.senseRes
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'VinMsb',
+ description = 'Vin MSB Data',
+ offset = (0x2 << 2),
+ bitSize = 8,
+ bitOffset = 0,
+ base = pr.UInt,
+ mode = 'RO',
+ pollInterval = pollInterval,
+ hidden = True,
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'VinLsb',
+ description = 'Vin LSB Data',
+ offset = (0x3 << 2),
+ bitSize = 4,
+ bitOffset = 4,
+ base = pr.UInt,
+ mode = 'RO',
+ pollInterval = pollInterval,
+ hidden = True,
+ ))
+
+ self.add(pr.LinkVariable(
+ name = 'Vin',
+ description = 'Voltage Measurment',
+ mode = 'RO',
+ units = 'V',
+ disp = '{:1.3f}',
+ dependencies = [self.VinMsb,self.VinLsb],
+ linkedGet = lambda: (int(self.VinMsb.value()<<4)|int(self.VinLsb.value()&0xF))*25.0E-3
+ ))
+
+ self.add(pr.LinkVariable(
+ name = 'Pin',
+ description = 'Power Measurment',
+ mode = 'RO',
+ units = 'W',
+ disp = '{:1.3f}',
+ dependencies = [self.Vin,self.Iin],
+ linkedGet = lambda: (self.Vin.value())*(self.Iin.value())
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'AdinMsb',
+ description = 'Adin MSB Data',
+ offset = (0x4 << 2),
+ bitSize = 8,
+ bitOffset = 0,
+ base = pr.UInt,
+ mode = 'RO',
+ pollInterval = pollInterval,
+ hidden = True,
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'AdinLsb',
+ description = 'Adin LSB Data',
+ offset = (0x5 << 2),
+ bitSize = 4,
+ bitOffset = 4,
+ base = pr.UInt,
+ mode = 'RO',
+ pollInterval = pollInterval,
+ hidden = True,
+ ))
+
+ self.add(pr.LinkVariable(
+ name = 'ADC Input',
+ description = 'ADC Voltage Measurment',
+ mode = 'RO',
+ units = 'V',
+ disp = '{:1.3f}',
+ dependencies = [self.AdinMsb,self.AdinLsb],
+ linkedGet = lambda: (int(self.AdinMsb.value()<<4)|int(self.AdinLsb.value()&0xF))*500.0E-6
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'Control',
+ description = 'Controls ADC Operation Mode and Test Mode',
+ offset = (0x06 << 2),
+ bitSize = 8,
+ bitOffset = 0,
+ base = pr.UInt,
+ mode = 'RW',
+ ))
+
\ No newline at end of file
diff --git a/python/surf/devices/linear/__init__.py b/python/surf/devices/linear/__init__.py
index dfb4d8eb0d..091310662c 100644
--- a/python/surf/devices/linear/__init__.py
+++ b/python/surf/devices/linear/__init__.py
@@ -10,3 +10,4 @@
##############################################################################
from surf.devices.linear._ltc2270 import *
from surf.devices.linear._Ltc2945 import *
+from surf.devices.linear._Ltc4151 import *
diff --git a/python/surf/devices/micron/_AxiMicronMt28ew.py b/python/surf/devices/micron/_AxiMicronMt28ew.py
index 0b7d322d8a..a998433713 100644
--- a/python/surf/devices/micron/_AxiMicronMt28ew.py
+++ b/python/surf/devices/micron/_AxiMicronMt28ew.py
@@ -83,7 +83,7 @@ def LoadMcsFile(arg):
***************************************************\n\
The MCS data has been written into the PROM. \n\
To reprogram the FPGA with the new PROM data, \n\
- a IPROG CMD, reboot, or power cycle is be required.\n\
+ a IPROG CMD or power cycle is be required.\n\
***************************************************\n\
***************************************************\n\n"\
, bg='green',
diff --git a/python/surf/devices/micron/_AxiMicronN25Q.py b/python/surf/devices/micron/_AxiMicronN25Q.py
index 2eb28464af..edebcac364 100644
--- a/python/surf/devices/micron/_AxiMicronN25Q.py
+++ b/python/surf/devices/micron/_AxiMicronN25Q.py
@@ -145,7 +145,7 @@ def LoadMcsFile(arg):
***************************************************\n\
The MCS data has been written into the PROM. \n\
To reprogram the FPGA with the new PROM data, \n\
- a IPROG CMD, reboot, or power cycle is be required.\n\
+ a IPROG CMD or power cycle is be required.\n\
***************************************************\n\
***************************************************\n\n"\
, bg='green',
diff --git a/python/surf/devices/micron/_AxiMicronP30.py b/python/surf/devices/micron/_AxiMicronP30.py
index 8565d5a0b5..5c7e8b82ac 100644
--- a/python/surf/devices/micron/_AxiMicronP30.py
+++ b/python/surf/devices/micron/_AxiMicronP30.py
@@ -89,7 +89,7 @@ def LoadMcsFile(arg):
***************************************************\n\
The MCS data has been written into the PROM. \n\
To reprogram the FPGA with the new PROM data, \n\
- a IPROG CMD, reboot, or power cycle is be required.\n\
+ a IPROG CMD or power cycle is be required.\n\
***************************************************\n\
***************************************************\n\n"\
, bg='green',
diff --git a/python/surf/devices/nxp/_Sa56004x.py b/python/surf/devices/nxp/_Sa56004x.py
index 3e498549ba..4c39db6ee9 100644
--- a/python/surf/devices/nxp/_Sa56004x.py
+++ b/python/surf/devices/nxp/_Sa56004x.py
@@ -6,8 +6,8 @@
# Created : 2017-01-17
# Last update: 2017-01-17
#-----------------------------------------------------------------------------
-# Description:
-# PyRogue _Sa56004x Module
+# Description: PyRogue _Sa56004x Module
+# Note: This implementation doesn't use LSB and rounds all variables to 1 degC
#-----------------------------------------------------------------------------
# This file is part of 'SLAC Firmware Standard Library'.
# It is subject to the license terms in the LICENSE.txt file found in the
@@ -24,78 +24,324 @@ class Sa56004x(pr.Device):
def __init__(self,
name = "Sa56004x",
description = "Sa56004x",
+ pollInterval = 1,
**kwargs):
super().__init__(name=name, description=description, **kwargs)
+ ############################################################################
+
+ def getTempReg(var):
+ x = var.dependencies[0].value()
+ sign = x >> 7 # Get the sign bit
+ x &= 0x7F # mask off sign bit
+ x = float(x)# Covert to degC
+ if (sign==1):
+ x *= -1.0
+ return int(x)
+
+ def setTempReg(deps):
+ def setTempValues(var, value, write):
+ if (value<0):
+ sign = 0x80
+ else:
+ sign = 0x00
+ x = int(abs(value))
+ rawVal = (x&0xFF) | sign
+ deps[0].set(rawVal,write)
+ return setTempValues
+
+ def addBoolPair(name,description,rdOffset,wrOffset,bitOffset):
+ self.add(pr.RemoteVariable(
+ name = (name+"Read"),
+ description = description,
+ offset = rdOffset,
+ bitSize = 1,
+ bitOffset = bitOffset,
+ base = pr.Bool,
+ mode = 'RO',
+ hidden = True,
+ ))
+ self.add(pr.RemoteVariable(
+ name = (name+"Write"),
+ description = description,
+ offset = wrOffset,
+ bitSize = 1,
+ bitOffset = bitOffset,
+ base = pr.Bool,
+ mode = 'WO',
+ hidden = True,
+ ))
+
+ rdVar = self.variables[name+"Read"]
+ wrVar = self.variables[name+"Write"]
+
+ self.add(pr.LinkVariable(
+ name = name,
+ description = description,
+ mode = 'RW',
+ linkedGet = lambda: rdVar.value(),
+ linkedSet = lambda value, write: wrVar.set(value),
+ dependencies = [rdVar],
+ enum = {
+ False: 'False',
+ True: 'True',
+ },
+
+ ))
+
+ ############################################################################
+
self.add(pr.RemoteVariable(
name = 'LocalTemperatureHighByte',
- description = 'local temperature high byte (LTHB)',
+ description = 'Local temperature high byte (LTHB)',
offset = (0x00 << 2),
bitSize = 8,
bitOffset = 0,
base = pr.UInt,
mode = 'RO',
- ))
+ pollInterval= pollInterval,
+ hidden = True,
+ ))
+
+ self.add(pr.LinkVariable(
+ name = 'LocalTemperature',
+ description = 'Local temperature',
+ mode = 'RO',
+ units = 'degC',
+ linkedGet = getTempReg,
+ disp = '{:d}',
+ dependencies = [self.LocalTemperatureHighByte],
+ ))
+ ############################################################################
+
self.add(pr.RemoteVariable(
name = 'RemoteTemperatureHighByte',
- description = 'remote temperature high byte (RTHB)',
+ description = 'Remote temperature high byte (RTHB)',
offset = (0x01 << 2),
bitSize = 8,
bitOffset = 0,
base = pr.UInt,
mode = 'RO',
- ))
+ pollInterval= pollInterval,
+ hidden = True,
+ ))
+
+ self.add(pr.LinkVariable(
+ name = 'RemoteTemperature',
+ description = 'Remote Temperature',
+ mode = 'RO',
+ units = 'degC',
+ linkedGet = getTempReg,
+ disp = '{:d}',
+ dependencies = [self.RemoteTemperatureHighByte],
+ ))
+
+ ############################################################################
self.add(pr.RemoteVariable(
- name = 'StatusRegister',
- description = 'status register (SR)',
+ name = 'Busy',
+ description = 'When logic 1, A/D is busy converting. POR state = n/a.',
offset = (0x02 << 2),
- bitSize = 8,
- bitOffset = 0,
- base = pr.UInt,
+ bitSize = 1,
+ bitOffset = 7,
+ base = pr.Bool,
mode = 'RO',
- ))
+ pollInterval= pollInterval,
+ hidden = True,
+ ))
self.add(pr.RemoteVariable(
- name = 'ConfigurationRegisterRead',
- description = 'configuration register read access (CON))',
- offset = (0x03 << 2),
- bitSize = 8,
- bitOffset = 0,
- base = pr.UInt,
+ name = 'Lhigh',
+ description = 'When logic 1, indicates local HIGH temperature alarm. POR state = 0.',
+ offset = (0x02 << 2),
+ bitSize = 1,
+ bitOffset = 6,
+ base = pr.Bool,
mode = 'RO',
- ))
-
+ pollInterval= pollInterval,
+ ))
+
self.add(pr.RemoteVariable(
- name = 'ConfigurationRegisterWrite',
- description = 'configuration register write access (CON))',
- offset = (0x09 << 2),
- bitSize = 8,
+ name = 'Llow',
+ description = 'When logic 1, indicates a local LOW temperature alarm. POR state = 0.',
+ offset = (0x02 << 2),
+ bitSize = 1,
+ bitOffset = 5,
+ base = pr.Bool,
+ mode = 'RO',
+ pollInterval= pollInterval,
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'Rhigh',
+ description = 'When logic 1, indicates a remote diode HIGH temperature alarm. POR state = 0.',
+ offset = (0x02 << 2),
+ bitSize = 1,
+ bitOffset = 4,
+ base = pr.Bool,
+ mode = 'RO',
+ pollInterval= pollInterval,
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'Rlow',
+ description = 'When logic 1, indicates a remote diode LOW temperature alarm. POR state = 0.',
+ offset = (0x02 << 2),
+ bitSize = 1,
+ bitOffset = 3,
+ base = pr.Bool,
+ mode = 'RO',
+ pollInterval= pollInterval,
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'Open',
+ description = 'When logic 1, indicates a remote diode disconnect. POR state = 0.',
+ offset = (0x02 << 2),
+ bitSize = 1,
+ bitOffset = 2,
+ base = pr.Bool,
+ mode = 'RO',
+ pollInterval= pollInterval,
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'Rcrit',
+ description = 'When logic 1, indicates a remote diode critical temperature alarm. POR state = 0.',
+ offset = (0x02 << 2),
+ bitSize = 1,
+ bitOffset = 1,
+ base = pr.Bool,
+ mode = 'RO',
+ pollInterval= pollInterval,
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'Lcrit',
+ description = 'When logic 1, indicates a local critical temperature alarm. POR state = 0.',
+ offset = (0x02 << 2),
+ bitSize = 1,
bitOffset = 0,
- base = pr.UInt,
- mode = 'WO',
+ base = pr.Bool,
+ mode = 'RO',
+ pollInterval= pollInterval,
))
+
+ ############################################################################
+
+ addBoolPair(
+ name = 'AlertMask',
+ rdOffset = (0x03 << 2),
+ wrOffset = (0x09 << 2),
+ bitOffset = 7,
+ description = """
+ The ALERT interrupt is enabled when this bit is LOW. The
+ ALERT interrupt is disabled (masked) when this bit is HIGH.
+ """,
+ )
+
+ addBoolPair(
+ name = 'Stop',
+ rdOffset = (0x03 << 2),
+ wrOffset = (0x09 << 2),
+ bitOffset = 6,
+ description = """
+ Standby or run mode control. Running mode is enabled when
+ this bit is LOW. The SA56004X is in standby mode when this
+ bit is HIGH.
+ """,
+
+ )
+
+ addBoolPair(
+ name = 'RcritMask',
+ rdOffset = (0x03 << 2),
+ wrOffset = (0x09 << 2),
+ bitOffset = 4,
+ description = """
+ The T_CRIT output will be activated by a remote temperature
+ that exceeds the remote T_CRIT setpoint when this bit is LOW.
+ The T_CRIT output will not be activated under this condition
+ when this bit is HIGH.
+ """,
+ )
+ addBoolPair(
+ name = 'LcritMask',
+ rdOffset = (0x03 << 2),
+ wrOffset = (0x09 << 2),
+ bitOffset = 2,
+ description = """
+ The T_CRIT output will be activated by a local temperature that
+ exceeds the local T_CRIT setpoint when this bit is LOW. The
+ T_CRIT output will not be activated under this condition when
+ this bit is HIGH.
+ """,
+ )
+
+ addBoolPair(
+ name = 'FaultQueue',
+ rdOffset = (0x03 << 2),
+ wrOffset = (0x09 << 2),
+ bitOffset = 0,
+ description = """
+ A single remote temperature measurement outside the HIGH,
+ LOW or T_CRIT setpoints will trigger an outside limit condition
+ resulting in setting the status bits and associated output pins
+ when this bit is LOW. Three consecutive measurements outside of
+ one of these setpoints are required to trigger an outside of
+ limit condition when this bit is HIGH.""",
+ )
+
+ ############################################################################
+
self.add(pr.RemoteVariable(
- name = 'ConversionRateRead',
+ name = 'ConvertRateRead',
description = 'conversion rate read access (CR)',
offset = (0x04 << 2),
bitSize = 4,
bitOffset = 0,
base = pr.UInt,
mode = 'RO',
+ hidden = True,
))
self.add(pr.RemoteVariable(
- name = 'ConversionRateWrite',
+ name = 'ConvertRateWrite',
description = 'conversion rate write access (CR)',
offset = (0x0A << 2),
bitSize = 4,
bitOffset = 0,
base = pr.UInt,
- mode = 'WO',
- ))
+ mode = 'WO',
+ hidden = True,
+ ))
+
+ self.add(pr.LinkVariable(
+ name = 'ConvertRate',
+ description = 'Conversion rate',
+ mode = 'RW',
+ linkedGet = lambda: self.ConvertRateRead.value(),
+ linkedSet = lambda value, write: self.ConvertRateWrite.set(value),
+ dependencies = [self.ConvertRateRead],
+ units = 'Hz',
+ enum = {
+ 0x00: '0.06',
+ 0x01: '0.12',
+ 0x02: '0.25',
+ 0x03: '0.50',
+ 0x04: '1.0',
+ 0x05: '2',
+ 0x06: '4',
+ 0x07: '8',
+ 0x08: '16',
+ 0x09: '32',
+ },
+
+ ))
+
+ ############################################################################
self.add(pr.RemoteVariable(
name = 'LocalHighSetpointRead',
@@ -104,9 +350,10 @@ def __init__(self,
bitSize = 8,
bitOffset = 0,
base = pr.UInt,
- mode = 'RO',
+ mode = 'RO',
+ hidden = True,
))
-
+
self.add(pr.RemoteVariable(
name = 'LocalHighSetpointWrite',
description = 'local high setpoint write access (LHS)',
@@ -115,182 +362,185 @@ def __init__(self,
bitOffset = 0,
base = pr.UInt,
mode = 'WO',
+ hidden = True,
))
+ self.add(pr.LinkVariable(
+ name = 'LocalHighSetpoint',
+ description = 'Local High setpoint',
+ mode = 'RW',
+ linkedGet = getTempReg,
+ linkedSet = setTempReg([self.LocalHighSetpointWrite]),
+ dependencies = [self.LocalHighSetpointRead],
+ units = 'degC',
+ ))
+
+ ############################################################################
+
self.add(pr.RemoteVariable(
name = 'LocalLowSetpointRead',
- description = 'local low setpoint read access (LLS)',
+ description = 'Local Low setpoint read access (LLS)',
offset = (0x06 << 2),
bitSize = 8,
bitOffset = 0,
base = pr.UInt,
- mode = 'RO',
+ mode = 'RO',
+ hidden = True,
))
-
+
self.add(pr.RemoteVariable(
name = 'LocalLowSetpointWrite',
- description = 'local low setpoint write access (LLS)',
+ description = 'Local Low setpoint write access (LLS)',
offset = (0x0C << 2),
bitSize = 8,
bitOffset = 0,
base = pr.UInt,
mode = 'WO',
- ))
-
+ hidden = True,
+ ))
+
+ self.add(pr.LinkVariable(
+ name = 'LocalLowSetpoint',
+ description = 'Local low setpoint',
+ mode = 'RW',
+ linkedGet = getTempReg,
+ linkedSet = setTempReg([self.LocalLowSetpointWrite]),
+ dependencies = [self.LocalLowSetpointRead],
+ units = 'degC',
+ ))
+
+ ############################################################################
+
self.add(pr.RemoteVariable(
name = 'RemoteHighSetpointHighByteRead',
- description = 'remote high setpoint high byte read access (RHSHB)',
+ description = 'Remote high setpoint high byte read access (RHSHB)',
offset = (0x07 << 2),
bitSize = 8,
bitOffset = 0,
base = pr.UInt,
mode = 'RO',
+ hidden = True,
))
-
+
self.add(pr.RemoteVariable(
name = 'RemoteHighSetpointHighByteWrite',
- description = 'remote high setpoint high byte write access (RHSHB)',
+ description = 'Remote high setpoint high byte write access (RHSHB)',
offset = (0x0D << 2),
bitSize = 8,
bitOffset = 0,
base = pr.UInt,
mode = 'WO',
+ hidden = True,
))
+
+ self.add(pr.LinkVariable(
+ name = 'RemoteHighSetpoint',
+ description = 'Remote High setpoint',
+ mode = 'RW',
+ linkedGet = getTempReg,
+ linkedSet = setTempReg([self.RemoteHighSetpointHighByteWrite]),
+ dependencies = [self.RemoteHighSetpointHighByteRead],
+ units = 'degC',
+ ))
+ ############################################################################
+
self.add(pr.RemoteVariable(
- name = 'RemoteHighSetpointLowByteRead',
- description = 'remote high setpoint low byte read access (RLSHB)',
+ name = 'RemoteLowSetpointHighByteRead',
+ description = 'Remote Low setpoint high byte read access (RLSHB)',
offset = (0x08 << 2),
bitSize = 8,
bitOffset = 0,
base = pr.UInt,
mode = 'RO',
+ hidden = True,
))
-
+
self.add(pr.RemoteVariable(
- name = 'RemoteHighSetpointLowByteWrite',
- description = 'remote high setpoint low byte write access (RLSHB)',
+ name = 'RemoteLowSetpointHighByteWrite',
+ description = 'Remote Low setpoint high byte write access (RLSHB)',
offset = (0x0E << 2),
bitSize = 8,
bitOffset = 0,
base = pr.UInt,
mode = 'WO',
- ))
+ hidden = True,
+ ))
- self.add(pr.RemoteCommand(
- name = 'OneShot',
- description = 'writing register initiates a one-shot conversion (One Shot)',
- offset = (0x0F << 2),
- bitSize = 1,
- bitOffset = 0,
- base = pr.UInt,
- function = lambda cmd: cmd.set(1),
- hidden = False,
- ))
+ self.add(pr.LinkVariable(
+ name = 'RemoteLowSetpoint',
+ description = 'Remote Low setpoint',
+ mode = 'RW',
+ linkedGet = getTempReg,
+ linkedSet = setTempReg([self.RemoteLowSetpointHighByteWrite]),
+ dependencies = [self.RemoteLowSetpointHighByteRead],
+ units = 'degC',
+ ))
+
+ ############################################################################
self.add(pr.RemoteVariable(
- name = 'RemoteTemperatureLowByte',
- description = 'remote temperature low byte (RTLB)',
- offset = (0x10 << 2),
- bitSize = 6,
- bitOffset = 2,
- base = pr.UInt,
- mode = 'RO',
- ))
-
- self.add(pr.RemoteVariable(
- name = 'RemoteTemperatureOffsetHighByte',
- description = 'remote temperature offset high byte (RTOHB)',
- offset = (0x11 << 2),
- bitSize = 8,
- bitOffset = 0,
- base = pr.UInt,
- mode = 'RW',
- ))
-
- self.add(pr.RemoteVariable(
- name = 'RemoteTemperatureOffsetLowByte',
- description = 'remote temperature offset low byte (RTOLB)',
- offset = (0x12 << 2),
- bitSize = 3,
- bitOffset = 5,
- base = pr.UInt,
- mode = 'RW',
- ))
-
- self.add(pr.RemoteVariable(
- name = 'RemoteHighSetpointLowByte',
- description = 'remote high setpoint low byte (RHSLB)',
- offset = (0x13 << 2),
- bitSize = 3,
- bitOffset = 5,
- base = pr.UInt,
- mode = 'RW',
- ))
-
- self.add(pr.RemoteVariable(
- name = 'RemoteLowSetpointLowByte',
- description = 'remote low setpoint low byte (RLSLB)',
- offset = (0x14 << 2),
- bitSize = 3,
- bitOffset = 5,
- base = pr.UInt,
- mode = 'RW',
- ))
-
- self.add(pr.RemoteVariable(
- name = 'RemoteTCritSetpoint',
- description = 'remote T_CRIT setpoint (RCS)',
+ name = 'RemoteTcritSetpoint',
+ description = 'Remote T_CRIT setpoint (RCS)',
offset = (0x19 << 2),
bitSize = 8,
bitOffset = 0,
- base = pr.UInt,
+ base = pr.Int,
mode = 'RW',
+ units = 'degC',
+ disp = '{:d}',
))
self.add(pr.RemoteVariable(
- name = 'LocalTCritSetpoint',
- description = 'local T_CRIT setpoint (LCS)',
+ name = 'LocalTcritSetpoint',
+ description = 'Local T_CRIT setpoint (LCS)',
offset = (0x20 << 2),
bitSize = 8,
bitOffset = 0,
- base = pr.UInt,
+ base = pr.Int,
mode = 'RW',
+ units = 'degC',
+ disp = '{:d}',
))
self.add(pr.RemoteVariable(
- name = 'TCritHysteresis',
+ name = 'TcritHysteresis',
description = 'T_CRIT hysteresis (TH)',
offset = (0x21 << 2),
bitSize = 5,
bitOffset = 0,
base = pr.UInt,
mode = 'RW',
+ units = 'degC',
+ disp = '{:d}',
))
- self.add(pr.RemoteVariable(
- name = 'LocalTemperatureLowByte',
- description = 'local temperature low byte (LTLB))',
- offset = (0x22 << 2),
- bitSize = 3,
- bitOffset = 5,
- base = pr.UInt,
- mode = 'RO',
- ))
-
+ ############################################################################
+
+ self.add(pr.RemoteCommand(
+ name = 'OneShot',
+ description = 'writing register initiates a one-shot conversion (One Shot)',
+ offset = (0x0F << 2),
+ bitSize = 1,
+ bitOffset = 0,
+ base = pr.UInt,
+ function = lambda cmd: cmd.set(1),
+ hidden = False,
+ ))
+
self.add(pr.RemoteVariable(
name = 'AlertMode',
description = 'Alert mode (AM))',
offset = (0xBF << 2),
bitSize = 1,
bitOffset = 0,
- base = pr.UInt,
+ base = pr.Bool,
mode = 'RW',
))
self.add(pr.RemoteVariable(
name = 'ManufacturerId',
- description = 'read manufacturers ID (RMID))',
+ description = 'Read manufacturers ID (RMID) should be 0xA1',
offset = (0xFE << 2),
bitSize = 8,
bitOffset = 0,
@@ -300,7 +550,7 @@ def __init__(self,
self.add(pr.RemoteVariable(
name = 'DieRevision',
- description = 'read stepping or die revision (RDR))',
+ description = 'Read stepping or die revision (RDR) should be 0x00',
offset = (0xFF << 2),
bitSize = 8,
bitOffset = 0,
@@ -308,3 +558,5 @@ def __init__(self,
mode = 'RO',
))
+ ############################################################################
+
\ No newline at end of file
diff --git a/python/surf/devices/transceivers/_Sff8472.py b/python/surf/devices/transceivers/_Sff8472.py
new file mode 100644
index 0000000000..a2f71d55e7
--- /dev/null
+++ b/python/surf/devices/transceivers/_Sff8472.py
@@ -0,0 +1,590 @@
+#!/usr/bin/env python
+#-----------------------------------------------------------------------------
+# Title : PyRogue Sff8472 Module
+#-----------------------------------------------------------------------------
+# File : Sff8472.py
+# Created : 2017-04-12
+#-----------------------------------------------------------------------------
+# Description: PyRogue Sff8472 Module
+#
+# Refer to AN-2030: Digital Diagnostic Monitoring Interface for Optical Transceivers
+#
+#-----------------------------------------------------------------------------
+# This file is part of the rogue software platform. It is subject to
+# the license terms in the LICENSE.txt file found in the top-level directory
+# of this distribution and at:
+# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+# No part of the rogue software platform, including this file, may be
+# copied, modified, propagated, or distributed except according to the terms
+# contained in the LICENSE.txt file.
+#-----------------------------------------------------------------------------
+
+import pyrogue as pr
+
+class Sff8472(pr.Device):
+ def __init__(
+ self,
+ name = "Sff8472",
+ description = "SFF-8472 Module",
+ **kwargs):
+
+ super().__init__(
+ name = name,
+ description = description,
+ **kwargs)
+
+ #####################################################
+ # Serial ID: Data Fields – Address A0h #
+ #####################################################
+
+ ################
+ # BASE ID FIELDS
+ ################
+
+ self.add(pr.RemoteVariable(
+ name = 'Identifier',
+ description = 'Type of serial transceiver',
+ offset = (0 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ enum = {
+ 0x0: 'Unspecified',
+ 0x1: 'GBIC',
+ 0x2: 'Module/connector soldered to motherboard',
+ 0x3: 'SFP or SFP+',
+ 0x4: '300 pin XBI',
+ 0x5: 'XENPAK',
+ 0x6: 'XFP',
+ 0x7: 'XFF',
+ 0x8: 'XFP-E',
+ 0x9: 'XPAK',
+ 0xA: 'X2',
+ 0xB: 'DWDM-SFP',
+ 0xC: 'QSFP',
+ 0xD: 'QSFP+',
+ 0xE: 'CXP',
+ },
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'ExtIdentifier',
+ description = 'Extended identifier of type of serial transceiver',
+ offset = (1 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'Connector',
+ description = 'Code for connector type',
+ offset = (2 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ enum = {
+ 0x00: 'Unspecified',
+ 0x01: 'SC',
+ 0x02: 'Fibre Channel Style 1 copper connector',
+ 0x03: 'Fibre Channel Style 2 copper connector',
+ 0x04: 'BNC/TNC',
+ 0x05: 'Fibre Channel coaxial headers',
+ 0x06: 'FiberJack',
+ 0x07: 'LC',
+ 0x08: 'MT-RJ',
+ 0x09: 'MU',
+ 0x0A: 'SG',
+ 0x0B: 'Optical pigtail',
+ 0x0C: 'MPO Parallel Optic',
+ 0x20: 'HSSDC II',
+ 0x21: 'Copper Pigtail',
+ 0x22: 'RJ45',
+ },
+ ))
+
+ ## Any some point we should rewrite this variable to display the Transceiver Compliance Codes as enums
+ self.addRemoteVariables(
+ name = 'Transceiver',
+ description = 'Code for electronic compatibility or optical compatibility',
+ offset = (3 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 8,
+ stride = 4,
+ )
+
+ self.add(pr.RemoteVariable(
+ name = 'Encoding',
+ description = 'Code for serial encoding algorithm',
+ offset = (11 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ enum = {
+ 0x0: 'Unspecified',
+ 0x1: '8B10B',
+ 0x2: '4B5B',
+ 0x3: 'NRZ',
+ 0x4: 'Manchester',
+ 0x5: 'SONET Scrambled',
+ 0x6: '64B/66B',
+ },
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'BrNominal',
+ description = 'The nominal bit rate (BR, nominal) is specified in units of 100 Megabits per second, rounded off to the nearest 100 Megabits per second. The bit rate includes those bits necessary to encode and delimit the signal as well as those bits carrying data information. A value of 0 indicates that the bit rate is not specified and must be determined from the transceiver technology. The actual information transfer rate will depend on the encoding of the data, as defined by the encoding value.',
+ offset = (12 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ units = '100 Mbps',
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'RateId',
+ description = 'The Rate Identifier refers to several (optional) industry standard definitions of Rate Select or Application Select control behaviors, intended to manage transceiver optimization for multiple operating rates.',
+ offset = (13 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ enum = {
+ 0x0: 'Unspecified',
+ 0x1: 'SFF-8079 (4/2/1G Rate Select and AS0/AS1)',
+ 0x2: 'SFF-8431 (8/4/2G RX Rate Select Only)',
+ 0x3: 'Unspecified',
+ 0x4: 'SFF-8431 (8/4/2G TX Rate Select Only)',
+ 0x5: 'Unspecified',
+ 0x6: 'SFF-8431 (8/4/2G Independent TX and RX Rate Select)',
+ 0x7: 'Unspecified',
+ 0x8: 'FC-PI-5 (16/8/4G RX Rate Select Only) High=16G, Low=8/4G',
+ 0x9: 'Unspecified',
+ 0xA: 'FC-PI-5 (16/8/4G Independent TX and RX Rate Select) High=16G, Low=8/4G',
+ },
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'Length9umKm',
+ description = 'Link length supported for 9/125 um fiber',
+ offset = (14 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ units = 'km',
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'Length9um',
+ description = 'Link length supported for 9/125 um fiber',
+ offset = (15 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ units = '100 m',
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'Length50um[0]',
+ description = 'Link length supported for 50/125 um OM2 fiber',
+ offset = (16 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ units = '10 m',
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'Length62um',
+ description = 'Link length supported for 62.5/125 um OM1 fiber',
+ offset = (17 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ units = '10 m',
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'LengthCopper',
+ description = 'Link length supported for copper and Active Cable,',
+ offset = (18 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ units = 'm',
+
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'Length50um[1]',
+ description = 'Link length supported for 50/125 um fiber',
+ offset = (19 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ units = '10 m',
+ ))
+
+ self.addRemoteVariables(
+ name = 'VendorName',
+ description = 'SFP vendor name (ASCII)',
+ offset = (20 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 16,
+ stride = 4,
+ )
+
+ self.addRemoteVariables(
+ name = 'VendorOui',
+ description = 'SFP vendor IEEE company ID',
+ offset = (37 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 3,
+ stride = 4,
+ )
+
+ self.addRemoteVariables(
+ name = 'VendorPn',
+ description = 'Part number provided by SFP vendor (ASCII)',
+ offset = (40 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 16,
+ stride = 4,
+ )
+
+ self.addRemoteVariables(
+ name = 'VendorRev',
+ description = 'Revision level for part number provided by vendor (ASCII)',
+ offset = (56 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 4,
+ stride = 4,
+ )
+
+ self.addRemoteVariables(
+ name = 'Wavelength',
+ description = 'Laser wavelength',
+ offset = (60 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 2,
+ stride = 4,
+ )
+
+ self.add(pr.RemoteVariable(
+ name = 'CcBase',
+ description = 'Check code for Base ID Fields (addresses 0 to 62)',
+ offset = (63 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ ))
+
+ ####################
+ # EXTENDED ID FIELDS
+ ####################
+
+ self.addRemoteVariables(
+ name = 'Options',
+ description = 'Indicates which optional transceiver signals are implemented',
+ offset = (64 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 2,
+ stride = 4,
+ )
+
+ self.add(pr.RemoteVariable(
+ name = 'BrMax',
+ description = 'Upper bit rate margin',
+ offset = (66 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ units = '%',
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'BrMin',
+ description = 'Lower bit rate margin',
+ offset = (67 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ units = '%',
+ ))
+
+ self.addRemoteVariables(
+ name = 'VendorSn',
+ description = 'Serial number provided by vendor (ASCII)',
+ offset = (68 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 16,
+ stride = 4,
+ )
+
+ self.addRemoteVariables(
+ name = 'DateCode',
+ description = 'Vendor’s manufacturing date code',
+ offset = (84 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 8,
+ stride = 4,
+ )
+
+ self.add(pr.RemoteVariable(
+ name = 'DiagnosticMonitoringType',
+ description = 'Indicates which type of diagnostic monitoring is implemented (if any) in the transceiver',
+ offset = (92 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'EnhancedOptions',
+ description = 'Indicates which optional enhanced features are implemented (if any) in the transceiver',
+ offset = (93 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'Sff8472Compliance',
+ description = 'Indicates which revision of SFF-8472 the transceiver complies with',
+ offset = (94 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = 'CcExt',
+ description = 'Check code for the Extended ID Fields (addresses 64 to 94)',
+ offset = (95 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ ))
+
+ ###########################
+ # VENDOR SPECIFIC ID FIELDS
+ ###########################
+
+ self.addRemoteVariables(
+ name = 'VendorSpecificA',
+ description = 'Vendor Specific EEPROM',
+ offset = (96 << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 32,
+ stride = 4,
+ )
+
+ # self.addRemoteVariables(
+ # name = 'ReservedA',
+ # description = 'Reserved for SFF-8079',
+ # offset = (128 << 2),
+ # bitSize = 8,
+ # mode = 'RO',
+ # base = pr.UInt,
+ # number = 128,
+ # stride = 4,
+ # )
+
+
+ #####################################################
+ # Diagnostics: Data Fields – Address A2h #
+ #####################################################
+
+ ######################################
+ # DIAGNOSTIC AND CONTROL/STATUS FIELDS
+ ######################################
+
+ # self.addRemoteVariables(
+ # name = 'AwThresholds',
+ # description = 'Diagnostic Flag Alarm and Warning Thresholds',
+ # offset = ((256+0) << 2),
+ # bitSize = 8,
+ # mode = 'RO',
+ # base = pr.UInt,
+ # number = 40,
+ # stride = 4,
+ # )
+
+ # self.addRemoteVariables(
+ # name = 'UnallocatedA',
+ # description = 'Reserved',
+ # offset = ((256+40) << 2),
+ # bitSize = 8,
+ # mode = 'RO',
+ # base = pr.UInt,
+ # number = 16,
+ # stride = 4,
+ # )
+
+ self.addRemoteVariables(
+ name = 'ExtCalConstants',
+ description = 'Diagnostic Calibration Constants for Ext Cal',
+ offset = ((256+56) << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 36,
+ stride = 4,
+ )
+
+ # self.addRemoteVariables(
+ # name = 'UnallocatedB',
+ # description = 'Reserved',
+ # offset = ((256+92) << 2),
+ # bitSize = 8,
+ # mode = 'RO',
+ # base = pr.UInt,
+ # number = 3,
+ # stride = 4,
+ # )
+
+ self.add(pr.RemoteVariable(
+ name = 'CcDmi',
+ description = 'Check Code for Base Diagnostic Fields 0-94',
+ offset = ((256+95) << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ ))
+
+ self.addRemoteVariables(
+ name = 'Diagnostics',
+ description = 'Diagnostic Monitor Data (internal or external)',
+ offset = ((256+96) << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 10,
+ stride = 4,
+ )
+
+ # self.addRemoteVariables(
+ # name = 'UnallocatedC',
+ # description = 'Reserved',
+ # offset = ((256+109) << 2),
+ # bitSize = 8,
+ # mode = 'RO',
+ # base = pr.UInt,
+ # number = 4,
+ # stride = 4,
+ # )
+
+ self.add(pr.RemoteVariable(
+ name = 'StatusControl',
+ description = 'Optional Status and Control Bits',
+ offset = ((256+110) << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ ))
+
+ # self.add(pr.RemoteVariable(
+ # name = 'ReservedB',
+ # description = 'Reserved for SFF-8079',
+ # offset = (111 << 2),
+ # bitSize = 8,
+ # mode = 'RO',
+ # base = pr.UInt,
+ # ))
+
+ self.addRemoteVariables(
+ name = 'AlarmFlags',
+ description = 'Diagnostic Alarm Flags Status Bits',
+ offset = ((256+112) << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 2,
+ stride = 4,
+ )
+
+ # self.addRemoteVariables(
+ # name = 'UnallocatedD',
+ # description = 'Reserved',
+ # offset = ((256+114) << 2),
+ # bitSize = 8,
+ # mode = 'RO',
+ # base = pr.UInt,
+ # number = 2,
+ # stride = 4,
+ # )
+
+ self.addRemoteVariables(
+ name = 'Warning Flags',
+ description = 'Diagnostic Warning Flag Status Bits',
+ offset = ((256+116) << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 2,
+ stride = 4,
+ )
+
+ self.addRemoteVariables(
+ name = 'ExtStatusControl',
+ description = 'Extened Module Control and Status Bits',
+ offset = ((256+118) << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 2,
+ stride = 4,
+ )
+
+ ######################################
+ # GENERAL USE FIELDS
+ ######################################
+
+ self.addRemoteVariables(
+ name = 'DiagnosticsVendorSpecific',
+ description = 'Diagnostics: Data Field Vendor Specific EEPROM',
+ offset = ((256+120) << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 8,
+ stride = 4,
+ )
+
+ self.addRemoteVariables(
+ name = 'UserEeprom',
+ description = 'User writeable non-volatile memory',
+ offset = ((256+128) << 2),
+ bitSize = 8,
+ mode = 'RW',
+ base = pr.UInt,
+ number = 120,
+ stride = 4,
+ hidden = True,
+ )
+
+ self.addRemoteVariables(
+ name = 'VendorControl',
+ description = 'Vendor specific control addresses',
+ offset = ((256+248) << 2),
+ bitSize = 8,
+ mode = 'RO',
+ base = pr.UInt,
+ number = 8,
+ stride = 4,
+ )
diff --git a/python/surf/devices/transceivers/__init__.py b/python/surf/devices/transceivers/__init__.py
new file mode 100644
index 0000000000..96fe595593
--- /dev/null
+++ b/python/surf/devices/transceivers/__init__.py
@@ -0,0 +1,11 @@
+#!/usr/bin/env python
+##############################################################################
+## This file is part of 'SLAC Firmware Standard Library'.
+## It is subject to the license terms in the LICENSE.txt file found in the
+## top-level directory of this distribution and at:
+## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+## No part of 'SLAC Firmware Standard Library', including this file,
+## may be copied, modified, propagated, or distributed except according to
+## the terms contained in the LICENSE.txt file.
+##############################################################################
+from surf.devices.transceivers._Sff8472 import *
diff --git a/python/surf/protocols/jesd204b/_JesdRx.py b/python/surf/protocols/jesd204b/_JesdRx.py
index 4dfd6f4764..4c825719ec 100644
--- a/python/surf/protocols/jesd204b/_JesdRx.py
+++ b/python/surf/protocols/jesd204b/_JesdRx.py
@@ -152,6 +152,38 @@ def __init__( self,
base = pr.UInt,
mode = "RW",
))
+
+ self.add(pr.RemoteVariable(
+ name = "PowerDown",
+ description = "Power Down Mask 1-PowerDown, 0-normal.",
+ offset = 0x24,
+ bitSize = numRxLanes,
+ bitOffset = 0x00,
+ base = pr.UInt,
+ mode = "RW",
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = "SysRefPeriodmin",
+ description = "SysRef Period min",
+ offset = 0x28,
+ bitSize = 16,
+ bitOffset = 0,
+ base = pr.UInt,
+ mode = "RO",
+ pollInterval = 1,
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = "SysRefPeriodmax",
+ description = "SysRef Period max",
+ offset = 0x28,
+ bitSize = 16,
+ bitOffset = 16,
+ base = pr.UInt,
+ mode = "RO",
+ pollInterval = 1,
+ ))
self.add(pr.RemoteVariable(
name = "GTReady",
diff --git a/python/surf/protocols/jesd204b/_JesdTx.py b/python/surf/protocols/jesd204b/_JesdTx.py
index 18922531b9..5c268d627d 100644
--- a/python/surf/protocols/jesd204b/_JesdTx.py
+++ b/python/surf/protocols/jesd204b/_JesdTx.py
@@ -185,6 +185,38 @@ def __init__( self,
base = pr.UInt,
mode = "RW",
))
+
+ self.add(pr.RemoteVariable(
+ name = "PowerDown",
+ description = "Power Down Mask 1-PowerDown, 0-normal.",
+ offset = 0x24,
+ bitSize = numTxLanes,
+ bitOffset = 0x00,
+ base = pr.UInt,
+ mode = "RW",
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = "SysRefPeriodmin",
+ description = "SysRef Period min",
+ offset = 0x28,
+ bitSize = 16,
+ bitOffset = 0,
+ base = pr.UInt,
+ mode = "RO",
+ pollInterval = 1,
+ ))
+
+ self.add(pr.RemoteVariable(
+ name = "SysRefPeriodmax",
+ description = "SysRef Period max",
+ offset = 0x28,
+ bitSize = 16,
+ bitOffset = 16,
+ base = pr.UInt,
+ mode = "RO",
+ pollInterval = 1,
+ ))
self.add(pr.RemoteVariable(
name = "GTReady",
diff --git a/yaml/JesdRx.yaml b/yaml/JesdRx.yaml
index f37bda3489..da0c9377b3 100644
--- a/yaml/JesdRx.yaml
+++ b/yaml/JesdRx.yaml
@@ -135,7 +135,34 @@ JesdRx: &JesdRx
sizeBits: *numRxLanes
mode: RW
description: "Mask Enable the ADC data inversion. 1-Inverted, 0-normal."
- #########################################################
+ #########################################################
+ PowerDown:
+ at:
+ offset: 0x24
+ class: IntField
+ name: PowerDown
+ sizeBits: *numRxLanes
+ mode: RW
+ description: "Power Down Mask 1-PowerDown, 0-normal."
+ #########################################################
+ SysRefPeriodmin:
+ at:
+ offset: 0x28
+ class: IntField
+ name: SysRefPeriodmin
+ sizeBits: 16
+ mode: RO
+ description: "SysRef Period min"
+ #########################################################
+ SysRefPeriodmax:
+ at:
+ offset: 0x2A
+ class: IntField
+ name: SysRefPeriodmax
+ sizeBits: 16
+ mode: RO
+ description: "SysRef Period max"
+ #########################################################
GTReady:
at:
offset: 0x040
diff --git a/yaml/JesdTx.yaml b/yaml/JesdTx.yaml
index 83c02a0383..cc741f6fad 100644
--- a/yaml/JesdTx.yaml
+++ b/yaml/JesdTx.yaml
@@ -148,6 +148,33 @@ JesdTx: &JesdTx
sizeBits: *numTxLanes
mode: RW
description: "Mask Enable the DAC data inversion. 1-Inverted, 0-normal."
+ #########################################################
+ PowerDown:
+ at:
+ offset: 0x24
+ class: IntField
+ name: PowerDown
+ sizeBits: *numTxLanes
+ mode: RW
+ description: "Power Down Mask 1-PowerDown, 0-normal."
+ #########################################################
+ SysRefPeriodmin:
+ at:
+ offset: 0x28
+ class: IntField
+ name: SysRefPeriodmin
+ sizeBits: 16
+ mode: RO
+ description: "SysRef Period min"
+ #########################################################
+ SysRefPeriodmax:
+ at:
+ offset: 0x2A
+ class: IntField
+ name: SysRefPeriodmax
+ sizeBits: 16
+ mode: RO
+ description: "SysRef Period max"
#########################################################
GTReady:
at: