From 393350fd9fc3b628b3e7791e2200ca922923a706 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 13 Sep 2024 13:19:51 -0700 Subject: [PATCH] cherry picking the surf AxiStreamFifoV2 changes up to v2.5.0 ... but comment out the RST_ASYNC_G related changes --- axi/axi-stream/rtl/AxiStreamFifoV2.vhd | 75 +++++++++++++++++--------- 1 file changed, 49 insertions(+), 26 deletions(-) diff --git a/axi/axi-stream/rtl/AxiStreamFifoV2.vhd b/axi/axi-stream/rtl/AxiStreamFifoV2.vhd index 5f60a193fb..78d8612aaa 100644 --- a/axi/axi-stream/rtl/AxiStreamFifoV2.vhd +++ b/axi/axi-stream/rtl/AxiStreamFifoV2.vhd @@ -20,16 +20,15 @@ use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; - library surf; use surf.StdRtlPkg.all; use surf.AxiStreamPkg.all; entity AxiStreamFifoV2 is generic ( - -- General Configurations TPD_G : time := 1 ns; +-- RST_ASYNC_G : boolean := false; INT_PIPE_STAGES_G : natural range 0 to 16 := 0; -- Internal FIFO setting PIPE_STAGES_G : natural range 0 to 16 := 1; SLAVE_READY_EN_G : boolean := true; @@ -44,8 +43,8 @@ entity AxiStreamFifoV2 is FIFO_ADDR_WIDTH_G : integer range 4 to 48 := 9; FIFO_FIXED_THRESH_G : boolean := true; FIFO_PAUSE_THRESH_G : integer range 1 to (2**24) := 1; - SYNTH_MODE_G : string := "inferred"; - MEMORY_TYPE_G : string := "block"; + SYNTH_MODE_G : string := "inferred"; + MEMORY_TYPE_G : string := "block"; -- Internal FIFO width select, "WIDE", "NARROW" or "CUSTOM" -- WIDE uses wider of slave / master. NARROW uses narrower. @@ -91,6 +90,8 @@ end AxiStreamFifoV2; architecture rtl of AxiStreamFifoV2 is + constant RST_ASYNC_G : boolean := false; -- workaround for this cherry picked code for SMURF + constant LAST_FIFO_ADDR_WIDTH_C : integer range 4 to 48 := ite(LAST_FIFO_ADDR_WIDTH_G < 4, FIFO_ADDR_WIDTH_G, LAST_FIFO_ADDR_WIDTH_G); @@ -159,9 +160,10 @@ architecture rtl of AxiStreamFifoV2 is signal fifoValidLast : sl; signal fifoInFrame : sl; - signal burstEn : sl; - signal burstLast : sl; - signal burstCnt : natural range 0 to VALID_THOLD_G := 0; + signal burstEn : sl; + signal burstLast : sl; + signal burstCnt : natural range 0 to VALID_THOLD_G := 0; + signal firstCycle : sl; signal sideBand : Slv8Array(1 downto 0); @@ -185,28 +187,31 @@ begin U_SlaveResize : entity surf.AxiStreamGearbox generic map ( TPD_G => TPD_G, +-- RST_ASYNC_G => RST_ASYNC_G, READY_EN_G => SLAVE_READY_EN_G, SLAVE_AXI_CONFIG_G => SLAVE_AXI_CONFIG_G, MASTER_AXI_CONFIG_G => FIFO_CONFIG_C) - port map ( - axisClk => sAxisClk, - axisRst => sAxisRst, - sAxisMaster => sAxisMaster, - sAxisSlave => sAxisSlave, - mAxisMaster => fifoWriteMaster, - mAxisSlave => fifoWriteSlave); + port map ( + axisClk => sAxisClk, + axisRst => sAxisRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + mAxisMaster => fifoWriteMaster, + mAxisSlave => fifoWriteSlave); ------------------------- -- FIFO ------------------------- -- Pause generation - process (fifoPFullVec, sAxisClk) is + process (fifoPFullVec, sAxisClk, sAxisRst, fifoWrCount, fifoPauseThresh) is begin if FIFO_FIXED_THRESH_G then sAxisCtrl.pause <= fifoPFullVec(CASCADE_PAUSE_SEL_G) after TPD_G; + elsif (RST_ASYNC_G) and (sAxisRst = '1' or fifoWrCount >= fifoPauseThresh) then + sAxisCtrl.pause <= '1' after TPD_G; elsif (rising_edge(sAxisClk)) then - if sAxisRst = '1' or fifoWrCount >= fifoPauseThresh then + if (RST_ASYNC_G = false) and (sAxisRst = '1' or fifoWrCount >= fifoPauseThresh) then sAxisCtrl.pause <= '1' after TPD_G; else sAxisCtrl.pause <= '0' after TPD_G; @@ -237,7 +242,7 @@ begin LAST_STAGE_ASYNC_G => true, PIPE_STAGES_G => INT_PIPE_STAGES_G, RST_POLARITY_G => '1', - RST_ASYNC_G => false, +-- RST_ASYNC_G => false, -- Synchronous reset might be required here GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_G, FWFT_EN_G => true, SYNTH_MODE_G => SYNTH_MODE_G, @@ -274,7 +279,7 @@ begin LAST_STAGE_ASYNC_G => true, PIPE_STAGES_G => INT_PIPE_STAGES_G, RST_POLARITY_G => '1', - RST_ASYNC_G => false, +-- RST_ASYNC_G => false, -- Synchronous reset might be required here GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_G, MEMORY_TYPE_G => "distributed", FWFT_EN_G => true, @@ -296,18 +301,26 @@ begin U_PreFillMode : if ((VALID_BURST_MODE_G = false) or (VALID_THOLD_G = 0)) generate - process (mAxisClk) is + process (mAxisClk, mAxisRst, fifoReadLast, fifoValidInt) is begin - if (rising_edge(mAxisClk)) then + if (RST_ASYNC_G) and (mAxisRst = '1' or fifoReadLast = '1' or fifoValidInt = '0') then + fifoInFrame <= '0' after TPD_G; + + elsif (rising_edge(mAxisClk)) then -- Stop output if fifo valid goes away, wait until another block is ready - if mAxisRst = '1' or fifoReadLast = '1' or fifoValidInt = '0' then + if (RST_ASYNC_G = false) and (mAxisRst = '1' or fifoReadLast = '1' or fifoValidInt = '0') then fifoInFrame <= '0' after TPD_G; -- Start output when a block or end of frame is available elsif fifoValidLast = '1' or (VALID_THOLD_G /= 0 and fifoRdCount >= VALID_THOLD_G) then fifoInFrame <= '1' after TPD_G; + + -- Prevent the FIFO from locking up when frame deeper than what the U_Fifo can hold + elsif (fifoAFull = '1') then + fifoInFrame <= '1' after TPD_G; end if; + end if; end process; @@ -315,15 +328,22 @@ begin U_BurstMode : if ((VALID_BURST_MODE_G = true) and (VALID_THOLD_G /= 0)) generate - process (mAxisClk) is + process (mAxisClk, mAxisRst) is begin - if (rising_edge(mAxisClk)) then - if (mAxisRst = '1') or (fifoReadLast = '1') then + if (RST_ASYNC_G and mAxisRst = '1') then + fifoInFrame <= '0' after TPD_G; + burstEn <= '0' after TPD_G; + burstLast <= '0' after TPD_G; + firstCycle <= '1' after TPD_G; + elsif (rising_edge(mAxisClk)) then + if (RST_ASYNC_G = false and mAxisRst = '1') or (fifoReadLast = '1') then -- Reset the flags fifoInFrame <= '0' after TPD_G; burstEn <= '0' after TPD_G; burstLast <= '0' after TPD_G; + firstCycle <= '1' after TPD_G; else + firstCycle <= '0' after TPD_G; -- Check if for burst mode if (burstEn = '1') and (burstLast = '0') and (fifoRead = '1') then -- Increment the counter @@ -335,7 +355,7 @@ begin burstEn <= '0' after TPD_G; end if; end if; - if (fifoValidLast = '1') or ((fifoRdCount >= VALID_THOLD_G) and (burstEn = '0')) then + if (fifoValidLast = '1') or ((fifoRdCount >= VALID_THOLD_G) and (burstEn = '0') and firstCycle = '0') then -- Set the flags burstEn <= '1' after TPD_G; burstLast <= fifoValidLast after TPD_G; @@ -360,7 +380,7 @@ begin fifoValid <= fifoValidInt; end generate; - sideBand(0) <= resize(fifoReadUser, 8); -- mTLastTUser + sideBand(0) <= resize(fifoReadUser, 8); -- mTLastTUser -- Map output Signals fifoReadMaster <= toAxiStreamMaster (fifoDout, fifoValid, FIFO_CONFIG_C); @@ -374,6 +394,7 @@ begin U_MasterResize : entity surf.AxiStreamGearbox generic map ( TPD_G => TPD_G, +-- RST_ASYNC_G => RST_ASYNC_G, READY_EN_G => true, SIDE_BAND_WIDTH_G => 8, SLAVE_AXI_CONFIG_G => FIFO_CONFIG_C, @@ -396,6 +417,7 @@ begin Synchronizer_1 : entity surf.Synchronizer generic map ( TPD_G => TPD_G, +-- RST_ASYNC_G => RST_ASYNC_G, OUT_POLARITY_G => '0') -- invert port map ( clk => sAxisClk, @@ -410,6 +432,7 @@ begin U_Pipe : entity surf.AxiStreamPipeline generic map ( TPD_G => TPD_G, +-- RST_ASYNC_G => RST_ASYNC_G, SIDE_BAND_WIDTH_G => 8, PIPE_STAGES_G => PIPE_STAGES_G) port map (