From f10199bfd9c1e378ceb351feb8586a8a34513f13 Mon Sep 17 00:00:00 2001 From: Jesus Vasquez Date: Mon, 17 Jun 2019 11:46:17 -0700 Subject: [PATCH 01/36] Remove trailing spaces --- yaml/Dac38J84.yaml | 68 +++++++++++++++++++++++----------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/yaml/Dac38J84.yaml b/yaml/Dac38J84.yaml index 1a7417396a..bfa1313881 100644 --- a/yaml/Dac38J84.yaml +++ b/yaml/Dac38J84.yaml @@ -1,10 +1,10 @@ ############################################################################## ## This file is part of 'SLAC Firmware Standard Library'. -## It is subject to the license terms in the LICENSE.txt file found in the -## top-level directory of this distribution and at: -## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -## No part of 'SLAC Firmware Standard Library', including this file, -## may be copied, modified, propagated, or distributed except according to +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to ## the terms contained in the LICENSE.txt file. ############################################################################## #schemaversion 3.0.0 @@ -19,7 +19,7 @@ Dac38J84: &Dac38J84 metadata: numTxLanes: &numTxLanes 2 children: - ######################################################### + ######################################################### DacReg: at: offset: 0x000 @@ -30,7 +30,7 @@ Dac38J84: &Dac38J84 sizeBits: 16 mode: RW description: "DAC Registers[125:0]" - ######################################################### + ######################################################### LaneBufferDelay: at: offset: 0x01C @@ -39,7 +39,7 @@ Dac38J84: &Dac38J84 sizeBits: 5 mode: RO description: Lane Buffer Delay - ######################################################### + ######################################################### Temperature: at: offset: 0x01D @@ -48,7 +48,7 @@ Dac38J84: &Dac38J84 sizeBits: 8 mode: RO description: Temperature - ######################################################### + ######################################################### LinkErrCnt: at: offset: 0x104 @@ -59,7 +59,7 @@ Dac38J84: &Dac38J84 sizeBits: 16 mode: RO description: "Link Error Count" - ######################################################### + ######################################################### ReadFifoEmpty: at: offset: 0x190 @@ -71,7 +71,7 @@ Dac38J84: &Dac38J84 lsBit: 0 mode: RO description: "ReadFifoEmpty" - ######################################################### + ######################################################### ReadFifoUnderflow: at: offset: 0x190 @@ -83,7 +83,7 @@ Dac38J84: &Dac38J84 lsBit: 1 mode: RO description: "ReadFifoUnderflow" - ######################################################### + ######################################################### ReadFifoFull: at: offset: 0x190 @@ -95,7 +95,7 @@ Dac38J84: &Dac38J84 lsBit: 2 mode: RO description: "ReadFifoFull" - ######################################################### + ######################################################### ReadFifoOverflow: at: offset: 0x190 @@ -107,7 +107,7 @@ Dac38J84: &Dac38J84 lsBit: 3 mode: RO description: "ReadFifoOverflow" - ######################################################### + ######################################################### DispErr: at: offset: 0x191 @@ -119,7 +119,7 @@ Dac38J84: &Dac38J84 lsBit: 0 mode: RO description: "DispErr" - ######################################################### + ######################################################### NotitableErr: at: offset: 0x191 @@ -131,7 +131,7 @@ Dac38J84: &Dac38J84 lsBit: 1 mode: RO description: "NotitableErr" - ######################################################### + ######################################################### CodeSyncErr: at: offset: 0x191 @@ -143,7 +143,7 @@ Dac38J84: &Dac38J84 lsBit: 2 mode: RO description: "CodeSyncErr" - ######################################################### + ######################################################### FirstDataMatchErr: at: offset: 0x191 @@ -155,7 +155,7 @@ Dac38J84: &Dac38J84 lsBit: 3 mode: RO description: "FirstDataMatchErr" - ######################################################### + ######################################################### ElasticBuffOverflow: at: offset: 0x191 @@ -167,7 +167,7 @@ Dac38J84: &Dac38J84 lsBit: 4 mode: RO description: "ElasticBuffOverflow" - ######################################################### + ######################################################### LinkConfigErr: at: offset: 0x191 @@ -179,7 +179,7 @@ Dac38J84: &Dac38J84 lsBit: 5 mode: RO description: "LinkConfigErr" - ######################################################### + ######################################################### FrameAlignErr: at: offset: 0x191 @@ -191,7 +191,7 @@ Dac38J84: &Dac38J84 lsBit: 6 mode: RO description: "FrameAlignErr" - ######################################################### + ######################################################### MultiFrameAlignErr: at: offset: 0x191 @@ -203,7 +203,7 @@ Dac38J84: &Dac38J84 lsBit: 7 mode: RO description: "MultiFrameAlignErr" - ######################################################### + ######################################################### Serdes1pllAlarm: at: offset: 0x1B0 @@ -213,7 +213,7 @@ Dac38J84: &Dac38J84 lsBit: 2 mode: RO description: Serdes1pllAlarm - ######################################################### + ######################################################### Serdes0pllAlarm: at: offset: 0x1B0 @@ -223,7 +223,7 @@ Dac38J84: &Dac38J84 lsBit: 3 mode: RO description: Serdes0pllAlarm - ######################################################### + ######################################################### SysRefAlarms: at: offset: 0x1B1 @@ -233,7 +233,7 @@ Dac38J84: &Dac38J84 lsBit: 4 mode: RO description: SysRefAlarms - ######################################################### + ######################################################### LaneLoss: at: offset: 0x1B4 @@ -242,7 +242,7 @@ Dac38J84: &Dac38J84 sizeBits: 8 mode: RO description: "LaneLoss" - ######################################################### + ######################################################### LaneAlarm: at: offset: 0x1B5 @@ -251,7 +251,7 @@ Dac38J84: &Dac38J84 sizeBits: 8 mode: RO description: "LaneAlarm" - ######################################################### + ######################################################### ID: at: offset: 0x1FC @@ -259,7 +259,7 @@ Dac38J84: &Dac38J84 name: ID mode: RO description: Serials and IDs - ######################################################### + ######################################################### EnableTx: at: offset: 0xC @@ -269,7 +269,7 @@ Dac38J84: &Dac38J84 lsBit: 0 mode: RW description: EnableTx - ######################################################### + ######################################################### InitJesd: at: offset: 0x128 @@ -279,7 +279,7 @@ Dac38J84: &Dac38J84 lsBit: 0 mode: RW description: InitJesd - ######################################################### + ######################################################### ClearAlarms: class: SequenceCommand at: @@ -314,16 +314,16 @@ Dac38J84: &Dac38J84 # Disable TX - entry: EnableTx value: 0x0 - + # Disable and initialize JESD - entry: InitJesd value: 0x1E - + # Enable JESD - entry: InitJesd value: 0x01 - + # Enable TX - entry: EnableTx value: 0x1 - ######################################################### + ######################################################### From aa940f23675bc739a590835fcf896d74689fedef Mon Sep 17 00:00:00 2001 From: Jesus Vasquez Date: Mon, 17 Jun 2019 12:13:53 -0700 Subject: [PATCH 02/36] Update definition based on the equivalent pyrogue class --- yaml/Dac38J84.yaml | 75 ++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 63 insertions(+), 12 deletions(-) diff --git a/yaml/Dac38J84.yaml b/yaml/Dac38J84.yaml index bfa1313881..d3a30c43e7 100644 --- a/yaml/Dac38J84.yaml +++ b/yaml/Dac38J84.yaml @@ -252,13 +252,25 @@ Dac38J84: &Dac38J84 mode: RO description: "LaneAlarm" ######################################################### - ID: + VersionId: at: offset: 0x1FC class: IntField - name: ID + name: VersionId + sizeBits: 3 + lsBit: 0 + mode: RO + description: Version ID + ######################################################### + VendorId: + at: + offset: 0x1FC + class: IntField + name: VendorId + sizeBits: 2 + lsBit: 3 mode: RO - description: Serials and IDs + description: Vendor ID ######################################################### EnableTx: at: @@ -270,13 +282,23 @@ Dac38J84: &Dac38J84 mode: RW description: EnableTx ######################################################### + JesdRstN: + at: + offset: 0x128 + class: IntField + name: JesdRstN + sizeBits: 1 + lsBit: 0 + mode: RW + description: JesdRstN + ######################################################### InitJesd: at: offset: 0x128 class: IntField name: InitJesd - sizeBits: 5 - lsBit: 0 + sizeBits: 4 + lsBit: 1 mode: RW description: InitJesd ######################################################### @@ -304,8 +326,10 @@ Dac38J84: &Dac38J84 value: 0x0 - entry: DacReg[108] value: 0x0 + - entry: DacReg[109] + value: 0x0 ######################################################### - InitDac: + Init: class: SequenceCommand at: offset: 0x0 @@ -315,13 +339,40 @@ Dac38J84: &Dac38J84 - entry: EnableTx value: 0x0 - # Disable and initialize JESD - - entry: InitJesd - value: 0x1E + # Clear alarms + - entry: ClearAlarms + value: 0 - # Enable JESD - - entry: InitJesd - value: 0x01 + - entry: DacReg[59] + value: 0x1800 + - entry: DacReg[37] + value: 0x4000 + - entry: DacReg[60] + value: 0x228 + - entry: DacReg[60] + value: 0x28 + - entry: DacReg[62] + value: 0x108 + - entry: DacReg[76] + value: 0x1F03 + - entry: DacReg[77] + value: 0x300 + - entry: DacReg[75] + value: 0x801 + - entry: DacReg[77] + value: 0x300 + - entry: DacReg[78] + value: 0xF2F + - entry: DacReg[0] + value: 0x218 + - entry: DacReg[74] + value: 0xF1E + - entry: DacReg[74] + value: 0xF1E + - entry: DacReg[74] + value: 0xF1F + - entry: DacReg[74] + value: 0xF01 # Enable TX - entry: EnableTx From 20f9b6946a23e5514ed43ac200e447470b1f0357 Mon Sep 17 00:00:00 2001 From: Jesus Vasquez Date: Mon, 17 Jun 2019 12:16:04 -0700 Subject: [PATCH 03/36] Remove redundant 'name' definitions --- yaml/Dac38J84.yaml | 27 --------------------------- 1 file changed, 27 deletions(-) diff --git a/yaml/Dac38J84.yaml b/yaml/Dac38J84.yaml index d3a30c43e7..6959876f07 100644 --- a/yaml/Dac38J84.yaml +++ b/yaml/Dac38J84.yaml @@ -11,7 +11,6 @@ #once Dac38J84.yaml Dac38J84: &Dac38J84 - name: Dac38J84 description: DAC38J84 Module size: 0x200 class: MMIODev @@ -26,7 +25,6 @@ Dac38J84: &Dac38J84 stride: 4 nelms: 126 class: IntField - name: DacReg sizeBits: 16 mode: RW description: "DAC Registers[125:0]" @@ -35,7 +33,6 @@ Dac38J84: &Dac38J84 at: offset: 0x01C class: IntField - name: LaneBufferDelay sizeBits: 5 mode: RO description: Lane Buffer Delay @@ -44,7 +41,6 @@ Dac38J84: &Dac38J84 at: offset: 0x01D class: IntField - name: Temperature sizeBits: 8 mode: RO description: Temperature @@ -55,7 +51,6 @@ Dac38J84: &Dac38J84 stride: 4 nelms: *numTxLanes class: IntField - name: LinkErrCnt sizeBits: 16 mode: RO description: "Link Error Count" @@ -66,7 +61,6 @@ Dac38J84: &Dac38J84 stride: 4 nelms: *numTxLanes class: IntField - name: ReadFifoEmpty sizeBits: 1 lsBit: 0 mode: RO @@ -78,7 +72,6 @@ Dac38J84: &Dac38J84 stride: 4 nelms: *numTxLanes class: IntField - name: ReadFifoUnderflow sizeBits: 1 lsBit: 1 mode: RO @@ -90,7 +83,6 @@ Dac38J84: &Dac38J84 stride: 4 nelms: *numTxLanes class: IntField - name: ReadFifoFull sizeBits: 1 lsBit: 2 mode: RO @@ -102,7 +94,6 @@ Dac38J84: &Dac38J84 stride: 4 nelms: *numTxLanes class: IntField - name: ReadFifoOverflow sizeBits: 1 lsBit: 3 mode: RO @@ -114,7 +105,6 @@ Dac38J84: &Dac38J84 stride: 4 nelms: *numTxLanes class: IntField - name: DispErr sizeBits: 1 lsBit: 0 mode: RO @@ -126,7 +116,6 @@ Dac38J84: &Dac38J84 stride: 4 nelms: *numTxLanes class: IntField - name: NotitableErr sizeBits: 1 lsBit: 1 mode: RO @@ -138,7 +127,6 @@ Dac38J84: &Dac38J84 stride: 4 nelms: *numTxLanes class: IntField - name: CodeSyncErr sizeBits: 1 lsBit: 2 mode: RO @@ -150,7 +138,6 @@ Dac38J84: &Dac38J84 stride: 4 nelms: *numTxLanes class: IntField - name: FirstDataMatchErr sizeBits: 1 lsBit: 3 mode: RO @@ -162,7 +149,6 @@ Dac38J84: &Dac38J84 stride: 4 nelms: *numTxLanes class: IntField - name: ElasticBuffOverflow sizeBits: 1 lsBit: 4 mode: RO @@ -174,7 +160,6 @@ Dac38J84: &Dac38J84 stride: 4 nelms: *numTxLanes class: IntField - name: LinkConfigErr sizeBits: 1 lsBit: 5 mode: RO @@ -186,7 +171,6 @@ Dac38J84: &Dac38J84 stride: 4 nelms: *numTxLanes class: IntField - name: FrameAlignErr sizeBits: 1 lsBit: 6 mode: RO @@ -198,7 +182,6 @@ Dac38J84: &Dac38J84 stride: 4 nelms: *numTxLanes class: IntField - name: MultiFrameAlignErr sizeBits: 1 lsBit: 7 mode: RO @@ -208,7 +191,6 @@ Dac38J84: &Dac38J84 at: offset: 0x1B0 class: IntField - name: Serdes1pllAlarm sizeBits: 1 lsBit: 2 mode: RO @@ -218,7 +200,6 @@ Dac38J84: &Dac38J84 at: offset: 0x1B0 class: IntField - name: Serdes0pllAlarm sizeBits: 1 lsBit: 3 mode: RO @@ -228,7 +209,6 @@ Dac38J84: &Dac38J84 at: offset: 0x1B1 class: IntField - name: SysRefAlarms sizeBits: 4 lsBit: 4 mode: RO @@ -238,7 +218,6 @@ Dac38J84: &Dac38J84 at: offset: 0x1B4 class: IntField - name: LaneLoss sizeBits: 8 mode: RO description: "LaneLoss" @@ -247,7 +226,6 @@ Dac38J84: &Dac38J84 at: offset: 0x1B5 class: IntField - name: LaneAlarm sizeBits: 8 mode: RO description: "LaneAlarm" @@ -256,7 +234,6 @@ Dac38J84: &Dac38J84 at: offset: 0x1FC class: IntField - name: VersionId sizeBits: 3 lsBit: 0 mode: RO @@ -266,7 +243,6 @@ Dac38J84: &Dac38J84 at: offset: 0x1FC class: IntField - name: VendorId sizeBits: 2 lsBit: 3 mode: RO @@ -276,7 +252,6 @@ Dac38J84: &Dac38J84 at: offset: 0xC class: IntField - name: EnableTx sizeBits: 1 lsBit: 0 mode: RW @@ -286,7 +261,6 @@ Dac38J84: &Dac38J84 at: offset: 0x128 class: IntField - name: JesdRstN sizeBits: 1 lsBit: 0 mode: RW @@ -296,7 +270,6 @@ Dac38J84: &Dac38J84 at: offset: 0x128 class: IntField - name: InitJesd sizeBits: 4 lsBit: 1 mode: RW From 212b6d7cc9a70112c2d4fbea07a2008da65780a8 Mon Sep 17 00:00:00 2001 From: Jesus Vasquez Date: Mon, 17 Jun 2019 12:23:29 -0700 Subject: [PATCH 04/36] Fix formatting for better readability --- yaml/Dac38J84.yaml | 480 ++++++++++++++++++++++----------------------- 1 file changed, 240 insertions(+), 240 deletions(-) diff --git a/yaml/Dac38J84.yaml b/yaml/Dac38J84.yaml index 6959876f07..8b0935b0ed 100644 --- a/yaml/Dac38J84.yaml +++ b/yaml/Dac38J84.yaml @@ -21,333 +21,333 @@ Dac38J84: &Dac38J84 ######################################################### DacReg: at: - offset: 0x000 - stride: 4 - nelms: 126 - class: IntField - sizeBits: 16 - mode: RW - description: "DAC Registers[125:0]" + offset: 0x000 + stride: 4 + nelms: 126 + class: IntField + sizeBits: 16 + mode: RW + description: DAC Registers[125:0] ######################################################### LaneBufferDelay: at: - offset: 0x01C - class: IntField - sizeBits: 5 - mode: RO - description: Lane Buffer Delay + offset: 0x01C + class: IntField + sizeBits: 5 + mode: RO + description: Lane Buffer Delay ######################################################### Temperature: at: - offset: 0x01D - class: IntField - sizeBits: 8 - mode: RO - description: Temperature + offset: 0x01D + class: IntField + sizeBits: 8 + mode: RO + description: Temperature ######################################################### LinkErrCnt: at: - offset: 0x104 - stride: 4 - nelms: *numTxLanes - class: IntField - sizeBits: 16 - mode: RO - description: "Link Error Count" + offset: 0x104 + stride: 4 + nelms: *numTxLanes + class: IntField + sizeBits: 16 + mode: RO + description: Link Error Count ######################################################### ReadFifoEmpty: at: - offset: 0x190 - stride: 4 - nelms: *numTxLanes - class: IntField - sizeBits: 1 - lsBit: 0 - mode: RO - description: "ReadFifoEmpty" + offset: 0x190 + stride: 4 + nelms: *numTxLanes + class: IntField + sizeBits: 1 + lsBit: 0 + mode: RO + description: ReadFifoEmpty ######################################################### ReadFifoUnderflow: at: - offset: 0x190 - stride: 4 - nelms: *numTxLanes - class: IntField - sizeBits: 1 - lsBit: 1 - mode: RO - description: "ReadFifoUnderflow" + offset: 0x190 + stride: 4 + nelms: *numTxLanes + class: IntField + sizeBits: 1 + lsBit: 1 + mode: RO + description: ReadFifoUnderflow ######################################################### ReadFifoFull: at: - offset: 0x190 - stride: 4 - nelms: *numTxLanes - class: IntField - sizeBits: 1 - lsBit: 2 - mode: RO - description: "ReadFifoFull" + offset: 0x190 + stride: 4 + nelms: *numTxLanes + class: IntField + sizeBits: 1 + lsBit: 2 + mode: RO + description: ReadFifoFull ######################################################### ReadFifoOverflow: at: - offset: 0x190 - stride: 4 - nelms: *numTxLanes - class: IntField - sizeBits: 1 - lsBit: 3 - mode: RO - description: "ReadFifoOverflow" + offset: 0x190 + stride: 4 + nelms: *numTxLanes + class: IntField + sizeBits: 1 + lsBit: 3 + mode: RO + description: ReadFifoOverflow ######################################################### DispErr: at: - offset: 0x191 - stride: 4 - nelms: *numTxLanes - class: IntField - sizeBits: 1 - lsBit: 0 - mode: RO - description: "DispErr" + offset: 0x191 + stride: 4 + nelms: *numTxLanes + class: IntField + sizeBits: 1 + lsBit: 0 + mode: RO + description: DispErr ######################################################### NotitableErr: at: - offset: 0x191 - stride: 4 - nelms: *numTxLanes - class: IntField - sizeBits: 1 - lsBit: 1 - mode: RO - description: "NotitableErr" + offset: 0x191 + stride: 4 + nelms: *numTxLanes + class: IntField + sizeBits: 1 + lsBit: 1 + mode: RO + description: NotitableErr ######################################################### CodeSyncErr: at: - offset: 0x191 - stride: 4 - nelms: *numTxLanes - class: IntField - sizeBits: 1 - lsBit: 2 - mode: RO - description: "CodeSyncErr" + offset: 0x191 + stride: 4 + nelms: *numTxLanes + class: IntField + sizeBits: 1 + lsBit: 2 + mode: RO + description: CodeSyncErr ######################################################### FirstDataMatchErr: at: - offset: 0x191 - stride: 4 - nelms: *numTxLanes - class: IntField - sizeBits: 1 - lsBit: 3 - mode: RO - description: "FirstDataMatchErr" + offset: 0x191 + stride: 4 + nelms: *numTxLanes + class: IntField + sizeBits: 1 + lsBit: 3 + mode: RO + description: FirstDataMatchErr ######################################################### ElasticBuffOverflow: at: - offset: 0x191 - stride: 4 - nelms: *numTxLanes - class: IntField - sizeBits: 1 - lsBit: 4 - mode: RO - description: "ElasticBuffOverflow" + offset: 0x191 + stride: 4 + nelms: *numTxLanes + class: IntField + sizeBits: 1 + lsBit: 4 + mode: RO + description: ElasticBuffOverflow ######################################################### LinkConfigErr: at: - offset: 0x191 - stride: 4 - nelms: *numTxLanes - class: IntField - sizeBits: 1 - lsBit: 5 - mode: RO - description: "LinkConfigErr" + offset: 0x191 + stride: 4 + nelms: *numTxLanes + class: IntField + sizeBits: 1 + lsBit: 5 + mode: RO + description: LinkConfigErr ######################################################### FrameAlignErr: at: - offset: 0x191 - stride: 4 - nelms: *numTxLanes - class: IntField - sizeBits: 1 - lsBit: 6 - mode: RO - description: "FrameAlignErr" + offset: 0x191 + stride: 4 + nelms: *numTxLanes + class: IntField + sizeBits: 1 + lsBit: 6 + mode: RO + description: FrameAlignErr ######################################################### MultiFrameAlignErr: at: - offset: 0x191 - stride: 4 - nelms: *numTxLanes - class: IntField - sizeBits: 1 - lsBit: 7 - mode: RO - description: "MultiFrameAlignErr" + offset: 0x191 + stride: 4 + nelms: *numTxLanes + class: IntField + sizeBits: 1 + lsBit: 7 + mode: RO + description: MultiFrameAlignErr ######################################################### Serdes1pllAlarm: at: - offset: 0x1B0 - class: IntField - sizeBits: 1 - lsBit: 2 - mode: RO - description: Serdes1pllAlarm + offset: 0x1B0 + class: IntField + sizeBits: 1 + lsBit: 2 + mode: RO + description: Serdes1pllAlarm ######################################################### Serdes0pllAlarm: at: - offset: 0x1B0 - class: IntField - sizeBits: 1 - lsBit: 3 - mode: RO - description: Serdes0pllAlarm + offset: 0x1B0 + class: IntField + sizeBits: 1 + lsBit: 3 + mode: RO + description: Serdes0pllAlarm ######################################################### SysRefAlarms: at: - offset: 0x1B1 - class: IntField - sizeBits: 4 - lsBit: 4 - mode: RO - description: SysRefAlarms + offset: 0x1B1 + class: IntField + sizeBits: 4 + lsBit: 4 + mode: RO + description: SysRefAlarms ######################################################### LaneLoss: at: - offset: 0x1B4 - class: IntField - sizeBits: 8 - mode: RO - description: "LaneLoss" + offset: 0x1B4 + class: IntField + sizeBits: 8 + mode: RO + description: LaneLoss ######################################################### LaneAlarm: at: - offset: 0x1B5 - class: IntField - sizeBits: 8 - mode: RO - description: "LaneAlarm" + offset: 0x1B5 + class: IntField + sizeBits: 8 + mode: RO + description: LaneAlarm ######################################################### VersionId: at: - offset: 0x1FC - class: IntField - sizeBits: 3 - lsBit: 0 - mode: RO - description: Version ID + offset: 0x1FC + class: IntField + sizeBits: 3 + lsBit: 0 + mode: RO + description: Version ID ######################################################### VendorId: at: - offset: 0x1FC - class: IntField - sizeBits: 2 - lsBit: 3 - mode: RO - description: Vendor ID + offset: 0x1FC + class: IntField + sizeBits: 2 + lsBit: 3 + mode: RO + description: Vendor ID ######################################################### EnableTx: at: - offset: 0xC - class: IntField - sizeBits: 1 - lsBit: 0 - mode: RW - description: EnableTx + offset: 0xC + class: IntField + sizeBits: 1 + lsBit: 0 + mode: RW + description: EnableTx ######################################################### JesdRstN: at: - offset: 0x128 - class: IntField - sizeBits: 1 - lsBit: 0 - mode: RW - description: JesdRstN + offset: 0x128 + class: IntField + sizeBits: 1 + lsBit: 0 + mode: RW + description: JesdRstN ######################################################### InitJesd: at: - offset: 0x128 - class: IntField - sizeBits: 4 - lsBit: 1 - mode: RW - description: InitJesd + offset: 0x128 + class: IntField + sizeBits: 4 + lsBit: 1 + mode: RW + description: InitJesd ######################################################### ClearAlarms: - class: SequenceCommand + class: SequenceCommand at: - offset: 0x0 - description: Clear all the DAC alarms + offset: 0x0 + description: Clear all the DAC alarms sequence: - - entry: DacReg[100] - value: 0x0 - - entry: DacReg[101] - value: 0x0 - - entry: DacReg[102] - value: 0x0 - - entry: DacReg[103] - value: 0x0 - - entry: DacReg[104] - value: 0x0 - - entry: DacReg[105] - value: 0x0 - - entry: DacReg[106] - value: 0x0 - - entry: DacReg[107] - value: 0x0 - - entry: DacReg[108] - value: 0x0 - - entry: DacReg[109] - value: 0x0 + - entry: DacReg[100] + value: 0x0 + - entry: DacReg[101] + value: 0x0 + - entry: DacReg[102] + value: 0x0 + - entry: DacReg[103] + value: 0x0 + - entry: DacReg[104] + value: 0x0 + - entry: DacReg[105] + value: 0x0 + - entry: DacReg[106] + value: 0x0 + - entry: DacReg[107] + value: 0x0 + - entry: DacReg[108] + value: 0x0 + - entry: DacReg[109] + value: 0x0 ######################################################### Init: - class: SequenceCommand + class: SequenceCommand at: - offset: 0x0 - description: Initialization sequence for the DAC JESD core + offset: 0x0 + description: Initialization sequence for the DAC JESD core sequence: # Disable TX - - entry: EnableTx - value: 0x0 + - entry: EnableTx + value: 0x0 # Clear alarms - - entry: ClearAlarms - value: 0 + - entry: ClearAlarms + value: 0 - - entry: DacReg[59] - value: 0x1800 - - entry: DacReg[37] - value: 0x4000 - - entry: DacReg[60] - value: 0x228 - - entry: DacReg[60] - value: 0x28 - - entry: DacReg[62] - value: 0x108 - - entry: DacReg[76] - value: 0x1F03 - - entry: DacReg[77] - value: 0x300 - - entry: DacReg[75] - value: 0x801 - - entry: DacReg[77] - value: 0x300 - - entry: DacReg[78] - value: 0xF2F - - entry: DacReg[0] - value: 0x218 - - entry: DacReg[74] - value: 0xF1E - - entry: DacReg[74] - value: 0xF1E - - entry: DacReg[74] - value: 0xF1F - - entry: DacReg[74] - value: 0xF01 + - entry: DacReg[59] + value: 0x1800 + - entry: DacReg[37] + value: 0x4000 + - entry: DacReg[60] + value: 0x228 + - entry: DacReg[60] + value: 0x28 + - entry: DacReg[62] + value: 0x108 + - entry: DacReg[76] + value: 0x1F03 + - entry: DacReg[77] + value: 0x300 + - entry: DacReg[75] + value: 0x801 + - entry: DacReg[77] + value: 0x300 + - entry: DacReg[78] + value: 0xF2F + - entry: DacReg[0] + value: 0x218 + - entry: DacReg[74] + value: 0xF1E + - entry: DacReg[74] + value: 0xF1E + - entry: DacReg[74] + value: 0xF1F + - entry: DacReg[74] + value: 0xF01 # Enable TX - - entry: EnableTx - value: 0x1 + - entry: EnableTx + value: 0x1 ######################################################### From 88e25e37961afa3ae2c78ca59f1290243a7e4146 Mon Sep 17 00:00:00 2001 From: Jesus Vasquez Date: Wed, 19 Jun 2019 18:10:50 -0700 Subject: [PATCH 05/36] Keep the same previous name for the Init function so it is backward compatible --- yaml/Dac38J84.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yaml/Dac38J84.yaml b/yaml/Dac38J84.yaml index 8b0935b0ed..298756b166 100644 --- a/yaml/Dac38J84.yaml +++ b/yaml/Dac38J84.yaml @@ -302,7 +302,7 @@ Dac38J84: &Dac38J84 - entry: DacReg[109] value: 0x0 ######################################################### - Init: + InitDac: class: SequenceCommand at: offset: 0x0 From 1638f6f7c48d6bda9594edbba0ff3324d1690ca0 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 28 Jul 2020 12:27:20 -0700 Subject: [PATCH 06/36] Bring out SYNTH_MODE_G generic for internal RAMs --- protocols/srp/rtl/AxiLiteSrpV0.vhd | 13 ++++++++----- protocols/srp/rtl/SrpV0AxiLite.vhd | 2 ++ protocols/srp/rtl/SrpV3AxiLite.vhd | 9 ++++++--- protocols/srp/rtl/SrpV3Core.vhd | 27 ++++++++++++++------------- 4 files changed, 30 insertions(+), 21 deletions(-) diff --git a/protocols/srp/rtl/AxiLiteSrpV0.vhd b/protocols/srp/rtl/AxiLiteSrpV0.vhd index f7fb9b2d88..be27c2d672 100644 --- a/protocols/srp/rtl/AxiLiteSrpV0.vhd +++ b/protocols/srp/rtl/AxiLiteSrpV0.vhd @@ -34,8 +34,9 @@ entity AxiLiteSrpV0 is TPD_G : time := 1 ns; -- FIFO Config - RESP_THOLD_G : integer range 0 to (2**24) := 1; -- =1 = normal operation + RESP_THOLD_G : integer range 0 to (2**24) := 1; -- =1 = normal operation SLAVE_READY_EN_G : boolean := false; + SYNTH_MODE_G : string := "inferred"; MEMORY_TYPE_G : string := "block"; GEN_SYNC_FIFO_G : boolean := false; FIFO_ADDR_WIDTH_G : integer range 4 to 48 := 9; @@ -124,6 +125,7 @@ begin PIPE_STAGES_G => 1, INT_PIPE_STAGES_G => 0, VALID_THOLD_G => RESP_THOLD_G, + SYNTH_MODE_G => SYNTH_MODE_G, MEMORY_TYPE_G => MEMORY_TYPE_G, GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_G, CASCADE_SIZE_G => 1, @@ -152,6 +154,7 @@ begin PIPE_STAGES_G => 1, INT_PIPE_STAGES_G => 0, SLAVE_READY_EN_G => SLAVE_READY_EN_G, + SYNTH_MODE_G => SYNTH_MODE_G, MEMORY_TYPE_G => MEMORY_TYPE_G, GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_G, CASCADE_SIZE_G => 1, @@ -176,7 +179,7 @@ begin ------------------------------------- comb : process (axilRst, r, rxFifoAxisMaster, sAxilReadMaster, sAxilWriteMaster, txFifoAxisSlave) is - variable v : RegType; + variable v : RegType; variable axilStatus : AxiLiteStatusType; begin v := r; @@ -256,15 +259,15 @@ begin then v.sAxilReadSlave.rdata := rxFifoAxisMaster.tdata(95 downto 64); axiSlaveReadResponse(v.sAxilReadSlave, AXI_RESP_OK_C); - v.state := WAIT_AXIL_REQ_S; + v.state := WAIT_AXIL_REQ_S; elsif (rxFifoAxisMaster.tLast = '0') then v.sAxilReadSlave.rdata := (others => '1'); axiSlaveReadResponse(v.sAxilReadSlave, AXI_RESP_SLVERR_C); - v.state := BLEED_S; + v.state := BLEED_S; else v.sAxilReadSlave.rdata := (others => '1'); axiSlaveReadResponse(v.sAxilReadSlave, AXI_RESP_SLVERR_C); - v.state := WAIT_AXIL_REQ_S; + v.state := WAIT_AXIL_REQ_S; end if; end if; diff --git a/protocols/srp/rtl/SrpV0AxiLite.vhd b/protocols/srp/rtl/SrpV0AxiLite.vhd index 021daecd38..6ea73cd673 100644 --- a/protocols/srp/rtl/SrpV0AxiLite.vhd +++ b/protocols/srp/rtl/SrpV0AxiLite.vhd @@ -37,6 +37,7 @@ entity SrpV0AxiLite is RESP_THOLD_G : integer range 0 to (2**24) := 1; -- =1 = normal operation SLAVE_READY_EN_G : boolean := false; EN_32BIT_ADDR_G : boolean := false; + SYNTH_MODE_G : string := "inferred"; MEMORY_TYPE_G : string := "block"; GEN_SYNC_FIFO_G : boolean := false; FIFO_ADDR_WIDTH_G : integer range 4 to 48 := 9; @@ -431,6 +432,7 @@ begin INT_PIPE_STAGES_G => 0, PIPE_STAGES_G => 1, VALID_THOLD_G => RESP_THOLD_G, + SYNTH_MODE_G => SYNTH_MODE_G, MEMORY_TYPE_G => MEMORY_TYPE_G, GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_G, CASCADE_SIZE_G => 1, diff --git a/protocols/srp/rtl/SrpV3AxiLite.vhd b/protocols/srp/rtl/SrpV3AxiLite.vhd index 3a598adcb5..38ce364ed9 100644 --- a/protocols/srp/rtl/SrpV3AxiLite.vhd +++ b/protocols/srp/rtl/SrpV3AxiLite.vhd @@ -37,8 +37,9 @@ entity SrpV3AxiLite is INT_PIPE_STAGES_G : natural range 0 to 16 := 1; PIPE_STAGES_G : natural range 0 to 16 := 1; FIFO_PAUSE_THRESH_G : positive range 1 to 511 := 256; - TX_VALID_THOLD_G : positive range 1 to 511 := 500; -- >1 = only when frame ready or # entries - TX_VALID_BURST_MODE_G : boolean := true; -- only used in VALID_THOLD_G>1 + FIFO_SYNTH_MODE_G : string := "inferred"; + TX_VALID_THOLD_G : positive range 1 to 511 := 500; -- >1 = only when frame ready or # entries + TX_VALID_BURST_MODE_G : boolean := true; -- only used in VALID_THOLD_G>1 SLAVE_READY_EN_G : boolean := false; GEN_SYNC_FIFO_G : boolean := false; AXIL_CLK_FREQ_G : real := 156.25E+6; -- units of Hz @@ -214,8 +215,9 @@ begin INT_PIPE_STAGES_G => INT_PIPE_STAGES_G, PIPE_STAGES_G => PIPE_STAGES_G, SLAVE_READY_EN_G => SLAVE_READY_EN_G, - VALID_THOLD_G => 0, -- = 0 = only when frame ready + VALID_THOLD_G => 0, -- = 0 = only when frame ready -- FIFO configurations + SYNTH_MODE_G => FIFO_SYNTH_MODE_G, MEMORY_TYPE_G => "block", GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_G, INT_WIDTH_SELECT_G => "CUSTOM", @@ -789,6 +791,7 @@ begin VALID_THOLD_G => TX_VALID_THOLD_G, VALID_BURST_MODE_G => TX_VALID_BURST_MODE_G, -- FIFO configurations + SYNTH_MODE_G => FIFO_SYNTH_MODE_G, MEMORY_TYPE_G => "block", GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_G, INT_WIDTH_SELECT_G => "CUSTOM", diff --git a/protocols/srp/rtl/SrpV3Core.vhd b/protocols/srp/rtl/SrpV3Core.vhd index a95e9d86c1..992c3f61db 100644 --- a/protocols/srp/rtl/SrpV3Core.vhd +++ b/protocols/srp/rtl/SrpV3Core.vhd @@ -152,21 +152,21 @@ begin RX_FIFO : entity surf.SsiFifo generic map ( -- General Configurations - TPD_G => TPD_G, - PIPE_STAGES_G => PIPE_STAGES_G, - SLAVE_READY_EN_G => SLAVE_READY_EN_G, - VALID_THOLD_G => 0, -- = 0 = only when frame ready + TPD_G => TPD_G, + PIPE_STAGES_G => PIPE_STAGES_G, + SLAVE_READY_EN_G => SLAVE_READY_EN_G, + VALID_THOLD_G => 0, -- = 0 = only when frame ready -- FIFO configurations - MEMORY_TYPE_G => "block", - GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_G, - FIFO_ADDR_WIDTH_G => 9, -- 2kB/FIFO = 32-bits x 512 entries - CASCADE_SIZE_G => 3, -- 6kB = 3 FIFOs x 2 kB/FIFO - CASCADE_PAUSE_SEL_G => 2, -- Set pause select on top FIFO - FIFO_FIXED_THRESH_G => true, - FIFO_PAUSE_THRESH_G => FIFO_PAUSE_THRESH_G, + MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_G, + FIFO_ADDR_WIDTH_G => 9, -- 2kB/FIFO = 32-bits x 512 entries + CASCADE_SIZE_G => 3, -- 6kB = 3 FIFOs x 2 kB/FIFO + CASCADE_PAUSE_SEL_G => 2, -- Set pause select on top FIFO + FIFO_FIXED_THRESH_G => true, + FIFO_PAUSE_THRESH_G => FIFO_PAUSE_THRESH_G, -- AXI Stream Port Configurations - SLAVE_AXI_CONFIG_G => AXI_STREAM_CONFIG_G, - MASTER_AXI_CONFIG_G => SRP_AXIS_CONFIG_C) + SLAVE_AXI_CONFIG_G => AXI_STREAM_CONFIG_G, + MASTER_AXI_CONFIG_G => SRP_AXIS_CONFIG_C) port map ( -- Slave Port sAxisClk => sAxisClk, @@ -675,6 +675,7 @@ begin SLAVE_READY_EN_G => true, VALID_THOLD_G => TX_VALID_THOLD_G, -- FIFO configurations + SYNTH_MODE_G => SYNTH_MODE_G, MEMORY_TYPE_G => "block", GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_G, CASCADE_SIZE_G => 1, From fd3c22debf229b95fe742cfcf160aa668aa1c3ee Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 28 Jul 2020 14:24:44 -0700 Subject: [PATCH 07/36] Expose SYNTH_MODE_G to top levels --- ethernet/EthMacCore/rtl/EthMacRx.vhd | 9 ++- ethernet/EthMacCore/rtl/EthMacRxImport.vhd | 8 ++- .../EthMacCore/rtl/EthMacRxImportGmii.vhd | 10 ++-- ethernet/EthMacCore/rtl/EthMacTop.vhd | 11 +++- ethernet/EthMacCore/rtl/EthMacTx.vhd | 9 ++- ethernet/EthMacCore/rtl/EthMacTxCsum.vhd | 55 ++++++++++--------- ethernet/EthMacCore/rtl/EthMacTxExport.vhd | 8 ++- .../EthMacCore/rtl/EthMacTxExportXgmii.vhd | 16 +++--- ethernet/EthMacCore/rtl/EthMacTxFifo.vhd | 6 +- ethernet/UdpEngine/rtl/UdpEngine.vhd | 18 +++--- ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd | 30 +++++----- ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd | 16 +++--- 12 files changed, 116 insertions(+), 80 deletions(-) diff --git a/ethernet/EthMacCore/rtl/EthMacRx.vhd b/ethernet/EthMacCore/rtl/EthMacRx.vhd index b5a7717005..d4d799cf95 100644 --- a/ethernet/EthMacCore/rtl/EthMacRx.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRx.vhd @@ -38,7 +38,9 @@ entity EthMacRx is -- VLAN Configurations VLAN_EN_G : boolean := false; VLAN_SIZE_G : positive range 1 to 8 := 1; - VLAN_VID_G : Slv12Array := (0 => x"001")); + VLAN_VID_G : Slv12Array := (0 => x"001"); + -- Internal RAM sythesis mode + SYNTH_MODE_G : string := "inferred"); port ( -- Clock and Reset ethClkEn : in sl; @@ -88,8 +90,9 @@ begin ------------------- U_Import : entity surf.EthMacRxImport generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => PHY_TYPE_G) + TPD_G => TPD_G, + PHY_TYPE_G => PHY_TYPE_G, + SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Clock and reset ethClkEn => ethClkEn, diff --git a/ethernet/EthMacCore/rtl/EthMacRxImport.vhd b/ethernet/EthMacCore/rtl/EthMacRxImport.vhd index 9126e3bd40..40efd91208 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxImport.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxImport.vhd @@ -25,8 +25,9 @@ use surf.EthMacPkg.all; entity EthMacRxImport is generic ( - TPD_G : time := 1 ns; - PHY_TYPE_G : string := "XGMII"); + TPD_G : time := 1 ns; + PHY_TYPE_G : string := "XGMII"; + SYNTH_MODE_G : string := "inferred"); port ( -- Clock and Reset ethClkEn : in sl; @@ -97,7 +98,8 @@ begin U_1G : if (PHY_TYPE_G = "GMII") generate U_GMII : entity surf.EthMacRxImportGmii generic map ( - TPD_G => TPD_G) + TPD_G => TPD_G; + SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Clock and Reset ethClkEn => ethClkEn, diff --git a/ethernet/EthMacCore/rtl/EthMacRxImportGmii.vhd b/ethernet/EthMacCore/rtl/EthMacRxImportGmii.vhd index f29210a4b5..cb6d8223c7 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxImportGmii.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxImportGmii.vhd @@ -25,7 +25,8 @@ use surf.EthMacPkg.all; entity EthMacRxImportGmii is generic ( - TPD_G : time := 1 ns); + TPD_G : time := 1 ns; + SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs port ( -- Clock and Reset ethClkEn : in sl; @@ -111,23 +112,24 @@ begin SLAVE_READY_EN_G => true, VALID_THOLD_G => 1, -- FIFO configurations + SYNTH_MODE_G => SYNTH_MODE_G, MEMORY_TYPE_G => "distributed", GEN_SYNC_FIFO_G => true, CASCADE_SIZE_G => 1, FIFO_ADDR_WIDTH_G => 4, -- AXI Stream Port Configurations - SLAVE_AXI_CONFIG_G => AXI_CONFIG_C, -- 8-bit AXI stream interface + SLAVE_AXI_CONFIG_G => AXI_CONFIG_C, -- 8-bit AXI stream interface MASTER_AXI_CONFIG_G => INT_EMAC_AXIS_CONFIG_C) -- 128-bit AXI stream interface port map ( -- Slave Port sAxisClk => ethClk, sAxisRst => ethRst, - sAxisMaster => macMaster, -- 8-bit AXI stream interface + sAxisMaster => macMaster, -- 8-bit AXI stream interface sAxisSlave => open, -- Master Port mAxisClk => ethClk, mAxisRst => ethRst, - mAxisMaster => macIbMaster, -- 128-bit AXI stream interface + mAxisMaster => macIbMaster, -- 128-bit AXI stream interface mAxisSlave => AXI_STREAM_SLAVE_FORCE_C); comb : process (crcIn, crcOut, ethClkEn, ethRst, gmiiRxDv, gmiiRxEr, diff --git a/ethernet/EthMacCore/rtl/EthMacTop.vhd b/ethernet/EthMacCore/rtl/EthMacTop.vhd index 5eb402fcbc..ea86bfd9c2 100644 --- a/ethernet/EthMacCore/rtl/EthMacTop.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTop.vhd @@ -147,7 +147,8 @@ begin VLAN_EN_G => VLAN_EN_G, VLAN_SIZE_G => VLAN_SIZE_G, VLAN_COMMON_CLK_G => VLAN_COMMON_CLK_G, - VLAN_CONFIG_G => VLAN_CONFIG_G) + VLAN_CONFIG_G => VLAN_CONFIG_G, + SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Master Clock and Reset mClk => ethClk, @@ -192,7 +193,9 @@ begin -- VLAN Configurations VLAN_EN_G => VLAN_EN_G, VLAN_SIZE_G => VLAN_SIZE_G, - VLAN_VID_G => VLAN_VID_G) + VLAN_VID_G => VLAN_VID_G, + -- RAM sythesis Mode + SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Clocks ethClkEn => ethClkEn, @@ -267,7 +270,9 @@ begin -- VLAN Configurations VLAN_EN_G => VLAN_EN_G, VLAN_SIZE_G => VLAN_SIZE_G, - VLAN_VID_G => VLAN_VID_G) + VLAN_VID_G => VLAN_VID_G, + -- RAM Synthesis mode + SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Clock and Reset ethClkEn => ethClkEn, diff --git a/ethernet/EthMacCore/rtl/EthMacTx.vhd b/ethernet/EthMacCore/rtl/EthMacTx.vhd index 72eefa5dc5..3f15208972 100644 --- a/ethernet/EthMacCore/rtl/EthMacTx.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTx.vhd @@ -38,7 +38,9 @@ entity EthMacTx is -- VLAN Configurations VLAN_EN_G : boolean := false; VLAN_SIZE_G : positive range 1 to 8 := 1; - VLAN_VID_G : Slv12Array := (0 => x"001")); + VLAN_VID_G : Slv12Array := (0 => x"001"); + -- RAM Synthesis mode + SYNTH_MODE_G : string := "inferred"); port ( -- Clock and Reset ethClkEn : in sl; @@ -208,8 +210,9 @@ begin ----------------------- U_Export : entity surf.EthMacTxExport generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => PHY_TYPE_G) + TPD_G => TPD_G, + PHY_TYPE_G => PHY_TYPE_G; + SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Clock and reset ethClkEn => ethClkEn, diff --git a/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd b/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd index b5ca860011..316c13c501 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd @@ -30,7 +30,8 @@ entity EthMacTxCsum is DROP_ERR_PKT_G : boolean := true; JUMBO_G : boolean := true; VLAN_G : boolean := false; - VID_G : slv(11 downto 0) := x"001"); + VID_G : slv(11 downto 0) := x"001"; + SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs port ( -- Clock and Reset ethClk : in sl; @@ -302,7 +303,7 @@ begin v.ipv4Hdr(9) := rxMaster.tData(63 downto 56); -- Protocol v.ipv4Hdr(12) := rxMaster.tData(87 downto 80); -- Source IP Address v.ipv4Hdr(13) := rxMaster.tData(95 downto 88); -- Source IP Address - v.ipv4Hdr(14) := rxMaster.tData(103 downto 96); -- Source IP Address + v.ipv4Hdr(14) := rxMaster.tData(103 downto 96); -- Source IP Address v.ipv4Hdr(15) := rxMaster.tData(111 downto 104); -- Source IP Address v.ipv4Hdr(16) := rxMaster.tData(119 downto 112); -- Destination IP Address v.ipv4Hdr(17) := rxMaster.tData(127 downto 120); -- Destination IP Address @@ -356,32 +357,32 @@ begin -- Check if NON-VLAN if (VLAN_G = false) then -- Fill in the IPv4 header checksum - v.ipv4Hdr(18) := rxMaster.tData(7 downto 0); -- Destination IP Address - v.ipv4Hdr(19) := rxMaster.tData(15 downto 8); -- Destination IP Address + v.ipv4Hdr(18) := rxMaster.tData(7 downto 0); -- Destination IP Address + v.ipv4Hdr(19) := rxMaster.tData(15 downto 8); -- Destination IP Address -- Check for UDP data with inbound length/checksum if (r.ipv4Det(0) = '1') and (r.udpDet(0) = '1') then -- Mask off inbound UDP length/checksum v.tData := rxMaster.tData(127 downto 80) & x"00000000" & rxMaster.tData(47 downto 0); end if; -- Track the number of bytes - v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep,INT_EMAC_AXIS_CONFIG_C) - 2; - v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep,INT_EMAC_AXIS_CONFIG_C) - 2; + v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 2; + v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 2; else -- Fill in the IPv4 header checksum - v.ipv4Hdr(14) := rxMaster.tData(7 downto 0); -- Source IP Address - v.ipv4Hdr(15) := rxMaster.tData(15 downto 8); -- Source IP Address - v.ipv4Hdr(16) := rxMaster.tData(23 downto 16); -- Destination IP Address - v.ipv4Hdr(17) := rxMaster.tData(31 downto 24); -- Destination IP Address - v.ipv4Hdr(18) := rxMaster.tData(39 downto 32); -- Destination IP Address - v.ipv4Hdr(19) := rxMaster.tData(47 downto 40); -- Destination IP Address + v.ipv4Hdr(14) := rxMaster.tData(7 downto 0); -- Source IP Address + v.ipv4Hdr(15) := rxMaster.tData(15 downto 8); -- Source IP Address + v.ipv4Hdr(16) := rxMaster.tData(23 downto 16); -- Destination IP Address + v.ipv4Hdr(17) := rxMaster.tData(31 downto 24); -- Destination IP Address + v.ipv4Hdr(18) := rxMaster.tData(39 downto 32); -- Destination IP Address + v.ipv4Hdr(19) := rxMaster.tData(47 downto 40); -- Destination IP Address -- Check for UDP data with inbound length/checksum if (r.ipv4Det(0) = '1') and (r.udpDet(0) = '1') then -- Mask off inbound UDP length/checksum v.tData := rxMaster.tData(127 downto 112) & x"00000000" & rxMaster.tData(79 downto 0); end if; -- Track the number of bytes - v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep,INT_EMAC_AXIS_CONFIG_C) - 6; - v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep,INT_EMAC_AXIS_CONFIG_C) - 6; + v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 6; + v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 6; end if; -- Check for EOF if (rxMaster.tLast = '1') then @@ -421,8 +422,8 @@ begin end if; end if; -- Track the number of bytes - v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep,INT_EMAC_AXIS_CONFIG_C); - v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep,INT_EMAC_AXIS_CONFIG_C); + v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C); + v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C); -- Check for EOF if (rxMaster.tLast = '1') or (v.ipv4Len(0) > MAX_FRAME_SIZE_C) then -- Save the EOFE value @@ -460,7 +461,7 @@ begin -- Fill in the IPv4 header v.ipv4Hdr(2) := v.ipv4Len(0)(15 downto 8); -- IPV4_Length(15 downto 8) - v.ipv4Hdr(3) := v.ipv4Len(0)(7 downto 0); -- IPV4_Length(7 downto 0) + v.ipv4Hdr(3) := v.ipv4Len(0)(7 downto 0); -- IPV4_Length(7 downto 0) -- Wait for the transaction data if (tranValid = '1') and (r.tranRd = '0') then @@ -642,6 +643,7 @@ begin SLAVE_READY_EN_G => true, VALID_THOLD_G => 1, -- FIFO configurations + SYNTH_MODE_G => SYNTH_MODE_G, MEMORY_TYPE_G => "block", GEN_SYNC_FIFO_G => true, CASCADE_SIZE_G => ite(JUMBO_G, 2, 1), @@ -661,17 +663,19 @@ begin mAxisMaster => mMaster, mAxisSlave => mSlave); - Fifo_Trans : entity surf.FifoSync + Fifo_Trans : entity surf.Fifo generic map ( - TPD_G => TPD_G, - MEMORY_TYPE_G => "distributed", - FWFT_EN_G => true, - DATA_WIDTH_G => 69, - ADDR_WIDTH_G => 4, - FULL_THRES_G => 8) + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + SYNTH_MODE_G => SYNTH_MODE_G, + MEMORY_TYPE_G => "distributed", + FWFT_EN_G => true, + DATA_WIDTH_G => 69, + ADDR_WIDTH_G => 4, + FULL_THRES_G => 8) port map ( - clk => ethClk, rst => ethRst, + wr_clk => ethClk, --Write Ports (wr_clk domain) wr_en => r.calc(0).step(EMAC_CSUM_PIPELINE_C), din(68) => r.fragDet(EMAC_CSUM_PIPELINE_C+1), @@ -685,6 +689,7 @@ begin din(15 downto 0) => r.protCsum, prog_full => tranPause, --Read Ports (rd_clk domain) + rd_clk => ethClk, rd_en => r.tranRd, dout(68) => fragDet, dout(67) => eofeDet, diff --git a/ethernet/EthMacCore/rtl/EthMacTxExport.vhd b/ethernet/EthMacCore/rtl/EthMacTxExport.vhd index 12e895c910..fbb75ba354 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxExport.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxExport.vhd @@ -24,8 +24,9 @@ use surf.StdRtlPkg.all; entity EthMacTxExport is generic ( - TPD_G : time := 1 ns; - PHY_TYPE_G : string := "XGMII"); + TPD_G : time := 1 ns; + PHY_TYPE_G : string := "XGMII"; + SYNTH_MODE_G : string := "inferred"); port ( -- Clock and Reset ethClkEn : in sl; @@ -87,7 +88,8 @@ begin U_10G : if (PHY_TYPE_G = "XGMII") generate U_XGMII : entity surf.EthMacTxExportXgmii generic map ( - TPD_G => TPD_G) + TPD_G => TPD_G; + SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Clock and Reset ethClk => ethClk, diff --git a/ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd b/ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd index 203b0b05bf..b47b1ad85f 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd @@ -25,7 +25,8 @@ use surf.EthMacPkg.all; entity EthMacTxExportXgmii is generic ( - TPD_G : time := 1 ns); + TPD_G : time := 1 ns; + SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs port ( -- Clock and Reset ethClk : in sl; @@ -146,23 +147,24 @@ begin SLAVE_READY_EN_G => true, VALID_THOLD_G => 1, -- FIFO configurations + SYNTH_MODE_G => SYNTH_MODE_G, MEMORY_TYPE_G => "distributed", GEN_SYNC_FIFO_G => true, CASCADE_SIZE_G => 1, FIFO_ADDR_WIDTH_G => 4, -- AXI Stream Port Configurations SLAVE_AXI_CONFIG_G => INT_EMAC_AXIS_CONFIG_C, -- 128-bit AXI stream interface - MASTER_AXI_CONFIG_G => AXI_CONFIG_C) -- 64-bit AXI stream interface + MASTER_AXI_CONFIG_G => AXI_CONFIG_C) -- 64-bit AXI stream interface port map ( -- Slave Port sAxisClk => ethClk, sAxisRst => ethRst, - sAxisMaster => macObMaster, -- 128-bit AXI stream interface + sAxisMaster => macObMaster, -- 128-bit AXI stream interface sAxisSlave => macObSlave, -- Master Port mAxisClk => ethClk, mAxisRst => ethRst, - mAxisMaster => macMaster, -- 64-bit AXI stream interface + mAxisMaster => macMaster, -- 64-bit AXI stream interface mAxisSlave => macSlave); -- Generate read @@ -340,9 +342,9 @@ begin -- Wait for gap, min 3 clocks if stateCount >= INTERGAP_C and stateCount >= 3 then - nxtState <= ST_IDLE_C; + nxtState <= ST_IDLE_C; else - nxtState <= curState; + nxtState <= curState; end if; -- Padding frame @@ -414,7 +416,7 @@ begin -- CRC Valid crcDataValid <= intAdvance after TPD_G; - crcIn <= intData after TPD_G; + crcIn <= intData after TPD_G; -- Last line if intLastLine = '1' then diff --git a/ethernet/EthMacCore/rtl/EthMacTxFifo.vhd b/ethernet/EthMacCore/rtl/EthMacTxFifo.vhd index f379e74195..d893aab7ae 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxFifo.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxFifo.vhd @@ -32,7 +32,8 @@ entity EthMacTxFifo is VLAN_EN_G : boolean := false; VLAN_SIZE_G : positive := 1; VLAN_COMMON_CLK_G : boolean := false; - VLAN_CONFIG_G : AxiStreamConfigType := INT_EMAC_AXIS_CONFIG_C); + VLAN_CONFIG_G : AxiStreamConfigType := INT_EMAC_AXIS_CONFIG_C; + SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs port ( -- Master Clock and Reset mClk : in sl; @@ -79,6 +80,7 @@ begin SLAVE_READY_EN_G => true, VALID_THOLD_G => 1, -- FIFO configurations + SYNTH_MODE_G => SYNTH_MODE_G, MEMORY_TYPE_G => "distributed", GEN_SYNC_FIFO_G => PRIM_COMMON_CLK_G, CASCADE_SIZE_G => 1, @@ -119,6 +121,7 @@ begin SLAVE_READY_EN_G => true, VALID_THOLD_G => 1, -- FIFO configurations + SYNTH_MODE_G => SYNTH_MODE_G, MEMORY_TYPE_G => "distributed", GEN_SYNC_FIFO_G => BYP_COMMON_CLK_G, CASCADE_SIZE_G => 1, @@ -161,6 +164,7 @@ begin SLAVE_READY_EN_G => true, VALID_THOLD_G => 1, -- FIFO configurations + SYNTH_MODE_G => SYNTH_MODE_G, MEMORY_TYPE_G => "distributed", GEN_SYNC_FIFO_G => VLAN_COMMON_CLK_G, CASCADE_SIZE_G => 1, diff --git a/ethernet/UdpEngine/rtl/UdpEngine.vhd b/ethernet/UdpEngine/rtl/UdpEngine.vhd index 165ad166fe..463ff9f137 100644 --- a/ethernet/UdpEngine/rtl/UdpEngine.vhd +++ b/ethernet/UdpEngine/rtl/UdpEngine.vhd @@ -33,16 +33,17 @@ entity UdpEngine is CLIENT_SIZE_G : positive := 1; CLIENT_PORTS_G : PositiveArray := (0 => 8193); -- General UDP/ARP/DHCP Generics - TX_FLOW_CTRL_G : boolean := true; -- True: Blow off the UDP TX data if link down, False: Backpressure until TX link is up + TX_FLOW_CTRL_G : boolean := true; -- True: Blow off the UDP TX data if link down, False: Backpressure until TX link is up DHCP_G : boolean := false; - CLK_FREQ_G : real := 156.25E+06; -- In units of Hz - COMM_TIMEOUT_G : positive := 30); -- In units of seconds, Client's Communication timeout before re-ARPing or DHCP discover/request + CLK_FREQ_G : real := 156.25E+06; -- In units of Hz + COMM_TIMEOUT_G : positive := 30; -- In units of seconds, Client's Communication timeout before re-ARPing or DHCP discover/request + SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs port ( -- Local Configurations - localMac : in slv(47 downto 0); -- big-Endian configuration - broadcastIp : in slv(31 downto 0); -- big-Endian configuration - localIpIn : in slv(31 downto 0); -- big-Endian configuration - dhcpIpOut : out slv(31 downto 0); -- big-Endian configuration + localMac : in slv(47 downto 0); -- big-Endian configuration + broadcastIp : in slv(31 downto 0); -- big-Endian configuration + localIpIn : in slv(31 downto 0); -- big-Endian configuration + dhcpIpOut : out slv(31 downto 0); -- big-Endian configuration -- Interface to IPV4 Engine obUdpMaster : out AxiStreamMasterType; obUdpSlave : in AxiStreamSlaveType; @@ -143,7 +144,8 @@ begin TPD_G => TPD_G, -- UDP ARP/DHCP Generics CLK_FREQ_G => CLK_FREQ_G, - COMM_TIMEOUT_G => COMM_TIMEOUT_G) + COMM_TIMEOUT_G => COMM_TIMEOUT_G; + SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Local Configurations localMac => localMac, diff --git a/ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd b/ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd index bfdba0ff5c..62b2e5387e 100644 --- a/ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd +++ b/ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd @@ -30,12 +30,14 @@ entity UdpEngineDhcp is TPD_G : time := 1 ns; -- UDP ARP/DHCP Generics CLK_FREQ_G : real := 156.25E+06; -- In units of Hz - COMM_TIMEOUT_G : positive := 30); + COMM_TIMEOUT_G : positive := 30; + -- RAM/FIFO synthesis mode + SYNTH_MODE_G : string := "inferred"); port ( -- Local Configurations - localMac : in slv(47 downto 0); -- big-Endian configuration - localIp : in slv(31 downto 0); -- big-Endian configuration - dhcpIp : out slv(31 downto 0); -- big-Endian configuration + localMac : in slv(47 downto 0); -- big-Endian configuration + localIp : in slv(31 downto 0); -- big-Endian configuration + dhcpIp : out slv(31 downto 0); -- big-Endian configuration -- Interface to DHCP Engine ibDhcpMaster : in AxiStreamMasterType; ibDhcpSlave : out AxiStreamSlaveType; @@ -149,6 +151,7 @@ begin SLAVE_READY_EN_G => true, VALID_THOLD_G => 1, -- FIFO configurations + SYNTH_MODE_G => SYNTH_MODE_G, MEMORY_TYPE_G => "distributed", GEN_SYNC_FIFO_G => true, CASCADE_SIZE_G => 1, @@ -310,9 +313,9 @@ begin -- Check for DHCP Discover if r.dhcpReq = '0' then v.txMaster.tData(7 downto 0) := toSlv(53, 8); -- code = DHCP Message Type - v.txMaster.tData(15 downto 8) := x"01"; -- len = 1 byte - v.txMaster.tData(23 downto 16) := x"01"; -- DHCP Discover = 0x1 - v.txMaster.tData(31 downto 24) := x"FF"; -- Endmark + v.txMaster.tData(15 downto 8) := x"01"; -- len = 1 byte + v.txMaster.tData(23 downto 16) := x"01"; -- DHCP Discover = 0x1 + v.txMaster.tData(31 downto 24) := x"FF"; -- Endmark v.txMaster.tLast := '1'; -- Start the communication timer v.commCnt := COMM_TIMEOUT_C; @@ -322,13 +325,13 @@ begin v.state := IDLE_S; else v.txMaster.tData(7 downto 0) := toSlv(53, 8); -- code = DHCP Message Type - v.txMaster.tData(15 downto 8) := x"01"; -- len = 1 byte - v.txMaster.tData(23 downto 16) := x"03"; -- DHCP request = 0x3 + v.txMaster.tData(15 downto 8) := x"01"; -- len = 1 byte + v.txMaster.tData(23 downto 16) := x"03"; -- DHCP request = 0x3 end if; -- Requested IP address[15:0] when 61 => v.txMaster.tData(7 downto 0) := toSlv(50, 8); -- code = Requested IP address - v.txMaster.tData(15 downto 8) := x"04"; -- len = 4 byte + v.txMaster.tData(15 downto 8) := x"04"; -- len = 4 byte v.txMaster.tData(31 downto 16) := r.yiaddr(15 downto 0); -- YIADDR[15:0] -- Requested IP address[32:16] when 62 => @@ -336,13 +339,13 @@ begin -- Server Identifier[15:0] when 63 => v.txMaster.tData(7 downto 0) := toSlv(54, 8); -- code = Server Identifier - v.txMaster.tData(15 downto 8) := x"04"; -- len = 4 byte + v.txMaster.tData(15 downto 8) := x"04"; -- len = 4 byte v.txMaster.tData(31 downto 16) := r.siaddr(15 downto 0); -- SIADDR[15:0] -- Server Identifier[32:16] when 64 => v.txMaster.tData(15 downto 0) := r.siaddr(31 downto 16); -- SIADDR[31:16] when 65 => - v.txMaster.tData(7 downto 0) := x"FF"; -- Endmark + v.txMaster.tData(7 downto 0) := x"FF"; -- Endmark v.txMaster.tKeep(15 downto 0) := x"0001"; v.txMaster.tLast := '1'; -- Start the communication timer @@ -455,7 +458,7 @@ begin v.decode := CODE_S; end if; -- Check the Code - if (r.opCode = 53) then -- Note: Assuming zero padding + if (r.opCode = 53) then -- Note: Assuming zero padding -- Check for DHCP Message Type if (r.len = 1) then @@ -577,6 +580,7 @@ begin SLAVE_READY_EN_G => true, VALID_THOLD_G => 1, -- FIFO configurations + SYNTH_MODE_G => SYNTH_MODE_G, MEMORY_TYPE_G => "distributed", GEN_SYNC_FIFO_G => true, CASCADE_SIZE_G => 1, diff --git a/ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd b/ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd index 4c81690335..4f115b7c2f 100644 --- a/ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd +++ b/ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd @@ -38,18 +38,19 @@ entity UdpEngineWrapper is CLIENT_PORTS_G : PositiveArray := (0 => 8193); CLIENT_EXT_CONFIG_G : boolean := false; -- General IPv4/ICMP/ARP/DHCP Generics - TX_FLOW_CTRL_G : boolean := true; -- True: Blow off the UDP TX data if link down, False: Backpressure until TX link is up + TX_FLOW_CTRL_G : boolean := true; -- True: Blow off the UDP TX data if link down, False: Backpressure until TX link is up DHCP_G : boolean := false; ICMP_G : boolean := true; ARP_G : boolean := true; - CLK_FREQ_G : real := 156.25E+06; -- In units of Hz + CLK_FREQ_G : real := 156.25E+06; -- In units of Hz COMM_TIMEOUT_G : positive := 30; -- In units of seconds, Client's Communication timeout before re-ARPing or DHCP discover/request - TTL_G : slv(7 downto 0) := x"20"; -- IPv4's Time-To-Live (TTL) - VLAN_G : boolean := false); -- true = VLAN support + TTL_G : slv(7 downto 0) := x"20"; -- IPv4's Time-To-Live (TTL) + VLAN_G : boolean := false; -- true = VLAN support + SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs port ( -- Local Configurations - localMac : in slv(47 downto 0); -- big-Endian configuration - localIp : in slv(31 downto 0); -- big-Endian configuration + localMac : in slv(47 downto 0); -- big-Endian configuration + localIp : in slv(31 downto 0); -- big-Endian configuration -- Remote Configurations clientRemotePort : in Slv16Array(CLIENT_SIZE_G-1 downto 0) := (others => x"0000"); clientRemoteIp : in Slv32Array(CLIENT_SIZE_G-1 downto 0) := (others => x"00000000"); @@ -169,7 +170,8 @@ begin TX_FLOW_CTRL_G => TX_FLOW_CTRL_G, DHCP_G => DHCP_G, CLK_FREQ_G => CLK_FREQ_G, - COMM_TIMEOUT_G => COMM_TIMEOUT_G) + COMM_TIMEOUT_G => COMM_TIMEOUT_G, + SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Local Configurations localMac => localMac, From 0c7b4bc29b6f6e55124736020f1ff7728a816e71 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 28 Jul 2020 14:29:42 -0700 Subject: [PATCH 08/36] Fix syntax errors --- ethernet/EthMacCore/rtl/EthMacRxImport.vhd | 2 +- ethernet/EthMacCore/rtl/EthMacTx.vhd | 2 +- ethernet/EthMacCore/rtl/EthMacTxExport.vhd | 2 +- ethernet/UdpEngine/rtl/UdpEngine.vhd | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/ethernet/EthMacCore/rtl/EthMacRxImport.vhd b/ethernet/EthMacCore/rtl/EthMacRxImport.vhd index 40efd91208..1483ffa6ca 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxImport.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxImport.vhd @@ -98,7 +98,7 @@ begin U_1G : if (PHY_TYPE_G = "GMII") generate U_GMII : entity surf.EthMacRxImportGmii generic map ( - TPD_G => TPD_G; + TPD_G => TPD_G, SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Clock and Reset diff --git a/ethernet/EthMacCore/rtl/EthMacTx.vhd b/ethernet/EthMacCore/rtl/EthMacTx.vhd index 3f15208972..27cd40a8c4 100644 --- a/ethernet/EthMacCore/rtl/EthMacTx.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTx.vhd @@ -211,7 +211,7 @@ begin U_Export : entity surf.EthMacTxExport generic map ( TPD_G => TPD_G, - PHY_TYPE_G => PHY_TYPE_G; + PHY_TYPE_G => PHY_TYPE_G, SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Clock and reset diff --git a/ethernet/EthMacCore/rtl/EthMacTxExport.vhd b/ethernet/EthMacCore/rtl/EthMacTxExport.vhd index fbb75ba354..1af44fe417 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxExport.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxExport.vhd @@ -88,7 +88,7 @@ begin U_10G : if (PHY_TYPE_G = "XGMII") generate U_XGMII : entity surf.EthMacTxExportXgmii generic map ( - TPD_G => TPD_G; + TPD_G => TPD_G, SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Clock and Reset diff --git a/ethernet/UdpEngine/rtl/UdpEngine.vhd b/ethernet/UdpEngine/rtl/UdpEngine.vhd index 463ff9f137..9a0d9be660 100644 --- a/ethernet/UdpEngine/rtl/UdpEngine.vhd +++ b/ethernet/UdpEngine/rtl/UdpEngine.vhd @@ -144,7 +144,7 @@ begin TPD_G => TPD_G, -- UDP ARP/DHCP Generics CLK_FREQ_G => CLK_FREQ_G, - COMM_TIMEOUT_G => COMM_TIMEOUT_G; + COMM_TIMEOUT_G => COMM_TIMEOUT_G, SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Local Configurations From 37c452f4c8eedb486638db2496d3b6d0520518a1 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 30 Jul 2020 11:02:09 -0700 Subject: [PATCH 09/36] Expose SYNTH_MODE_G in GigEthGtx7 --- ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd | 2 + protocols/rssi/v1/rtl/RssiCore.vhd | 56 +++++++++++---------- 2 files changed, 31 insertions(+), 27 deletions(-) diff --git a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd index 8a78a9c639..5d28d3a8c5 100644 --- a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd +++ b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd @@ -28,6 +28,7 @@ entity GigEthGtx7 is generic ( TPD_G : time := 1 ns; PAUSE_EN_G : boolean := true; + SYNTH_MODE_G : string := "inferred"; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; AXIL_BASE_ADDR_G : slv(31 downto 0) := X"00000000"; @@ -237,6 +238,7 @@ begin PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, PHY_TYPE_G => "GMII", + SYNTH_MODE_G => SYNTH_MODE_G, PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface diff --git a/protocols/rssi/v1/rtl/RssiCore.vhd b/protocols/rssi/v1/rtl/RssiCore.vhd index 03cf12a431..9c76286c00 100644 --- a/protocols/rssi/v1/rtl/RssiCore.vhd +++ b/protocols/rssi/v1/rtl/RssiCore.vhd @@ -58,18 +58,18 @@ entity RssiCore is RETRANSMIT_ENABLE_G : boolean := true; -- Enable/Disable retransmissions in tx module WINDOW_ADDR_SIZE_G : positive range 1 to 10 := 3; -- 2^WINDOW_ADDR_SIZE_G = Max number of segments in buffer - SEGMENT_ADDR_SIZE_G : positive := 7; -- 2^SEGMENT_ADDR_SIZE_G = Number of 64 bit wide data words + SEGMENT_ADDR_SIZE_G : positive := 7; -- 2^SEGMENT_ADDR_SIZE_G = Number of 64 bit wide data words -- AXIS Configurations - APP_AXIS_CONFIG_G : AxiStreamConfigType; - TSP_AXIS_CONFIG_G : AxiStreamConfigType; + APP_AXIS_CONFIG_G : AxiStreamConfigType; + TSP_AXIS_CONFIG_G : AxiStreamConfigType; -- Generic RSSI parameters BYP_TX_BUFFER_G : boolean := false; BYP_RX_BUFFER_G : boolean := false; - SYNTH_MODE_G : string := "inferred"; - MEMORY_TYPE_G : string := "block"; + SYNTH_MODE_G : string := "inferred"; + MEMORY_TYPE_G : string := "block"; -- Version and connection ID INIT_SEQ_N_G : natural := 16#80#; @@ -78,17 +78,17 @@ entity RssiCore is HEADER_CHKSUM_EN_G : boolean := true; -- Window parameters of receiver module - MAX_NUM_OUTS_SEG_G : positive range 2 to 1024 := 8; -- <=(2**WINDOW_ADDR_SIZE_G) - MAX_SEG_SIZE_G : positive := 1024; -- <= (2**SEGMENT_ADDR_SIZE_G)*8 Number of bytes + MAX_NUM_OUTS_SEG_G : positive range 2 to 1024 := 8; -- <=(2**WINDOW_ADDR_SIZE_G) + MAX_SEG_SIZE_G : positive := 1024; -- <= (2**SEGMENT_ADDR_SIZE_G)*8 Number of bytes -- RSSI Timeouts - ACK_TOUT_G : positive := 25; -- unit depends on TIMEOUT_UNIT_G - RETRANS_TOUT_G : positive := 50; -- unit depends on TIMEOUT_UNIT_G (Recommended >= MAX_NUM_OUTS_SEG_G*Data segment transmission time) + ACK_TOUT_G : positive := 25; -- unit depends on TIMEOUT_UNIT_G + RETRANS_TOUT_G : positive := 50; -- unit depends on TIMEOUT_UNIT_G (Recommended >= MAX_NUM_OUTS_SEG_G*Data segment transmission time) NULL_TOUT_G : positive := 200; -- unit depends on TIMEOUT_UNIT_G (Recommended >= 4*RETRANS_TOUT_G) -- Counters - MAX_RETRANS_CNT_G : positive := 2; - MAX_CUM_ACK_CNT_G : positive := 3 + MAX_RETRANS_CNT_G : positive := 2; + MAX_CUM_ACK_CNT_G : positive := 3 ); port ( clk_i : in sl; @@ -120,9 +120,9 @@ entity RssiCore is axilWriteSlave : out AxiLiteWriteSlaveType; -- Internal statuses - statusReg_o : out slv(6 downto 0); + statusReg_o : out slv(6 downto 0); - maxSegSize_o : out slv(15 downto 0)); + maxSegSize_o : out slv(15 downto 0)); end entity RssiCore; architecture rtl of RssiCore is @@ -266,9 +266,9 @@ architecture rtl of RssiCore is signal s_initSeqNReg : slv(7 downto 0); signal s_appRssiParamReg : RssiParamType; - signal s_statusReg : slv(statusReg_o'range); - signal s_dropCntReg : slv(31 downto 0); - signal s_validCntReg : slv(31 downto 0); + signal s_statusReg : slv(statusReg_o'range); + signal s_dropCntReg : slv(31 downto 0); + signal s_validCntReg : slv(31 downto 0); signal s_reconCntReg : slv(31 downto 0); signal s_resendCntReg : slv(31 downto 0); @@ -285,8 +285,8 @@ architecture rtl of RssiCore is ---------------------------------------------------------------------- begin -- Assertions to check generics - assert (1 <= MAX_NUM_OUTS_SEG_G and MAX_NUM_OUTS_SEG_G <=(2**WINDOW_ADDR_SIZE_G)) report "MAX_NUM_OUTS_SEG_G should be less or equal to 2**WINDOW_ADDR_SIZE_G" severity failure; - assert (8 <= MAX_SEG_SIZE_G and MAX_SEG_SIZE_G <=(2**SEGMENT_ADDR_SIZE_G)*8) report "MAX_SEG_SIZE_G should be less or equal to (2**SEGMENT_ADDR_SIZE_G)*8" severity failure; + assert (1 <= MAX_NUM_OUTS_SEG_G and MAX_NUM_OUTS_SEG_G <= (2**WINDOW_ADDR_SIZE_G)) report "MAX_NUM_OUTS_SEG_G should be less or equal to 2**WINDOW_ADDR_SIZE_G" severity failure; + assert (8 <= MAX_SEG_SIZE_G and MAX_SEG_SIZE_G <= (2**SEGMENT_ADDR_SIZE_G)*8) report "MAX_SEG_SIZE_G should be less or equal to (2**SEGMENT_ADDR_SIZE_G)*8" severity failure; -- ///////////////////////////////////////////////////////// @@ -340,7 +340,7 @@ begin validCnt_i => s_validCntReg, resendCnt_i => s_resendCntReg, reconCnt_i => s_reconCntReg - ); + ); s_injectFault <= s_injectFaultReg or inject_i; @@ -528,7 +528,7 @@ begin validCnt_o => s_validCntReg, resendCnt_o => s_resendCntReg, reconCnt_o => s_reconCntReg - ); + ); -- ///////////////////////////////////////////////////////// ------------------------------------------------------------ @@ -877,12 +877,13 @@ begin AppFifoOut_INST : entity surf.AxiStreamFifoV2 generic map ( TPD_G => TPD_G, - SLAVE_READY_EN_G => false, -- Using pause + SLAVE_READY_EN_G => false, -- Using pause GEN_SYNC_FIFO_G => true, + SYNTH_MODE_G => SYNTH_MODE_G, MEMORY_TYPE_G => "block", - FIFO_ADDR_WIDTH_G => SEGMENT_ADDR_SIZE_G+1, -- Enough to store 2 segments + FIFO_ADDR_WIDTH_G => SEGMENT_ADDR_SIZE_G+1, -- Enough to store 2 segments FIFO_FIXED_THRESH_G => true, - FIFO_PAUSE_THRESH_G => (2**SEGMENT_ADDR_SIZE_G) - 16, -- Threshold at 1 segment minus padding + FIFO_PAUSE_THRESH_G => (2**SEGMENT_ADDR_SIZE_G) - 16, -- Threshold at 1 segment minus padding INT_WIDTH_SELECT_G => "CUSTOM", INT_DATA_WIDTH_G => RSSI_WORD_WIDTH_C, SLAVE_AXI_CONFIG_G => RSSI_AXIS_CONFIG_C, @@ -907,12 +908,13 @@ begin TspFifoOut_INST : entity surf.AxiStreamFifoV2 generic map ( TPD_G => TPD_G, - SLAVE_READY_EN_G => false, -- Using pause + SLAVE_READY_EN_G => false, -- Using pause GEN_SYNC_FIFO_G => true, + SYNTH_MODE_G => SYNTH_MODE_G, MEMORY_TYPE_G => "block", - FIFO_ADDR_WIDTH_G => SEGMENT_ADDR_SIZE_G+1, -- Enough to store 2 segments + FIFO_ADDR_WIDTH_G => SEGMENT_ADDR_SIZE_G+1, -- Enough to store 2 segments FIFO_FIXED_THRESH_G => true, - FIFO_PAUSE_THRESH_G => (2**SEGMENT_ADDR_SIZE_G) - 16, -- Threshold at 1 segment minus padding + FIFO_PAUSE_THRESH_G => (2**SEGMENT_ADDR_SIZE_G) - 16, -- Threshold at 1 segment minus padding INT_WIDTH_SELECT_G => "CUSTOM", INT_DATA_WIDTH_G => RSSI_WORD_WIDTH_C, SLAVE_AXI_CONFIG_G => RSSI_AXIS_CONFIG_C, @@ -937,7 +939,7 @@ begin for i in 1 downto 0 generate U_AxiStreamMon : entity surf.AxiStreamMon generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, AXIS_CLK_FREQ_G => CLK_FREQUENCY_G, AXIS_CONFIG_G => APP_AXIS_CONFIG_G) port map ( From 7e0b4ad5a8bf04e2837acace98b9a5649abeabea Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 10 Aug 2020 16:15:17 -0700 Subject: [PATCH 10/36] adding AxiMonAxiL.vhd and AxiMonAxiL.py --- axi/axi-stream/rtl/AxiStreamMonAxiL.vhd | 2 +- axi/axi4/rtl/AxiMonAxiL.vhd | 112 ++++++++++++++++++++++++ python/surf/axi/_AxiMonAxiL.py | 28 ++++++ python/surf/axi/_AxiStreamMonAxiL.py | 17 +++- python/surf/axi/__init__.py | 1 + 5 files changed, 157 insertions(+), 3 deletions(-) create mode 100644 axi/axi4/rtl/AxiMonAxiL.vhd create mode 100644 python/surf/axi/_AxiMonAxiL.py diff --git a/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd b/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd index 84260f80cd..5dda52596d 100644 --- a/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd +++ b/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd @@ -25,7 +25,7 @@ use surf.AxiLitePkg.all; entity AxiStreamMonAxiL is generic ( TPD_G : time := 1 ns; - COMMON_CLK_G : boolean := false; -- true if axisClk = statusClk + COMMON_CLK_G : boolean := false; -- true if axisClk = axilClk AXIS_CLK_FREQ_G : real := 156.25E+6; -- units of Hz AXIS_NUM_SLOTS_G : positive := 1; AXIS_CONFIG_G : AxiStreamConfigType); diff --git a/axi/axi4/rtl/AxiMonAxiL.vhd b/axi/axi4/rtl/AxiMonAxiL.vhd new file mode 100644 index 0000000000..2bfbf09204 --- /dev/null +++ b/axi/axi4/rtl/AxiMonAxiL.vhd @@ -0,0 +1,112 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: AXI-Lite Wrapper on AXI4 Monitor Module +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiPkg.all; + +entity AxiMonAxiL is + generic ( + TPD_G : time := 1 ns; + COMMON_CLK_G : boolean := false; -- true if axiClk = axilClk + AXI_CLK_FREQ_G : real := 156.25E+6; -- units of Hz + AXI_NUM_SLOTS_G : positive := 1; + AXI_CONFIG_C : AxiConfigType := AXI_CONFIG_INIT_C); + port ( + -- AXI Stream Monitoring Interface + axiClk : in sl; + axiRst : in sl; + axiWriteMasters : in AxiWriteMasterArray(AXI_NUM_SLOTS_G-1 downto 0); + axiWriteSlaves : in AxiWriteSlaveArray(AXI_NUM_SLOTS_G-1 downto 0); + axiReadMasters : in AxiReadMasterArray(AXI_NUM_SLOTS_G-1 downto 0); + axiReadSlaves : in AxiReadSlaveArray(AXI_NUM_SLOTS_G-1 downto 0); + -- AXI-Lite for register access + axilClk : in std_logic; + axilRst : in std_logic; + sAxilWriteMaster : in AxiLiteWriteMasterType; + sAxilWriteSlave : out AxiLiteWriteSlaveType; + sAxilReadMaster : in AxiLiteReadMasterType; + sAxilReadSlave : out AxiLiteReadSlaveType); +end AxiMonAxiL; + +architecture mapping of AxiMonAxiL is + + constant AXIS_CONFIG_C : AxiStreamConfigType := ( + TSTRB_EN_C => AXI_STREAM_CONFIG_INIT_C.TSTRB_EN_C, + TDATA_BYTES_C => AXI_CONFIG_C.DATA_BYTES_C, + TDEST_BITS_C => AXI_STREAM_CONFIG_INIT_C.TDEST_BITS_C, + TID_BITS_C => AXI_STREAM_CONFIG_INIT_C.TID_BITS_C, + TKEEP_MODE_C => AXI_STREAM_CONFIG_INIT_C.TKEEP_MODE_C, + TUSER_BITS_C => AXI_STREAM_CONFIG_INIT_C.TUSER_BITS_C, + TUSER_MODE_C => AXI_STREAM_CONFIG_INIT_C.TUSER_MODE_C); + + signal axisMasters : AxiStreamMasterArray(2*AXI_NUM_SLOTS_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal axisSlaves : AxiStreamSlaveArray(2*AXI_NUM_SLOTS_G-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); + +begin + + GEN_VEC : for i in 0 to (AXI_NUM_SLOTS_G-1) generate + + ------------------------------------- + -- Remap AXI4.WRITE[i] to AXIS[2*i+0] + ------------------------------------- + axisMasters(2*i+0).tValid <= axiWriteMasters(i).wvalid; + axisMasters(2*i+0).tStrb(AXI_CONFIG_C.DATA_BYTES_C-1 downto 0) <= axiWriteMasters(i).wstrb(AXI_CONFIG_C.DATA_BYTES_C-1 downto 0); + axisMasters(2*i+0).tKeep(AXI_CONFIG_C.DATA_BYTES_C-1 downto 0) <= axiWriteMasters(i).wstrb(AXI_CONFIG_C.DATA_BYTES_C-1 downto 0); + axisMasters(2*i+0).tLast <= axiWriteMasters(i).wlast; + axisSlaves(2*i+0).tReady <= axiWriteSlaves(i).wready; + + ------------------------------------ + -- Remap AXI4.READ[i] to AXIS[2*i+1] + ------------------------------------ + axisMasters(2*i+1).tValid <= axiReadSlaves(i).rvalid; + axisMasters(2*i+1).tStrb(AXI_CONFIG_C.DATA_BYTES_C-1 downto 0) <= (others => '1'); + axisMasters(2*i+1).tKeep(AXI_CONFIG_C.DATA_BYTES_C-1 downto 0) <= (others => '1'); + axisMasters(2*i+1).tLast <= axiReadSlaves(i).rlast; + axisSlaves(2*i+1).tReady <= axiReadMasters(i).rready; + + end generate; + + ---------------------------------------------------------------------- + -- Re-propose the existing AXI stream monitor as a AXI4 memory monitor + ---------------------------------------------------------------------- + U_Monitor : entity surf.AxiStreamMonAxiL + generic map( + TPD_G => TPD_G, + COMMON_CLK_G => COMMON_CLK_G, + AXIS_CLK_FREQ_G => AXI_CLK_FREQ_G, + AXIS_NUM_SLOTS_G => 2*AXI_NUM_SLOTS_G, + AXIS_CONFIG_G => AXIS_CONFIG_C) + port map( + -- AXIS Stream Interface + axisClk => axiClk, + axisRst => axiRst, + axisMasters => axisMasters, + axisSlaves => axisSlaves, + -- AXI lite slave port for register access + axilClk => axilClk, + axilRst => axilRst, + sAxilWriteMaster => sAxilWriteMaster, + sAxilWriteSlave => sAxilWriteSlave, + sAxilReadMaster => sAxilReadMaster, + sAxilReadSlave => sAxilReadSlave); + +end mapping; diff --git a/python/surf/axi/_AxiMonAxiL.py b/python/surf/axi/_AxiMonAxiL.py new file mode 100644 index 0000000000..630e73655b --- /dev/null +++ b/python/surf/axi/_AxiMonAxiL.py @@ -0,0 +1,28 @@ +#----------------------------------------------------------------------------- +# Description: +# PyRogue AXI4 Monitor Module Module +#----------------------------------------------------------------------------- +# This file is part of the 'SLAC Firmware Standard Library'. It is subject to +# the license terms in the LICENSE.txt file found in the top-level directory +# of this distribution and at: +# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +# No part of the 'SLAC Firmware Standard Library', including this file, may be +# copied, modified, propagated, or distributed except according to the terms +# contained in the LICENSE.txt file. +#----------------------------------------------------------------------------- + +import pyrogue as pr +import surf.axi as axi + +class AxiMonAxiL(axi.AxiStreamMonAxiL): + def __init__(self, numberLanes=1, **kwargs): + + axiType = [None for i in range(2*numberLanes)] + for i in range(numberLanes): + axiType[2*i+0] = f'Write[{i}]' + axiType[2*i+1] = f'Read[{i}]' + + super().__init__( + numberLanes = 2*numberLanes, + chName = axiType, + **kwargs) diff --git a/python/surf/axi/_AxiStreamMonAxiL.py b/python/surf/axi/_AxiStreamMonAxiL.py index 523c948e60..1665522187 100644 --- a/python/surf/axi/_AxiStreamMonAxiL.py +++ b/python/surf/axi/_AxiStreamMonAxiL.py @@ -159,7 +159,7 @@ def convMbps(var): return var.dependencies[0].value() * 8e-6 class AxiStreamMonAxiL(pr.Device): - def __init__(self, numberLanes=1, **kwargs): + def __init__(self, numberLanes=1, hideConfig=True, chName=None, **kwargs): super().__init__(**kwargs) self.add(pr.RemoteCommand( @@ -179,6 +179,7 @@ def __init__(self, numberLanes=1, **kwargs): mode = 'RO', disp = '{:d}', overlapEn = True, + hidden = hideConfig, )) self.add(pr.RemoteVariable( @@ -189,6 +190,7 @@ def __init__(self, numberLanes=1, **kwargs): mode = 'RO', disp = '{:d}', overlapEn = True, + hidden = hideConfig, )) self.add(pr.RemoteVariable( @@ -199,6 +201,7 @@ def __init__(self, numberLanes=1, **kwargs): mode = 'RO', disp = '{:d}', overlapEn = True, + hidden = hideConfig, )) self.add(pr.RemoteVariable( @@ -208,6 +211,7 @@ def __init__(self, numberLanes=1, **kwargs): bitOffset = 12, mode = 'RO', overlapEn = True, + hidden = hideConfig, )) self.add(pr.RemoteVariable( @@ -224,6 +228,7 @@ def __init__(self, numberLanes=1, **kwargs): 0xF: 'UNDEFINED', }, overlapEn = True, + hidden = hideConfig, )) self.add(pr.RemoteVariable( @@ -240,6 +245,7 @@ def __init__(self, numberLanes=1, **kwargs): 0xF: 'UNDEFINED', }, overlapEn = True, + hidden = hideConfig, )) self.add(pr.RemoteVariable( @@ -250,6 +256,7 @@ def __init__(self, numberLanes=1, **kwargs): mode = 'RO', base = pr.Bool, overlapEn = True, + hidden = hideConfig, )) self.add(pr.RemoteVariable( @@ -260,11 +267,17 @@ def __init__(self, numberLanes=1, **kwargs): mode = 'RO', base = pr.Bool, overlapEn = True, + hidden = hideConfig, )) + if chName is None: + self.chName = [f'Ch[{i}]' for i in range(numberLanes)] + else: + self.chName = chName + for i in range(numberLanes): self.add(AxiStreamMonChannel( - name = f'Ch[{i}]', + name = self.chName[i], offset = (i*0x40), expand = True, )) diff --git a/python/surf/axi/__init__.py b/python/surf/axi/__init__.py index 04c3304b61..3e60fe6234 100644 --- a/python/surf/axi/__init__.py +++ b/python/surf/axi/__init__.py @@ -12,6 +12,7 @@ from surf.axi._AxiMemTester import * from surf.axi._AxiStreamDmaRingWrite import * from surf.axi._AxiStreamMonAxiL import * +from surf.axi._AxiMonAxiL import * from surf.axi._AxiVersion import * from surf.axi._AxiVersionLegacy import * from surf.axi._AxiStreamDmaFifo import * From ba6c05309779088dad1fde702c07d70ff1659bbb Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 10 Aug 2020 16:20:05 -0700 Subject: [PATCH 11/36] removing generic default to force user to define AXI_CONFIG_C --- axi/axi4/rtl/AxiMonAxiL.vhd | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/axi/axi4/rtl/AxiMonAxiL.vhd b/axi/axi4/rtl/AxiMonAxiL.vhd index 2bfbf09204..70aafb7dda 100644 --- a/axi/axi4/rtl/AxiMonAxiL.vhd +++ b/axi/axi4/rtl/AxiMonAxiL.vhd @@ -25,11 +25,11 @@ use surf.AxiPkg.all; entity AxiMonAxiL is generic ( - TPD_G : time := 1 ns; - COMMON_CLK_G : boolean := false; -- true if axiClk = axilClk - AXI_CLK_FREQ_G : real := 156.25E+6; -- units of Hz - AXI_NUM_SLOTS_G : positive := 1; - AXI_CONFIG_C : AxiConfigType := AXI_CONFIG_INIT_C); + TPD_G : time := 1 ns; + COMMON_CLK_G : boolean := false; -- true if axiClk = axilClk + AXI_CLK_FREQ_G : real := 156.25E+6; -- units of Hz + AXI_NUM_SLOTS_G : positive := 1; + AXI_CONFIG_C : AxiConfigType); port ( -- AXI Stream Monitoring Interface axiClk : in sl; From b5c26b0e1819eb990f94dca1ce0b5681e018cf6d Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 10 Aug 2020 16:20:51 -0700 Subject: [PATCH 12/36] fixed typo --- axi/axi4/rtl/AxiMonAxiL.vhd | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/axi/axi4/rtl/AxiMonAxiL.vhd b/axi/axi4/rtl/AxiMonAxiL.vhd index 70aafb7dda..a7a036c635 100644 --- a/axi/axi4/rtl/AxiMonAxiL.vhd +++ b/axi/axi4/rtl/AxiMonAxiL.vhd @@ -29,7 +29,7 @@ entity AxiMonAxiL is COMMON_CLK_G : boolean := false; -- true if axiClk = axilClk AXI_CLK_FREQ_G : real := 156.25E+6; -- units of Hz AXI_NUM_SLOTS_G : positive := 1; - AXI_CONFIG_C : AxiConfigType); + AXI_CONFIG_G : AxiConfigType); port ( -- AXI Stream Monitoring Interface axiClk : in sl; @@ -51,7 +51,7 @@ architecture mapping of AxiMonAxiL is constant AXIS_CONFIG_C : AxiStreamConfigType := ( TSTRB_EN_C => AXI_STREAM_CONFIG_INIT_C.TSTRB_EN_C, - TDATA_BYTES_C => AXI_CONFIG_C.DATA_BYTES_C, + TDATA_BYTES_C => AXI_CONFIG_G.DATA_BYTES_C, TDEST_BITS_C => AXI_STREAM_CONFIG_INIT_C.TDEST_BITS_C, TID_BITS_C => AXI_STREAM_CONFIG_INIT_C.TID_BITS_C, TKEEP_MODE_C => AXI_STREAM_CONFIG_INIT_C.TKEEP_MODE_C, @@ -69,8 +69,8 @@ begin -- Remap AXI4.WRITE[i] to AXIS[2*i+0] ------------------------------------- axisMasters(2*i+0).tValid <= axiWriteMasters(i).wvalid; - axisMasters(2*i+0).tStrb(AXI_CONFIG_C.DATA_BYTES_C-1 downto 0) <= axiWriteMasters(i).wstrb(AXI_CONFIG_C.DATA_BYTES_C-1 downto 0); - axisMasters(2*i+0).tKeep(AXI_CONFIG_C.DATA_BYTES_C-1 downto 0) <= axiWriteMasters(i).wstrb(AXI_CONFIG_C.DATA_BYTES_C-1 downto 0); + axisMasters(2*i+0).tStrb(AXI_CONFIG_G.DATA_BYTES_C-1 downto 0) <= axiWriteMasters(i).wstrb(AXI_CONFIG_G.DATA_BYTES_C-1 downto 0); + axisMasters(2*i+0).tKeep(AXI_CONFIG_G.DATA_BYTES_C-1 downto 0) <= axiWriteMasters(i).wstrb(AXI_CONFIG_G.DATA_BYTES_C-1 downto 0); axisMasters(2*i+0).tLast <= axiWriteMasters(i).wlast; axisSlaves(2*i+0).tReady <= axiWriteSlaves(i).wready; @@ -78,8 +78,8 @@ begin -- Remap AXI4.READ[i] to AXIS[2*i+1] ------------------------------------ axisMasters(2*i+1).tValid <= axiReadSlaves(i).rvalid; - axisMasters(2*i+1).tStrb(AXI_CONFIG_C.DATA_BYTES_C-1 downto 0) <= (others => '1'); - axisMasters(2*i+1).tKeep(AXI_CONFIG_C.DATA_BYTES_C-1 downto 0) <= (others => '1'); + axisMasters(2*i+1).tStrb(AXI_CONFIG_G.DATA_BYTES_C-1 downto 0) <= (others => '1'); + axisMasters(2*i+1).tKeep(AXI_CONFIG_G.DATA_BYTES_C-1 downto 0) <= (others => '1'); axisMasters(2*i+1).tLast <= axiReadSlaves(i).rlast; axisSlaves(2*i+1).tReady <= axiReadMasters(i).rready; From db0f91f4d9cee689ae7ff3d398443b36958c060e Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 10 Aug 2020 16:21:38 -0700 Subject: [PATCH 13/36] using sl naming convention --- axi/axi-stream/rtl/AxiStreamMonAxiL.vhd | 4 ++-- axi/axi4/rtl/AxiMonAxiL.vhd | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd b/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd index 5dda52596d..ae4af0fe4b 100644 --- a/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd +++ b/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd @@ -36,8 +36,8 @@ entity AxiStreamMonAxiL is axisMasters : in AxiStreamMasterArray(AXIS_NUM_SLOTS_G-1 downto 0); axisSlaves : in AxiStreamSlaveArray(AXIS_NUM_SLOTS_G-1 downto 0); -- AXI lite slave port for register access - axilClk : in std_logic; - axilRst : in std_logic; + axilClk : in sl; + axilRst : in sl; sAxilWriteMaster : in AxiLiteWriteMasterType; sAxilWriteSlave : out AxiLiteWriteSlaveType; sAxilReadMaster : in AxiLiteReadMasterType; diff --git a/axi/axi4/rtl/AxiMonAxiL.vhd b/axi/axi4/rtl/AxiMonAxiL.vhd index a7a036c635..05a78de85a 100644 --- a/axi/axi4/rtl/AxiMonAxiL.vhd +++ b/axi/axi4/rtl/AxiMonAxiL.vhd @@ -39,8 +39,8 @@ entity AxiMonAxiL is axiReadMasters : in AxiReadMasterArray(AXI_NUM_SLOTS_G-1 downto 0); axiReadSlaves : in AxiReadSlaveArray(AXI_NUM_SLOTS_G-1 downto 0); -- AXI-Lite for register access - axilClk : in std_logic; - axilRst : in std_logic; + axilClk : in sl; + axilRst : in sl; sAxilWriteMaster : in AxiLiteWriteMasterType; sAxilWriteSlave : out AxiLiteWriteSlaveType; sAxilReadMaster : in AxiLiteReadMasterType; From 6811a1d85051d68dd5eb6394e89f348070a1e7ee Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 10 Aug 2020 16:23:31 -0700 Subject: [PATCH 14/36] flake8 fix --- python/surf/axi/_AxiMonAxiL.py | 1 - 1 file changed, 1 deletion(-) diff --git a/python/surf/axi/_AxiMonAxiL.py b/python/surf/axi/_AxiMonAxiL.py index 630e73655b..b9cbb79141 100644 --- a/python/surf/axi/_AxiMonAxiL.py +++ b/python/surf/axi/_AxiMonAxiL.py @@ -11,7 +11,6 @@ # contained in the LICENSE.txt file. #----------------------------------------------------------------------------- -import pyrogue as pr import surf.axi as axi class AxiMonAxiL(axi.AxiStreamMonAxiL): From b93561350d18de3ec1668716e5a43aa2e97746ce Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 11 Aug 2020 10:11:31 -0700 Subject: [PATCH 15/36] adding AxiRateGen.vhd --- axi/axi4/rtl/AxiRateGen.vhd | 354 ++++++++++++++++++++++++++++++++++++ 1 file changed, 354 insertions(+) create mode 100644 axi/axi4/rtl/AxiRateGen.vhd diff --git a/axi/axi4/rtl/AxiRateGen.vhd b/axi/axi4/rtl/AxiRateGen.vhd new file mode 100644 index 0000000000..67236d6727 --- /dev/null +++ b/axi/axi4/rtl/AxiRateGen.vhd @@ -0,0 +1,354 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: General Purpose AXI4 memory rate generator +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiPkg.all; + +entity AxiRateGen is + generic ( + TPD_G : time := 1 ns; + COMMON_CLK_G : boolean := false; + AXI_CONFIG_G : AxiConfigType); + port ( + -- AXI4 Memory Interface + axiClk : in sl; + axiRst : in sl; + axiWriteMaster : out AxiWriteMasterType; + axiWriteSlave : in AxiWriteSlaveType; + axiReadMaster : out AxiReadMasterType; + axiReadSlave : in AxiReadSlaveType; + -- AXI-Lite Interface + axilClk : in sl; + axilRst : in sl; + sAxilReadMaster : in AxiLiteReadMasterType; + sAxilReadSlave : out AxiLiteReadSlaveType; + sAxilWriteMaster : in AxiLiteWriteMasterType; + sAxilWriteSlave : out AxiLiteWriteSlaveType); +end AxiRateGen; + +architecture rtl of AxiRateGen is + + type WrStateType is ( + WRITE_ADDR_S, + WRITE_DATA_S, + WRITE_RESP_S); + + type RdStateType is ( + READ_ADDR_S, + READ_DATA_S); + + type RegType is record + wrState : WrStateType; + rdState : RdStateType; + awlen : slv(7 downto 0); + writeSize : slv(11 downto 0); + wrTimer : slv(31 downto 0); + rdTimer : slv(31 downto 0); + -- Registers + wrEnable : sl; + rdEnable : sl; + wrSize : slv(11 downto 0); + rdSize : slv(11 downto 0); + wrPeriod : slv(31 downto 0); + rdPeriod : slv(31 downto 0); + awburst : slv(1 downto 0); + awcache : slv(3 downto 0); + arburst : slv(1 downto 0); + arcache : slv(3 downto 0); + -- AXI4 + axiWriteMaster : AxiWriteMasterType; + axiReadMaster : AxiReadMasterType; + -- AXI-Lite + axilReadSlave : AxiLiteReadSlaveType; + axilWriteSlave : AxiLiteWriteSlaveType; + end record; + + constant REG_INIT_C : RegType := ( + wrState => WRITE_ADDR_S, + rdState => READ_ADDR_S, + awlen => x"00", + writeSize => x"FFF", + wrTimer => x"0000_0000", + rdTimer => x"0000_0000", + -- Registers + wrEnable => '0', + rdEnable => '0', + wrSize => x"FFF", + rdSize => x"FFF", + wrPeriod => x"0000_FFFF", + rdPeriod => x"0000_FFFF", + awburst => "01", + awcache => "1111", + arburst => "01", + arcache => "1111", + -- AXI4 + axiWriteMaster => axiWriteMasterInit(AXI_CONFIG_G), + axiReadMaster => axiReadMasterInit(AXI_CONFIG_G), + -- AXI-Lite + axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, + axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal axilReadMaster : AxiLiteReadMasterType; + signal axilReadSlave : AxiLiteReadSlaveType; + signal axilWriteMaster : AxiLiteWriteMasterType; + signal axilWriteSlave : AxiLiteWriteSlaveType; + +begin + + U_AxiLiteAsync : entity surf.AxiLiteAsync + generic map ( + TPD_G => TPD_G, + COMMON_CLK_G => COMMON_CLK_G, + NUM_ADDR_BITS_G => 8) + port map ( + -- Slave Interface + sAxiClk => axilClk, + sAxiClkRst => axilRst, + sAxiReadMaster => sAxilReadMaster, + sAxiReadSlave => sAxilReadSlave, + sAxiWriteMaster => sAxilWriteMaster, + sAxiWriteSlave => sAxilWriteSlave, + -- Master Interface + mAxiClk => axiClk, + mAxiClkRst => axiRst, + mAxiReadMaster => axilReadMaster, + mAxiReadSlave => axilReadSlave, + mAxiWriteMaster => axilWriteMaster, + mAxiWriteSlave => axilWriteSlave); + + comb : process (axiReadSlave, axiRst, axiWriteSlave, axilReadMaster, + axilWriteMaster, r) is + variable v : RegType; + variable axilEp : AxiLiteEndpointType; + begin + -- Latch the current value + v := r; + + ---------------------------------------------------------------------- + -- AXI-Lite Transactions + ---------------------------------------------------------------------- + + -- Determine the transaction type + axiSlaveWaitTxn(axilEp, axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave); + + axiSlaveRegister(axilEp, x"00", 0, v.wrEnable); + axiSlaveRegister(axilEp, x"04", 0, v.rdEnable); + + axiSlaveRegister(axilEp, x"10", 0, v.wrSize); + axiSlaveRegister(axilEp, x"14", 0, v.rdSize); + + axiSlaveRegister(axilEp, x"20", 0, v.wrPeriod); + axiSlaveRegister(axilEp, x"24", 0, v.rdPeriod); + + axiSlaveRegister(axilEp, x"30", 0, v.awburst); + axiSlaveRegister(axilEp, x"34", 0, v.arburst); + + axiSlaveRegister(axilEp, x"40", 0, v.awcache); + axiSlaveRegister(axilEp, x"44", 0, v.arcache); + + -- Close the transaction + axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C); + + ---------------------------------------------------------------------- + + -- Write Timer + if (r.wrPeriod /= v.wrPeriod) then + -- Reset the timer + v.wrTimer := (others => '0'); + elsif (r.wrTimer /= 0) then + -- Decrement the counter + v.wrTimer := r.wrTimer - 1; + end if; + + -- Write AXI Flow Control + v.axiWriteMaster.bready := '0'; + if axiWriteSlave.awready = '1' then + v.axiWriteMaster.awvalid := '0'; + end if; + if axiWriteSlave.wready = '1' then + v.axiWriteMaster.wvalid := '0'; + v.axiWriteMaster.wlast := '0'; + end if; + + -- State Machine + case (r.wrState) is + ---------------------------------------------------------------------- + when WRITE_ADDR_S => + -- Check if enabled and timeout + if (r.wrEnable = '1') and (r.wrTimer = 0) and (v.axiWriteMaster.awvalid = '0') then + + -- Arm the timer + v.wrTimer := r.wrPeriod; + + -- Latch the write size + v.writeSize := r.wrSize; + + -- Write Address channel + v.axiWriteMaster.awvalid := '1'; + v.axiWriteMaster.awsize := toSlv(log2(AXI_CONFIG_G.DATA_BYTES_C), 3); + v.axiWriteMaster.awlen := getAxiLen(AXI_CONFIG_G, conv_integer(r.wrSize)+1); + v.awlen := getAxiLen(AXI_CONFIG_G, conv_integer(r.wrSize)+1); + v.axiWriteMaster.awaddr := r.axiWriteMaster.awaddr + 4096; -- 4kB address alignment + v.axiWriteMaster.awburst := r.awburst; + v.axiWriteMaster.awcache := r.awcache; + + -- Next State + v.wrState := WRITE_DATA_S; + + end if; + ---------------------------------------------------------------------- + when WRITE_DATA_S => + -- Check if ready to move write data + if (v.axiWriteMaster.wvalid = '0') then + + -- Write Data channel + v.axiWriteMaster.wvalid := '1'; + v.axiWriteMaster.wstrb := (others => '1'); + + -- Decrement the counters + v.awlen := r.awlen - 1; + v.writeSize := r.writeSize - AXI_CONFIG_G.DATA_BYTES_C; + + -- Check for last write + if (r.awlen = 0) then + + -- Terminate the frame + v.axiWriteMaster.wlast := '1'; + + -- Update the WSTRB + if (r.writeSize < AXI_CONFIG_G.DATA_BYTES_C) then + v.axiWriteMaster.wstrb := (others => '0'); + v.axiWriteMaster.wstrb(conv_integer(r.writeSize) downto 0) := (others => '1'); + end if; + + -- Next State + v.wrState := WRITE_RESP_S; + + end if; + + end if; + ---------------------------------------------------------------------- + when WRITE_RESP_S => + -- Wait for the response + if axiWriteSlave.bvalid = '1' then + + -- Accept the response + v.axiWriteMaster.bready := '1'; + + -- Next State + v.wrState := WRITE_ADDR_S; + + end if; + ---------------------------------------------------------------------- + end case; + + ---------------------------------------------------------------------- + + -- Read Timer + if (r.rdPeriod /= v.rdPeriod) then + -- Reset the timer + v.rdTimer := (others => '0'); + elsif (r.rdTimer /= 0) then + -- Decrement the counter + v.rdTimer := r.rdTimer - 1; + end if; + + -- Read AXI Flow Control + v.axiReadMaster.rready := '0'; + if axiReadSlave.arready = '1' then + v.axiReadMaster.arvalid := '0'; + end if; + + -- State Machine + case (r.rdState) is + ---------------------------------------------------------------------- + when READ_ADDR_S => + -- Check if enabled and timeout + if (r.rdEnable = '1') and (r.rdTimer = 0) and (v.axiReadMaster.arvalid = '0') then + + -- Arm the timer + v.rdTimer := r.rdPeriod; + + -- Write Address channel + v.axiReadMaster.arvalid := '1'; + v.axiReadMaster.arsize := toSlv(log2(AXI_CONFIG_G.DATA_BYTES_C), 3); + v.axiReadMaster.arlen := getAxiLen(AXI_CONFIG_G, conv_integer(r.rdSize)+1); + v.axiReadMaster.araddr := r.axiReadMaster.araddr + 4096; -- 4kB address alignment + v.axiReadMaster.arburst := r.arburst; + v.axiReadMaster.arcache := r.arcache; + + -- Next State + v.rdState := READ_DATA_S; + + end if; + ---------------------------------------------------------------------- + when READ_DATA_S => + -- Check for new data + if (axiReadSlave.rvalid = '1') then + + -- Accept the data + v.axiReadMaster.rready := '1'; + + -- Check for last transfer + if axiReadSlave.rlast = '1' then + + -- Next State + v.rdState := READ_ADDR_S; + + end if; + + end if; + ---------------------------------------------------------------------- + end case; + + -- AXI-Lite Outputs + axilReadSlave <= r.axilReadSlave; + axilWriteSlave <= r.axilWriteSlave; + + -- AXI4 Write Outputs + axiWriteMaster <= r.axiWriteMaster; + axiWriteMaster.bready <= v.axiWriteMaster.bready; + + -- AXI4 Read Outputs + axiReadMaster <= r.axiReadMaster; + axiReadMaster.rready <= v.axiReadMaster.rready; + + -- Reset + if axiRst = '1' then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (axiClk) is + begin + if rising_edge(axiClk) then + r <= rin after TPD_G; + end if; + end process seq; + +end rtl; From 6b1292f4c0096cbee7ff62f7ddcb80024c333312 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 11 Aug 2020 10:11:41 -0700 Subject: [PATCH 16/36] fixed comments --- axi/axi4/rtl/AxiMemTester.vhd | 2 +- axi/axi4/rtl/AxiMonAxiL.vhd | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/axi/axi4/rtl/AxiMemTester.vhd b/axi/axi4/rtl/AxiMemTester.vhd index 19ebedd3ac..3194fc9c8c 100644 --- a/axi/axi4/rtl/AxiMemTester.vhd +++ b/axi/axi4/rtl/AxiMemTester.vhd @@ -40,7 +40,7 @@ entity AxiMemTester is axilWriteSlave : out AxiLiteWriteSlaveType; memReady : out sl; memError : out sl; - -- DDR Memory Interface + -- AXI4 Memory Interface axiClk : in sl; axiRst : in sl; start : in sl; diff --git a/axi/axi4/rtl/AxiMonAxiL.vhd b/axi/axi4/rtl/AxiMonAxiL.vhd index 05a78de85a..a4f26ad23e 100644 --- a/axi/axi4/rtl/AxiMonAxiL.vhd +++ b/axi/axi4/rtl/AxiMonAxiL.vhd @@ -31,7 +31,7 @@ entity AxiMonAxiL is AXI_NUM_SLOTS_G : positive := 1; AXI_CONFIG_G : AxiConfigType); port ( - -- AXI Stream Monitoring Interface + -- AXI4 Memory Interfaces axiClk : in sl; axiRst : in sl; axiWriteMasters : in AxiWriteMasterArray(AXI_NUM_SLOTS_G-1 downto 0); From 9e948375f05526d9d42874ce7a59329ce36c04f4 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 11 Aug 2020 10:12:03 -0700 Subject: [PATCH 17/36] removed whitespace --- axi/axi4/rtl/AxiRateGen.vhd | 4 +- .../UltraScale/rtl/Ad9249Deserializer.vhd | 52 ++++++++-------- .../UltraScale/rtl/Ad9249ReadoutGroup.vhd | 62 +++++++++---------- 3 files changed, 59 insertions(+), 59 deletions(-) diff --git a/axi/axi4/rtl/AxiRateGen.vhd b/axi/axi4/rtl/AxiRateGen.vhd index 67236d6727..0b1045ce47 100644 --- a/axi/axi4/rtl/AxiRateGen.vhd +++ b/axi/axi4/rtl/AxiRateGen.vhd @@ -195,7 +195,7 @@ begin case (r.wrState) is ---------------------------------------------------------------------- when WRITE_ADDR_S => - -- Check if enabled and timeout + -- Check if enabled and timeout if (r.wrEnable = '1') and (r.wrTimer = 0) and (v.axiWriteMaster.awvalid = '0') then -- Arm the timer @@ -284,7 +284,7 @@ begin case (r.rdState) is ---------------------------------------------------------------------- when READ_ADDR_S => - -- Check if enabled and timeout + -- Check if enabled and timeout if (r.rdEnable = '1') and (r.rdTimer = 0) and (v.axiReadMaster.arvalid = '0') then -- Arm the timer diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd index 52026162d7..d6912882e1 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd @@ -7,11 +7,11 @@ -- Designed specifically for Xilinx 7 series FPGAs ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to -- the terms contained in the LICENSE.txt file. ------------------------------------------------------------------------------- @@ -64,7 +64,7 @@ architecture rtl of Ad9249Deserializer is ------------------------------------------------------------------------------------------------- -- ADC Readout Clocked Registers ------------------------------------------------------------------------------------------------- - + constant CASCADE_C : string := ite(IDELAY_CASCADE_G, "MASTER", "NONE"); @@ -82,7 +82,7 @@ architecture rtl of Ad9249Deserializer is -- iserdes signal signal masterData : slv(7 downto 0); signal iAdcData : slv(13 downto 0); - + attribute keep of sData_i : signal is "true"; begin @@ -106,7 +106,7 @@ begin -- Optionally invert the pad input sData_i <= sDataPadP when ADC_INVERT_CH_G = '0' else sDataPadN; ---------------------------------------------------------------------------- - -- idelay3 + -- idelay3 ---------------------------------------------------------------------------- U_IDELAYE3_0 : entity surf.Idelaye3Wrapper generic map ( @@ -139,11 +139,11 @@ begin LOAD => loadDelay, -- 1-bit input: Load DELAY_VALUE input RST => dRstDiv4 -- 1-bit input: Asynchronous Reset to the DELAY_VALUE ); - + G_IdelayCascade: if IDELAY_CASCADE_G = true generate signal masterCntValue : slv(9 downto 0); begin - + U_ODELAYE3_0 : entity surf.Odelaye3Wrapper generic map ( CASCADE => "SLAVE_END", -- Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE) @@ -156,29 +156,29 @@ begin UPDATE_MODE => "ASYNC") -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC) port map ( CASC_IN => cascOut, -- 1-bit input: Cascade delay input from slave IDELAY CASCADE_OUT - CASC_OUT => open, -- 1-bit output: Cascade delay output to IDELAY input cascade - CASC_RETURN => '0', -- 1-bit input: Cascade delay returning from slave IDELAY DATAOUT + CASC_OUT => open, -- 1-bit output: Cascade delay output to IDELAY input cascade + CASC_RETURN => '0', -- 1-bit input: Cascade delay returning from slave IDELAY DATAOUT ODATAIN => '0', -- 1-bit input: Data input - DATAOUT => cascRet, -- 1-bit output: Delayed data from ODATAIN input port - CLK => dClkDiv4, -- 1-bit input: Clock input - EN_VTC => '0', -- 1-bit input: Keep delay constant over VT + DATAOUT => cascRet, -- 1-bit output: Delayed data from ODATAIN input port + CLK => dClkDiv4, -- 1-bit input: Clock input + EN_VTC => '0', -- 1-bit input: Keep delay constant over VT INC => '0', -- 1-bit input: Increment / Decrement tap delay input - CE => '0', -- 1-bit input: Active high enable increment/decrement input - LOAD => loadDelay, -- 1-bit input: Load DELAY_VALUE input - RST => dRstDiv4, -- 1-bit input: Asynchronous Reset to the DELAY_VALUE + CE => '0', -- 1-bit input: Active high enable increment/decrement input + LOAD => loadDelay, -- 1-bit input: Load DELAY_VALUE input + RST => dRstDiv4, -- 1-bit input: Asynchronous Reset to the DELAY_VALUE CNTVALUEIN => delay, -- 9-bit input: Counter value input - CNTVALUEOUT => masterCntValue2); -- 9-bit output: Counter value output - + CNTVALUEOUT => masterCntValue2); -- 9-bit output: Counter value output + masterCntValue <= resize(masterCntValue1, 10, '0') + masterCntValue2; delayValueOut <= masterCntValue(9 downto 1); - + end generate; G_IdelayNoCascade: if IDELAY_CASCADE_G = false generate delayValueOut <= masterCntValue1; masterCntValue2 <= (others=>'0'); cascRet <= '0'; end generate; - + ---------------------------------------------------------------------------- -- iserdes3 ---------------------------------------------------------------------------- @@ -204,9 +204,9 @@ begin FIFO_RD_EN => '1', -- 1-bit input: Enables reading the FIFO when asserted RST => dRstDiv4 -- 1-bit input: Asynchronous Reset ); - - - + + + U_Gearbox : entity surf.Gearbox generic map ( TPD_G => TPD_G, @@ -227,6 +227,6 @@ begin ); adcData <= iAdcData when BIT_REV_G = '0' else bitReverse(iAdcData(6 downto 0)) & bitReverse(iAdcData(13 downto 7)); - + end rtl; diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd index 9b3014f07a..9290f6a143 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd @@ -7,11 +7,11 @@ -- Designed specifically for Xilinx Ultrascale series FPGAs ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to -- the terms contained in the LICENSE.txt file. ------------------------------------------------------------------------------- @@ -55,7 +55,7 @@ entity Ad9249ReadoutGroup is -- Reset for adc deserializer (axilClk domain) adcClkRst : in sl; - + -- clocks must be provided with USE_MMCME_G = false -- this option is necessary if there is many ADCs -- one external MMCM should be instantiated to be used with all Ad9249ReadoutGroups @@ -143,7 +143,7 @@ architecture rtl of Ad9249ReadoutGroup is signal adcR : AdcRegType := ADC_REG_INIT_C; signal adcRin : AdcRegType; - + signal adcDataValid : slv(NUM_CHANNELS_G-1 downto 0); signal adcFrameValid : sl; @@ -168,12 +168,12 @@ architecture rtl of Ad9249ReadoutGroup is signal debugDataValid : slv(NUM_CHANNELS_G-1 downto 0); signal debugData : slv16Array(NUM_CHANNELS_G-1 downto 0); - + signal frameDelay : slv(8 downto 0); signal frameDelaySet : sl; - + signal invertSync : sl; - + attribute KEEP_HIERARCHY : string; attribute KEEP_HIERARCHY of AdcClk_I_Ibufds : label is "TRUE"; attribute dont_touch : string; @@ -224,7 +224,7 @@ begin rst => axilRst, dataIn => adcFrame, dataOut => adcFrameSync); - + Synchronizer_2 : entity surf.Synchronizer generic map ( TPD_G => TPD_G, @@ -282,7 +282,7 @@ begin axiSlaveRegisterR(axilEp, X"30", 16, lockedSync); axiSlaveRegisterR(axilEp, X"34", 0, adcFrameSync); axiSlaveRegister(axilEp, X"38", 0, v.lockedCountRst); - + axiSlaveRegister(axilEp, X"40", 0, v.invert); -- Debug registers. Output the last 2 words received @@ -294,7 +294,7 @@ begin axiSlaveRegister(axilEp, X"A0", 0, v.freezeDebug); axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C); - + if adcClkRst = '1' then v.lockedCountRst := '1'; end if; @@ -332,8 +332,8 @@ begin ------------------------------------------------------------------------------------------------- G_MMCM : if USE_MMCME_G = true generate - - + + ------------------------------------------ -- Generate clocks from ADC incoming clock ------------------------------------------ @@ -367,16 +367,16 @@ begin rstOut(1) => adcBitRstDiv4, locked => open ); - + end generate G_MMCM; - + G_NO_MMCM : if USE_MMCME_G = false generate - + adcBitClk <= adcBitClkIn; adcBitClkDiv4 <= adcBitClkDiv4In; adcBitRst <= adcBitRstIn; adcBitRstDiv4 <= adcBitRstDiv4In; - + end generate G_NO_MMCM; ------------------------------------------------------------------------------------------------- @@ -405,7 +405,7 @@ begin adcData => adcFrame, adcValid => adcFrameValid ); - + U_FrmDlyFifo : entity surf.SynchronizerFifo generic map ( TPD_G => TPD_G, @@ -422,7 +422,7 @@ begin rd_en => '1', valid => frameDelaySet, dout => frameDelay); - + -------------------------------- -- Data Input, 8 channels -------------------------------- @@ -454,8 +454,8 @@ begin adcData => adcData(i), adcValid => adcDataValid(i) ); - - + + U_DataDlyFifo : entity surf.SynchronizerFifo generic map ( TPD_G => TPD_G, @@ -472,7 +472,7 @@ begin rd_en => '1', valid => dataDelaySet(i), dout => dataDelay(i)); - + end generate; ------------------------------------------------------------------------------------------------- @@ -540,7 +540,7 @@ begin end if; end if; end process adcSeq; - + RstSync_1 : entity surf.RstSync generic map ( TPD_G => TPD_G @@ -553,8 +553,8 @@ begin -- synchronize data cross-clocks G_FIFO_SYNC : for i in NUM_CHANNELS_G-1 downto 0 generate - - + + U_DataFifo : entity surf.SynchronizerFifo generic map ( TPD_G => TPD_G, @@ -570,11 +570,11 @@ begin valid => fifoDataValid(i), dout => adcStreams(i).tdata(15 downto 0) ); - + fifoDataRdEn(i) <= adcReady(i) and fifoDataValid(i); adcStreams(i).tDest <= toSlv(i, 8); adcStreams(i).tValid <= fifoDataValid(i); - + U_DataFifoDebug : entity surf.SynchronizerFifo generic map ( TPD_G => TPD_G, @@ -590,9 +590,9 @@ begin valid => debugDataValid(i), dout => debugData(i) ); - + end generate; - + end rtl; From 51318e3d0c6a990efcadbb560967d25f2c37f27b Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 11 Aug 2020 11:16:24 -0700 Subject: [PATCH 18/36] adding _AxiRateGen.py --- axi/axi4/rtl/AxiRateGen.vhd | 5 + python/surf/axi/_AxiRateGen.py | 179 +++++++++++++++++++++++++++++++++ python/surf/axi/__init__.py | 1 + 3 files changed, 185 insertions(+) create mode 100644 python/surf/axi/_AxiRateGen.py diff --git a/axi/axi4/rtl/AxiRateGen.vhd b/axi/axi4/rtl/AxiRateGen.vhd index 0b1045ce47..57a68256d0 100644 --- a/axi/axi4/rtl/AxiRateGen.vhd +++ b/axi/axi4/rtl/AxiRateGen.vhd @@ -167,6 +167,11 @@ begin axiSlaveRegister(axilEp, x"40", 0, v.awcache); axiSlaveRegister(axilEp, x"44", 0, v.arcache); + axiSlaveRegisterR(axilEp, x"80", 0, toSlv(AXI_CONFIG_G.ADDR_WIDTH_C, 8)); + axiSlaveRegisterR(axilEp, x"80", 8, toSlv(AXI_CONFIG_G.DATA_BYTES_C, 8)); + axiSlaveRegisterR(axilEp, x"80", 16, toSlv(AXI_CONFIG_G.ID_BITS_C, 8)); + axiSlaveRegisterR(axilEp, x"80", 24, toSlv(AXI_CONFIG_G.LEN_BITS_C, 8)); + -- Close the transaction axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C); diff --git a/python/surf/axi/_AxiRateGen.py b/python/surf/axi/_AxiRateGen.py new file mode 100644 index 0000000000..9b9247d786 --- /dev/null +++ b/python/surf/axi/_AxiRateGen.py @@ -0,0 +1,179 @@ +#----------------------------------------------------------------------------- +# This file is part of the 'SLAC Firmware Standard Library'. It is subject to +# the license terms in the LICENSE.txt file found in the top-level directory +# of this distribution and at: +# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +# No part of the 'SLAC Firmware Standard Library', including this file, may be +# copied, modified, propagated, or distributed except according to the terms +# contained in the LICENSE.txt file. +#----------------------------------------------------------------------------- + +import pyrogue as pr + +class AxiRateGen(pr.Device): + def __init__(self, **kwargs): + super().__init__(**kwargs) + + self.add(pr.RemoteVariable( + name = 'WriteEnable', + offset = 0x00, + bitSize = 1, + base = pr.Bool, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'ReadEnable', + offset = 0x04, + bitSize = 1, + base = pr.Bool, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'WriteSize', + description = 'Number of bytes for transaction (zero inclusive)', + offset = 0x10, + bitSize = 12, + mode = 'RW', + units = 'Bytes', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'ReadSize', + description = 'Number of bytes for transaction (zero inclusive)', + offset = 0x14, + bitSize = 12, + mode = 'RW', + units = 'Bytes', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'WriteTimerConfig', + description = 'Minimum number clock cycles between transaction (zero inclusive)', + offset = 0x20, + bitSize = 32, + mode = 'RW', + units = 'Clock Cycles', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'ReadTimerConfig', + description = 'Minimum number clock cycles between transaction (zero inclusive)', + offset = 0x24, + bitSize = 32, + mode = 'RW', + units = 'Clock Cycles', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'awburst', + offset = 0x30, + bitSize = 2, + mode = 'RW', + enum = { + 0 : "FIXED", + 1 : "INCR", + 2 : "WRAP", + 3 : "Reserved", + }, + )) + + self.add(pr.RemoteVariable( + name = 'arburst', + offset = 0x34, + bitSize = 2, + mode = 'RW', + enum = { + 0 : "FIXED", + 1 : "INCR", + 2 : "WRAP", + 3 : "Reserved", + }, + )) + + self.add(pr.RemoteVariable( + name = 'awcache', + offset = 0x40, + bitSize = 4, + mode = 'RW', + enum = { + 0b0000 : "Device Non-bufferable", + 0b0001 : "Device Bufferable", + 0b0010 : "Normal Non-cacheable Non-bufferable", + 0b0011 : "Normal Non-cacheable Bufferable", + 0b0110 : "Write-through No-allocate", + 0b0110 : "Write-through Read-allocate", + 0b1010 : "Write-through Write-allocate", + 0b1110 : "Write-through Read and Write-allocate", + 0b0111 : "Write-back No-allocate", + 0b0111 : "Write-back Read-allocate", + 0b1011 : "Write-back Write-allocate", + 0b1111 : "Write-back Read and Write-allocate", + }, + )) + + self.add(pr.RemoteVariable( + name = 'arcache', + offset = 0x44, + bitSize = 4, + mode = 'RW', + enum = { + 0b0000 : "Device Non-bufferable", + 0b0001 : "Device Bufferable", + 0b0010 : "Normal Non-cacheable Non-bufferable", + 0b0011 : "Normal Non-cacheable Bufferable", + 0b1010 : "Write-through No-allocate", + 0b0110 : "Write-through Read-allocate", + 0b1010 : "Write-through Write-allocate", + 0b1110 : "Write-through Read and Write-allocate", + 0b1011 : "Write-back No-allocate", + 0b0111 : "Write-back Read-allocate", + 0b1011 : "Write-back Write-allocate", + 0b1111 : "Write-back Read and Write-allocate", + }, + )) + + self.add(pr.RemoteVariable( + name = 'ADDR_WIDTH_C', + description = 'AXI_CONFIG_G.ADDR_WIDTH_C', + offset = 0x80, + bitSize = 8, + bitOffset = 0, + mode = 'RO', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'DATA_BYTES_C', + description = 'AXI_CONFIG_G.DATA_BYTES_C', + offset = 0x80, + bitSize = 8, + bitOffset = 8, + mode = 'RO', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'ID_BITS_C', + description = 'AXI_CONFIG_G.ID_BITS_C', + offset = 0x80, + bitSize = 8, + bitOffset = 16, + mode = 'RO', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'LEN_BITS_C', + description = 'AXI_CONFIG_G.LEN_BITS_C', + offset = 0x80, + bitSize = 8, + bitOffset = 24, + mode = 'RO', + disp = '{:d}', + )) diff --git a/python/surf/axi/__init__.py b/python/surf/axi/__init__.py index 3e60fe6234..c7a61b82e2 100644 --- a/python/surf/axi/__init__.py +++ b/python/surf/axi/__init__.py @@ -13,6 +13,7 @@ from surf.axi._AxiStreamDmaRingWrite import * from surf.axi._AxiStreamMonAxiL import * from surf.axi._AxiMonAxiL import * +from surf.axi._AxiRateGen import * from surf.axi._AxiVersion import * from surf.axi._AxiVersionLegacy import * from surf.axi._AxiStreamDmaFifo import * From 9a42f83cbefca56f268c20eeb0edbe47a7ec4db3 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 11 Aug 2020 11:30:08 -0700 Subject: [PATCH 19/36] flake8 fix --- python/surf/axi/_AxiRateGen.py | 56 +++++++++++++++++----------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/python/surf/axi/_AxiRateGen.py b/python/surf/axi/_AxiRateGen.py index 9b9247d786..243db284c8 100644 --- a/python/surf/axi/_AxiRateGen.py +++ b/python/surf/axi/_AxiRateGen.py @@ -101,20 +101,20 @@ def __init__(self, **kwargs): offset = 0x40, bitSize = 4, mode = 'RW', - enum = { - 0b0000 : "Device Non-bufferable", - 0b0001 : "Device Bufferable", - 0b0010 : "Normal Non-cacheable Non-bufferable", - 0b0011 : "Normal Non-cacheable Bufferable", - 0b0110 : "Write-through No-allocate", - 0b0110 : "Write-through Read-allocate", - 0b1010 : "Write-through Write-allocate", - 0b1110 : "Write-through Read and Write-allocate", - 0b0111 : "Write-back No-allocate", - 0b0111 : "Write-back Read-allocate", - 0b1011 : "Write-back Write-allocate", - 0b1111 : "Write-back Read and Write-allocate", - }, + # enum = { + # 0b0000 : "Device_Non-bufferable", + # 0b0001 : "Device_Bufferable", + # 0b0010 : "Normal_Non-cacheable_Non-bufferable", + # 0b0011 : "Normal_Non-cacheable_Bufferable", + # 0b0110 : "Write-through_No-allocate", + # 0b0110 : "Write-through_Read-allocate", + # 0b1010 : "Write-through_Write-allocate", + # 0b1110 : "Write-through_Read_and_Write-allocate", + # 0b0111 : "Write-back_No-allocate", + # 0b0111 : "Write-back_Read-allocate", + # 0b1011 : "Write-back_Write-allocate", + # 0b1111 : "Write-back_Read_and_Write-allocate", + # }, )) self.add(pr.RemoteVariable( @@ -122,20 +122,20 @@ def __init__(self, **kwargs): offset = 0x44, bitSize = 4, mode = 'RW', - enum = { - 0b0000 : "Device Non-bufferable", - 0b0001 : "Device Bufferable", - 0b0010 : "Normal Non-cacheable Non-bufferable", - 0b0011 : "Normal Non-cacheable Bufferable", - 0b1010 : "Write-through No-allocate", - 0b0110 : "Write-through Read-allocate", - 0b1010 : "Write-through Write-allocate", - 0b1110 : "Write-through Read and Write-allocate", - 0b1011 : "Write-back No-allocate", - 0b0111 : "Write-back Read-allocate", - 0b1011 : "Write-back Write-allocate", - 0b1111 : "Write-back Read and Write-allocate", - }, + # enum = { + # 0b0000 : "Device_Non-bufferable", + # 0b0001 : "Device_Bufferable", + # 0b0010 : "Normal_Non-cacheable_Non-bufferable", + # 0b0011 : "Normal_Non-cacheable_Bufferable", + # 0b1010 : "Write-through_No-allocate", + # 0b0110 : "Write-through_Read-allocate", + # 0b1010 : "Write-through_Write-allocate", + # 0b1110 : "Write-through_Read_and_Write-allocate", + # 0b1011 : "Write-back_No-allocate", + # 0b0111 : "Write-back_Read-allocate", + # 0b1011 : "Write-back_Write-allocate", + # 0b1111 : "Write-back_Read_and_Write-allocate", + # }, )) self.add(pr.RemoteVariable( From ec5512956aa782feb9c1298be6078663ce4ce32e Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 14 Aug 2020 16:10:10 -0700 Subject: [PATCH 20/36] flake8 fix --- python/surf/axi/_AxiRateGen.py | 52 ++++++++++++++++------------------ 1 file changed, 24 insertions(+), 28 deletions(-) diff --git a/python/surf/axi/_AxiRateGen.py b/python/surf/axi/_AxiRateGen.py index 243db284c8..c9b029a823 100644 --- a/python/surf/axi/_AxiRateGen.py +++ b/python/surf/axi/_AxiRateGen.py @@ -101,20 +101,18 @@ def __init__(self, **kwargs): offset = 0x40, bitSize = 4, mode = 'RW', - # enum = { - # 0b0000 : "Device_Non-bufferable", - # 0b0001 : "Device_Bufferable", - # 0b0010 : "Normal_Non-cacheable_Non-bufferable", - # 0b0011 : "Normal_Non-cacheable_Bufferable", - # 0b0110 : "Write-through_No-allocate", - # 0b0110 : "Write-through_Read-allocate", - # 0b1010 : "Write-through_Write-allocate", - # 0b1110 : "Write-through_Read_and_Write-allocate", - # 0b0111 : "Write-back_No-allocate", - # 0b0111 : "Write-back_Read-allocate", - # 0b1011 : "Write-back_Write-allocate", - # 0b1111 : "Write-back_Read_and_Write-allocate", - # }, + enum = { + 0b0000 : "Device_Non-bufferable", + 0b0001 : "Device_Bufferable", + 0b0010 : "Normal_Non-cacheable_Non-bufferable", + 0b0011 : "Normal_Non-cacheable_Bufferable", + 0b0110 : "Write-through_Read-allocate", + 0b1010 : "Write-through_Write-allocate", + 0b1110 : "Write-through_Read_and_Write-allocate", + 0b0111 : "Write-back_Read-allocate", + 0b1011 : "Write-back_Write-allocate", + 0b1111 : "Write-back_Read_and_Write-allocate", + }, )) self.add(pr.RemoteVariable( @@ -122,20 +120,18 @@ def __init__(self, **kwargs): offset = 0x44, bitSize = 4, mode = 'RW', - # enum = { - # 0b0000 : "Device_Non-bufferable", - # 0b0001 : "Device_Bufferable", - # 0b0010 : "Normal_Non-cacheable_Non-bufferable", - # 0b0011 : "Normal_Non-cacheable_Bufferable", - # 0b1010 : "Write-through_No-allocate", - # 0b0110 : "Write-through_Read-allocate", - # 0b1010 : "Write-through_Write-allocate", - # 0b1110 : "Write-through_Read_and_Write-allocate", - # 0b1011 : "Write-back_No-allocate", - # 0b0111 : "Write-back_Read-allocate", - # 0b1011 : "Write-back_Write-allocate", - # 0b1111 : "Write-back_Read_and_Write-allocate", - # }, + enum = { + 0b0000 : "Device_Non-bufferable", + 0b0001 : "Device_Bufferable", + 0b0010 : "Normal_Non-cacheable_Non-bufferable", + 0b0011 : "Normal_Non-cacheable_Bufferable", + 0b0110 : "Write-through_Read-allocate", + 0b1010 : "Write-through_Write-allocate", + 0b1110 : "Write-through_Read_and_Write-allocate", + 0b0111 : "Write-back_Read-allocate", + 0b1011 : "Write-back_Write-allocate", + 0b1111 : "Write-back_Read_and_Write-allocate", + }, )) self.add(pr.RemoteVariable( From c3271d52ae1fe7df502704ca065f011fc7758e84 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 14 Aug 2020 16:38:33 -0700 Subject: [PATCH 21/36] bug fix for super wide AXI4 memory bus and bypassing AxiStreamShift --- axi/dma/rtl/v1/AxiStreamDmaRead.vhd | 4 +++- axi/dma/rtl/v1/AxiStreamDmaWrite.vhd | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/axi/dma/rtl/v1/AxiStreamDmaRead.vhd b/axi/dma/rtl/v1/AxiStreamDmaRead.vhd index 6ed6a72bfd..38ca930949 100644 --- a/axi/dma/rtl/v1/AxiStreamDmaRead.vhd +++ b/axi/dma/rtl/v1/AxiStreamDmaRead.vhd @@ -200,7 +200,9 @@ begin -- Align shift and address to transfer size if (DATA_BYTES_C /= 1) then v.dmaReq.address(ADDR_LSB_C-1 downto 0) := (others => '0'); - v.shift(ADDR_LSB_C-1 downto 0) := dmaReq.address(ADDR_LSB_C-1 downto 0); + if (BYP_SHIFT_G = false) then + v.shift(ADDR_LSB_C-1 downto 0) := dmaReq.address(ADDR_LSB_C-1 downto 0); + end if; end if; -- Check for DMA request if (dmaReq.request = '1') then diff --git a/axi/dma/rtl/v1/AxiStreamDmaWrite.vhd b/axi/dma/rtl/v1/AxiStreamDmaWrite.vhd index fed27c13c0..a6b39cb756 100644 --- a/axi/dma/rtl/v1/AxiStreamDmaWrite.vhd +++ b/axi/dma/rtl/v1/AxiStreamDmaWrite.vhd @@ -283,7 +283,9 @@ begin -- Align shift and address to transfer size if (DATA_BYTES_C /= 1) then v.dmaReq.address(ADDR_LSB_C-1 downto 0) := (others => '0'); - v.shift(ADDR_LSB_C-1 downto 0) := dmaReq.address(ADDR_LSB_C-1 downto 0); + if (BYP_SHIFT_G = false) then + v.shift(ADDR_LSB_C-1 downto 0) := dmaReq.address(ADDR_LSB_C-1 downto 0); + end if; end if; -- Check for DMA request if (dmaReq.request = '1') then From 838e045a5616fc17e950f12c06838e0ab56d3200 Mon Sep 17 00:00:00 2001 From: Jesus Vasquez Date: Thu, 20 Aug 2020 13:26:33 -0700 Subject: [PATCH 22/36] Add NcoSync command --- yaml/Dac38J84.yaml | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/yaml/Dac38J84.yaml b/yaml/Dac38J84.yaml index 298756b166..a5f1f63215 100644 --- a/yaml/Dac38J84.yaml +++ b/yaml/Dac38J84.yaml @@ -351,3 +351,33 @@ Dac38J84: &Dac38J84 - entry: EnableTx value: 0x1 ######################################################### + NcoSync: + class: SequenceCommand + at: + offset: 0x0 + description: Special DAC Init procedure to sync NCO + sequence: + - entry: EnableTx + value: 0x0 + - entry: usleep + value: 10000 + - entry: InitJesd + value: 0x1 + - entry: usleep + value: 10000 + - entry: JesdRstN + value: 0x0 + - entry: usleep + value: 10000 + - entry: JesdRstN + value: 0x1 + - entry: usleep + value: 10000 + - entry: InitJesd + value: 0x0 + - entry: usleep + value: 10000 + - entry: EnableTx + value: 0x1 + - entry: usleep + value: 10000 From f1714c5598ef1594da9914e02f72476aca7e60ed Mon Sep 17 00:00:00 2001 From: Jesus Vasquez Date: Thu, 20 Aug 2020 13:29:09 -0700 Subject: [PATCH 23/36] Update InitDac Command sequence --- yaml/Dac38J84.yaml | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/yaml/Dac38J84.yaml b/yaml/Dac38J84.yaml index a5f1f63215..44c6a55627 100644 --- a/yaml/Dac38J84.yaml +++ b/yaml/Dac38J84.yaml @@ -314,38 +314,36 @@ Dac38J84: &Dac38J84 # Clear alarms - entry: ClearAlarms - value: 0 + value: 0x1 - entry: DacReg[59] - value: 0x1800 + value: 0x00 - entry: DacReg[37] - value: 0x4000 + value: 0x00 - entry: DacReg[60] value: 0x228 - - entry: DacReg[60] - value: 0x28 - entry: DacReg[62] value: 0x108 - entry: DacReg[76] - value: 0x1F03 + value: 0x1F01 - entry: DacReg[77] - value: 0x300 + value: 0x100 - entry: DacReg[75] - value: 0x801 + value: 0x501 - entry: DacReg[77] - value: 0x300 + value: 0x100 - entry: DacReg[78] value: 0xF2F - entry: DacReg[0] - value: 0x218 + value: 0x018 - entry: DacReg[74] - value: 0xF1E + value: 0x83E - entry: DacReg[74] - value: 0xF1E + value: 0x83E - entry: DacReg[74] - value: 0xF1F + value: 0x83F - entry: DacReg[74] - value: 0xF01 + value: 0x821 # Enable TX - entry: EnableTx From 81d4552e954fd6c5cbfaad97ec18564c07e349d6 Mon Sep 17 00:00:00 2001 From: Jesus Vasquez Date: Thu, 20 Aug 2020 13:30:10 -0700 Subject: [PATCH 24/36] Fit formatting --- yaml/Dac38J84.yaml | 54 +++++++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/yaml/Dac38J84.yaml b/yaml/Dac38J84.yaml index 44c6a55627..27428c0010 100644 --- a/yaml/Dac38J84.yaml +++ b/yaml/Dac38J84.yaml @@ -350,32 +350,32 @@ Dac38J84: &Dac38J84 value: 0x1 ######################################################### NcoSync: - class: SequenceCommand + class: SequenceCommand at: - offset: 0x0 - description: Special DAC Init procedure to sync NCO + offset: 0x0 + description: Special DAC Init procedure to sync NCO sequence: - - entry: EnableTx - value: 0x0 - - entry: usleep - value: 10000 - - entry: InitJesd - value: 0x1 - - entry: usleep - value: 10000 - - entry: JesdRstN - value: 0x0 - - entry: usleep - value: 10000 - - entry: JesdRstN - value: 0x1 - - entry: usleep - value: 10000 - - entry: InitJesd - value: 0x0 - - entry: usleep - value: 10000 - - entry: EnableTx - value: 0x1 - - entry: usleep - value: 10000 + - entry: EnableTx + value: 0x0 + - entry: usleep + value: 10000 + - entry: InitJesd + value: 0x1 + - entry: usleep + value: 10000 + - entry: JesdRstN + value: 0x0 + - entry: usleep + value: 10000 + - entry: JesdRstN + value: 0x1 + - entry: usleep + value: 10000 + - entry: InitJesd + value: 0x0 + - entry: usleep + value: 10000 + - entry: EnableTx + value: 0x1 + - entry: usleep + value: 10000 From 9ebbde25658585580d9d17e798882353a41eda15 Mon Sep 17 00:00:00 2001 From: Jesus Vasquez Date: Thu, 20 Aug 2020 13:35:05 -0700 Subject: [PATCH 25/36] Restore original InitDac command. This sequence is now handled by the C++ driver --- yaml/Dac38J84.yaml | 37 ++++++------------------------------- 1 file changed, 6 insertions(+), 31 deletions(-) diff --git a/yaml/Dac38J84.yaml b/yaml/Dac38J84.yaml index 27428c0010..fbdf095daf 100644 --- a/yaml/Dac38J84.yaml +++ b/yaml/Dac38J84.yaml @@ -312,38 +312,13 @@ Dac38J84: &Dac38J84 - entry: EnableTx value: 0x0 - # Clear alarms - - entry: ClearAlarms - value: 0x1 + # Disable and initialize JESD + - entry: InitJesd + value: 0x1E - - entry: DacReg[59] - value: 0x00 - - entry: DacReg[37] - value: 0x00 - - entry: DacReg[60] - value: 0x228 - - entry: DacReg[62] - value: 0x108 - - entry: DacReg[76] - value: 0x1F01 - - entry: DacReg[77] - value: 0x100 - - entry: DacReg[75] - value: 0x501 - - entry: DacReg[77] - value: 0x100 - - entry: DacReg[78] - value: 0xF2F - - entry: DacReg[0] - value: 0x018 - - entry: DacReg[74] - value: 0x83E - - entry: DacReg[74] - value: 0x83E - - entry: DacReg[74] - value: 0x83F - - entry: DacReg[74] - value: 0x821 + # Enable JESD + - entry: InitJesd + value: 0x01 # Enable TX - entry: EnableTx From 76a9d0bb1e4fc02269404ecc9b35986031646483 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 20 Aug 2020 13:40:53 -0700 Subject: [PATCH 26/36] similiar to the XPM FIFOs, adding TPD_G output delay to XPM RAMs --- base/ram/xilinx/SimpleDualPortRamXpm.vhd | 7 +++++-- base/ram/xilinx/TrueDualPortRamXpm.vhd | 11 ++++++++--- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/base/ram/xilinx/SimpleDualPortRamXpm.vhd b/base/ram/xilinx/SimpleDualPortRamXpm.vhd index feae1a1530..656bad00df 100644 --- a/base/ram/xilinx/SimpleDualPortRamXpm.vhd +++ b/base/ram/xilinx/SimpleDualPortRamXpm.vhd @@ -17,7 +17,6 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; - library surf; use surf.StdRtlPkg.all; @@ -57,6 +56,8 @@ architecture rtl of SimpleDualPortRamXpm is signal resetB : sl; + signal doutb_xpm : slv(DATA_WIDTH_G-1 downto 0); + begin U_RAM : xpm_memory_sdpram @@ -91,7 +92,7 @@ begin enb => enb, clkb => clkb, addrb => addrb, - doutb => doutb, + doutb => doutb_xpm, regceb => regceb, -- Misc.Interface rstb => resetB, @@ -103,4 +104,6 @@ begin resetB <= rstb when(RST_POLARITY_G = '1') else not(rstb); + doutb <= doutb_xpm after TPD_G; + end rtl; diff --git a/base/ram/xilinx/TrueDualPortRamXpm.vhd b/base/ram/xilinx/TrueDualPortRamXpm.vhd index 2607a935a3..eea54451d5 100644 --- a/base/ram/xilinx/TrueDualPortRamXpm.vhd +++ b/base/ram/xilinx/TrueDualPortRamXpm.vhd @@ -17,7 +17,6 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; - library surf; use surf.StdRtlPkg.all; @@ -63,6 +62,9 @@ architecture rtl of TrueDualPortRamXpm is signal resetA : sl; signal resetB : sl; + signal douta_xpm : slv(DATA_WIDTH_G-1 downto 0); + signal doutb_xpm : slv(DATA_WIDTH_G-1 downto 0); + begin U_RAM : xpm_memory_tdpram @@ -100,7 +102,7 @@ begin rsta => resetA, addra => addra, dina => dina, - douta => douta, + douta => douta_xpm, -- Port B clkb => clkb, enb => enb, @@ -109,7 +111,7 @@ begin rstb => resetB, addrb => addrb, dinb => dinb, - doutb => doutb, + doutb => doutb_xpm, -- Misc.Interface dbiterra => open, dbiterrb => open, @@ -124,4 +126,7 @@ begin resetA <= rsta when(RST_POLARITY_G = '1') else not(rsta); resetB <= rstb when(RST_POLARITY_G = '1') else not(rstb); + douta <= douta_xpm after TPD_G; + doutb <= doutb_xpm after TPD_G; + end rtl; From 0ec72e9b23b348ccce2175fa4752f8a1fe567f82 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 21 Aug 2020 10:22:46 -0700 Subject: [PATCH 27/36] adding dacReady_o to JESD TX --- protocols/jesd204b/rtl/Jesd204bTx.vhd | 4 +++- protocols/jesd204b/rtl/JesdTxLane.vhd | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/protocols/jesd204b/rtl/Jesd204bTx.vhd b/protocols/jesd204b/rtl/Jesd204bTx.vhd index 6a74d3eb36..d02810971b 100644 --- a/protocols/jesd204b/rtl/Jesd204bTx.vhd +++ b/protocols/jesd204b/rtl/Jesd204bTx.vhd @@ -72,7 +72,8 @@ entity Jesd204bTx is nSync_i : in slv(L_G-1 downto 0); -- External sample data input - extSampleDataArray_i : in sampleDataArray(L_G-1 downto 0); + extSampleDataArray_i : in sampleDataArray(L_G-1 downto 0); + dacReady_o : out slv(L_G-1 downto 0); -- GT is ready to transmit data after reset gtTxReset_o : out slv(L_G-1 downto 0); @@ -342,6 +343,7 @@ begin gtTxReady_i => gtTxReady_i(i), sysRef_i => s_sysrefRe(i), status_o => s_statusTxArr(i), -- To AXI lite + dacReady_o => dacReady_o(i), sampleData_i => s_sampleDataArr(i), r_jesdGtTx => s_jesdGtTxArr(i)); diff --git a/protocols/jesd204b/rtl/JesdTxLane.vhd b/protocols/jesd204b/rtl/JesdTxLane.vhd index 5ac3210c72..7ce8cad191 100644 --- a/protocols/jesd204b/rtl/JesdTxLane.vhd +++ b/protocols/jesd204b/rtl/JesdTxLane.vhd @@ -79,6 +79,7 @@ entity JesdTxLane is -- Status of the transmitter status_o : out slv(TX_STAT_WIDTH_C-1 downto 0); + dacReady_o : out sl; -- Sample data input sampleData_i : in slv((GT_WORD_SIZE_C*8)-1 downto 0); @@ -185,6 +186,7 @@ begin s_commaDataMux when others; -- Output assignment - status_o <= s_refDetected & enable_i & nSync_i & s_ila & s_dataValid & gtTxReady_i; + status_o <= s_refDetected & enable_i & nSync_i & s_ila & s_dataValid & gtTxReady_i; + dacReady_o <= s_dataValid; -------------------------------------------- end rtl; From 6ff145c530873ceedc4e0a4cb3a6dd462e1879aa Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 24 Aug 2020 14:32:44 -0700 Subject: [PATCH 28/36] adding AxiStreamGearbox.vhd --- axi/axi-stream/rtl/AxiStreamGearbox.vhd | 337 ++++++++++++++++++++++++ 1 file changed, 337 insertions(+) create mode 100644 axi/axi-stream/rtl/AxiStreamGearbox.vhd diff --git a/axi/axi-stream/rtl/AxiStreamGearbox.vhd b/axi/axi-stream/rtl/AxiStreamGearbox.vhd new file mode 100644 index 0000000000..3f5b151a50 --- /dev/null +++ b/axi/axi-stream/rtl/AxiStreamGearbox.vhd @@ -0,0 +1,337 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Block to resize AXI Streams. Re-sizing is always little endian. +-- Resizer should not be used when interleaving tDests +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity AxiStreamGearbox is + generic ( + -- General Configurations + TPD_G : time := 1 ns; + READY_EN_G : boolean := true; + PIPE_STAGES_G : natural := 0; + SIDE_BAND_WIDTH_G : positive := 1; -- General purpose sideband + -- AXI Stream Port Configurations + SLAVE_AXI_CONFIG_G : AxiStreamConfigType; + MASTER_AXI_CONFIG_G : AxiStreamConfigType); + port ( + -- Clock and reset + axisClk : in sl; + axisRst : in sl; + -- Slave Port + sAxisMaster : in AxiStreamMasterType; + sSideBand : in slv(SIDE_BAND_WIDTH_G-1 downto 0) := (others => '0'); + sAxisSlave : out AxiStreamSlaveType; + -- Master Port + mAxisMaster : out AxiStreamMasterType; + mSideBand : out slv(SIDE_BAND_WIDTH_G-1 downto 0); + mAxisSlave : in AxiStreamSlaveType); +end AxiStreamGearbox; + +architecture rtl of AxiStreamGearbox is + + constant SLV_BYTES_C : positive := SLAVE_AXI_CONFIG_G.TDATA_BYTES_C; + constant MST_BYTES_C : positive := MASTER_AXI_CONFIG_G.TDATA_BYTES_C; + + constant SLV_USER_C : positive := ite(SLAVE_AXI_CONFIG_G.TUSER_BITS_C /= 0, SLAVE_AXI_CONFIG_G.TUSER_BITS_C, 1); + constant MST_USER_C : positive := ite(MASTER_AXI_CONFIG_G.TUSER_BITS_C /= 0, MASTER_AXI_CONFIG_G.TUSER_BITS_C, 1); + + constant WORD_MULTIPLE_C : boolean := (SLV_BYTES_C >= MST_BYTES_C and SLV_BYTES_C mod MST_BYTES_C = 0) + or (MST_BYTES_C >= SLV_BYTES_C and MST_BYTES_C mod SLV_BYTES_C = 0); + + constant TSTRB_EN_C : boolean := SLAVE_AXI_CONFIG_G.TSTRB_EN_C and MASTER_AXI_CONFIG_G.TSTRB_EN_C; + constant TDEST_EN_C : boolean := (SLAVE_AXI_CONFIG_G.TDEST_BITS_C > 0) and (MASTER_AXI_CONFIG_G.TDEST_BITS_C > 0); + constant TID_EN_C : boolean := (SLAVE_AXI_CONFIG_G.TID_BITS_C > 0) and (MASTER_AXI_CONFIG_G.TID_BITS_C > 0); + constant TUSER_EN_C : boolean := (SLAVE_AXI_CONFIG_G.TUSER_BITS_C > 0) and (MASTER_AXI_CONFIG_G.TUSER_BITS_C > 0) + and (SLAVE_AXI_CONFIG_G.TUSER_MODE_C /= TUSER_NONE_C) and (MASTER_AXI_CONFIG_G.TUSER_MODE_C /= TUSER_NONE_C); + + constant TDEST_BITS_C : natural := ite(TDEST_EN_C, minimum(SLAVE_AXI_CONFIG_G.TDEST_BITS_C, MASTER_AXI_CONFIG_G.TDEST_BITS_C), 1); + constant TID_BITS_C : natural := ite(TID_EN_C, minimum(SLAVE_AXI_CONFIG_G.TID_BITS_C, MASTER_AXI_CONFIG_G.TID_BITS_C), 1); + constant TUSER_BITS_C : natural := ite(TUSER_EN_C, minimum(SLAVE_AXI_CONFIG_G.TUSER_BITS_C, MASTER_AXI_CONFIG_G.TUSER_BITS_C), 1); + + constant MAX_C : positive := maximum(MST_BYTES_C, SLV_BYTES_C); + constant MIN_C : positive := minimum(MST_BYTES_C, SLV_BYTES_C); + + constant SHIFT_WIDTH_C : positive := wordCount(MAX_C, MIN_C) * MIN_C + MIN_C; + + type RegType is record + writeIndex : natural range 0 to SHIFT_WIDTH_C-1; + tValid : sl; + tData : slv(8*SHIFT_WIDTH_C-1 downto 0); + tStrb : slv(1*SHIFT_WIDTH_C-1 downto 0); + tKeep : slv(1*SHIFT_WIDTH_C-1 downto 0); + tLast : sl; + tLastDly : sl; + tDest : slv(TDEST_BITS_C-1 downto 0); + tId : slv(TID_BITS_C-1 downto 0); + tUser : slv(TUSER_BITS_C*SHIFT_WIDTH_C-1 downto 0); + sideBand : slv(SIDE_BAND_WIDTH_G-1 downto 0); + sAxisSlave : AxiStreamSlaveType; + end record RegType; + + constant REG_INIT_C : RegType := ( + writeIndex => 0, + tValid => '0', + tData => (others => '0'), + tStrb => (others => '0'), + tKeep => (others => '0'), + tLast => '0', + tLastDly => '0', + tDest => (others => '0'), + tId => (others => '0'), + tUser => (others => '0'), + sideBand => (others => '0'), + sAxisSlave => AXI_STREAM_SLAVE_INIT_C); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal pipeAxisMaster : AxiStreamMasterType; + signal pipeSideBand : slv(SIDE_BAND_WIDTH_G-1 downto 0); + signal pipeAxisSlave : AxiStreamSlaveType; + +begin + + -- When going from a large bus to a small bus, ready is necessary + assert (SLV_BYTES_C <= MST_BYTES_C or READY_EN_G = true) + report "READY_EN_G must be true if slave width is great than master" severity failure; + + -- Cant use tkeep_fixed on master side when resizing or if not on slave side + assert (not (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_FIXED_C and + SLAVE_AXI_CONFIG_G.TKEEP_MODE_C /= TKEEP_FIXED_C)) + report "AxiStreamGearbox: Can't have TKEEP_MODE = TKEEP_FIXED on master side if not on slave side" + severity error; + + comb : process (axisRst, pipeAxisSlave, r, sAxisMaster, sSideBand) is + variable v : RegType; + begin + -- Latch the current value + v := r; + + -- Flow Control + v.sAxisSlave.tReady := '0'; + if (pipeAxisSlave.tReady = '1') or (READY_EN_G = false) then + + v.tValid := '0'; + v.tLast := '0'; + + -- Check if previous word terminated the frame + if (r.tLast = '0') then + + -- Reset the sequence + v.writeIndex := 0; + v.tStrb := (others => '0'); + v.tKeep := (others => '0'); + + end if; + + end if; + + -- Only do anything if ready for data output + if (v.tValid = '0') then + + -- If current write index (assigned last cycle) is greater than output width, then we have to shift down before assigning an new input + if (v.writeIndex >= MST_BYTES_C) then + + -- Decrement the counter + v.writeIndex := v.writeIndex - MST_BYTES_C; + + -- Shift TDATA with zero padding + v.tData := slvZero(8*MST_BYTES_C) & r.tData(8*SHIFT_WIDTH_C-1 downto 8*MST_BYTES_C); + + -- Check if TSTRB enabled + if(TSTRB_EN_C) then + -- Shift TSTRB with zero padding + v.tStrb := slvZero(1*MST_BYTES_C) & r.tStrb(1*SHIFT_WIDTH_C-1 downto 1*MST_BYTES_C); + end if; + + -- Shift TKEEP with zero padding + v.tKeep := slvZero(1*MST_BYTES_C) & r.tKeep(1*SHIFT_WIDTH_C-1 downto 1*MST_BYTES_C); + + -- Check if TUSER enabled + if (TUSER_EN_C) then + -- Shift TUSER with zero padding + v.tUser := slvZero(TUSER_BITS_C*MST_BYTES_C) & r.tUser(TUSER_BITS_C*SHIFT_WIDTH_C-1 downto TUSER_BITS_C*MST_BYTES_C); + end if; + + -- If write index still greater than output width after shift, then we have a valid word to output + if (v.writeIndex >= MST_BYTES_C) or (r.tLastDly = '1') then + + -- Set the flags + v.tValid := '1'; + v.tLast := r.tLastDly; + v.tLastDly := '0'; + + end if; + + end if; + end if; + + -- Accept new data if ready to output and shift above did not create an output valid or terminate the frame + if (sAxisMaster.tValid = '1') and (v.tValid = '0') and (v.tLast = '0') then + + -- Accept the input word + v.sAxisSlave.tReady := '1'; + + -- Assign incoming sideband + v.sideBand := sSideBand; + + -- Assign incoming TDATA + v.tData(8*v.writeIndex+8*SLV_BYTES_C-1 downto 8*v.writeIndex) := sAxisMaster.tData(8*SLV_BYTES_C-1 downto 0); + + -- Check if TSTRB enabled + if(TSTRB_EN_C) then + -- Assign incoming TSTRB + v.tStrb(1*v.writeIndex+1*SLV_BYTES_C-1 downto 1*v.writeIndex) := sAxisMaster.tStrb(1*SLV_BYTES_C-1 downto 0); + end if; + + -- Assign incoming TKEEP + if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then + v.tKeep(1*v.writeIndex+1*SLV_BYTES_C-1 downto 1*v.writeIndex) := genTKeep(conv_integer(sAxisMaster.tKeep(bitSize(SLV_BYTES_C)-1 downto 0))); + else + v.tKeep(1*v.writeIndex+1*SLV_BYTES_C-1 downto 1*v.writeIndex) := sAxisMaster.tKeep(1*SLV_BYTES_C-1 downto 0); + end if; + + -- Check if TDEST enabled + if(TDEST_EN_C) then + v.tDest := sAxisMaster.tDest(TDEST_BITS_C-1 downto 0); + end if; + + -- Check if TID enabled + if(TID_EN_C) then + v.tId := sAxisMaster.tId(TID_BITS_C-1 downto 0); + end if; + + if (TUSER_EN_C) then + for i in 0 to SLV_BYTES_C-1 loop + v.tUser( + (TUSER_BITS_C*v.writeIndex)+(i*TUSER_BITS_C)+(TUSER_BITS_C-1) downto + (TUSER_BITS_C*v.writeIndex)+(i*TUSER_BITS_C)) := + sAxisMaster.tUser((i*SLV_USER_C)+(TUSER_BITS_C-1) downto (i*SLV_USER_C)); + end loop; + end if; + + -- Increment writeIndex + v.writeIndex := v.writeIndex + SLV_BYTES_C; + + -- Assert tValid + if (v.writeIndex >= MST_BYTES_C) or (sAxisMaster.tLast = '1') then + + -- Set the flags + v.tValid := '1'; + v.tLast := '0'; + v.tLastDly := '0'; + + -- Check if spans frame termination two cycles + if (v.writeIndex > MST_BYTES_C) then + v.tLastDly := sAxisMaster.tLast; + else + v.tLast := sAxisMaster.tLast; + end if; + + end if; + + end if; + + -- Outputs + sAxisSlave <= v.sAxisSlave; + pipeSideBand <= r.sideBand; + + pipeAxisMaster.tValid <= r.tValid; + + pipeAxisMaster.tData <= (others => '0'); + pipeAxisMaster.tData(8*MST_BYTES_C-1 downto 0) <= r.tData(8*MST_BYTES_C-1 downto 0); + + if(TSTRB_EN_C) then + pipeAxisMaster.tStrb <= (others => '0'); + pipeAxisMaster.tStrb(1*MST_BYTES_C-1 downto 0) <= r.tData(1*MST_BYTES_C-1 downto 0); + else + pipeAxisMaster.tStrb <= (others => '1'); + end if; + + if (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then + pipeAxisMaster.tKeep <= toSlv(getTKeep(resize(r.tKeep(1*MST_BYTES_C-1 downto 0), AXI_STREAM_MAX_TKEEP_WIDTH_C), MASTER_AXI_CONFIG_G), AXI_STREAM_MAX_TKEEP_WIDTH_C); + else + pipeAxisMaster.tKeep <= (others => '0'); + pipeAxisMaster.tKeep(1*MST_BYTES_C-1 downto 0) <= r.tKeep(1*MST_BYTES_C-1 downto 0); + end if; + + pipeAxisMaster.tLast <= r.tLast; + + pipeAxisMaster.tDest <= (others => '0'); + if(TDEST_EN_C) then + pipeAxisMaster.tDest(TDEST_BITS_C-1 downto 0) <= r.tDest; + end if; + + pipeAxisMaster.tId <= (others => '0'); + if(TID_EN_C) then + pipeAxisMaster.tId(TID_BITS_C-1 downto 0) <= r.tId; + end if; + + pipeAxisMaster.tUser <= (others => '0'); + if (TUSER_EN_C) then + for i in 0 to MST_BYTES_C-1 loop + pipeAxisMaster.tUser((i*MST_USER_C)+(TUSER_BITS_C-1) downto (i*MST_USER_C)) <= + r.tUser((i*TUSER_BITS_C)+(TUSER_BITS_C-1) downto (i*TUSER_BITS_C)); + end loop; + end if; + + -- Synchronous Reset + if axisRst = '1' then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (axisClk) is + begin + if rising_edge(axisClk) then + r <= rin after TPD_G; + end if; + end process seq; + + ---------------------------------------------------- + -- Optional output pipeline registers to ease timing + ---------------------------------------------------- + U_Pipeline : entity surf.AxiStreamPipeline + generic map ( + TPD_G => TPD_G, + SIDE_BAND_WIDTH_G => SIDE_BAND_WIDTH_G, + PIPE_STAGES_G => PIPE_STAGES_G) + port map ( + -- Clock and Reset + axisClk => axisClk, + axisRst => axisRst, + -- Slave Port + sAxisMaster => pipeAxisMaster, + sSideBand => pipeSideBand, + sAxisSlave => pipeAxisSlave, + -- Master Port + mAxisMaster => mAxisMaster, + mSideBand => mSideBand, + mAxisSlave => mAxisSlave); + +end rtl; + From 557714b0f7ed9ad6c3168be72f37249cc0df4e40 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 24 Aug 2020 15:00:54 -0700 Subject: [PATCH 29/36] Use AxiStreamResize if word multiple because less LUTs --- axi/axi-stream/rtl/AxiStreamGearbox.vhd | 354 +++++++++++++----------- 1 file changed, 194 insertions(+), 160 deletions(-) diff --git a/axi/axi-stream/rtl/AxiStreamGearbox.vhd b/axi/axi-stream/rtl/AxiStreamGearbox.vhd index 3f5b151a50..109aff3773 100644 --- a/axi/axi-stream/rtl/AxiStreamGearbox.vhd +++ b/axi/axi-stream/rtl/AxiStreamGearbox.vhd @@ -121,217 +121,251 @@ begin report "AxiStreamGearbox: Can't have TKEEP_MODE = TKEEP_FIXED on master side if not on slave side" severity error; - comb : process (axisRst, pipeAxisSlave, r, sAxisMaster, sSideBand) is - variable v : RegType; - begin - -- Latch the current value - v := r; + --------------------------------------------------------- + -- Use AxiStreamResize if word multiple because less LUTs + --------------------------------------------------------- + GEN_RESIZE : if (WORD_MULTIPLE_C = true) generate + + U_Resize : entity surf.AxiStreamResize + generic map ( + -- General Configurations + TPD_G => TPD_G, + READY_EN_G => READY_EN_G, + PIPE_STAGES_G => PIPE_STAGES_G, + SIDE_BAND_WIDTH_G => SIDE_BAND_WIDTH_G, + -- AXI Stream Port Configurations + SLAVE_AXI_CONFIG_G => nexoAxisConfig(ADC_TYPE_G), + MASTER_AXI_CONFIG_G => AXIS_CONFIG_C) + port map ( + -- Clock and reset + axisClk => axisClk, + axisRst => axisRst, + -- Slave Port + sAxisMaster => sAxisMaster, + sSideBand => sSideBand, + sAxisSlave => sAxisSlave, + -- Master Port + mAxisMaster => mAxisMaster, + mSideBand => mSideBand, + mAxisSlave => mAxisSlave); + + end generate; + + GEN_GEARBOX : if (WORD_MULTIPLE_C = false) generate + + comb : process (axisRst, pipeAxisSlave, r, sAxisMaster, sSideBand) is + variable v : RegType; + begin + -- Latch the current value + v := r; + + -- Flow Control + v.sAxisSlave.tReady := '0'; + if (pipeAxisSlave.tReady = '1') or (READY_EN_G = false) then + + v.tValid := '0'; + v.tLast := '0'; + + -- Check if previous word terminated the frame + if (r.tLast = '0') then + + -- Reset the sequence + v.writeIndex := 0; + v.tStrb := (others => '0'); + v.tKeep := (others => '0'); - -- Flow Control - v.sAxisSlave.tReady := '0'; - if (pipeAxisSlave.tReady = '1') or (READY_EN_G = false) then + end if; + + end if; - v.tValid := '0'; - v.tLast := '0'; + -- Only do anything if ready for data output + if (v.tValid = '0') then - -- Check if previous word terminated the frame - if (r.tLast = '0') then + -- If current write index (assigned last cycle) is greater than output width, then we have to shift down before assigning an new input + if (v.writeIndex >= MST_BYTES_C) then - -- Reset the sequence - v.writeIndex := 0; - v.tStrb := (others => '0'); - v.tKeep := (others => '0'); + -- Decrement the counter + v.writeIndex := v.writeIndex - MST_BYTES_C; - end if; + -- Shift TDATA with zero padding + v.tData := slvZero(8*MST_BYTES_C) & r.tData(8*SHIFT_WIDTH_C-1 downto 8*MST_BYTES_C); + + -- Check if TSTRB enabled + if(TSTRB_EN_C) then + -- Shift TSTRB with zero padding + v.tStrb := slvZero(1*MST_BYTES_C) & r.tStrb(1*SHIFT_WIDTH_C-1 downto 1*MST_BYTES_C); + end if; + + -- Shift TKEEP with zero padding + v.tKeep := slvZero(1*MST_BYTES_C) & r.tKeep(1*SHIFT_WIDTH_C-1 downto 1*MST_BYTES_C); + + -- Check if TUSER enabled + if (TUSER_EN_C) then + -- Shift TUSER with zero padding + v.tUser := slvZero(TUSER_BITS_C*MST_BYTES_C) & r.tUser(TUSER_BITS_C*SHIFT_WIDTH_C-1 downto TUSER_BITS_C*MST_BYTES_C); + end if; - end if; + -- If write index still greater than output width after shift, then we have a valid word to output + if (v.writeIndex >= MST_BYTES_C) or (r.tLastDly = '1') then - -- Only do anything if ready for data output - if (v.tValid = '0') then + -- Set the flags + v.tValid := '1'; + v.tLast := r.tLastDly; + v.tLastDly := '0'; - -- If current write index (assigned last cycle) is greater than output width, then we have to shift down before assigning an new input - if (v.writeIndex >= MST_BYTES_C) then + end if; - -- Decrement the counter - v.writeIndex := v.writeIndex - MST_BYTES_C; + end if; + end if; + + -- Accept new data if ready to output and shift above did not create an output valid or terminate the frame + if (sAxisMaster.tValid = '1') and (v.tValid = '0') and (v.tLast = '0') then + + -- Accept the input word + v.sAxisSlave.tReady := '1'; - -- Shift TDATA with zero padding - v.tData := slvZero(8*MST_BYTES_C) & r.tData(8*SHIFT_WIDTH_C-1 downto 8*MST_BYTES_C); + -- Assign incoming sideband + v.sideBand := sSideBand; + + -- Assign incoming TDATA + v.tData(8*v.writeIndex+8*SLV_BYTES_C-1 downto 8*v.writeIndex) := sAxisMaster.tData(8*SLV_BYTES_C-1 downto 0); -- Check if TSTRB enabled if(TSTRB_EN_C) then - -- Shift TSTRB with zero padding - v.tStrb := slvZero(1*MST_BYTES_C) & r.tStrb(1*SHIFT_WIDTH_C-1 downto 1*MST_BYTES_C); + -- Assign incoming TSTRB + v.tStrb(1*v.writeIndex+1*SLV_BYTES_C-1 downto 1*v.writeIndex) := sAxisMaster.tStrb(1*SLV_BYTES_C-1 downto 0); + end if; + + -- Assign incoming TKEEP + if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then + v.tKeep(1*v.writeIndex+1*SLV_BYTES_C-1 downto 1*v.writeIndex) := genTKeep(conv_integer(sAxisMaster.tKeep(bitSize(SLV_BYTES_C)-1 downto 0))); + else + v.tKeep(1*v.writeIndex+1*SLV_BYTES_C-1 downto 1*v.writeIndex) := sAxisMaster.tKeep(1*SLV_BYTES_C-1 downto 0); + end if; + + -- Check if TDEST enabled + if(TDEST_EN_C) then + v.tDest := sAxisMaster.tDest(TDEST_BITS_C-1 downto 0); end if; - -- Shift TKEEP with zero padding - v.tKeep := slvZero(1*MST_BYTES_C) & r.tKeep(1*SHIFT_WIDTH_C-1 downto 1*MST_BYTES_C); + -- Check if TID enabled + if(TID_EN_C) then + v.tId := sAxisMaster.tId(TID_BITS_C-1 downto 0); + end if; - -- Check if TUSER enabled if (TUSER_EN_C) then - -- Shift TUSER with zero padding - v.tUser := slvZero(TUSER_BITS_C*MST_BYTES_C) & r.tUser(TUSER_BITS_C*SHIFT_WIDTH_C-1 downto TUSER_BITS_C*MST_BYTES_C); + for i in 0 to SLV_BYTES_C-1 loop + v.tUser( + (TUSER_BITS_C*v.writeIndex)+(i*TUSER_BITS_C)+(TUSER_BITS_C-1) downto + (TUSER_BITS_C*v.writeIndex)+(i*TUSER_BITS_C)) := + sAxisMaster.tUser((i*SLV_USER_C)+(TUSER_BITS_C-1) downto (i*SLV_USER_C)); + end loop; end if; - -- If write index still greater than output width after shift, then we have a valid word to output - if (v.writeIndex >= MST_BYTES_C) or (r.tLastDly = '1') then + -- Increment writeIndex + v.writeIndex := v.writeIndex + SLV_BYTES_C; + + -- Assert tValid + if (v.writeIndex >= MST_BYTES_C) or (sAxisMaster.tLast = '1') then -- Set the flags v.tValid := '1'; - v.tLast := r.tLastDly; + v.tLast := '0'; v.tLastDly := '0'; + -- Check if spans frame termination two cycles + if (v.writeIndex > MST_BYTES_C) then + v.tLastDly := sAxisMaster.tLast; + else + v.tLast := sAxisMaster.tLast; + end if; + end if; end if; - end if; - - -- Accept new data if ready to output and shift above did not create an output valid or terminate the frame - if (sAxisMaster.tValid = '1') and (v.tValid = '0') and (v.tLast = '0') then - -- Accept the input word - v.sAxisSlave.tReady := '1'; + -- Outputs + sAxisSlave <= v.sAxisSlave; + pipeSideBand <= r.sideBand; - -- Assign incoming sideband - v.sideBand := sSideBand; + pipeAxisMaster.tValid <= r.tValid; - -- Assign incoming TDATA - v.tData(8*v.writeIndex+8*SLV_BYTES_C-1 downto 8*v.writeIndex) := sAxisMaster.tData(8*SLV_BYTES_C-1 downto 0); + pipeAxisMaster.tData <= (others => '0'); + pipeAxisMaster.tData(8*MST_BYTES_C-1 downto 0) <= r.tData(8*MST_BYTES_C-1 downto 0); - -- Check if TSTRB enabled if(TSTRB_EN_C) then - -- Assign incoming TSTRB - v.tStrb(1*v.writeIndex+1*SLV_BYTES_C-1 downto 1*v.writeIndex) := sAxisMaster.tStrb(1*SLV_BYTES_C-1 downto 0); + pipeAxisMaster.tStrb <= (others => '0'); + pipeAxisMaster.tStrb(1*MST_BYTES_C-1 downto 0) <= r.tData(1*MST_BYTES_C-1 downto 0); + else + pipeAxisMaster.tStrb <= (others => '1'); end if; - -- Assign incoming TKEEP - if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - v.tKeep(1*v.writeIndex+1*SLV_BYTES_C-1 downto 1*v.writeIndex) := genTKeep(conv_integer(sAxisMaster.tKeep(bitSize(SLV_BYTES_C)-1 downto 0))); + if (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then + pipeAxisMaster.tKeep <= toSlv(getTKeep(resize(r.tKeep(1*MST_BYTES_C-1 downto 0), AXI_STREAM_MAX_TKEEP_WIDTH_C), MASTER_AXI_CONFIG_G), AXI_STREAM_MAX_TKEEP_WIDTH_C); else - v.tKeep(1*v.writeIndex+1*SLV_BYTES_C-1 downto 1*v.writeIndex) := sAxisMaster.tKeep(1*SLV_BYTES_C-1 downto 0); + pipeAxisMaster.tKeep <= (others => '0'); + pipeAxisMaster.tKeep(1*MST_BYTES_C-1 downto 0) <= r.tKeep(1*MST_BYTES_C-1 downto 0); end if; - -- Check if TDEST enabled + pipeAxisMaster.tLast <= r.tLast; + + pipeAxisMaster.tDest <= (others => '0'); if(TDEST_EN_C) then - v.tDest := sAxisMaster.tDest(TDEST_BITS_C-1 downto 0); + pipeAxisMaster.tDest(TDEST_BITS_C-1 downto 0) <= r.tDest; end if; - -- Check if TID enabled + pipeAxisMaster.tId <= (others => '0'); if(TID_EN_C) then - v.tId := sAxisMaster.tId(TID_BITS_C-1 downto 0); + pipeAxisMaster.tId(TID_BITS_C-1 downto 0) <= r.tId; end if; + pipeAxisMaster.tUser <= (others => '0'); if (TUSER_EN_C) then - for i in 0 to SLV_BYTES_C-1 loop - v.tUser( - (TUSER_BITS_C*v.writeIndex)+(i*TUSER_BITS_C)+(TUSER_BITS_C-1) downto - (TUSER_BITS_C*v.writeIndex)+(i*TUSER_BITS_C)) := - sAxisMaster.tUser((i*SLV_USER_C)+(TUSER_BITS_C-1) downto (i*SLV_USER_C)); + for i in 0 to MST_BYTES_C-1 loop + pipeAxisMaster.tUser((i*MST_USER_C)+(TUSER_BITS_C-1) downto (i*MST_USER_C)) <= + r.tUser((i*TUSER_BITS_C)+(TUSER_BITS_C-1) downto (i*TUSER_BITS_C)); end loop; end if; - -- Increment writeIndex - v.writeIndex := v.writeIndex + SLV_BYTES_C; + -- Synchronous Reset + if axisRst = '1' then + v := REG_INIT_C; + end if; - -- Assert tValid - if (v.writeIndex >= MST_BYTES_C) or (sAxisMaster.tLast = '1') then + -- Register the variable for next clock cycle + rin <= v; - -- Set the flags - v.tValid := '1'; - v.tLast := '0'; - v.tLastDly := '0'; - - -- Check if spans frame termination two cycles - if (v.writeIndex > MST_BYTES_C) then - v.tLastDly := sAxisMaster.tLast; - else - v.tLast := sAxisMaster.tLast; - end if; + end process comb; + seq : process (axisClk) is + begin + if rising_edge(axisClk) then + r <= rin after TPD_G; end if; - - end if; - - -- Outputs - sAxisSlave <= v.sAxisSlave; - pipeSideBand <= r.sideBand; - - pipeAxisMaster.tValid <= r.tValid; - - pipeAxisMaster.tData <= (others => '0'); - pipeAxisMaster.tData(8*MST_BYTES_C-1 downto 0) <= r.tData(8*MST_BYTES_C-1 downto 0); - - if(TSTRB_EN_C) then - pipeAxisMaster.tStrb <= (others => '0'); - pipeAxisMaster.tStrb(1*MST_BYTES_C-1 downto 0) <= r.tData(1*MST_BYTES_C-1 downto 0); - else - pipeAxisMaster.tStrb <= (others => '1'); - end if; - - if (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - pipeAxisMaster.tKeep <= toSlv(getTKeep(resize(r.tKeep(1*MST_BYTES_C-1 downto 0), AXI_STREAM_MAX_TKEEP_WIDTH_C), MASTER_AXI_CONFIG_G), AXI_STREAM_MAX_TKEEP_WIDTH_C); - else - pipeAxisMaster.tKeep <= (others => '0'); - pipeAxisMaster.tKeep(1*MST_BYTES_C-1 downto 0) <= r.tKeep(1*MST_BYTES_C-1 downto 0); - end if; - - pipeAxisMaster.tLast <= r.tLast; - - pipeAxisMaster.tDest <= (others => '0'); - if(TDEST_EN_C) then - pipeAxisMaster.tDest(TDEST_BITS_C-1 downto 0) <= r.tDest; - end if; - - pipeAxisMaster.tId <= (others => '0'); - if(TID_EN_C) then - pipeAxisMaster.tId(TID_BITS_C-1 downto 0) <= r.tId; - end if; - - pipeAxisMaster.tUser <= (others => '0'); - if (TUSER_EN_C) then - for i in 0 to MST_BYTES_C-1 loop - pipeAxisMaster.tUser((i*MST_USER_C)+(TUSER_BITS_C-1) downto (i*MST_USER_C)) <= - r.tUser((i*TUSER_BITS_C)+(TUSER_BITS_C-1) downto (i*TUSER_BITS_C)); - end loop; - end if; - - -- Synchronous Reset - if axisRst = '1' then - v := REG_INIT_C; - end if; - - -- Register the variable for next clock cycle - rin <= v; - - end process comb; - - seq : process (axisClk) is - begin - if rising_edge(axisClk) then - r <= rin after TPD_G; - end if; - end process seq; - - ---------------------------------------------------- - -- Optional output pipeline registers to ease timing - ---------------------------------------------------- - U_Pipeline : entity surf.AxiStreamPipeline - generic map ( - TPD_G => TPD_G, - SIDE_BAND_WIDTH_G => SIDE_BAND_WIDTH_G, - PIPE_STAGES_G => PIPE_STAGES_G) - port map ( - -- Clock and Reset - axisClk => axisClk, - axisRst => axisRst, - -- Slave Port - sAxisMaster => pipeAxisMaster, - sSideBand => pipeSideBand, - sAxisSlave => pipeAxisSlave, - -- Master Port - mAxisMaster => mAxisMaster, - mSideBand => mSideBand, - mAxisSlave => mAxisSlave); + end process seq; + + ---------------------------------------------------- + -- Optional output pipeline registers to ease timing + ---------------------------------------------------- + U_Pipeline : entity surf.AxiStreamPipeline + generic map ( + TPD_G => TPD_G, + SIDE_BAND_WIDTH_G => SIDE_BAND_WIDTH_G, + PIPE_STAGES_G => PIPE_STAGES_G) + port map ( + -- Clock and Reset + axisClk => axisClk, + axisRst => axisRst, + -- Slave Port + sAxisMaster => pipeAxisMaster, + sSideBand => pipeSideBand, + sAxisSlave => pipeAxisSlave, + -- Master Port + mAxisMaster => mAxisMaster, + mSideBand => mSideBand, + mAxisSlave => mAxisSlave); + + end generate; end rtl; From 659d8cf86cadd6eeb42fa42229c948a9e89feae6 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 24 Aug 2020 15:02:34 -0700 Subject: [PATCH 30/36] copy+paste bug fix --- axi/axi-stream/rtl/AxiStreamGearbox.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/axi/axi-stream/rtl/AxiStreamGearbox.vhd b/axi/axi-stream/rtl/AxiStreamGearbox.vhd index 109aff3773..260a0a6cfb 100644 --- a/axi/axi-stream/rtl/AxiStreamGearbox.vhd +++ b/axi/axi-stream/rtl/AxiStreamGearbox.vhd @@ -134,8 +134,8 @@ begin PIPE_STAGES_G => PIPE_STAGES_G, SIDE_BAND_WIDTH_G => SIDE_BAND_WIDTH_G, -- AXI Stream Port Configurations - SLAVE_AXI_CONFIG_G => nexoAxisConfig(ADC_TYPE_G), - MASTER_AXI_CONFIG_G => AXIS_CONFIG_C) + SLAVE_AXI_CONFIG_G => SLAVE_AXI_CONFIG_G, + MASTER_AXI_CONFIG_G => MASTER_AXI_CONFIG_G) port map ( -- Clock and reset axisClk => axisClk, From 895699808ebeb5e64582ce68e79e241f6c7e3270 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 24 Aug 2020 15:51:48 -0700 Subject: [PATCH 31/36] bug fix --- axi/axi-stream/rtl/AxiStreamGearbox.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/axi/axi-stream/rtl/AxiStreamGearbox.vhd b/axi/axi-stream/rtl/AxiStreamGearbox.vhd index 260a0a6cfb..fb822d0ed7 100644 --- a/axi/axi-stream/rtl/AxiStreamGearbox.vhd +++ b/axi/axi-stream/rtl/AxiStreamGearbox.vhd @@ -167,7 +167,7 @@ begin v.tLast := '0'; -- Check if previous word terminated the frame - if (r.tLast = '0') then + if (r.tLast = '1') then -- Reset the sequence v.writeIndex := 0; From 73a20dd2dc1b997b58362b0086c58bdaefa9c60a Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 24 Aug 2020 16:41:40 -0700 Subject: [PATCH 32/36] clean up --- axi/axi-stream/rtl/AxiStreamGearbox.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/axi/axi-stream/rtl/AxiStreamGearbox.vhd b/axi/axi-stream/rtl/AxiStreamGearbox.vhd index fb822d0ed7..841c4e9a6c 100644 --- a/axi/axi-stream/rtl/AxiStreamGearbox.vhd +++ b/axi/axi-stream/rtl/AxiStreamGearbox.vhd @@ -293,11 +293,11 @@ begin pipeAxisMaster.tData <= (others => '0'); pipeAxisMaster.tData(8*MST_BYTES_C-1 downto 0) <= r.tData(8*MST_BYTES_C-1 downto 0); + pipeAxisMaster.tStrb <= (others => '0'); if(TSTRB_EN_C) then - pipeAxisMaster.tStrb <= (others => '0'); pipeAxisMaster.tStrb(1*MST_BYTES_C-1 downto 0) <= r.tData(1*MST_BYTES_C-1 downto 0); else - pipeAxisMaster.tStrb <= (others => '1'); + pipeAxisMaster.tStrb(1*MST_BYTES_C-1 downto 0) <= (others => '1'); end if; if (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then From 158cf1a0678079fc5256a0fb3b9d8e875d206470 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 27 Aug 2020 09:45:46 -0700 Subject: [PATCH 33/36] adding Ip integrator Support --- .../AxiDualPortRamIpIntegrator.vhd | 178 ++++++++++++ .../ip_integrator/AxiVersionIpIntegrator.vhd | 180 ++++++++++++ .../MasterAxiLiteIpIntegrator.vhd | 157 +++++++++++ .../SlaveAxiLiteIpIntegrator.vhd | 157 +++++++++++ axi/axi-lite/ruckus.tcl | 1 + .../MasterAxiStreamIpIntegrator.vhd | 118 ++++++++ .../MasterAxiStreamTerminateIpIntegrator.vhd | 85 ++++++ .../SlaveAxiStreamIpIntegrator.vhd | 118 ++++++++ .../SlaveAxiStreamTerminateIpIntegrator.vhd | 81 ++++++ axi/axi-stream/ruckus.tcl | 1 + .../ip_integrator/MasterAxiIpIntegrator.vhd | 266 ++++++++++++++++++ .../ip_integrator/SlaveAxiIpIntegrator.vhd | 266 ++++++++++++++++++ axi/axi4/ruckus.tcl | 1 + .../ip_integrator/MasterRamIpIntegrator.vhd | 78 +++++ .../ip_integrator/SlaveRamIpIntegrator.vhd | 78 +++++ base/general/ruckus.tcl | 1 + 16 files changed, 1766 insertions(+) create mode 100644 axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd create mode 100644 axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd create mode 100644 axi/axi-lite/ip_integrator/MasterAxiLiteIpIntegrator.vhd create mode 100644 axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd create mode 100644 axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd create mode 100644 axi/axi-stream/ip_integrator/MasterAxiStreamTerminateIpIntegrator.vhd create mode 100644 axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd create mode 100644 axi/axi-stream/ip_integrator/SlaveAxiStreamTerminateIpIntegrator.vhd create mode 100644 axi/axi4/ip_integrator/MasterAxiIpIntegrator.vhd create mode 100644 axi/axi4/ip_integrator/SlaveAxiIpIntegrator.vhd create mode 100644 base/general/ip_integrator/MasterRamIpIntegrator.vhd create mode 100644 base/general/ip_integrator/SlaveRamIpIntegrator.vhd diff --git a/axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd new file mode 100644 index 0000000000..26acd42f43 --- /dev/null +++ b/axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd @@ -0,0 +1,178 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: IP Integrator Wrapper for surf.AxiVersion +------------------------------------------------------------------------------- +-- TCL Command: create_bd_cell -type module -reference AxiDualPortRamIpIntegrator AxiDualPortRam_0 +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +entity AxiDualPortRamIpIntegrator is + generic ( + EN_ERROR_RESP : boolean := false; + SYNTH_MODE : string := "inferred"; + MEMORY_TYPE : string := "block"; + MEMORY_INIT_FILE : string := "none"; -- Used for MEMORY_TYPE="XPM only + MEMORY_INIT_PARAM : string := "0"; -- Used for MEMORY_TYPE="XPM only + READ_LATENCY : natural range 0 to 3 := 3; + AXI_WR_EN : boolean := true; + SYS_WR_EN : boolean := false; + SYS_BYTE_WR_EN : boolean := false; + COMMON_CLK : boolean := false; + ADDR_WIDTH : positive := 5; + DATA_WIDTH : positive := 32); + port ( + -- AXI-Lite Interface + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(ADDR_WIDTH+1 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(31 downto 0); + S_AXI_WSTRB : in std_logic_vector(3 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(ADDR_WIDTH+1 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(31 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic; + -- SYS RAM Interface + CLK : in std_logic := '0'; + EN : in std_logic := '1'; + WE : in std_logic_vector((DATA_WIDTH/8)-1 downto 0) := (others => '0'); + RST : in std_logic := '0'; + ADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0'); + DIN : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0'); + DOUT : out std_logic_vector(DATA_WIDTH-1 downto 0)); +end AxiDualPortRamIpIntegrator; + +architecture mapping of AxiDualPortRamIpIntegrator is + + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_PARAMETER : string; + + attribute X_INTERFACE_INFO of CLK : signal is "xilinx.com:interface:bram:1.0 RAM_PORT CLK"; + attribute X_INTERFACE_INFO of EN : signal is "xilinx.com:interface:bram:1.0 RAM_PORT EN"; + attribute X_INTERFACE_INFO of WE : signal is "xilinx.com:interface:bram:1.0 RAM_PORT WE"; + attribute X_INTERFACE_INFO of RST : signal is "xilinx.com:interface:bram:1.0 RAM_PORT RST"; + attribute X_INTERFACE_INFO of ADDR : signal is "xilinx.com:interface:bram:1.0 RAM_PORT ADDR"; + attribute X_INTERFACE_INFO of DIN : signal is "xilinx.com:interface:bram:1.0 RAM_PORT DIN"; + attribute X_INTERFACE_INFO of DOUT : signal is "xilinx.com:interface:bram:1.0 RAM_PORT DOUT"; + + attribute X_INTERFACE_PARAMETER of ADDR : signal is + "XIL_INTERFACENAME RAM_PORT, " & + "MEM_SIZE " & integer'image(2**ADDR_WIDTH) & ", " & + "MEM_WIDTH " & integer'image(DATA_WIDTH) & ", " & + "MEM_ECC NONE, " & + "MASTER_TYPE OTHER, " & + "READ_LATENCY " & integer'image(READ_LATENCY); + + signal uOrWe : sl; + signal intWe : sl; + signal intWeByte : slv(wordCount(DATA_WIDTH, 8)-1 downto 0); + + signal axilClk : sl; + signal axilRst : sl; + signal axilReadMaster : AxiLiteReadMasterType; + signal axilReadSlave : AxiLiteReadSlaveType; + signal axilWriteMaster : AxiLiteWriteMasterType; + signal axilWriteSlave : AxiLiteWriteSlaveType; + +begin + + U_ShimLayer : entity surf.SlaveAxiLiteIpIntegrator + generic map ( + EN_ERROR_RESP => EN_ERROR_RESP, + HAS_WSTRB => 1, -- Using write strobe + ADDR_WIDTH => ADDR_WIDTH+2) + port map ( + -- IP Integrator AXI-Lite Interface + S_AXI_ACLK => S_AXI_ACLK, + S_AXI_ARESETN => S_AXI_ARESETN, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWPROT => S_AXI_AWPROT, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARPROT => S_AXI_ARPROT, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + -- SURF AXI-Lite Interface + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + + U_AxiDualPortRam : entity surf.AxiDualPortRam + generic map ( + SYNTH_MODE_G => SYNTH_MODE, + MEMORY_TYPE_G => MEMORY_TYPE, + MEMORY_INIT_FILE_G => MEMORY_INIT_FILE, + MEMORY_INIT_PARAM_G => MEMORY_INIT_PARAM, + READ_LATENCY_G => READ_LATENCY, + AXI_WR_EN_G => AXI_WR_EN, + SYS_WR_EN_G => SYS_WR_EN, + SYS_BYTE_WR_EN_G => SYS_BYTE_WR_EN, + COMMON_CLK_G => COMMON_CLK, + ADDR_WIDTH_G => ADDR_WIDTH, + DATA_WIDTH_G => DATA_WIDTH) + port map ( + -- AXI-Lite Interface + axiClk => axilClk, + axiRst => axilRst, + axiReadMaster => axilReadMaster, + axiReadSlave => axilReadSlave, + axiWriteMaster => axilWriteMaster, + axiWriteSlave => axilWriteSlave, + -- Standard Port + clk => CLK, + en => EN, + we => intWe, + weByte => intWeByte, + rst => RST, + addr => ADDR, + din => DIN, + dout => DOUT); + + uOrWe <= uOr(WE); + intWe <= uOrWe; + intWeByte <= WE when(SYS_BYTE_WR_EN) else (others => uOrWe); + +end mapping; diff --git a/axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd new file mode 100644 index 0000000000..39d8d2f07c --- /dev/null +++ b/axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd @@ -0,0 +1,180 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: IP Integrator Wrapper for surf.AxiVersion +------------------------------------------------------------------------------- +-- TCL Command: create_bd_cell -type module -reference AxiVersionIpIntegrator AxiVersion_0 +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +library ruckus; +use ruckus.BuildInfoPkg.all; + +entity AxiVersionIpIntegrator is + generic ( + EN_ERROR_RESP : boolean := false; + FREQ_HZ : positive := 125000000; + EN_DEVICE_DNA : boolean := false; + EN_ICAP : boolean := false; + EN_DS2411 : boolean := false; + USE_SLOWCLK : boolean := false; + BUFR_CLK_DIV : positive := 8; + AUTO_RELOAD_EN : boolean := false; + AUTO_RELOAD_TIME : positive := 10; -- units of seconds + AUTO_RELOAD_ADDR : std_logic_vector(31 downto 0) := x"00000000"); + port ( + -- AXI-Lite Interface + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(11 downto 0); -- Must match ADDR_WIDTH_C + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(31 downto 0); + S_AXI_WSTRB : in std_logic_vector(3 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(11 downto 0); -- Must match ADDR_WIDTH_C + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(31 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic; + -- Optional: User Reset + userReset : out std_logic; + -- Optional: FPGA Reloading Interface + fpgaEnReload : in std_logic := '1'; + fpgaReload : out std_logic; + fpgaReloadAddr : out std_logic_vector(31 downto 0); + upTimeCnt : out std_logic_vector(31 downto 0); + -- Optional: Serial Number outputs + slowClk : in std_logic := '0'; + dnaValueOut : out std_logic_vector(127 downto 0); + fdValueOut : out std_logic_vector(63 downto 0); + -- Optional: user values + userValues : in std_logic_vector((64*32)-1 downto 0) := (others => '0'); + -- Optional: DS2411 interface + fdSerSdio : inout std_logic := 'Z'); +end AxiVersionIpIntegrator; + +architecture mapping of AxiVersionIpIntegrator is + + constant ADDR_WIDTH_C : positive := 12; -- Must match the entity's port width + + constant CLK_PERIOD_C : real := (1.0/real(FREQ_HZ)); -- units of seconds + + signal axilClk : sl; + signal axilRst : sl; + signal axilReadMaster : AxiLiteReadMasterType; + signal axilReadSlave : AxiLiteReadSlaveType; + signal axilWriteMaster : AxiLiteWriteMasterType; + signal axilWriteSlave : AxiLiteWriteSlaveType; + + signal userValuesArray : Slv32Array(0 to 63); + +begin + + U_ShimLayer : entity surf.SlaveAxiLiteIpIntegrator + generic map ( + EN_ERROR_RESP => EN_ERROR_RESP, + FREQ_HZ => FREQ_HZ, + ADDR_WIDTH => ADDR_WIDTH_C) + port map ( + -- IP Integrator AXI-Lite Interface + S_AXI_ACLK => S_AXI_ACLK, + S_AXI_ARESETN => S_AXI_ARESETN, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWPROT => S_AXI_AWPROT, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARPROT => S_AXI_ARPROT, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + -- SURF AXI-Lite Interface + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + + process(userValues) + variable i : natural; + variable retVar : Slv32Array(0 to 63); + begin + for i in 0 to 63 loop + retVar(i) := userValues((i*32)+31 downto i*32); + end loop; + userValuesArray <= retVar; + end process; + + U_AxiVersion : entity surf.AxiVersion + generic map ( + BUILD_INFO_G => BUILD_INFO_C, + CLK_PERIOD_G => CLK_PERIOD_C, + EN_DEVICE_DNA_G => EN_DEVICE_DNA, + EN_DS2411_G => EN_DS2411, + EN_ICAP_G => EN_ICAP, + USE_SLOWCLK_G => USE_SLOWCLK, + BUFR_CLK_DIV_G => BUFR_CLK_DIV, + AUTO_RELOAD_EN_G => AUTO_RELOAD_EN, + AUTO_RELOAD_TIME_G => AUTO_RELOAD_TIME, + AUTO_RELOAD_ADDR_G => AUTO_RELOAD_ADDR) + port map ( + -- AXI-Lite Interface + axiClk => axilClk, + axiRst => axilRst, + axiReadMaster => axilReadMaster, + axiReadSlave => axilReadSlave, + axiWriteMaster => axilWriteMaster, + axiWriteSlave => axilWriteSlave, + -- Optional: User Reset + userReset => userReset, + -- Optional: FPGA Reloading Interface + fpgaEnReload => fpgaEnReload, + fpgaReload => fpgaReload, + fpgaReloadAddr => fpgaReloadAddr, + upTimeCnt => upTimeCnt, + -- Optional: Serial Number outputs + slowClk => slowClk, + dnaValueOut => dnaValueOut, + fdValueOut => fdValueOut, + -- Optional: user values + userValues => userValuesArray, + -- Optional: DS2411 interface + fdSerSdio => fdSerSdio); + +end mapping; diff --git a/axi/axi-lite/ip_integrator/MasterAxiLiteIpIntegrator.vhd b/axi/axi-lite/ip_integrator/MasterAxiLiteIpIntegrator.vhd new file mode 100644 index 0000000000..62fbfae2f1 --- /dev/null +++ b/axi/axi-lite/ip_integrator/MasterAxiLiteIpIntegrator.vhd @@ -0,0 +1,157 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Common shim layer between IP Integrator interface and surf AXI-Lite interface +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +entity MasterAxiLiteIpIntegrator is + generic ( + INTERFACENAME : string := "M_AXI"; + EN_ERROR_RESP : boolean := false; + HAS_PROT : natural range 0 to 1 := 0; + HAS_WSTRB : natural range 0 to 1 := 0; + FREQ_HZ : positive := 100000000; + ADDR_WIDTH : positive := 12); + port ( + -- IP Integrator AXI-Lite Interface + M_AXI_ACLK : in std_logic; + M_AXI_ARESETN : in std_logic; + M_AXI_AWADDR : out std_logic_vector(ADDR_WIDTH-1 downto 0); + M_AXI_AWPROT : out std_logic_vector(2 downto 0); + M_AXI_AWVALID : out std_logic; + M_AXI_AWREADY : in std_logic; + M_AXI_WDATA : out std_logic_vector(31 downto 0); + M_AXI_WSTRB : out std_logic_vector(3 downto 0); + M_AXI_WVALID : out std_logic; + M_AXI_WREADY : in std_logic; + M_AXI_BRESP : in std_logic_vector(1 downto 0); + M_AXI_BVALID : in std_logic; + M_AXI_BREADY : out std_logic; + M_AXI_ARADDR : out std_logic_vector(ADDR_WIDTH-1 downto 0); + M_AXI_ARPROT : out std_logic_vector(2 downto 0); + M_AXI_ARVALID : out std_logic; + M_AXI_ARREADY : in std_logic; + M_AXI_RDATA : in std_logic_vector(31 downto 0); + M_AXI_RRESP : in std_logic_vector(1 downto 0); + M_AXI_RVALID : in std_logic; + M_AXI_RREADY : out std_logic; + -- SURF AXI-Lite Interface + axilClk : out sl; + axilRst : out sl; + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType); +end MasterAxiLiteIpIntegrator; + +architecture mapping of MasterAxiLiteIpIntegrator is + + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_PARAMETER : string; + + attribute X_INTERFACE_INFO of M_AXI_RREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RREADY"; + attribute X_INTERFACE_INFO of M_AXI_RVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RVALID"; + attribute X_INTERFACE_INFO of M_AXI_RRESP : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RRESP"; + attribute X_INTERFACE_INFO of M_AXI_RDATA : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RDATA"; + attribute X_INTERFACE_INFO of M_AXI_ARREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARREADY"; + attribute X_INTERFACE_INFO of M_AXI_ARVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARVALID"; + attribute X_INTERFACE_INFO of M_AXI_ARADDR : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARADDR"; + attribute X_INTERFACE_INFO of M_AXI_ARPROT : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARPROT"; + attribute X_INTERFACE_INFO of M_AXI_BREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BREADY"; + attribute X_INTERFACE_INFO of M_AXI_BVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BVALID"; + attribute X_INTERFACE_INFO of M_AXI_BRESP : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BRESP"; + attribute X_INTERFACE_INFO of M_AXI_WREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WREADY"; + attribute X_INTERFACE_INFO of M_AXI_WVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WVALID"; + attribute X_INTERFACE_INFO of M_AXI_WDATA : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WDATA"; + attribute X_INTERFACE_INFO of M_AXI_WSTRB : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WSTRB"; + attribute X_INTERFACE_INFO of M_AXI_AWREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWREADY"; + attribute X_INTERFACE_INFO of M_AXI_AWVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWVALID"; + attribute X_INTERFACE_INFO of M_AXI_AWPROT : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWPROT"; + attribute X_INTERFACE_INFO of M_AXI_AWADDR : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWADDR"; + attribute X_INTERFACE_PARAMETER of M_AXI_AWADDR : signal is + "XIL_INTERFACENAME " & INTERFACENAME & ", " & + "PROTOCOL AXI4LITE, " & + "DATA_WIDTH 32, " & + "HAS_PROT " & integer'image(HAS_PROT) & ", " & + "HAS_WSTRB " & integer'image(HAS_WSTRB) & ", " & + "MAX_BURST_LENGTH 1, " & + "ADDR_WIDTH " & integer'image(ADDR_WIDTH) & ", " & + "FREQ_HZ " & integer'image(FREQ_HZ); + + attribute X_INTERFACE_INFO of M_AXI_ARESETN : signal is "xilinx.com:signal:reset:1.0 RST." & INTERFACENAME & "_ARESETN RST"; + attribute X_INTERFACE_PARAMETER of M_AXI_ARESETN : signal is + "XIL_INTERFACENAME RST." & INTERFACENAME & "_ARESETN, " & + "POLARITY ACTIVE_LOW"; + + attribute X_INTERFACE_INFO of M_AXI_ACLK : signal is "xilinx.com:signal:clock:1.0 CLK." & INTERFACENAME & "_ACLK CLK"; + attribute X_INTERFACE_PARAMETER of M_AXI_ACLK : signal is + "XIL_INTERFACENAME CLK." & INTERFACENAME & "_ACLK, " & + "ASSOCIATED_BUSIF " & INTERFACENAME & ", " & + "ASSOCIATED_RESET " & INTERFACENAME & "_ARESETN, " & + "FREQ_HZ " & integer'image(FREQ_HZ); + + signal M_AXI_ReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal M_AXI_ReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal M_AXI_WriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal M_AXI_WriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + +begin + + axilClk <= M_AXI_ACLK; + + M_AXI_ReadMaster <= axilReadMaster; + axilReadSlave <= M_AXI_ReadSlave; + + M_AXI_WriteMaster <= axilWriteMaster; + axilWriteSlave <= M_AXI_WriteSlave; + + U_RstSync : entity surf.RstSync + generic map ( + IN_POLARITY_G => '0', + OUT_POLARITY_G => '1') + port map ( + clk => M_AXI_ACLK, + asyncRst => M_AXI_ARESETN, + syncRst => axilRst); + + M_AXI_ARADDR <= M_AXI_ReadMaster.araddr(ADDR_WIDTH-1 downto 0); + M_AXI_ARPROT <= M_AXI_ReadMaster.arprot; + M_AXI_ARVALID <= M_AXI_ReadMaster.arvalid; + M_AXI_RREADY <= M_AXI_ReadMaster.rready; + + M_AXI_ReadSlave.arready <= M_AXI_ARREADY; + M_AXI_ReadSlave.rdata <= M_AXI_RDATA; + M_AXI_ReadSlave.rresp <= M_AXI_RRESP when(EN_ERROR_RESP) else AXI_RESP_OK_C; + M_AXI_ReadSlave.rvalid <= M_AXI_RVALID; + + M_AXI_AWADDR <= M_AXI_WriteMaster.awaddr(ADDR_WIDTH-1 downto 0); + M_AXI_AWPROT <= M_AXI_WriteMaster.awprot; + M_AXI_AWVALID <= M_AXI_WriteMaster.awvalid; + M_AXI_WDATA <= M_AXI_WriteMaster.wdata; + M_AXI_WSTRB <= M_AXI_WriteMaster.wstrb when(HAS_WSTRB /= 0) else x"F"; + M_AXI_WVALID <= M_AXI_WriteMaster.wvalid; + M_AXI_BREADY <= M_AXI_WriteMaster.bready; + + M_AXI_WriteSlave.awready <= M_AXI_AWREADY; + M_AXI_WriteSlave.wready <= M_AXI_WREADY; + M_AXI_WriteSlave.bresp <= M_AXI_BRESP when(EN_ERROR_RESP) else AXI_RESP_OK_C; + M_AXI_WriteSlave.bvalid <= M_AXI_BVALID; + +end mapping; diff --git a/axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd b/axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd new file mode 100644 index 0000000000..b309afca30 --- /dev/null +++ b/axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd @@ -0,0 +1,157 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Common shim layer between IP Integrator interface and surf AXI-Lite interface +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +entity SlaveAxiLiteIpIntegrator is + generic ( + INTERFACENAME : string := "S_AXI"; + EN_ERROR_RESP : boolean := false; + HAS_PROT : natural range 0 to 1 := 0; + HAS_WSTRB : natural range 0 to 1 := 0; + FREQ_HZ : positive := 100000000; + ADDR_WIDTH : positive := 12); + port ( + -- IP Integrator AXI-Lite Interface + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(31 downto 0); + S_AXI_WSTRB : in std_logic_vector(3 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(31 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic; + -- SURF AXI-Lite Interface + axilClk : out sl; + axilRst : out sl; + axilReadMaster : out AxiLiteReadMasterType; + axilReadSlave : in AxiLiteReadSlaveType; + axilWriteMaster : out AxiLiteWriteMasterType; + axilWriteSlave : in AxiLiteWriteSlaveType); +end SlaveAxiLiteIpIntegrator; + +architecture mapping of SlaveAxiLiteIpIntegrator is + + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_PARAMETER : string; + + attribute X_INTERFACE_INFO of S_AXI_RREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RREADY"; + attribute X_INTERFACE_INFO of S_AXI_RVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RVALID"; + attribute X_INTERFACE_INFO of S_AXI_RRESP : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RRESP"; + attribute X_INTERFACE_INFO of S_AXI_RDATA : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RDATA"; + attribute X_INTERFACE_INFO of S_AXI_ARREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARREADY"; + attribute X_INTERFACE_INFO of S_AXI_ARVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARVALID"; + attribute X_INTERFACE_INFO of S_AXI_ARADDR : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARADDR"; + attribute X_INTERFACE_INFO of S_AXI_ARPROT : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARPROT"; + attribute X_INTERFACE_INFO of S_AXI_BREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BREADY"; + attribute X_INTERFACE_INFO of S_AXI_BVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BVALID"; + attribute X_INTERFACE_INFO of S_AXI_BRESP : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BRESP"; + attribute X_INTERFACE_INFO of S_AXI_WREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WREADY"; + attribute X_INTERFACE_INFO of S_AXI_WVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WVALID"; + attribute X_INTERFACE_INFO of S_AXI_WDATA : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WDATA"; + attribute X_INTERFACE_INFO of S_AXI_WSTRB : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WSTRB"; + attribute X_INTERFACE_INFO of S_AXI_AWREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWREADY"; + attribute X_INTERFACE_INFO of S_AXI_AWVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWVALID"; + attribute X_INTERFACE_INFO of S_AXI_AWPROT : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWPROT"; + attribute X_INTERFACE_INFO of S_AXI_AWADDR : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWADDR"; + attribute X_INTERFACE_PARAMETER of S_AXI_AWADDR : signal is + "XIL_INTERFACENAME " & INTERFACENAME & ", " & + "PROTOCOL AXI4LITE, " & + "DATA_WIDTH 32, " & + "HAS_PROT " & integer'image(HAS_PROT) & ", " & + "HAS_WSTRB " & integer'image(HAS_WSTRB) & ", " & + "MAX_BURST_LENGTH 1, " & + "ADDR_WIDTH " & integer'image(ADDR_WIDTH) & ", " & + "FREQ_HZ " & integer'image(FREQ_HZ); + + attribute X_INTERFACE_INFO of S_AXI_ARESETN : signal is "xilinx.com:signal:reset:1.0 RST." & INTERFACENAME & "_ARESETN RST"; + attribute X_INTERFACE_PARAMETER of S_AXI_ARESETN : signal is + "XIL_INTERFACENAME RST." & INTERFACENAME & "_ARESETN, " & + "POLARITY ACTIVE_LOW"; + + attribute X_INTERFACE_INFO of S_AXI_ACLK : signal is "xilinx.com:signal:clock:1.0 CLK." & INTERFACENAME & "_ACLK CLK"; + attribute X_INTERFACE_PARAMETER of S_AXI_ACLK : signal is + "XIL_INTERFACENAME CLK." & INTERFACENAME & "_ACLK, " & + "ASSOCIATED_BUSIF " & INTERFACENAME & ", " & + "ASSOCIATED_RESET " & INTERFACENAME & "_ARESETN, " & + "FREQ_HZ " & integer'image(FREQ_HZ); + + signal S_AXI_ReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal S_AXI_ReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal S_AXI_WriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal S_AXI_WriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + +begin + + axilClk <= S_AXI_ACLK; + + axilReadMaster <= S_AXI_ReadMaster; + S_AXI_ReadSlave <= axilReadSlave; + + axilWriteMaster <= S_AXI_WriteMaster; + S_AXI_WriteSlave <= axilWriteSlave; + + U_RstSync : entity surf.RstSync + generic map ( + IN_POLARITY_G => '0', + OUT_POLARITY_G => '1') + port map ( + clk => S_AXI_ACLK, + asyncRst => S_AXI_ARESETN, + syncRst => axilRst); + + S_AXI_ReadMaster.araddr(ADDR_WIDTH-1 downto 0) <= S_AXI_ARADDR; + S_AXI_ReadMaster.arprot <= S_AXI_ARPROT; + S_AXI_ReadMaster.arvalid <= S_AXI_ARVALID; + S_AXI_ReadMaster.rready <= S_AXI_RREADY; + + S_AXI_ARREADY <= S_AXI_ReadSlave.arready; + S_AXI_RDATA <= S_AXI_ReadSlave.rdata; + S_AXI_RRESP <= S_AXI_ReadSlave.rresp when(EN_ERROR_RESP) else AXI_RESP_OK_C; + S_AXI_RVALID <= S_AXI_ReadSlave.rvalid; + + S_AXI_WriteMaster.awaddr(ADDR_WIDTH-1 downto 0) <= S_AXI_AWADDR; + S_AXI_WriteMaster.awprot <= S_AXI_AWPROT; + S_AXI_WriteMaster.awvalid <= S_AXI_AWVALID; + S_AXI_WriteMaster.wdata <= S_AXI_WDATA; + S_AXI_WriteMaster.wstrb <= S_AXI_WSTRB when(HAS_WSTRB /= 0) else x"F"; + S_AXI_WriteMaster.wvalid <= S_AXI_WVALID; + S_AXI_WriteMaster.bready <= S_AXI_BREADY; + + S_AXI_AWREADY <= S_AXI_WriteSlave.awready; + S_AXI_WREADY <= S_AXI_WriteSlave.wready; + S_AXI_BRESP <= S_AXI_WriteSlave.bresp when(EN_ERROR_RESP) else AXI_RESP_OK_C; + S_AXI_BVALID <= S_AXI_WriteSlave.bvalid; + +end mapping; diff --git a/axi/axi-lite/ruckus.tcl b/axi/axi-lite/ruckus.tcl index 6e82fc29b1..7598c569ff 100644 --- a/axi/axi-lite/ruckus.tcl +++ b/axi/axi-lite/ruckus.tcl @@ -3,6 +3,7 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Load Source Code loadSource -lib surf -dir "$::DIR_PATH/rtl" +loadSource -lib surf -dir "$::DIR_PATH/ip_integrator" # Load Simulation loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb" diff --git a/axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd b/axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd new file mode 100644 index 0000000000..bb980c25ed --- /dev/null +++ b/axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd @@ -0,0 +1,118 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Common shim layer between IP Integrator interface and surf AXI Stream interface +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity MasterAxiStreamIpIntegrator is + generic ( + INTERFACENAME : string := "M_AXIS"; + HAS_TLAST : natural range 0 to 1 := 1; + HAS_TKEEP : natural range 0 to 1 := 1; + HAS_TSTRB : natural range 0 to 1 := 0; + HAS_TREADY : natural range 0 to 1 := 1; + TUSER_WIDTH : natural range 1 to 8 := 2; + TID_WIDTH : natural range 1 to 8 := 1; + TDEST_WIDTH : natural range 1 to 8 := 1; + TDATA_NUM_BYTES : natural range 1 to 128 := 1); + port ( + -- IP Integrator AXI Stream Interface + M_AXIS_ACLK : in std_logic := '0'; + M_AXIS_ARESETN : in std_logic := '0'; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector((8*TDATA_NUM_BYTES)-1 downto 0); + M_AXIS_TSTRB : out std_logic_vector(TDATA_NUM_BYTES-1 downto 0); + M_AXIS_TKEEP : out std_logic_vector(TDATA_NUM_BYTES-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TDEST : out std_logic_vector(TDEST_WIDTH-1 downto 0); + M_AXIS_TID : out std_logic_vector(TID_WIDTH-1 downto 0); + M_AXIS_TUSER : out std_logic_vector(TUSER_WIDTH-1 downto 0); + M_AXIS_TREADY : in std_logic := '1'; + -- SURF AXI Stream Interface + axisClk : out sl; + axisRst : out sl; + axisMaster : in AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + axisSlave : out AxiStreamSlaveType); +end MasterAxiStreamIpIntegrator; + +architecture mapping of MasterAxiStreamIpIntegrator is + + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_PARAMETER : string; + + attribute X_INTERFACE_INFO of M_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 " & INTERFACENAME & " TVALID"; + attribute X_INTERFACE_INFO of M_AXIS_TLAST : signal is "xilinx.com:interface:axis:1.0 " & INTERFACENAME & " TLAST"; + attribute X_INTERFACE_INFO of M_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 " & INTERFACENAME & " TDATA"; + attribute X_INTERFACE_INFO of M_AXIS_TKEEP : signal is "xilinx.com:interface:axis:1.0 " & INTERFACENAME & " TKEEP"; + attribute X_INTERFACE_INFO of M_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 " & INTERFACENAME & " TREADY"; + attribute X_INTERFACE_PARAMETER of M_AXIS_TDATA : signal is + "XIL_INTERFACENAME " & INTERFACENAME & ", " & + "LAYERED_METADATA undef, " & + "HAS_TLAST " & integer'image(HAS_TLAST) & ", " & + "HAS_TKEEP " & integer'image(HAS_TKEEP) & ", " & + "HAS_TSTRB " & integer'image(HAS_TSTRB) & ", " & + "HAS_TREADY " & integer'image(HAS_TREADY) & ", " & + "TUSER_WIDTH " & integer'image(TUSER_WIDTH) & ", " & + "TID_WIDTH " & integer'image(TID_WIDTH) & ", " & + "TDEST_WIDTH " & integer'image(TDEST_WIDTH) & ", " & + "TDATA_NUM_BYTES " & integer'image(TDATA_NUM_BYTES); + + attribute X_INTERFACE_INFO of M_AXIS_ARESETN : signal is "xilinx.com:signal:reset:1.0 RST." & INTERFACENAME & "_ARESETN RST"; + attribute X_INTERFACE_PARAMETER of M_AXIS_ARESETN : signal is + "XIL_INTERFACENAME RST." & INTERFACENAME & "_ARESETN, " & + "POLARITY ACTIVE_LOW"; + + attribute X_INTERFACE_INFO of M_AXIS_ACLK : signal is "xilinx.com:signal:clock:1.0 CLK." & INTERFACENAME & "_ACLK CLK"; + attribute X_INTERFACE_PARAMETER of M_AXIS_ACLK : signal is + "XIL_INTERFACENAME CLK." & INTERFACENAME & "_ACLK, " & + "ASSOCIATED_BUSIF " & INTERFACENAME & ", " & + "ASSOCIATED_RESET " & INTERFACENAME & "_ARESETN"; + + signal M_AXIS_Master : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal M_AXIS_Slave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + +begin + + axisClk <= M_AXIS_ACLK; + + M_AXIS_Master <= axisMaster; + axisSlave <= M_AXIS_Slave; + + U_RstSync : entity surf.RstSync + generic map ( + IN_POLARITY_G => '0', + OUT_POLARITY_G => '1') + port map ( + clk => M_AXIS_ACLK, + asyncRst => M_AXIS_ARESETN, + syncRst => axisRst); + + M_AXIS_TVALID <= M_AXIS_Master.tValid; + M_AXIS_TDATA <= M_AXIS_Master.tData((8*TDATA_NUM_BYTES)-1 downto 0); + M_AXIS_TSTRB <= M_AXIS_Master.tStrb(TDATA_NUM_BYTES-1 downto 0) when(HAS_TSTRB /= 0) else (others => '1'); + M_AXIS_TKEEP <= M_AXIS_Master.tKeep(TDATA_NUM_BYTES-1 downto 0) when(HAS_TKEEP /= 0) else (others => '1'); + M_AXIS_TLAST <= M_AXIS_Master.tLast when(HAS_TLAST /= 0) else '0'; + M_AXIS_TDEST <= M_AXIS_Master.tDest(TDEST_WIDTH-1 downto 0); + M_AXIS_TID <= M_AXIS_Master.tId(TID_WIDTH-1 downto 0); + M_AXIS_TUSER <= M_AXIS_Master.tUser(TUSER_WIDTH-1 downto 0); + + M_AXIS_Slave.tReady <= M_AXIS_TREADY when(HAS_TREADY /= 0) else '1'; + +end mapping; diff --git a/axi/axi-stream/ip_integrator/MasterAxiStreamTerminateIpIntegrator.vhd b/axi/axi-stream/ip_integrator/MasterAxiStreamTerminateIpIntegrator.vhd new file mode 100644 index 0000000000..3b2b8d7d73 --- /dev/null +++ b/axi/axi-stream/ip_integrator/MasterAxiStreamTerminateIpIntegrator.vhd @@ -0,0 +1,85 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: IP Integrator Wrapper for terminating a MASTER AXI stream bus +------------------------------------------------------------------------------- +-- TCL Command: create_bd_cell -type module -reference MasterAxiStreamTerminateIpIntegrator MasterAxisTerm_0 +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity MasterAxiStreamTerminateIpIntegrator is + generic ( + INTERFACENAME : string := "M_AXIS"; + HAS_TLAST : natural range 0 to 1 := 1; + HAS_TKEEP : natural range 0 to 1 := 1; + HAS_TSTRB : natural range 0 to 1 := 0; + HAS_TREADY : natural range 0 to 1 := 1; + TUSER_WIDTH : natural range 1 to 8 := 2; + TID_WIDTH : natural range 1 to 8 := 1; + TDEST_WIDTH : natural range 1 to 8 := 1; + TDATA_NUM_BYTES : natural range 1 to 128 := 1); + port ( + -- IP Integrator AXI Stream Interface + M_AXIS_ACLK : in std_logic := '0'; + M_AXIS_ARESETN : in std_logic := '0'; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector((8*TDATA_NUM_BYTES)-1 downto 0); + M_AXIS_TSTRB : out std_logic_vector(TDATA_NUM_BYTES-1 downto 0); + M_AXIS_TKEEP : out std_logic_vector(TDATA_NUM_BYTES-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TDEST : out std_logic_vector(TDEST_WIDTH-1 downto 0); + M_AXIS_TID : out std_logic_vector(TID_WIDTH-1 downto 0); + M_AXIS_TUSER : out std_logic_vector(TUSER_WIDTH-1 downto 0); + M_AXIS_TREADY : in std_logic := '1'); +end MasterAxiStreamTerminateIpIntegrator; + +architecture mapping of MasterAxiStreamTerminateIpIntegrator is + +begin + + U_ShimLayer : entity surf.MasterAxiStreamIpIntegrator + generic map ( + HAS_TLAST => HAS_TLAST, + HAS_TKEEP => HAS_TKEEP, + HAS_TSTRB => HAS_TSTRB, + HAS_TREADY => HAS_TREADY, + TUSER_WIDTH => TUSER_WIDTH, + TID_WIDTH => TID_WIDTH, + TDEST_WIDTH => TDEST_WIDTH, + TDATA_NUM_BYTES => TDATA_NUM_BYTES) + port map ( + -- IP Integrator AXI Stream Interface + M_AXIS_ACLK => M_AXIS_ACLK, + M_AXIS_ARESETN => M_AXIS_ARESETN, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TSTRB => M_AXIS_TSTRB, + M_AXIS_TKEEP => M_AXIS_TKEEP, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TDEST => M_AXIS_TDEST, + M_AXIS_TID => M_AXIS_TID, + M_AXIS_TUSER => M_AXIS_TUSER, + M_AXIS_TREADY => M_AXIS_TREADY, + -- SURF AXI Stream Interface + axisClk => open, + axisRst => open, + axisMaster => AXI_STREAM_MASTER_INIT_C, + axisSlave => open); + +end mapping; diff --git a/axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd b/axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd new file mode 100644 index 0000000000..c5b6054999 --- /dev/null +++ b/axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd @@ -0,0 +1,118 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Common shim layer between IP Integrator interface and surf AXI Stream interface +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity SlaveAxiStreamIpIntegrator is + generic ( + INTERFACENAME : string := "S_AXIS"; + HAS_TLAST : natural range 0 to 1 := 1; + HAS_TKEEP : natural range 0 to 1 := 1; + HAS_TSTRB : natural range 0 to 1 := 0; + HAS_TREADY : natural range 0 to 1 := 1; + TUSER_WIDTH : natural range 1 to 8 := 2; + TID_WIDTH : natural range 1 to 8 := 1; + TDEST_WIDTH : natural range 1 to 8 := 1; + TDATA_NUM_BYTES : natural range 1 to 128 := 1); + port ( + -- IP Integrator AXI Stream Interface + S_AXIS_ACLK : in std_logic := '0'; + S_AXIS_ARESETN : in std_logic := '0'; + S_AXIS_TVALID : in std_logic := '0'; + S_AXIS_TDATA : in std_logic_vector((8*TDATA_NUM_BYTES)-1 downto 0) := (others => '0'); + S_AXIS_TSTRB : in std_logic_vector(TDATA_NUM_BYTES-1 downto 0) := (others => '0'); + S_AXIS_TKEEP : in std_logic_vector(TDATA_NUM_BYTES-1 downto 0) := (others => '0'); + S_AXIS_TLAST : in std_logic := '0'; + S_AXIS_TDEST : in std_logic_vector(TDEST_WIDTH-1 downto 0) := (others => '0'); + S_AXIS_TID : in std_logic_vector(TID_WIDTH-1 downto 0) := (others => '0'); + S_AXIS_TUSER : in std_logic_vector(TUSER_WIDTH-1 downto 0) := (others => '0'); + S_AXIS_TREADY : out std_logic; + -- SURF AXI Stream Interface + axisClk : out sl; + axisRst : out sl; + axisMaster : out AxiStreamMasterType; + axisSlave : in AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C); +end SlaveAxiStreamIpIntegrator; + +architecture mapping of SlaveAxiStreamIpIntegrator is + + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_PARAMETER : string; + + attribute X_INTERFACE_INFO of S_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 " & INTERFACENAME & " TVALID"; + attribute X_INTERFACE_INFO of S_AXIS_TLAST : signal is "xilinx.com:interface:axis:1.0 " & INTERFACENAME & " TLAST"; + attribute X_INTERFACE_INFO of S_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 " & INTERFACENAME & " TDATA"; + attribute X_INTERFACE_INFO of S_AXIS_TKEEP : signal is "xilinx.com:interface:axis:1.0 " & INTERFACENAME & " TKEEP"; + attribute X_INTERFACE_INFO of S_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 " & INTERFACENAME & " TREADY"; + attribute X_INTERFACE_PARAMETER of S_AXIS_TDATA : signal is + "XIL_INTERFACENAME " & INTERFACENAME & ", " & + "LAYERED_METADATA undef, " & + "HAS_TLAST " & integer'image(HAS_TLAST) & ", " & + "HAS_TKEEP " & integer'image(HAS_TKEEP) & ", " & + "HAS_TSTRB " & integer'image(HAS_TSTRB) & ", " & + "HAS_TREADY " & integer'image(HAS_TREADY) & ", " & + "TUSER_WIDTH " & integer'image(TUSER_WIDTH) & ", " & + "TID_WIDTH " & integer'image(TID_WIDTH) & ", " & + "TDEST_WIDTH " & integer'image(TDEST_WIDTH) & ", " & + "TDATA_NUM_BYTES " & integer'image(TDATA_NUM_BYTES); + + attribute X_INTERFACE_INFO of S_AXIS_ARESETN : signal is "xilinx.com:signal:reset:1.0 RST." & INTERFACENAME & "_ARESETN RST"; + attribute X_INTERFACE_PARAMETER of S_AXIS_ARESETN : signal is + "XIL_INTERFACENAME RST." & INTERFACENAME & "_ARESETN, " & + "POLARITY ACTIVE_LOW"; + + attribute X_INTERFACE_INFO of S_AXIS_ACLK : signal is "xilinx.com:signal:clock:1.0 CLK." & INTERFACENAME & "_ACLK CLK"; + attribute X_INTERFACE_PARAMETER of S_AXIS_ACLK : signal is + "XIL_INTERFACENAME CLK." & INTERFACENAME & "_ACLK, " & + "ASSOCIATED_BUSIF " & INTERFACENAME & ", " & + "ASSOCIATED_RESET " & INTERFACENAME & "_ARESETN"; + + signal S_AXIS_Master : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal S_AXIS_Slave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + +begin + + axisClk <= S_AXIS_ACLK; + + axisMaster <= S_AXIS_Master; + S_AXIS_Slave <= axisSlave; + + U_RstSync : entity surf.RstSync + generic map ( + IN_POLARITY_G => '0', + OUT_POLARITY_G => '1') + port map ( + clk => S_AXIS_ACLK, + asyncRst => S_AXIS_ARESETN, + syncRst => axisRst); + + S_AXIS_Master.tValid <= S_AXIS_TVALID; + S_AXIS_Master.tData((8*TDATA_NUM_BYTES)-1 downto 0) <= S_AXIS_TDATA; + S_AXIS_Master.tStrb(TDATA_NUM_BYTES-1 downto 0) <= S_AXIS_TSTRB when(HAS_TSTRB /= 0) else (others => '1'); + S_AXIS_Master.tKeep(TDATA_NUM_BYTES-1 downto 0) <= S_AXIS_TKEEP when(HAS_TKEEP /= 0) else (others => '1'); + S_AXIS_Master.tLast <= S_AXIS_TLAST when(HAS_TLAST /= 0) else '0'; + S_AXIS_Master.tDest(TDEST_WIDTH-1 downto 0) <= S_AXIS_TDEST; + S_AXIS_Master.tId(TID_WIDTH-1 downto 0) <= S_AXIS_TID; + S_AXIS_Master.tUser(TUSER_WIDTH-1 downto 0) <= S_AXIS_TUSER; + + S_AXIS_TREADY <= S_AXIS_Slave.tReady when(HAS_TREADY /= 0) else '1'; + +end mapping; diff --git a/axi/axi-stream/ip_integrator/SlaveAxiStreamTerminateIpIntegrator.vhd b/axi/axi-stream/ip_integrator/SlaveAxiStreamTerminateIpIntegrator.vhd new file mode 100644 index 0000000000..7218506f8c --- /dev/null +++ b/axi/axi-stream/ip_integrator/SlaveAxiStreamTerminateIpIntegrator.vhd @@ -0,0 +1,81 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: IP Integrator Wrapper for terminating a SLAVE AXI stream bus +------------------------------------------------------------------------------- +-- TCL Command: create_bd_cell -type module -reference SlaveAxiStreamTerminateIpIntegrator SlaveAxisTerm_0 +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity SlaveAxiStreamTerminateIpIntegrator is + generic ( + INTERFACENAME : string := "S_AXIS"; + HAS_TLAST : natural range 0 to 1 := 1; + HAS_TKEEP : natural range 0 to 1 := 1; + HAS_TSTRB : natural range 0 to 1 := 0; + HAS_TREADY : natural range 0 to 1 := 1; + TUSER_WIDTH : natural range 1 to 8 := 2; + TID_WIDTH : natural range 1 to 8 := 1; + TDEST_WIDTH : natural range 1 to 8 := 1; + TDATA_NUM_BYTES : natural range 1 to 128 := 1); + port ( + -- IP Integrator AXI Stream Interface + S_AXIS_TVALID : in std_logic := '0'; + S_AXIS_TDATA : in std_logic_vector((8*TDATA_NUM_BYTES)-1 downto 0) := (others => '0'); + S_AXIS_TSTRB : in std_logic_vector(TDATA_NUM_BYTES-1 downto 0) := (others => '0'); + S_AXIS_TKEEP : in std_logic_vector(TDATA_NUM_BYTES-1 downto 0) := (others => '0'); + S_AXIS_TLAST : in std_logic := '0'; + S_AXIS_TDEST : in std_logic_vector(TDEST_WIDTH-1 downto 0) := (others => '0'); + S_AXIS_TID : in std_logic_vector(TID_WIDTH-1 downto 0) := (others => '0'); + S_AXIS_TUSER : in std_logic_vector(TUSER_WIDTH-1 downto 0) := (others => '0'); + S_AXIS_TREADY : out std_logic); +end SlaveAxiStreamTerminateIpIntegrator; + +architecture mapping of SlaveAxiStreamTerminateIpIntegrator is + +begin + + U_ShimLayer : entity surf.SlaveAxiStreamIpIntegrator + generic map ( + HAS_TLAST => HAS_TLAST, + HAS_TKEEP => HAS_TKEEP, + HAS_TSTRB => HAS_TSTRB, + HAS_TREADY => HAS_TREADY, + TUSER_WIDTH => TUSER_WIDTH, + TID_WIDTH => TID_WIDTH, + TDEST_WIDTH => TDEST_WIDTH, + TDATA_NUM_BYTES => TDATA_NUM_BYTES) + port map ( + -- IP Integrator AXI Stream Interface + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TSTRB => S_AXIS_TSTRB, + S_AXIS_TKEEP => S_AXIS_TKEEP, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TDEST => S_AXIS_TDEST, + S_AXIS_TID => S_AXIS_TID, + S_AXIS_TUSER => S_AXIS_TUSER, + S_AXIS_TREADY => S_AXIS_TREADY, + -- SURF AXI Stream Interface + axisClk => open, + axisRst => open, + axisMaster => open, + axisSlave => AXI_STREAM_SLAVE_FORCE_C); + +end mapping; diff --git a/axi/axi-stream/ruckus.tcl b/axi/axi-stream/ruckus.tcl index 6e82fc29b1..7598c569ff 100644 --- a/axi/axi-stream/ruckus.tcl +++ b/axi/axi-stream/ruckus.tcl @@ -3,6 +3,7 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Load Source Code loadSource -lib surf -dir "$::DIR_PATH/rtl" +loadSource -lib surf -dir "$::DIR_PATH/ip_integrator" # Load Simulation loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb" diff --git a/axi/axi4/ip_integrator/MasterAxiIpIntegrator.vhd b/axi/axi4/ip_integrator/MasterAxiIpIntegrator.vhd new file mode 100644 index 0000000000..c21b3e3d2b --- /dev/null +++ b/axi/axi4/ip_integrator/MasterAxiIpIntegrator.vhd @@ -0,0 +1,266 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Common shim layer between IP Integrator interface and surf AXI interface +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiPkg.all; + +entity MasterAxiIpIntegrator is + generic ( + INTERFACENAME : string := "M_AXI"; + EN_ERROR_RESP : boolean := false; + MAX_BURST_LENGTH : positive range 1 to 256 := 256; -- [1, 256] + NUM_WRITE_OUTSTANDING : natural range 0 to 32 := 1; -- [0, 32] + NUM_READ_OUTSTANDING : natural range 0 to 32 := 1; -- [0, 32] + SUPPORTS_NARROW_BURST : natural range 0 to 1 := 1; +-- BUSER_WIDTH : positive := 1; +-- RUSER_WIDTH : positive := 1; +-- WUSER_WIDTH : positive := 1; +-- ARUSER_WIDTH : positive := 1; +-- AWUSER_WIDTH : positive := 1; + ADDR_WIDTH : positive range 1 to 64 := 32; -- [1, 64] + ID_WIDTH : positive := 1; + DATA_WIDTH : positive range 32 to 1024 := 32; -- [32,64,128,256,512,1024] + HAS_BURST : natural range 0 to 1 := 1; + HAS_CACHE : natural range 0 to 1 := 1; + HAS_LOCK : natural range 0 to 1 := 1; + HAS_PROT : natural range 0 to 1 := 1; + HAS_QOS : natural range 0 to 1 := 1; + HAS_REGION : natural range 0 to 1 := 1; + HAS_WSTRB : natural range 0 to 1 := 1; + HAS_BRESP : natural range 0 to 1 := 1; + HAS_RRESP : natural range 0 to 1 := 1); + port ( + -- IP Integrator AXI-Lite Interface + M_AXI_ACLK : in std_logic; + M_AXI_ARESETN : in std_logic; + M_AXI_AWID : out std_logic_vector(ID_WIDTH-1 downto 0); + M_AXI_AWADDR : out std_logic_vector(ADDR_WIDTH-1 downto 0); + M_AXI_AWLEN : out std_logic_vector(7 downto 0); + M_AXI_AWSIZE : out std_logic_vector(2 downto 0); + M_AXI_AWBURST : out std_logic_vector(1 downto 0); + M_AXI_AWLOCK : out std_logic_vector(1 downto 0); + M_AXI_AWCACHE : out std_logic_vector(3 downto 0); + M_AXI_AWPROT : out std_logic_vector(2 downto 0); + M_AXI_AWREGION : out std_logic_vector(3 downto 0); + M_AXI_AWQOS : out std_logic_vector(3 downto 0); +-- M_AXI_AWUSER : out std_logic_vector(AWUSER_WIDTH-1 downto 0); + M_AXI_AWVALID : out std_logic; + M_AXI_AWREADY : in std_logic; + M_AXI_WID : out std_logic_vector(ID_WIDTH-1 downto 0); + M_AXI_WDATA : out std_logic_vector(DATA_WIDTH-1 downto 0); + M_AXI_WSTRB : out std_logic_vector((DATA_WIDTH/8)-1 downto 0); + M_AXI_WLAST : out std_logic; +-- M_AXI_WUSER : out std_logic_vector(WUSER_WIDTH-1 downto 0); + M_AXI_WVALID : out std_logic; + M_AXI_WREADY : in std_logic; + M_AXI_BID : in std_logic_vector(ID_WIDTH-1 downto 0); + M_AXI_BRESP : in std_logic_vector(1 downto 0); +-- M_AXI_BUSER : in std_logic_vector(BUSER_WIDTH downto 0); + M_AXI_BVALID : in std_logic; + M_AXI_BREADY : out std_logic; + M_AXI_ARID : out std_logic_vector(ID_WIDTH-1 downto 0); + M_AXI_ARADDR : out std_logic_vector(ADDR_WIDTH-1 downto 0); + M_AXI_ARLEN : out std_logic_vector(7 downto 0); + M_AXI_ARSIZE : out std_logic_vector(2 downto 0); + M_AXI_ARBURST : out std_logic_vector(1 downto 0); + M_AXI_ARLOCK : out std_logic_vector(1 downto 0); + M_AXI_ARCACHE : out std_logic_vector(3 downto 0); + M_AXI_ARPROT : out std_logic_vector(2 downto 0); + M_AXI_ARREGION : out std_logic_vector(3 downto 0); + M_AXI_ARQOS : out std_logic_vector(3 downto 0); +-- M_AXI_ARUSER : out std_logic_vector(ARUSER_WIDTH-1 downto 0); + M_AXI_ARVALID : out std_logic; + M_AXI_ARREADY : in std_logic; + M_AXI_RID : in std_logic_vector(ID_WIDTH-1 downto 0); + M_AXI_RDATA : in std_logic_vector(DATA_WIDTH-1 downto 0); + M_AXI_RRESP : in std_logic_vector(1 downto 0); + M_AXI_RLAST : in std_logic; +-- M_AXI_RUSER : in std_logic_vector(RUSER_WIDTH-1 downto 0); + M_AXI_RVALID : in std_logic; + M_AXI_RREADY : out std_logic; + -- SURF AXI Interface + axiClk : out sl; + axiRst : out sl; + axiReadMaster : in AxiReadMasterType; + axiReadSlave : out AxiReadSlaveType; + axiWriteMaster : in AxiWriteMasterType; + axiWriteSlave : out AxiWriteSlaveType); +end MasterAxiIpIntegrator; + +architecture mapping of MasterAxiIpIntegrator is + + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_PARAMETER : string; + + attribute X_INTERFACE_INFO of M_AXI_AWID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWID"; + attribute X_INTERFACE_INFO of M_AXI_AWADDR : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWADDR"; + attribute X_INTERFACE_INFO of M_AXI_AWLEN : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWLEN"; + attribute X_INTERFACE_INFO of M_AXI_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWSIZE"; + attribute X_INTERFACE_INFO of M_AXI_AWBURST : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWBURST"; + attribute X_INTERFACE_INFO of M_AXI_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWLOCK"; + attribute X_INTERFACE_INFO of M_AXI_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWCACHE"; + attribute X_INTERFACE_INFO of M_AXI_AWPROT : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWPROT"; + attribute X_INTERFACE_INFO of M_AXI_AWREGION : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWREGION"; + attribute X_INTERFACE_INFO of M_AXI_AWQOS : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWQOS"; +-- attribute X_INTERFACE_INFO of M_AXI_AWUSER : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWUSER"; + attribute X_INTERFACE_INFO of M_AXI_AWVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWVALID"; + attribute X_INTERFACE_INFO of M_AXI_AWREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWREADY"; + attribute X_INTERFACE_INFO of M_AXI_WID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WID"; + attribute X_INTERFACE_INFO of M_AXI_WDATA : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WDATA"; + attribute X_INTERFACE_INFO of M_AXI_WSTRB : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WSTRB"; + attribute X_INTERFACE_INFO of M_AXI_WLAST : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WLAST"; +-- attribute X_INTERFACE_INFO of M_AXI_WUSER : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WUSER"; + attribute X_INTERFACE_INFO of M_AXI_WVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WVALID"; + attribute X_INTERFACE_INFO of M_AXI_WREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WREADY"; + attribute X_INTERFACE_INFO of M_AXI_BID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BID"; + attribute X_INTERFACE_INFO of M_AXI_BRESP : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BRESP"; +-- attribute X_INTERFACE_INFO of M_AXI_BUSER : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BUSER"; + attribute X_INTERFACE_INFO of M_AXI_BVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BVALID"; + attribute X_INTERFACE_INFO of M_AXI_BREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BREADY"; + attribute X_INTERFACE_INFO of M_AXI_ARID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARID"; + attribute X_INTERFACE_INFO of M_AXI_ARADDR : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARADDR"; + attribute X_INTERFACE_INFO of M_AXI_ARLEN : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARLEN"; + attribute X_INTERFACE_INFO of M_AXI_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARSIZE"; + attribute X_INTERFACE_INFO of M_AXI_ARBURST : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARBURST"; + attribute X_INTERFACE_INFO of M_AXI_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARLOCK"; + attribute X_INTERFACE_INFO of M_AXI_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARCACHE"; + attribute X_INTERFACE_INFO of M_AXI_ARPROT : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARPROT"; + attribute X_INTERFACE_INFO of M_AXI_ARREGION : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARREGION"; + attribute X_INTERFACE_INFO of M_AXI_ARQOS : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARQOS"; +-- attribute X_INTERFACE_INFO of M_AXI_ARUSER : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARUSER"; + attribute X_INTERFACE_INFO of M_AXI_ARVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARVALID"; + attribute X_INTERFACE_INFO of M_AXI_ARREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARREADY"; + attribute X_INTERFACE_INFO of M_AXI_RID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RID"; + attribute X_INTERFACE_INFO of M_AXI_RDATA : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RDATA"; + attribute X_INTERFACE_INFO of M_AXI_RRESP : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RRESP"; + attribute X_INTERFACE_INFO of M_AXI_RLAST : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RLAST"; +-- attribute X_INTERFACE_INFO of M_AXI_RUSER : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RUSER"; + attribute X_INTERFACE_INFO of M_AXI_RVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RVALID"; + attribute X_INTERFACE_INFO of M_AXI_RREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RREADY"; + attribute X_INTERFACE_PARAMETER of M_AXI_AWADDR : signal is + "XIL_INTERFACENAME " & INTERFACENAME & ", " & + "PROTOCOL AXI4, " & + "MAX_BURST_LENGTH " & integer'image(MAX_BURST_LENGTH) & ", " & + "NUM_WRITE_OUTSTANDING " & integer'image(NUM_WRITE_OUTSTANDING) & ", " & + "NUM_READ_OUTSTANDING " & integer'image(NUM_READ_OUTSTANDING) & ", " & + "SUPPORTS_NARROW_BURST " & integer'image(SUPPORTS_NARROW_BURST) & ", " & +-- "BUSER_WIDTH " & integer'image(BUSER_WIDTH) & ", " & +-- "RUSER_WIDTH " & integer'image(RUSER_WIDTH) & ", " & +-- "WUSER_WIDTH " & integer'image(WUSER_WIDTH) & ", " & +-- "ARUSER_WIDTH " & integer'image(ARUSER_WIDTH) & ", " & +-- "AWUSER_WIDTH " & integer'image(AWUSER_WIDTH) & ", " & + "ADDR_WIDTH " & integer'image(ADDR_WIDTH) & ", " & + "ID_WIDTH " & integer'image(ID_WIDTH) & ", " & + "DATA_WIDTH " & integer'image(DATA_WIDTH) & ", " & + "HAS_BURST " & integer'image(HAS_BURST) & ", " & + "HAS_CACHE " & integer'image(HAS_CACHE) & ", " & + "HAS_LOCK " & integer'image(HAS_LOCK) & ", " & + "HAS_PROT " & integer'image(HAS_PROT) & ", " & + "HAS_QOS " & integer'image(HAS_QOS) & ", " & + "HAS_REGION " & integer'image(HAS_REGION) & ", " & + "HAS_WSTRB " & integer'image(HAS_WSTRB) & ", " & + "HAS_BRESP " & integer'image(HAS_BRESP) & ", " & + "HAS_RRESP " & integer'image(HAS_RRESP); + + attribute X_INTERFACE_INFO of M_AXI_ARESETN : signal is "xilinx.com:signal:reset:1.0 RST." & INTERFACENAME & "_ARESETN RST"; + attribute X_INTERFACE_PARAMETER of M_AXI_ARESETN : signal is + "XIL_INTERFACENAME RST." & INTERFACENAME & "_ARESETN, " & + "POLARITY ACTIVE_LOW"; + + attribute X_INTERFACE_INFO of M_AXI_ACLK : signal is "xilinx.com:signal:clock:1.0 CLK." & INTERFACENAME & "_ACLK CLK"; + attribute X_INTERFACE_PARAMETER of M_AXI_ACLK : signal is + "XIL_INTERFACENAME CLK." & INTERFACENAME & "_ACLK, " & + "ASSOCIATED_BUSIF " & INTERFACENAME & ", " & + "ASSOCIATED_RESET " & INTERFACENAME & "_ARESETN"; + + signal M_AXI_ReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; + signal M_AXI_ReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; + signal M_AXI_WriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + signal M_AXI_WriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; + +begin + + axiClk <= M_AXI_ACLK; + + M_AXI_ReadMaster <= axiReadMaster; + axiReadSlave <= M_AXI_ReadSlave; + + M_AXI_WriteMaster <= axiWriteMaster; + axiWriteSlave <= M_AXI_WriteSlave; + + U_RstSync : entity surf.RstSync + generic map ( + IN_POLARITY_G => '0', + OUT_POLARITY_G => '1') + port map ( + clk => M_AXI_ACLK, + asyncRst => M_AXI_ARESETN, + syncRst => axiRst); + + M_AXI_AWID <= M_AXI_WriteMaster.awid(ID_WIDTH-1 downto 0); + M_AXI_AWADDR <= M_AXI_WriteMaster.awaddr(ADDR_WIDTH-1 downto 0); + M_AXI_AWLEN <= M_AXI_WriteMaster.awlen(7 downto 0); + M_AXI_AWSIZE <= M_AXI_WriteMaster.awsize(2 downto 0); + M_AXI_AWBURST <= M_AXI_WriteMaster.awburst(1 downto 0); + M_AXI_AWLOCK <= M_AXI_WriteMaster.awlock(1 downto 0); + M_AXI_AWCACHE <= M_AXI_WriteMaster.awcache(3 downto 0); + M_AXI_AWPROT <= M_AXI_WriteMaster.awprot; + M_AXI_AWREGION <= M_AXI_WriteMaster.awregion(3 downto 0); + M_AXI_AWQOS <= M_AXI_WriteMaster.awqos(3 downto 0); +-- M_AXI_AWUSER <= M_AXI_WriteMaster.awuser(AWUSER_WIDTH-1 downto 0); + M_AXI_AWVALID <= M_AXI_WriteMaster.awvalid; + M_AXI_WID <= M_AXI_WriteMaster.wid(ID_WIDTH-1 downto 0); + M_AXI_WDATA <= M_AXI_WriteMaster.wdata(DATA_WIDTH-1 downto 0); + M_AXI_WSTRB <= M_AXI_WriteMaster.wstrb((DATA_WIDTH/8)-1 downto 0) when(HAS_WSTRB /= 0) else (others => '1'); + M_AXI_WLAST <= M_AXI_WriteMaster.wlast; +-- M_AXI_WUSER <= M_AXI_WriteMaster.wuser(WUSER_WIDTH-1 downto 0); + M_AXI_WVALID <= M_AXI_WriteMaster.wvalid; + M_AXI_BREADY <= M_AXI_WriteMaster.bready; + + M_AXI_WriteSlave.awready <= M_AXI_AWREADY; + M_AXI_WriteSlave.wready <= M_AXI_WREADY; + M_AXI_WriteSlave.bid(ID_WIDTH-1 downto 0) <= M_AXI_BID; + M_AXI_WriteSlave.bresp <= M_AXI_BRESP when(EN_ERROR_RESP and (HAS_BRESP /= 0)) else "00"; +-- M_AXI_WriteSlave.buser(BUSER_WIDTH-1 downto 0) <= M_AXI_BUSER; + M_AXI_WriteSlave.bvalid <= M_AXI_BVALID; + + M_AXI_ARID <= M_AXI_ReadMaster.arid(ID_WIDTH-1 downto 0); + M_AXI_ARADDR <= M_AXI_ReadMaster.araddr(ADDR_WIDTH-1 downto 0); + M_AXI_ARLEN <= M_AXI_ReadMaster.arlen; + M_AXI_ARSIZE <= M_AXI_ReadMaster.arsize; + M_AXI_ARBURST <= M_AXI_ReadMaster.arburst; + M_AXI_ARLOCK <= M_AXI_ReadMaster.arlock; + M_AXI_ARCACHE <= M_AXI_ReadMaster.arcache; + M_AXI_ARPROT <= M_AXI_ReadMaster.arprot; + M_AXI_ARREGION <= M_AXI_ReadMaster.arregion(3 downto 0); + M_AXI_ARQOS <= M_AXI_ReadMaster.arqos(3 downto 0); +-- M_AXI_ARUSER <= M_AXI_ReadMaster.aruser(ARUSER_WIDTH-1 downto 0); + M_AXI_ARVALID <= M_AXI_ReadMaster.arvalid; + M_AXI_RREADY <= M_AXI_ReadMaster.rready; + + M_AXI_ReadSlave.arready <= M_AXI_ARREADY; + M_AXI_ReadSlave.rid(ID_WIDTH-1 downto 0) <= M_AXI_RID; + M_AXI_ReadSlave.rdata(DATA_WIDTH-1 downto 0) <= M_AXI_RDATA; + M_AXI_ReadSlave.rresp <= M_AXI_RRESP when(EN_ERROR_RESP and (HAS_RRESP /= 0)) else "00"; + M_AXI_ReadSlave.rlast <= M_AXI_RLAST; +-- M_AXI_ReadSlave.ruser(RUSER_WIDTH-1 downto 0) <= M_AXI_RUSER; + M_AXI_ReadSlave.rvalid <= M_AXI_RVALID; + +end mapping; diff --git a/axi/axi4/ip_integrator/SlaveAxiIpIntegrator.vhd b/axi/axi4/ip_integrator/SlaveAxiIpIntegrator.vhd new file mode 100644 index 0000000000..231c81f6d7 --- /dev/null +++ b/axi/axi4/ip_integrator/SlaveAxiIpIntegrator.vhd @@ -0,0 +1,266 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Common shim layer between IP Integrator interface and surf AXI interface +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiPkg.all; + +entity SlaveAxiIpIntegrator is + generic ( + INTERFACENAME : string := "S_AXI"; + EN_ERROR_RESP : boolean := false; + MAX_BURST_LENGTH : positive range 1 to 256 := 256; -- [1, 256] + NUM_WRITE_OUTSTANDING : natural range 0 to 32 := 1; -- [0, 32] + NUM_READ_OUTSTANDING : natural range 0 to 32 := 1; -- [0, 32] + SUPPORTS_NARROW_BURST : natural range 0 to 1 := 1; +-- BUSER_WIDTH : positive := 1; +-- RUSER_WIDTH : positive := 1; +-- WUSER_WIDTH : positive := 1; +-- ARUSER_WIDTH : positive := 1; +-- AWUSER_WIDTH : positive := 1; + ADDR_WIDTH : positive range 1 to 64 := 32; -- [1, 64] + ID_WIDTH : positive := 1; + DATA_WIDTH : positive range 32 to 1024 := 32; -- [32,64,128,256,512,1024] + HAS_BURST : natural range 0 to 1 := 1; + HAS_CACHE : natural range 0 to 1 := 1; + HAS_LOCK : natural range 0 to 1 := 1; + HAS_PROT : natural range 0 to 1 := 1; + HAS_QOS : natural range 0 to 1 := 1; + HAS_REGION : natural range 0 to 1 := 1; + HAS_WSTRB : natural range 0 to 1 := 1; + HAS_BRESP : natural range 0 to 1 := 1; + HAS_RRESP : natural range 0 to 1 := 1); + port ( + -- IP Integrator AXI-Lite Interface + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWID : in std_logic_vector(ID_WIDTH-1 downto 0); + S_AXI_AWADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0); + S_AXI_AWLEN : in std_logic_vector(7 downto 0); + S_AXI_AWSIZE : in std_logic_vector(2 downto 0); + S_AXI_AWBURST : in std_logic_vector(1 downto 0); + S_AXI_AWLOCK : in std_logic_vector(1 downto 0); + S_AXI_AWCACHE : in std_logic_vector(3 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWREGION : in std_logic_vector(3 downto 0); + S_AXI_AWQOS : in std_logic_vector(3 downto 0); +-- S_AXI_AWUSER : in std_logic_vector(AWUSER_WIDTH-1 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WID : in std_logic_vector(ID_WIDTH-1 downto 0); + S_AXI_WDATA : in std_logic_vector(DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((DATA_WIDTH/8)-1 downto 0); + S_AXI_WLAST : in std_logic; +-- S_AXI_WUSER : in std_logic_vector(WUSER_WIDTH-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BID : out std_logic_vector(ID_WIDTH-1 downto 0); + S_AXI_BRESP : out std_logic_vector(1 downto 0); +-- S_AXI_BUSER : out std_logic_vector(BUSER_WIDTH downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARID : in std_logic_vector(ID_WIDTH-1 downto 0); + S_AXI_ARADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0); + S_AXI_ARLEN : in std_logic_vector(7 downto 0); + S_AXI_ARSIZE : in std_logic_vector(2 downto 0); + S_AXI_ARBURST : in std_logic_vector(1 downto 0); + S_AXI_ARLOCK : in std_logic_vector(1 downto 0); + S_AXI_ARCACHE : in std_logic_vector(3 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARREGION : in std_logic_vector(3 downto 0); + S_AXI_ARQOS : in std_logic_vector(3 downto 0); +-- S_AXI_ARUSER : in std_logic_vector(ARUSER_WIDTH-1 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RID : out std_logic_vector(ID_WIDTH-1 downto 0); + S_AXI_RDATA : out std_logic_vector(DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RLAST : out std_logic; +-- S_AXI_RUSER : out std_logic_vector(RUSER_WIDTH-1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic; + -- SURF AXI Interface + axiClk : out sl; + axiRst : out sl; + axiReadMaster : out AxiReadMasterType; + axiReadSlave : in AxiReadSlaveType; + axiWriteMaster : out AxiWriteMasterType; + axiWriteSlave : in AxiWriteSlaveType); +end SlaveAxiIpIntegrator; + +architecture mapping of SlaveAxiIpIntegrator is + + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_PARAMETER : string; + + attribute X_INTERFACE_INFO of S_AXI_AWID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWID"; + attribute X_INTERFACE_INFO of S_AXI_AWADDR : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWADDR"; + attribute X_INTERFACE_INFO of S_AXI_AWLEN : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWLEN"; + attribute X_INTERFACE_INFO of S_AXI_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWSIZE"; + attribute X_INTERFACE_INFO of S_AXI_AWBURST : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWBURST"; + attribute X_INTERFACE_INFO of S_AXI_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWLOCK"; + attribute X_INTERFACE_INFO of S_AXI_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWCACHE"; + attribute X_INTERFACE_INFO of S_AXI_AWPROT : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWPROT"; + attribute X_INTERFACE_INFO of S_AXI_AWREGION : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWREGION"; + attribute X_INTERFACE_INFO of S_AXI_AWQOS : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWQOS"; +-- attribute X_INTERFACE_INFO of S_AXI_AWUSER : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWUSER"; + attribute X_INTERFACE_INFO of S_AXI_AWVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWVALID"; + attribute X_INTERFACE_INFO of S_AXI_AWREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " AWREADY"; + attribute X_INTERFACE_INFO of S_AXI_WID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WID"; + attribute X_INTERFACE_INFO of S_AXI_WDATA : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WDATA"; + attribute X_INTERFACE_INFO of S_AXI_WSTRB : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WSTRB"; + attribute X_INTERFACE_INFO of S_AXI_WLAST : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WLAST"; +-- attribute X_INTERFACE_INFO of S_AXI_WUSER : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WUSER"; + attribute X_INTERFACE_INFO of S_AXI_WVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WVALID"; + attribute X_INTERFACE_INFO of S_AXI_WREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " WREADY"; + attribute X_INTERFACE_INFO of S_AXI_BID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BID"; + attribute X_INTERFACE_INFO of S_AXI_BRESP : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BRESP"; +-- attribute X_INTERFACE_INFO of S_AXI_BUSER : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BUSER"; + attribute X_INTERFACE_INFO of S_AXI_BVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BVALID"; + attribute X_INTERFACE_INFO of S_AXI_BREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " BREADY"; + attribute X_INTERFACE_INFO of S_AXI_ARID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARID"; + attribute X_INTERFACE_INFO of S_AXI_ARADDR : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARADDR"; + attribute X_INTERFACE_INFO of S_AXI_ARLEN : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARLEN"; + attribute X_INTERFACE_INFO of S_AXI_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARSIZE"; + attribute X_INTERFACE_INFO of S_AXI_ARBURST : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARBURST"; + attribute X_INTERFACE_INFO of S_AXI_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARLOCK"; + attribute X_INTERFACE_INFO of S_AXI_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARCACHE"; + attribute X_INTERFACE_INFO of S_AXI_ARPROT : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARPROT"; + attribute X_INTERFACE_INFO of S_AXI_ARREGION : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARREGION"; + attribute X_INTERFACE_INFO of S_AXI_ARQOS : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARQOS"; +-- attribute X_INTERFACE_INFO of S_AXI_ARUSER : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARUSER"; + attribute X_INTERFACE_INFO of S_AXI_ARVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARVALID"; + attribute X_INTERFACE_INFO of S_AXI_ARREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " ARREADY"; + attribute X_INTERFACE_INFO of S_AXI_RID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RID"; + attribute X_INTERFACE_INFO of S_AXI_RDATA : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RDATA"; + attribute X_INTERFACE_INFO of S_AXI_RRESP : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RRESP"; + attribute X_INTERFACE_INFO of S_AXI_RLAST : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RLAST"; +-- attribute X_INTERFACE_INFO of S_AXI_RUSER : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RUSER"; + attribute X_INTERFACE_INFO of S_AXI_RVALID : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RVALID"; + attribute X_INTERFACE_INFO of S_AXI_RREADY : signal is "xilinx.com:interface:aximm:1.0 " & INTERFACENAME & " RREADY"; + attribute X_INTERFACE_PARAMETER of S_AXI_AWADDR : signal is + "XIL_INTERFACENAME " & INTERFACENAME & ", " & + "PROTOCOL AXI4, " & + "MAX_BURST_LENGTH " & integer'image(MAX_BURST_LENGTH) & ", " & + "NUM_WRITE_OUTSTANDING " & integer'image(NUM_WRITE_OUTSTANDING) & ", " & + "NUM_READ_OUTSTANDING " & integer'image(NUM_READ_OUTSTANDING) & ", " & + "SUPPORTS_NARROW_BURST " & integer'image(SUPPORTS_NARROW_BURST) & ", " & +-- "BUSER_WIDTH " & integer'image(BUSER_WIDTH) & ", " & +-- "RUSER_WIDTH " & integer'image(RUSER_WIDTH) & ", " & +-- "WUSER_WIDTH " & integer'image(WUSER_WIDTH) & ", " & +-- "ARUSER_WIDTH " & integer'image(ARUSER_WIDTH) & ", " & +-- "AWUSER_WIDTH " & integer'image(AWUSER_WIDTH) & ", " & + "ADDR_WIDTH " & integer'image(ADDR_WIDTH) & ", " & + "ID_WIDTH " & integer'image(ID_WIDTH) & ", " & + "DATA_WIDTH " & integer'image(DATA_WIDTH) & ", " & + "HAS_BURST " & integer'image(HAS_BURST) & ", " & + "HAS_CACHE " & integer'image(HAS_CACHE) & ", " & + "HAS_LOCK " & integer'image(HAS_LOCK) & ", " & + "HAS_PROT " & integer'image(HAS_PROT) & ", " & + "HAS_QOS " & integer'image(HAS_QOS) & ", " & + "HAS_REGION " & integer'image(HAS_REGION) & ", " & + "HAS_WSTRB " & integer'image(HAS_WSTRB) & ", " & + "HAS_BRESP " & integer'image(HAS_BRESP) & ", " & + "HAS_RRESP " & integer'image(HAS_RRESP); + + attribute X_INTERFACE_INFO of S_AXI_ARESETN : signal is "xilinx.com:signal:reset:1.0 RST." & INTERFACENAME & "_ARESETN RST"; + attribute X_INTERFACE_PARAMETER of S_AXI_ARESETN : signal is + "XIL_INTERFACENAME RST." & INTERFACENAME & "_ARESETN, " & + "POLARITY ACTIVE_LOW"; + + attribute X_INTERFACE_INFO of S_AXI_ACLK : signal is "xilinx.com:signal:clock:1.0 CLK." & INTERFACENAME & "_ACLK CLK"; + attribute X_INTERFACE_PARAMETER of S_AXI_ACLK : signal is + "XIL_INTERFACENAME CLK." & INTERFACENAME & "_ACLK, " & + "ASSOCIATED_BUSIF " & INTERFACENAME & ", " & + "ASSOCIATED_RESET " & INTERFACENAME & "_ARESETN"; + + signal S_AXI_ReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; + signal S_AXI_ReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; + signal S_AXI_WriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + signal S_AXI_WriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; + +begin + + axiClk <= S_AXI_ACLK; + + axiReadMaster <= S_AXI_ReadMaster; + S_AXI_ReadSlave <= axiReadSlave; + + axiWriteMaster <= S_AXI_WriteMaster; + S_AXI_WriteSlave <= axiWriteSlave; + + U_RstSync : entity surf.RstSync + generic map ( + IN_POLARITY_G => '0', + OUT_POLARITY_G => '1') + port map ( + clk => S_AXI_ACLK, + asyncRst => S_AXI_ARESETN, + syncRst => axiRst); + + S_AXI_WriteMaster.awid(ID_WIDTH-1 downto 0) <= S_AXI_AWID; + S_AXI_WriteMaster.awaddr(ADDR_WIDTH-1 downto 0) <= S_AXI_AWADDR; + S_AXI_WriteMaster.awlen(7 downto 0) <= S_AXI_AWLEN; + S_AXI_WriteMaster.awsize(2 downto 0) <= S_AXI_AWSIZE; + S_AXI_WriteMaster.awburst(1 downto 0) <= S_AXI_AWBURST; + S_AXI_WriteMaster.awlock(1 downto 0) <= S_AXI_AWLOCK; + S_AXI_WriteMaster.awcache(3 downto 0) <= S_AXI_AWCACHE; + S_AXI_WriteMaster.awprot <= S_AXI_AWPROT; + S_AXI_WriteMaster.awregion(3 downto 0) <= S_AXI_AWREGION; + S_AXI_WriteMaster.awqos(3 downto 0) <= S_AXI_AWQOS; +-- S_AXI_WriteMaster.awuser(AWUSER_WIDTH-1 downto 0) <= S_AXI_AWUSER; + S_AXI_WriteMaster.awvalid <= S_AXI_AWVALID; + S_AXI_WriteMaster.wid(ID_WIDTH-1 downto 0) <= S_AXI_WID; + S_AXI_WriteMaster.wdata(DATA_WIDTH-1 downto 0) <= S_AXI_WDATA; + S_AXI_WriteMaster.wstrb((DATA_WIDTH/8)-1 downto 0) <= S_AXI_WSTRB when(HAS_WSTRB /= 0) else (others => '1'); + S_AXI_WriteMaster.wlast <= S_AXI_WLAST; +-- S_AXI_WriteMaster.wuser(WUSER_WIDTH-1 downto 0) <= S_AXI_WUSER; + S_AXI_WriteMaster.wvalid <= S_AXI_WVALID; + S_AXI_WriteMaster.bready <= S_AXI_BREADY; + + S_AXI_AWREADY <= S_AXI_WriteSlave.awready; + S_AXI_WREADY <= S_AXI_WriteSlave.wready; + S_AXI_BID <= S_AXI_WriteSlave.bid(ID_WIDTH-1 downto 0); + S_AXI_BRESP <= S_AXI_WriteSlave.bresp when(EN_ERROR_RESP and (HAS_BRESP /= 0)) else "00"; +-- S_AXI_BUSER <= S_AXI_WriteSlave.buser(BUSER_WIDTH-1 downto 0); + S_AXI_BVALID <= S_AXI_WriteSlave.bvalid; + + S_AXI_ReadMaster.arid(ID_WIDTH-1 downto 0) <= S_AXI_ARID; + S_AXI_ReadMaster.araddr(ADDR_WIDTH-1 downto 0) <= S_AXI_ARADDR; + S_AXI_ReadMaster.arlen <= S_AXI_ARLEN; + S_AXI_ReadMaster.arsize <= S_AXI_ARSIZE; + S_AXI_ReadMaster.arburst <= S_AXI_ARBURST; + S_AXI_ReadMaster.arlock <= S_AXI_ARLOCK; + S_AXI_ReadMaster.arcache <= S_AXI_ARCACHE; + S_AXI_ReadMaster.arprot <= S_AXI_ARPROT; + S_AXI_ReadMaster.arregion(3 downto 0) <= S_AXI_ARREGION; + S_AXI_ReadMaster.arqos(3 downto 0) <= S_AXI_ARQOS; +-- S_AXI_ReadMaster.aruser(ARUSER_WIDTH-1 downto 0) <= S_AXI_ARUSER; + S_AXI_ReadMaster.arvalid <= S_AXI_ARVALID; + S_AXI_ReadMaster.rready <= S_AXI_RREADY; + + S_AXI_ARREADY <= S_AXI_ReadSlave.arready; + S_AXI_RID <= S_AXI_ReadSlave.rid(ID_WIDTH-1 downto 0); + S_AXI_RDATA <= S_AXI_ReadSlave.rdata(DATA_WIDTH-1 downto 0); + S_AXI_RRESP <= S_AXI_ReadSlave.rresp when(EN_ERROR_RESP and (HAS_RRESP /= 0)) else "00"; + S_AXI_RLAST <= S_AXI_ReadSlave.rlast; +-- S_AXI_RUSER <= S_AXI_ReadSlave.ruser(RUSER_WIDTH-1 downto 0); + S_AXI_RVALID <= S_AXI_ReadSlave.rvalid; + +end mapping; diff --git a/axi/axi4/ruckus.tcl b/axi/axi4/ruckus.tcl index 6e82fc29b1..7598c569ff 100644 --- a/axi/axi4/ruckus.tcl +++ b/axi/axi4/ruckus.tcl @@ -3,6 +3,7 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Load Source Code loadSource -lib surf -dir "$::DIR_PATH/rtl" +loadSource -lib surf -dir "$::DIR_PATH/ip_integrator" # Load Simulation loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb" diff --git a/base/general/ip_integrator/MasterRamIpIntegrator.vhd b/base/general/ip_integrator/MasterRamIpIntegrator.vhd new file mode 100644 index 0000000000..edaed30192 --- /dev/null +++ b/base/general/ip_integrator/MasterRamIpIntegrator.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Common shim layer between IP Integrator interface and surf RAM interface +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity MasterRamIpIntegrator is + generic ( + INTERFACENAME : string := "M_RAM"; + READ_LATENCY : natural range 0 to 3 := 1; + ADDR_WIDTH : positive := 5; + DATA_WIDTH : positive := 32); + port ( + -- IP Integrator RAM Interface + M_RAM_CLK : out std_logic; + M_RAM_EN : out std_logic; + M_RAM_WE : out std_logic_vector((DATA_WIDTH/8)-1 downto 0); + M_RAM_RST : out std_logic; + M_RAM_ADDR : out std_logic_vector(ADDR_WIDTH-1 downto 0); + M_RAM_DIN : out std_logic_vector(DATA_WIDTH-1 downto 0); + M_RAM_DOUT : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0'); + -- SURF RAM Interface + clk : in std_logic := '0'; + en : in std_logic := '1'; + we : in std_logic_vector((DATA_WIDTH/8)-1 downto 0) := (others => '0'); + rst : in std_logic := '0'; + addr : in std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0'); + din : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0'); + dout : out std_logic_vector(DATA_WIDTH-1 downto 0)); +end MasterRamIpIntegrator; + +architecture mapping of MasterRamIpIntegrator is + + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_PARAMETER : string; + + attribute X_INTERFACE_INFO of M_RAM_CLK : signal is "xilinx.com:interface:bram:1.0 " & INTERFACENAME & " CLK"; + attribute X_INTERFACE_INFO of M_RAM_EN : signal is "xilinx.com:interface:bram:1.0 " & INTERFACENAME & " EN"; + attribute X_INTERFACE_INFO of M_RAM_WE : signal is "xilinx.com:interface:bram:1.0 " & INTERFACENAME & " WE"; + attribute X_INTERFACE_INFO of M_RAM_RST : signal is "xilinx.com:interface:bram:1.0 " & INTERFACENAME & " RST"; + attribute X_INTERFACE_INFO of M_RAM_ADDR : signal is "xilinx.com:interface:bram:1.0 " & INTERFACENAME & " ADDR"; + attribute X_INTERFACE_INFO of M_RAM_DIN : signal is "xilinx.com:interface:bram:1.0 " & INTERFACENAME & " DIN"; + attribute X_INTERFACE_INFO of M_RAM_DOUT : signal is "xilinx.com:interface:bram:1.0 " & INTERFACENAME & " DOUT"; + + attribute X_INTERFACE_PARAMETER of M_RAM_ADDR : signal is + "XIL_INTERFACENAME " & INTERFACENAME & ", " & + "MEM_SIZE " & integer'image(2**ADDR_WIDTH) & ", " & + "MEM_WIDTH " & integer'image(DATA_WIDTH) & ", " & + "MEM_ECC NONE, " & + "MASTER_TYPE OTHER, " & + "READ_LATENCY " & integer'image(READ_LATENCY); + +begin + + assert (DATA_WIDTH mod 8 = 0) report "DATA_WIDTH must be a multiple of 8" severity failure; + + M_RAM_CLK <= clk; + M_RAM_EN <= en; + M_RAM_WE <= we; + M_RAM_RST <= rst; + M_RAM_ADDR <= addr; + M_RAM_DIN <= din; + dout <= M_RAM_DOUT; + +end mapping; diff --git a/base/general/ip_integrator/SlaveRamIpIntegrator.vhd b/base/general/ip_integrator/SlaveRamIpIntegrator.vhd new file mode 100644 index 0000000000..da4cdd7324 --- /dev/null +++ b/base/general/ip_integrator/SlaveRamIpIntegrator.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Common shim layer between IP Integrator interface and surf RAM interface +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity SlaveRamIpIntegrator is + generic ( + INTERFACENAME : string := "S_RAM"; + READ_LATENCY : natural range 0 to 3 := 1; + ADDR_WIDTH : positive := 5; + DATA_WIDTH : positive := 32); + port ( + -- IP Integrator RAM Interface + S_RAM_CLK : in std_logic := '0'; + S_RAM_EN : in std_logic := '1'; + S_RAM_WE : in std_logic_vector((DATA_WIDTH/8)-1 downto 0) := (others => '0'); + S_RAM_RST : in std_logic := '0'; + S_RAM_ADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0'); + S_RAM_DIN : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0'); + S_RAM_DOUT : out std_logic_vector(DATA_WIDTH-1 downto 0); + -- SURF RAM Interface + clk : out std_logic; + en : out std_logic; + we : out std_logic_vector((DATA_WIDTH/8)-1 downto 0); + rst : out std_logic; + addr : out std_logic_vector(ADDR_WIDTH-1 downto 0); + din : out std_logic_vector(DATA_WIDTH-1 downto 0); + dout : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0')); +end SlaveRamIpIntegrator; + +architecture mapping of SlaveRamIpIntegrator is + + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_PARAMETER : string; + + attribute X_INTERFACE_INFO of S_RAM_CLK : signal is "xilinx.com:interface:bram:1.0 " & INTERFACENAME & " CLK"; + attribute X_INTERFACE_INFO of S_RAM_EN : signal is "xilinx.com:interface:bram:1.0 " & INTERFACENAME & " EN"; + attribute X_INTERFACE_INFO of S_RAM_WE : signal is "xilinx.com:interface:bram:1.0 " & INTERFACENAME & " WE"; + attribute X_INTERFACE_INFO of S_RAM_RST : signal is "xilinx.com:interface:bram:1.0 " & INTERFACENAME & " RST"; + attribute X_INTERFACE_INFO of S_RAM_ADDR : signal is "xilinx.com:interface:bram:1.0 " & INTERFACENAME & " ADDR"; + attribute X_INTERFACE_INFO of S_RAM_DIN : signal is "xilinx.com:interface:bram:1.0 " & INTERFACENAME & " DIN"; + attribute X_INTERFACE_INFO of S_RAM_DOUT : signal is "xilinx.com:interface:bram:1.0 " & INTERFACENAME & " DOUT"; + + attribute X_INTERFACE_PARAMETER of S_RAM_ADDR : signal is + "XIL_INTERFACENAME " & INTERFACENAME & ", " & + "MEM_SIZE " & integer'image(2**ADDR_WIDTH) & ", " & + "MEM_WIDTH " & integer'image(DATA_WIDTH) & ", " & + "MEM_ECC NONE, " & + "MASTER_TYPE OTHER, " & + "READ_LATENCY " & integer'image(READ_LATENCY); + +begin + + assert (DATA_WIDTH mod 8 = 0) report "DATA_WIDTH must be a multiple of 8" severity failure; + + clk <= S_RAM_CLK; + en <= S_RAM_EN; + we <= S_RAM_WE; + rst <= S_RAM_RST; + addr <= S_RAM_ADDR; + din <= S_RAM_DIN; + S_RAM_DOUT <= dout; + +end mapping; diff --git a/base/general/ruckus.tcl b/base/general/ruckus.tcl index 6e82fc29b1..7598c569ff 100644 --- a/base/general/ruckus.tcl +++ b/base/general/ruckus.tcl @@ -3,6 +3,7 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Load Source Code loadSource -lib surf -dir "$::DIR_PATH/rtl" +loadSource -lib surf -dir "$::DIR_PATH/ip_integrator" # Load Simulation loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb" From 963bcd53900588574f791e14b1337e4f931e15b1 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 27 Aug 2020 09:49:15 -0700 Subject: [PATCH 34/36] clean up from having FpgaTypePkg.vhd removed --- .../ip_integrator/AxiVersionIpIntegrator.vhd | 24 ++++--------------- 1 file changed, 4 insertions(+), 20 deletions(-) diff --git a/axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd index 39d8d2f07c..fde99730e6 100644 --- a/axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd +++ b/axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd @@ -28,16 +28,8 @@ use ruckus.BuildInfoPkg.all; entity AxiVersionIpIntegrator is generic ( - EN_ERROR_RESP : boolean := false; - FREQ_HZ : positive := 125000000; - EN_DEVICE_DNA : boolean := false; - EN_ICAP : boolean := false; - EN_DS2411 : boolean := false; - USE_SLOWCLK : boolean := false; - BUFR_CLK_DIV : positive := 8; - AUTO_RELOAD_EN : boolean := false; - AUTO_RELOAD_TIME : positive := 10; -- units of seconds - AUTO_RELOAD_ADDR : std_logic_vector(31 downto 0) := x"00000000"); + EN_ERROR_RESP : boolean := false; + FREQ_HZ : positive := 125000000); port ( -- AXI-Lite Interface S_AXI_ACLK : in std_logic; @@ -143,16 +135,8 @@ begin U_AxiVersion : entity surf.AxiVersion generic map ( - BUILD_INFO_G => BUILD_INFO_C, - CLK_PERIOD_G => CLK_PERIOD_C, - EN_DEVICE_DNA_G => EN_DEVICE_DNA, - EN_DS2411_G => EN_DS2411, - EN_ICAP_G => EN_ICAP, - USE_SLOWCLK_G => USE_SLOWCLK, - BUFR_CLK_DIV_G => BUFR_CLK_DIV, - AUTO_RELOAD_EN_G => AUTO_RELOAD_EN, - AUTO_RELOAD_TIME_G => AUTO_RELOAD_TIME, - AUTO_RELOAD_ADDR_G => AUTO_RELOAD_ADDR) + BUILD_INFO_G => BUILD_INFO_C, + CLK_PERIOD_G => CLK_PERIOD_C) port map ( -- AXI-Lite Interface axiClk => axilClk, From 4863ed1d7914305b057f9fe131a8b2a9872adc74 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 31 Aug 2020 15:33:04 -0700 Subject: [PATCH 35/36] bug fix --- protocols/srp/rtl/SrpV3Core.vhd | 1 + 1 file changed, 1 insertion(+) diff --git a/protocols/srp/rtl/SrpV3Core.vhd b/protocols/srp/rtl/SrpV3Core.vhd index 992c3f61db..259f0e17c0 100644 --- a/protocols/srp/rtl/SrpV3Core.vhd +++ b/protocols/srp/rtl/SrpV3Core.vhd @@ -31,6 +31,7 @@ entity SrpV3Core is generic ( TPD_G : time := 1 ns; PIPE_STAGES_G : natural range 0 to 16 := 1; + SYNTH_MODE_G : string := "inferred"; FIFO_PAUSE_THRESH_G : positive range 1 to 511 := 256; TX_VALID_THOLD_G : positive := 1; SLAVE_READY_EN_G : boolean := false; From 6bd82b8249d097bedbd474da8bb42ff4399c769f Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 31 Aug 2020 15:33:13 -0700 Subject: [PATCH 36/36] remove white space --- ethernet/EthMacCore/rtl/EthMacTxCsum.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd b/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd index 316c13c501..4ad511ad5b 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd @@ -31,7 +31,7 @@ entity EthMacTxCsum is JUMBO_G : boolean := true; VLAN_G : boolean := false; VID_G : slv(11 downto 0) := x"001"; - SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs + SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs port ( -- Clock and Reset ethClk : in sl;