diff --git a/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore156MHz.dcp b/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore156MHz.dcp index e9d462a2d4..e7d304c34e 100644 --- a/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore156MHz.dcp +++ b/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore156MHz.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:373dad4d26b3b8f2da1dbfac8b6671054dea563d6ebb990320ab97a251e9eeef -size 1810312 +oid sha256:14a3866135de753034661a0342202799b346bb57b5c2f6a75c611047c2f22e69 +size 1531950 diff --git a/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore156MHz.xci b/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore156MHz.xci index f8df7797ee..2dc38a5ce8 100644 --- a/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore156MHz.xci +++ b/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore156MHz.xci @@ -7,7 +7,7 @@ Caui4GtyIpCore156MHz - + 100000000 @@ -17,7 +17,7 @@ 0 0 undef - 0.000 + 0.0 64 0 0 @@ -30,7 +30,7 @@ 0 0 undef - 0.000 + 0.0 64 0 0 @@ -44,8 +44,9 @@ 0 100000000 + 0 0 - 0.000 + 0.0 false 100000000 false @@ -57,79 +58,103 @@ 100000000 + 0 0 - 0.000 + 0.0 0 false 100000000 + 0 0 - 0.000 + 0.0 0 0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 false + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 + + + + 0 + 0 + 0.0 + + + + 0 + 0 + 0.0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 - + 0.0 + 0 0 - 0.000 + 0.0 0 0 0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 0 0 1 @@ -155,7 +180,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -165,15 +190,17 @@ 0 100000000 + 0 0 - 0.000 + 0.0 0 100000000 + 0 0 - 0.000 + 0.0 0 0 0 @@ -187,6 +214,7 @@ 0 1 0 + 0 virtexuplus 0 250.00 @@ -195,6 +223,7 @@ 156.25 2 GTY + 0 0 1 2 @@ -277,6 +306,7 @@ 1 0 Custom + 0 0 250.00 X1Y44~X1Y47 @@ -284,6 +314,7 @@ 156.25 NA GTY + 0 0 1 2 @@ -299,7 +330,7 @@ NA NA NA - 4 + 4x25 Duplex QPLL0 0 @@ -350,7 +381,7 @@ AXIS false virtexuplus - xilinx.com:au200:part0:1.0 + xilinx.com:au200:part0:1.3 xcu200 fsgd2104 @@ -363,12 +394,12 @@ TRUE TRUE IP_Flow - 0 + 4 TRUE - . + ../../../../XilinxAlveoU200Htsp_PerfTester_project.gen/sources_1/ip/Caui4GtyIpCore156MHz . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -436,6 +467,123 @@ + + + diff --git a/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore161MHz.dcp b/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore161MHz.dcp index f069a7ffa6..ed7b630637 100644 --- a/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore161MHz.dcp +++ b/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore161MHz.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:992e2eef60d8b0a4f16366f137ea59089efb63a6241feae4c23921766e4f17ed -size 1810510 +oid sha256:45e851181e8ac85f505ef40e4f1a1434bc9bea1205fc6617e1c12ac6f4917dee +size 1532274 diff --git a/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore161MHz.xci b/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore161MHz.xci index 1eacd0a74e..a8c6415f7d 100644 --- a/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore161MHz.xci +++ b/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore161MHz.xci @@ -7,7 +7,7 @@ Caui4GtyIpCore161MHz - + 100000000 @@ -17,7 +17,7 @@ 0 0 undef - 0.000 + 0.0 64 0 0 @@ -30,7 +30,7 @@ 0 0 undef - 0.000 + 0.0 64 0 0 @@ -44,8 +44,9 @@ 0 100000000 + 0 0 - 0.000 + 0.0 false 100000000 false @@ -57,79 +58,103 @@ 100000000 + 0 0 - 0.000 + 0.0 0 false 100000000 + 0 0 - 0.000 + 0.0 0 0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 false + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 + + + + 0 + 0 + 0.0 + + + + 0 + 0 + 0.0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 - + 0.0 + 0 0 - 0.000 + 0.0 0 0 0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 0 0 1 @@ -155,7 +180,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -165,15 +190,17 @@ 0 100000000 + 0 0 - 0.000 + 0.0 0 100000000 + 0 0 - 0.000 + 0.0 0 0 0 @@ -187,6 +214,7 @@ 0 1 0 + 0 virtexuplus 0 250.00 @@ -195,6 +223,7 @@ 161.1328125 2 GTY + 0 0 1 2 @@ -277,6 +306,7 @@ 1 0 Custom + 0 0 250.00 X1Y44~X1Y47 @@ -284,6 +314,7 @@ 161.1328125 NA GTY + 0 0 1 2 @@ -299,7 +330,7 @@ NA NA NA - 4 + 4x25 Duplex QPLL0 0 @@ -350,7 +381,7 @@ AXIS false virtexuplus - xilinx.com:au200:part0:1.0 + xilinx.com:au200:part0:1.3 xcu200 fsgd2104 @@ -363,12 +394,12 @@ TRUE TRUE IP_Flow - 0 + 4 TRUE - . + ../../../../XilinxAlveoU200Htsp_PerfTester_project.gen/sources_1/ip/Caui4GtyIpCore161MHz . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -436,6 +467,123 @@ + + + diff --git a/ethernet/Caui4Core/gtyUltraScale+/rtl/Caui4GtyIpWrapper.vhd b/ethernet/Caui4Core/gtyUltraScale+/rtl/Caui4GtyIpWrapper.vhd index 4d1b25e194..155ff05166 100644 --- a/ethernet/Caui4Core/gtyUltraScale+/rtl/Caui4GtyIpWrapper.vhd +++ b/ethernet/Caui4Core/gtyUltraScale+/rtl/Caui4GtyIpWrapper.vhd @@ -172,12 +172,40 @@ architecture mapping of Caui4GtyIpWrapper is rx_otn_data_2 : out std_logic_vector(65 downto 0); rx_otn_data_3 : out std_logic_vector(65 downto 0); rx_otn_data_4 : out std_logic_vector(65 downto 0); + rx_otn_ena : out std_logic; + rx_otn_lane0 : out std_logic; + rx_otn_vlmarker : out std_logic; rx_preambleout : out std_logic_vector(55 downto 0); usr_rx_reset : out std_logic; gt_rxusrclk2 : out std_logic; + stat_rx_aligned : out std_logic; + stat_rx_aligned_err : out std_logic; stat_rx_bad_code : out std_logic_vector(2 downto 0); stat_rx_bad_fcs : out std_logic_vector(2 downto 0); + stat_rx_bad_preamble : out std_logic; + stat_rx_bad_sfd : out std_logic; + stat_rx_bip_err_0 : out std_logic; + stat_rx_bip_err_1 : out std_logic; + stat_rx_bip_err_10 : out std_logic; + stat_rx_bip_err_11 : out std_logic; + stat_rx_bip_err_12 : out std_logic; + stat_rx_bip_err_13 : out std_logic; + stat_rx_bip_err_14 : out std_logic; + stat_rx_bip_err_15 : out std_logic; + stat_rx_bip_err_16 : out std_logic; + stat_rx_bip_err_17 : out std_logic; + stat_rx_bip_err_18 : out std_logic; + stat_rx_bip_err_19 : out std_logic; + stat_rx_bip_err_2 : out std_logic; + stat_rx_bip_err_3 : out std_logic; + stat_rx_bip_err_4 : out std_logic; + stat_rx_bip_err_5 : out std_logic; + stat_rx_bip_err_6 : out std_logic; + stat_rx_bip_err_7 : out std_logic; + stat_rx_bip_err_8 : out std_logic; + stat_rx_bip_err_9 : out std_logic; stat_rx_block_lock : out std_logic_vector(19 downto 0); + stat_rx_broadcast : out std_logic; stat_rx_fragment : out std_logic_vector(2 downto 0); stat_rx_framing_err_0 : out std_logic_vector(1 downto 0); stat_rx_framing_err_1 : out std_logic_vector(1 downto 0); @@ -199,23 +227,74 @@ architecture mapping of Caui4GtyIpWrapper is stat_rx_framing_err_7 : out std_logic_vector(1 downto 0); stat_rx_framing_err_8 : out std_logic_vector(1 downto 0); stat_rx_framing_err_9 : out std_logic_vector(1 downto 0); + stat_rx_framing_err_valid_0 : out std_logic; + stat_rx_framing_err_valid_1 : out std_logic; + stat_rx_framing_err_valid_10 : out std_logic; + stat_rx_framing_err_valid_11 : out std_logic; + stat_rx_framing_err_valid_12 : out std_logic; + stat_rx_framing_err_valid_13 : out std_logic; + stat_rx_framing_err_valid_14 : out std_logic; + stat_rx_framing_err_valid_15 : out std_logic; + stat_rx_framing_err_valid_16 : out std_logic; + stat_rx_framing_err_valid_17 : out std_logic; + stat_rx_framing_err_valid_18 : out std_logic; + stat_rx_framing_err_valid_19 : out std_logic; + stat_rx_framing_err_valid_2 : out std_logic; + stat_rx_framing_err_valid_3 : out std_logic; + stat_rx_framing_err_valid_4 : out std_logic; + stat_rx_framing_err_valid_5 : out std_logic; + stat_rx_framing_err_valid_6 : out std_logic; + stat_rx_framing_err_valid_7 : out std_logic; + stat_rx_framing_err_valid_8 : out std_logic; + stat_rx_framing_err_valid_9 : out std_logic; + stat_rx_got_signal_os : out std_logic; + stat_rx_hi_ber : out std_logic; + stat_rx_inrangeerr : out std_logic; + stat_rx_internal_local_fault : out std_logic; + stat_rx_jabber : out std_logic; + stat_rx_local_fault : out std_logic; stat_rx_mf_err : out std_logic_vector(19 downto 0); stat_rx_mf_len_err : out std_logic_vector(19 downto 0); stat_rx_mf_repeat_err : out std_logic_vector(19 downto 0); + stat_rx_misaligned : out std_logic; + stat_rx_multicast : out std_logic; + stat_rx_oversize : out std_logic; + stat_rx_packet_1024_1518_bytes : out std_logic; + stat_rx_packet_128_255_bytes : out std_logic; + stat_rx_packet_1519_1522_bytes : out std_logic; + stat_rx_packet_1523_1548_bytes : out std_logic; + stat_rx_packet_1549_2047_bytes : out std_logic; + stat_rx_packet_2048_4095_bytes : out std_logic; + stat_rx_packet_256_511_bytes : out std_logic; + stat_rx_packet_4096_8191_bytes : out std_logic; + stat_rx_packet_512_1023_bytes : out std_logic; + stat_rx_packet_64_bytes : out std_logic; + stat_rx_packet_65_127_bytes : out std_logic; + stat_rx_packet_8192_9215_bytes : out std_logic; + stat_rx_packet_bad_fcs : out std_logic; + stat_rx_packet_large : out std_logic; stat_rx_packet_small : out std_logic_vector(2 downto 0); ctl_rx_enable : in std_logic; ctl_rx_force_resync : in std_logic; ctl_rx_test_pattern : in std_logic; core_rx_reset : in std_logic; rx_clk : in std_logic; + stat_rx_received_local_fault : out std_logic; + stat_rx_remote_fault : out std_logic; + stat_rx_status : out std_logic; stat_rx_stomped_fcs : out std_logic_vector(2 downto 0); stat_rx_synced : out std_logic_vector(19 downto 0); stat_rx_synced_err : out std_logic_vector(19 downto 0); stat_rx_test_pattern_mismatch : out std_logic_vector(2 downto 0); + stat_rx_toolong : out std_logic; stat_rx_total_bytes : out std_logic_vector(6 downto 0); stat_rx_total_good_bytes : out std_logic_vector(13 downto 0); + stat_rx_total_good_packets : out std_logic; stat_rx_total_packets : out std_logic_vector(2 downto 0); + stat_rx_truncated : out std_logic; stat_rx_undersize : out std_logic_vector(2 downto 0); + stat_rx_unicast : out std_logic; + stat_rx_vlan : out std_logic; stat_rx_pcsl_demuxed : out std_logic_vector(19 downto 0); stat_rx_pcsl_number_0 : out std_logic_vector(4 downto 0); stat_rx_pcsl_number_1 : out std_logic_vector(4 downto 0); @@ -399,12 +478,40 @@ architecture mapping of Caui4GtyIpWrapper is rx_otn_data_2 : out std_logic_vector(65 downto 0); rx_otn_data_3 : out std_logic_vector(65 downto 0); rx_otn_data_4 : out std_logic_vector(65 downto 0); + rx_otn_ena : out std_logic; + rx_otn_lane0 : out std_logic; + rx_otn_vlmarker : out std_logic; rx_preambleout : out std_logic_vector(55 downto 0); usr_rx_reset : out std_logic; gt_rxusrclk2 : out std_logic; + stat_rx_aligned : out std_logic; + stat_rx_aligned_err : out std_logic; stat_rx_bad_code : out std_logic_vector(2 downto 0); stat_rx_bad_fcs : out std_logic_vector(2 downto 0); + stat_rx_bad_preamble : out std_logic; + stat_rx_bad_sfd : out std_logic; + stat_rx_bip_err_0 : out std_logic; + stat_rx_bip_err_1 : out std_logic; + stat_rx_bip_err_10 : out std_logic; + stat_rx_bip_err_11 : out std_logic; + stat_rx_bip_err_12 : out std_logic; + stat_rx_bip_err_13 : out std_logic; + stat_rx_bip_err_14 : out std_logic; + stat_rx_bip_err_15 : out std_logic; + stat_rx_bip_err_16 : out std_logic; + stat_rx_bip_err_17 : out std_logic; + stat_rx_bip_err_18 : out std_logic; + stat_rx_bip_err_19 : out std_logic; + stat_rx_bip_err_2 : out std_logic; + stat_rx_bip_err_3 : out std_logic; + stat_rx_bip_err_4 : out std_logic; + stat_rx_bip_err_5 : out std_logic; + stat_rx_bip_err_6 : out std_logic; + stat_rx_bip_err_7 : out std_logic; + stat_rx_bip_err_8 : out std_logic; + stat_rx_bip_err_9 : out std_logic; stat_rx_block_lock : out std_logic_vector(19 downto 0); + stat_rx_broadcast : out std_logic; stat_rx_fragment : out std_logic_vector(2 downto 0); stat_rx_framing_err_0 : out std_logic_vector(1 downto 0); stat_rx_framing_err_1 : out std_logic_vector(1 downto 0); @@ -426,23 +533,74 @@ architecture mapping of Caui4GtyIpWrapper is stat_rx_framing_err_7 : out std_logic_vector(1 downto 0); stat_rx_framing_err_8 : out std_logic_vector(1 downto 0); stat_rx_framing_err_9 : out std_logic_vector(1 downto 0); + stat_rx_framing_err_valid_0 : out std_logic; + stat_rx_framing_err_valid_1 : out std_logic; + stat_rx_framing_err_valid_10 : out std_logic; + stat_rx_framing_err_valid_11 : out std_logic; + stat_rx_framing_err_valid_12 : out std_logic; + stat_rx_framing_err_valid_13 : out std_logic; + stat_rx_framing_err_valid_14 : out std_logic; + stat_rx_framing_err_valid_15 : out std_logic; + stat_rx_framing_err_valid_16 : out std_logic; + stat_rx_framing_err_valid_17 : out std_logic; + stat_rx_framing_err_valid_18 : out std_logic; + stat_rx_framing_err_valid_19 : out std_logic; + stat_rx_framing_err_valid_2 : out std_logic; + stat_rx_framing_err_valid_3 : out std_logic; + stat_rx_framing_err_valid_4 : out std_logic; + stat_rx_framing_err_valid_5 : out std_logic; + stat_rx_framing_err_valid_6 : out std_logic; + stat_rx_framing_err_valid_7 : out std_logic; + stat_rx_framing_err_valid_8 : out std_logic; + stat_rx_framing_err_valid_9 : out std_logic; + stat_rx_got_signal_os : out std_logic; + stat_rx_hi_ber : out std_logic; + stat_rx_inrangeerr : out std_logic; + stat_rx_internal_local_fault : out std_logic; + stat_rx_jabber : out std_logic; + stat_rx_local_fault : out std_logic; stat_rx_mf_err : out std_logic_vector(19 downto 0); stat_rx_mf_len_err : out std_logic_vector(19 downto 0); stat_rx_mf_repeat_err : out std_logic_vector(19 downto 0); + stat_rx_misaligned : out std_logic; + stat_rx_multicast : out std_logic; + stat_rx_oversize : out std_logic; + stat_rx_packet_1024_1518_bytes : out std_logic; + stat_rx_packet_128_255_bytes : out std_logic; + stat_rx_packet_1519_1522_bytes : out std_logic; + stat_rx_packet_1523_1548_bytes : out std_logic; + stat_rx_packet_1549_2047_bytes : out std_logic; + stat_rx_packet_2048_4095_bytes : out std_logic; + stat_rx_packet_256_511_bytes : out std_logic; + stat_rx_packet_4096_8191_bytes : out std_logic; + stat_rx_packet_512_1023_bytes : out std_logic; + stat_rx_packet_64_bytes : out std_logic; + stat_rx_packet_65_127_bytes : out std_logic; + stat_rx_packet_8192_9215_bytes : out std_logic; + stat_rx_packet_bad_fcs : out std_logic; + stat_rx_packet_large : out std_logic; stat_rx_packet_small : out std_logic_vector(2 downto 0); ctl_rx_enable : in std_logic; ctl_rx_force_resync : in std_logic; ctl_rx_test_pattern : in std_logic; core_rx_reset : in std_logic; rx_clk : in std_logic; + stat_rx_received_local_fault : out std_logic; + stat_rx_remote_fault : out std_logic; + stat_rx_status : out std_logic; stat_rx_stomped_fcs : out std_logic_vector(2 downto 0); stat_rx_synced : out std_logic_vector(19 downto 0); stat_rx_synced_err : out std_logic_vector(19 downto 0); stat_rx_test_pattern_mismatch : out std_logic_vector(2 downto 0); + stat_rx_toolong : out std_logic; stat_rx_total_bytes : out std_logic_vector(6 downto 0); stat_rx_total_good_bytes : out std_logic_vector(13 downto 0); + stat_rx_total_good_packets : out std_logic; stat_rx_total_packets : out std_logic_vector(2 downto 0); + stat_rx_truncated : out std_logic; stat_rx_undersize : out std_logic_vector(2 downto 0); + stat_rx_unicast : out std_logic; + stat_rx_vlan : out std_logic; stat_rx_pcsl_demuxed : out std_logic_vector(19 downto 0); stat_rx_pcsl_number_0 : out std_logic_vector(4 downto 0); stat_rx_pcsl_number_1 : out std_logic_vector(4 downto 0); diff --git a/ethernet/Caui4Core/gtyUltraScale+/ruckus.tcl b/ethernet/Caui4Core/gtyUltraScale+/ruckus.tcl index 46df66e55a..9ecbec70c3 100644 --- a/ethernet/Caui4Core/gtyUltraScale+/ruckus.tcl +++ b/ethernet/Caui4Core/gtyUltraScale+/ruckus.tcl @@ -2,7 +2,7 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Load Source Code -if { $::env(VIVADO_VERSION) >= 2019.1 } { +if { $::env(VIVADO_VERSION) >= 2021.1 } { loadSource -lib surf -dir "$::DIR_PATH/rtl" @@ -13,5 +13,5 @@ if { $::env(VIVADO_VERSION) >= 2019.1 } { # loadIpCore -path "$::DIR_PATH/ip/Caui4GtyIpCore161MHz.xci" } else { - puts "\n\nWARNING: $::DIR_PATH requires Vivado 2019.1 (or later)\n\n" + puts "\n\nWARNING: $::DIR_PATH requires Vivado 2021.1 (or later)\n\n" } diff --git a/xilinx/general/microblaze/bd/.gitignore b/xilinx/general/microblaze/bd/.gitignore deleted file mode 100644 index 0bfbf96d6f..0000000000 --- a/xilinx/general/microblaze/bd/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -# Ignore the .TCL files from CopyBdCores() (ruckus@v2.0.3) -*.tcl diff --git a/xilinx/general/microblaze/bd/2021.1/MicroblazeBasicCore.tcl b/xilinx/general/microblaze/bd/2021.1/MicroblazeBasicCore.tcl new file mode 100644 index 0000000000..cfea51e229 --- /dev/null +++ b/xilinx/general/microblaze/bd/2021.1/MicroblazeBasicCore.tcl @@ -0,0 +1,465 @@ + +################################################################ +# This is a generated script based on design: MicroblazeBasicCore +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +# ################################################################ +# # Check if script is running in correct Vivado version. +# ################################################################ +# set scripts_vivado_version 2021.1 +# set current_vivado_version [version -short] + +# if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + # puts "" + # catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + # return 1 +# } + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source MicroblazeBasicCore_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xcku040-ffva1156-2-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name MicroblazeBasicCore + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + + # Add USER_COMMENTS on $design_name + set_property USER_COMMENTS.comment_1 "Example MicroBlaze Design in IP Integrator" [get_bd_designs $design_name] + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_gpio:2.0\ +xilinx.com:ip:axi_intc:4.1\ +xilinx.com:ip:axi_timer:2.0\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:mdm:3.2\ +xilinx.com:ip:microblaze:11.0\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:lmb_bram_if_cntlr:4.0\ +xilinx.com:ip:lmb_v10:3.0\ +xilinx.com:ip:blk_mem_gen:8.4\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + +# Hierarchical cell: microblaze_0_local_memory +proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB + + create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB + + + # Create pins + create_bd_pin -dir I -type clk LMB_Clk + create_bd_pin -dir I -type rst SYS_Rst + + # Create instance: dlmb_bram_if_cntlr, and set properties + set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ] + set_property -dict [ list \ + CONFIG.C_ECC {0} \ + ] $dlmb_bram_if_cntlr + + # Create instance: dlmb_v10, and set properties + set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ] + + # Create instance: ilmb_bram_if_cntlr, and set properties + set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ] + set_property -dict [ list \ + CONFIG.C_ECC {0} \ + ] $ilmb_bram_if_cntlr + + # Create instance: ilmb_v10, and set properties + set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ] + + # Create instance: lmb_bram, and set properties + set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 lmb_bram ] + set_property -dict [ list \ + CONFIG.Memory_Type {True_Dual_Port_RAM} \ + CONFIG.use_bram_block {BRAM_Controller} \ + ] $lmb_bram + + # Create interface connections + connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M] + connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0] + connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA] + connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M] + connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0] + connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB] + + # Create port connections + connect_bd_net -net SYS_Rst_1 [get_bd_pins SYS_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst] + connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk] + + # Restore current instance + current_bd_instance $oldCurInst +} + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set M0_AXIS [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M0_AXIS ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {156250000} \ + ] $M0_AXIS + + set M_AXI_DP [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_DP ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {156250000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_DP + + set S0_AXIS [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S0_AXIS ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {156250000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {4} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $S0_AXIS + + + # Create ports + set GPIO_0_OUT [ create_bd_port -dir O -from 0 -to 0 -type data GPIO_0_OUT ] + set INTERRUPT [ create_bd_port -dir I -from 7 -to 0 INTERRUPT ] + set clk [ create_bd_port -dir I -type clk -freq_hz 156250000 clk ] + set dcm_locked [ create_bd_port -dir I dcm_locked ] + set reset [ create_bd_port -dir I -type rst reset ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $reset + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {1} \ + ] $axi_gpio_0 + + # Create instance: axi_intc_0, and set properties + set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ] + set_property -dict [ list \ + CONFIG.C_HAS_FAST {1} \ + CONFIG.C_IRQ_IS_LEVEL {0} \ + CONFIG.C_KIND_OF_EDGE {0xFFFFFFFF} \ + CONFIG.C_KIND_OF_INTR {0xFFFFFC00} \ + CONFIG.C_KIND_OF_LVL {0xFFFFFFFF} \ + CONFIG.C_NUM_SW_INTR {10} \ + ] $axi_intc_0 + + # Create instance: axi_timer_0, and set properties + set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ] + + # Create instance: gnd_0, and set properties + set gnd_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_0 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + ] $gnd_0 + + # Create instance: mdm_1, and set properties + set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ] + set_property -dict [ list \ + CONFIG.C_USE_UART {1} \ + ] $mdm_1 + + # Create instance: microblaze_0, and set properties + set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:11.0 microblaze_0 ] + set_property -dict [ list \ + CONFIG.C_DEBUG_ENABLED {1} \ + CONFIG.C_D_AXI {1} \ + CONFIG.C_D_LMB {1} \ + CONFIG.C_FSL_LINKS {1} \ + CONFIG.C_I_LMB {1} \ + CONFIG.C_NUMBER_OF_PC_BRK {4} \ + CONFIG.C_USE_BARREL {1} \ + CONFIG.C_USE_DIV {1} \ + CONFIG.C_USE_EXTENDED_FSL_INSTR {1} \ + CONFIG.C_USE_FPU {2} \ + CONFIG.C_USE_HW_MUL {2} \ + CONFIG.C_USE_MSR_INSTR {1} \ + CONFIG.C_USE_PCMP_INSTR {1} \ + ] $microblaze_0 + + # Create instance: microblaze_0_local_memory + create_hier_cell_microblaze_0_local_memory [current_bd_instance .] microblaze_0_local_memory + + # Create instance: microblaze_axi_periph, and set properties + set microblaze_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_axi_periph ] + set_property -dict [ list \ + CONFIG.NUM_MI {5} \ + ] $microblaze_axi_periph + + # Create instance: rst_clk_wiz_1_100M, and set properties + set rst_clk_wiz_1_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_1_100M ] + set_property -dict [ list \ + CONFIG.C_AUX_RESET_HIGH {1} \ + CONFIG.C_AUX_RST_WIDTH {1} \ + CONFIG.C_EXT_RST_WIDTH {1} \ + ] $rst_clk_wiz_1_100M + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.IN0_WIDTH {8} \ + CONFIG.IN1_WIDTH {1} \ + CONFIG.IN2_WIDTH {1} \ + CONFIG.NUM_PORTS {3} \ + ] $xlconcat_0 + + # Create interface connections + connect_bd_intf_net -intf_net S0_AXIS_0_1 [get_bd_intf_ports S0_AXIS] [get_bd_intf_pins microblaze_0/S0_AXIS] + connect_bd_intf_net -intf_net axi_intc_0_interrupt [get_bd_intf_pins axi_intc_0/interrupt] [get_bd_intf_pins microblaze_0/INTERRUPT] + connect_bd_intf_net -intf_net microblaze_0_M0_AXIS [get_bd_intf_ports M0_AXIS] [get_bd_intf_pins microblaze_0/M0_AXIS] + connect_bd_intf_net -intf_net microblaze_0_M_AXI_DP [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_axi_periph/S00_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M00_AXI [get_bd_intf_ports M_AXI_DP] [get_bd_intf_pins microblaze_axi_periph/M00_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M01_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins microblaze_axi_periph/M01_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins microblaze_axi_periph/M02_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins mdm_1/S_AXI] [get_bd_intf_pins microblaze_axi_periph/M03_AXI] + connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG] + connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB] + connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB] + connect_bd_intf_net -intf_net microblaze_axi_periph_M04_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins microblaze_axi_periph/M04_AXI] + + # Create port connections + connect_bd_net -net In0_0_1 [get_bd_ports INTERRUPT] [get_bd_pins xlconcat_0/In0] + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_ports GPIO_0_OUT] [get_bd_pins axi_gpio_0/gpio_io_o] + connect_bd_net -net axi_timer_0_interrupt [get_bd_pins axi_timer_0/interrupt] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net dcm_locked_0_1 [get_bd_ports dcm_locked] [get_bd_pins rst_clk_wiz_1_100M/dcm_locked] + connect_bd_net -net gnd_0_dout [get_bd_pins axi_timer_0/capturetrig0] [get_bd_pins axi_timer_0/capturetrig1] [get_bd_pins axi_timer_0/freeze] [get_bd_pins gnd_0/dout] + connect_bd_net -net mdm_1_Interrupt [get_bd_pins mdm_1/Interrupt] [get_bd_pins xlconcat_0/In2] + connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_clk_wiz_1_100M/mb_debug_sys_rst] + connect_bd_net -net microblaze_0_Clk [get_bd_ports clk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_intc_0/processor_clk] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins mdm_1/S_AXI_ACLK] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins microblaze_axi_periph/ACLK] [get_bd_pins microblaze_axi_periph/M00_ACLK] [get_bd_pins microblaze_axi_periph/M01_ACLK] [get_bd_pins microblaze_axi_periph/M02_ACLK] [get_bd_pins microblaze_axi_periph/M03_ACLK] [get_bd_pins microblaze_axi_periph/M04_ACLK] [get_bd_pins microblaze_axi_periph/S00_ACLK] [get_bd_pins rst_clk_wiz_1_100M/slowest_sync_clk] + connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins rst_clk_wiz_1_100M/aux_reset_in] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in] + connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/SYS_Rst] [get_bd_pins rst_clk_wiz_1_100M/bus_struct_reset] + connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins microblaze_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_1_100M/interconnect_aresetn] + connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_pins axi_intc_0/processor_rst] [get_bd_pins microblaze_0/Reset] [get_bd_pins rst_clk_wiz_1_100M/mb_reset] + connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mdm_1/S_AXI_ARESETN] [get_bd_pins microblaze_axi_periph/M00_ARESETN] [get_bd_pins microblaze_axi_periph/M01_ARESETN] [get_bd_pins microblaze_axi_periph/M02_ARESETN] [get_bd_pins microblaze_axi_periph/M03_ARESETN] [get_bd_pins microblaze_axi_periph/M04_ARESETN] [get_bd_pins microblaze_axi_periph/S00_ARESETN] [get_bd_pins rst_clk_wiz_1_100M/peripheral_aresetn] + connect_bd_net -net xlconcat_0_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins xlconcat_0/dout] + + # Create address segments + assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs M_AXI_DP/Reg] -force + assign_bd_address -offset 0x00040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force + assign_bd_address -offset 0x00010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] -force + assign_bd_address -offset 0x00020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x00008000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] -force + assign_bd_address -offset 0x00000000 -range 0x00008000 -target_address_space [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] -force + assign_bd_address -offset 0x00030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs mdm_1/S_AXI/Reg] -force + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/xilinx/general/microblaze/ruckus.tcl b/xilinx/general/microblaze/ruckus.tcl index 8658735098..8f07b9decd 100644 --- a/xilinx/general/microblaze/ruckus.tcl +++ b/xilinx/general/microblaze/ruckus.tcl @@ -19,7 +19,12 @@ if { [info exists ::env(SDK_SRC_PATH)] != 1 } { loadSource -lib surf -path "$::DIR_PATH/generate/MicroblazeBasicCoreWrapper.vhd" # Load the .bd file - loadBlockDesign -path "$::DIR_PATH/bd/2020.1/MicroblazeBasicCore.bd" + if { $::env(VIVADO_VERSION) < 2021.1 } { + loadBlockDesign -path "$::DIR_PATH/bd/2020.1/MicroblazeBasicCore.bd" + } else { + loadBlockDesign -path "$::DIR_PATH/bd/2021.1/MicroblazeBasicCore.tcl" + } + } }