From 7db02de2687be720507e54209939134dbfe54047 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 2 Jun 2020 14:15:07 -0700 Subject: [PATCH 01/40] adding SelectIoRxGearboxAligner --- .../general/rtl/SelectIoRxGearboxAligner.vhd | 371 ++++++++++++++++++ 1 file changed, 371 insertions(+) create mode 100644 xilinx/general/rtl/SelectIoRxGearboxAligner.vhd diff --git a/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd b/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd new file mode 100644 index 0000000000..8e9720a2f4 --- /dev/null +++ b/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd @@ -0,0 +1,371 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Aligns the SELECTIO LVDS RX gearbox. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +library surf; +use surf.StdRtlPkg.all; + +entity SelectIoRxGearboxAligner is + generic ( + TPD_G : time := 1 ns; + NUM_BYTES_G : positive := 1; + ENCODE_G : boolean := false; + SIMULATION_G : boolean := false); + port ( + -- Clock and Reset + clk : in sl; + rst : in sl; + -- Line-Code Interface (ENCODE_G = false) + lineCodeValid : in sl; + lineCodeErr : in slv(NUM_BYTES_G-1 downto 0); + lineCodeDispErr : in slv(NUM_BYTES_G-1 downto 0); + -- 64b/66b Interface (ENCODE_G = true) + rxHeaderValid : in sl; + rxHeader : in slv(1 downto 0); + -- Gearbox Slip + bitSlip : out sl; + -- IDELAY (DELAY_TYPE="VAR_LOAD") Interface + dlyLoad : out sl; + dlyCfg : out slv(8 downto 0); + -- Configuration Interface + enUsrDlyCfg : in sl := '0'; -- Enable User delay config + usrDlyCfg : in slv(8 downto 0) := (others => '0'); -- User delay config + bypFirstBerDet : in sl := '1'; -- Set to '1' if IDELAY full scale range > 1 UI of serial rate (example: IDELAY range 2.5ns > 1 ns "1Gb/s" ) + minEyeWidth : in slv(7 downto 0) := toSlv(80, 8); -- Sets the minimum eye width required for locking (units of IDELAY step) + lockingCntCfg : in slv(23 downto 0) := ite(SIMULATION_G, x"00_0064", x"00_FFFF"); -- Number of error-free event before state=LOCKED_S + -- Status Interface + errorDet : out sl; + locked : out sl); +end entity SelectIoRxGearboxAligner; + +architecture rtl of SelectIoRxGearboxAligner is + + constant SLIP_WAIT_C : positive := ite(SIMULATION_G, 10, 100); + + type StateType is ( + UNLOCKED_S, + SLIP_WAIT_S, + LOCKING_S, + EYE_SCAN_S, + LOCKED_S); + + type RegType is record + enUsrDlyCfg : sl; + usrDlyCfg : slv(8 downto 0); + dlyLoad : slv(1 downto 0); + dlyConfig : slv(8 downto 0); + dlyCache : slv(8 downto 0); + slipWaitCnt : natural range 0 to SLIP_WAIT_C-1; + goodCnt : slv(23 downto 0); + slip : sl; + errorDet : sl; + firstError : sl; + armed : sl; + scanDone : sl; + locked : sl; + state : StateType; + end record RegType; + + constant REG_INIT_C : RegType := ( + enUsrDlyCfg => '0', + usrDlyCfg => (others => '0'), + dlyLoad => (others => '0'), + dlyConfig => (others => '0'), + dlyCache => (others => '0'), + slipWaitCnt => 0, + goodCnt => (others => '0'), + slip => '0', + errorDet => '0', + firstError => '0', + armed => '0', + scanDone => '0', + locked => '0', + state => UNLOCKED_S); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + +begin + + comb : process (bypFirstBerDet, enUsrDlyCfg, lineCodeDispErr, lineCodeErr, + lineCodeValid, lockingCntCfg, minEyeWidth, r, rst, rxHeader, + rxHeaderValid, usrDlyCfg) is + variable v : RegType; + + procedure slipProcedure is + begin + + -- Update the Delay module + v.dlyLoad(1) := '1'; + + -- Check for max value + if (r.dlyConfig >= 255) then + + -- Set min. value + v.dlyConfig := (others => '0'); + + -- Slip by 1-bit in the gearbox + v.slip := '1'; + + -- Reset the flag + v.firstError := '0'; + + else + + -- Increment the counter + v.dlyConfig := r.dlyConfig + 1; + + -- Reset the flag + v.firstError := '1'; + + end if; + + -- Reset the flags + v.armed := '0'; + v.scanDone := '0'; + v.locked := '0'; + + -- Reset the counter + v.goodCnt := (others => '0'); + + -- Next state + v.state := SLIP_WAIT_S; + + end procedure slipProcedure; + + variable scanCnt : slv(8 downto 0); + variable scanHalf : slv(8 downto 0); + variable eyescanCfg : slv(8 downto 0); + variable valid : sl; + + begin + -- Latch the current value + v := r; + + -- Update the local variables + scanCnt := (r.dlyConfig-r.dlyCache); + scanHalf := '0' & scanCnt(8 downto 1); + eyescanCfg := '0' & minEyeWidth; + + -- Reset strobes + v.slip := '0'; + v.errorDet := '0'; + + -- Shift register + v.dlyLoad := '0' & r.dlyLoad(1); + + -- 64b/66b Interface (ENCODE_G = true) + if ENCODE_G then + valid := rxHeaderValid; + -- Check for bad header + if (rxHeaderValid = '1') and ((rxHeader = "00") or (rxHeader = "11")) then + v.errorDet := '1'; + end if; + + -- Line-Code Interface (ENCODE_G = false) + else + valid := lineCodeValid; + -- Check for bad header + if (lineCodeValid = '1') and (uOr(lineCodeErr) = '1' or uOr(lineCodeDispErr) = '1') then + v.errorDet := '1'; + end if; + end if; + + -- State Machine + case r.state is + ---------------------------------------------------------------------- + when UNLOCKED_S => + -- Check for data + if (valid = '1') then + -- Check for bad header + if (v.errorDet = '1') then + -- Execute the slip procedure + slipProcedure; + else + -- Next state + v.state := LOCKING_S; + end if; + end if; + ---------------------------------------------------------------------- + when SLIP_WAIT_S => + -- Check the counter + if (r.slipWaitCnt = SLIP_WAIT_C-1) then + + -- Reset the counter + v.slipWaitCnt := 0; + + -- Check if eye scan completed + if (r.scanDone = '1') then + -- Next state + v.state := LOCKED_S; + -- Check for armed mode + elsif (r.armed = '1') then + -- Next state + v.state := EYE_SCAN_S; + else + -- Next state + v.state := UNLOCKED_S; + end if; + + else + -- Increment the counter + v.slipWaitCnt := r.slipWaitCnt + 1; + end if; + ---------------------------------------------------------------------- + when LOCKING_S => + -- Check for data + if (valid = '1') then + + -- Check for bad header + if (v.errorDet = '1') then + -- Execute the slip procedure + slipProcedure; + + elsif (r.goodCnt < lockingCntCfg) then + -- Increment the counter + v.goodCnt := r.goodCnt + 1; + else + + -- Check if no bit errors detected yet during this IDELAY sweep + if (r.firstError = '0') and (bypFirstBerDet = '0') then + -- Execute the slip procedure + slipProcedure; + + else + + -- Set the flag + v.armed := '1'; + + -- Reset the counter + v.goodCnt := (others => '0'); + + -- Make a cached copy + v.dlyCache := r.dlyConfig; + + -- Update the Delay module + v.dlyLoad(1) := '1'; + v.dlyConfig := r.dlyConfig + 1; + + -- Next state + v.state := SLIP_WAIT_S; + + end if; + + end if; + end if; + ---------------------------------------------------------------------- + when EYE_SCAN_S => + -- Check for data + if (valid = '1') then + + -- Check for bad header and less than min. eye width configuration + if (v.errorDet = '1') and (scanCnt <= eyescanCfg) then + -- Execute the slip procedure + slipProcedure; + + -- Check for not roll over and not + elsif (r.goodCnt < lockingCntCfg) and (v.errorDet = '0') then + -- Increment the counter + v.goodCnt := r.goodCnt + 1; + else + + -- Reset the counter + v.goodCnt := (others => '0'); + + -- Update the Delay module + v.dlyLoad(1) := '1'; + v.dlyConfig := r.dlyConfig + 1; + + -- Check for last count or first header error after min. eye width + if (scanCnt >= 255) or (v.errorDet = '1') then + + -- Set to half way between eye + v.dlyConfig := r.dlyCache + scanHalf; + + -- Set the flag + v.scanDone := '1'; + + end if; + + -- Next state + v.state := SLIP_WAIT_S; + + end if; + end if; + ---------------------------------------------------------------------- + when LOCKED_S => + -- Check for data + if (valid = '1') then + + -- Check for bad header + if (v.errorDet = '1') then + -- Execute the slip procedure + slipProcedure; + + else + -- Set the flag + v.locked := '1'; + end if; + + end if; + ---------------------------------------------------------------------- + end case; + + -- Keep a delayed copy + v.enUsrDlyCfg := enUsrDlyCfg; + v.usrDlyCfg := usrDlyCfg; + + -- Check for changes in enUsrDlyCfg values or usrDlyCfg values or dlyConfig value + if (r.enUsrDlyCfg /= v.enUsrDlyCfg) or (r.usrDlyCfg /= v.usrDlyCfg) or (r.dlyConfig /= v.dlyConfig) then + -- Update the RX IDELAY configuration + v.dlyLoad(1) := '1'; + end if; + + -- Outputs + locked <= r.locked; + bitSlip <= r.slip; + dlyLoad <= r.dlyLoad(0); + errorDet <= r.errorDet; + + -- Check if using user delay configuration + if (enUsrDlyCfg = '1') then + -- Force to user configuration + dlyCfg <= usrDlyCfg; + else + -- Else use the automatic value + dlyCfg <= r.dlyConfig; + end if; + + -- Reset + if (rst = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (clk) is + begin + if (rising_edge(clk)) then + r <= rin after TPD_G; + end if; + end process seq; + +end rtl; From 4a79b0a183c7069e0e1e6a5fcdf013534ffe3ff8 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 2 Jun 2020 20:49:18 -0700 Subject: [PATCH 02/40] updating generic from ENCODE_G to CODE_TYPE_G --- .../general/rtl/SelectIoRxGearboxAligner.vhd | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd b/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd index 8e9720a2f4..68cace6e15 100644 --- a/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd +++ b/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd @@ -24,17 +24,17 @@ entity SelectIoRxGearboxAligner is generic ( TPD_G : time := 1 ns; NUM_BYTES_G : positive := 1; - ENCODE_G : boolean := false; + CODE_TYPE_G : string := "LINE_CODE"; -- or "SCRAMBLER" SIMULATION_G : boolean := false); port ( -- Clock and Reset clk : in sl; rst : in sl; - -- Line-Code Interface (ENCODE_G = false) + -- Line-Code Interface (CODE_TYPE_G = "LINE_CODE") lineCodeValid : in sl; lineCodeErr : in slv(NUM_BYTES_G-1 downto 0); lineCodeDispErr : in slv(NUM_BYTES_G-1 downto 0); - -- 64b/66b Interface (ENCODE_G = true) + -- 64b/66b Interface (CODE_TYPE_G = "SCRAMBLER") rxHeaderValid : in sl; rxHeader : in slv(1 downto 0); -- Gearbox Slip @@ -102,6 +102,10 @@ architecture rtl of SelectIoRxGearboxAligner is begin + assert ((CODE_TYPE_G = "LINE_CODE") or (CODE_TYPE_G = "SCRAMBLER")) + report "CODE_TYPE_G must be LINE_CODE or SCRAMBLER" + severity failure; + comb : process (bypFirstBerDet, enUsrDlyCfg, lineCodeDispErr, lineCodeErr, lineCodeValid, lockingCntCfg, minEyeWidth, r, rst, rxHeader, rxHeaderValid, usrDlyCfg) is @@ -169,16 +173,16 @@ begin -- Shift register v.dlyLoad := '0' & r.dlyLoad(1); - -- 64b/66b Interface (ENCODE_G = true) - if ENCODE_G then + -- 64b/66b Interface + if (CODE_TYPE_G = "SCRAMBLER") then valid := rxHeaderValid; -- Check for bad header if (rxHeaderValid = '1') and ((rxHeader = "00") or (rxHeader = "11")) then v.errorDet := '1'; end if; - -- Line-Code Interface (ENCODE_G = false) - else + -- Line-Code Interface + elsif (CODE_TYPE_G = "LINE_CODE") then valid := lineCodeValid; -- Check for bad header if (lineCodeValid = '1') and (uOr(lineCodeErr) = '1' or uOr(lineCodeDispErr) = '1') then From 9e8c6a6486ea868e0e8f2ab9455e499dafd04949 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 3 Jun 2020 12:40:10 -0700 Subject: [PATCH 03/40] Updating comments --- xilinx/general/rtl/SelectIoRxGearboxAligner.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd b/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd index 68cace6e15..073836fdcf 100644 --- a/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd +++ b/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd @@ -41,11 +41,11 @@ entity SelectIoRxGearboxAligner is bitSlip : out sl; -- IDELAY (DELAY_TYPE="VAR_LOAD") Interface dlyLoad : out sl; - dlyCfg : out slv(8 downto 0); + dlyCfg : out slv(8 downto 0); -- Ultrascale: CNTVALUEIN=dlyCfg(8 downto 0), 7-series: CNTVALUEIN=dlyCfg(8 downto 4) -- Configuration Interface enUsrDlyCfg : in sl := '0'; -- Enable User delay config usrDlyCfg : in slv(8 downto 0) := (others => '0'); -- User delay config - bypFirstBerDet : in sl := '1'; -- Set to '1' if IDELAY full scale range > 1 UI of serial rate (example: IDELAY range 2.5ns > 1 ns "1Gb/s" ) + bypFirstBerDet : in sl := '1'; -- Set to '1' if IDELAY full scale range > 2 Unit Intervals (UI) of serial rate (example: IDELAY range 2.5ns > 1 ns "1Gb/s" ) minEyeWidth : in slv(7 downto 0) := toSlv(80, 8); -- Sets the minimum eye width required for locking (units of IDELAY step) lockingCntCfg : in slv(23 downto 0) := ite(SIMULATION_G, x"00_0064", x"00_FFFF"); -- Number of error-free event before state=LOCKED_S -- Status Interface From 24ab420bf0439210c9e0f144d34ec773c6695762 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 5 Jun 2020 11:32:02 -0700 Subject: [PATCH 04/40] Update _Dac38J84.py ### Description -- Adding NcoSync() command -- Optimization for the time.sleep() --- python/surf/devices/ti/_Dac38J84.py | 51 +++++++++++++++++++---------- 1 file changed, 33 insertions(+), 18 deletions(-) diff --git a/python/surf/devices/ti/_Dac38J84.py b/python/surf/devices/ti/_Dac38J84.py index e6d6fa5388..cd34c694e6 100644 --- a/python/surf/devices/ti/_Dac38J84.py +++ b/python/surf/devices/ti/_Dac38J84.py @@ -374,42 +374,57 @@ def ClearAlarms(): self.DacReg[108].set(0) self.DacReg[109].set(0) + @self.command(name="NcoSync", description="Special DAC Init procedure to sync NCO",) + def NcoSync(): + self.EnableTx.set(0x0) + time.sleep(0.100) # TODO: Optimize this timeout + self.InitJesd.set(0x1) + time.sleep(0.100) # TODO: Optimize this timeout + self.JesdRstN.set(0x0) + time.sleep(0.100) # TODO: Optimize this timeout + self.JesdRstN.set(0x1) + time.sleep(0.100) # TODO: Optimize this timeout + self.InitJesd.set(0x0) + time.sleep(0.100) # TODO: Optimize this timeout + self.EnableTx.set(0x1) + time.sleep(0.100) # TODO: Optimize this timeout + @self.command(name="Init", description="Initialization sequence for the DAC JESD core",) def Init(): self.writeBlocks(force=True) self.EnableTx.set(0) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.ClearAlarms() - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.DacReg[59].set( self.DacReg[59].value() ) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.DacReg[37].set( self.DacReg[37].value() ) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.DacReg[60].set( self.DacReg[60].value() | 0x0200 ) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.DacReg[60].set( self.DacReg[60].value() & 0xFDFF ) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.DacReg[62].set( self.DacReg[62].value() ) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.DacReg[76].set( self.DacReg[76].value() ) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.DacReg[77].set( self.DacReg[77].value() ) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.DacReg[75].set( self.DacReg[75].value() ) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.DacReg[77].set( self.DacReg[77].value() ) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.DacReg[78].set( self.DacReg[78].value() ) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.DacReg[0].set( self.DacReg[0].value() ) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.DacReg[74].set( (self.DacReg[74].value() & 0xFFE0) | 0x1E ) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.DacReg[74].set( (self.DacReg[74].value() & 0xFFE0) | 0x1E ) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.DacReg[74].set( (self.DacReg[74].value() & 0xFFE0) | 0x1F ) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.DacReg[74].set( (self.DacReg[74].value() & 0xFFE0) | 0x01 ) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout self.EnableTx.set(1) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.100) # TODO: Optimize this timeout From 4de0f7b54520ad60a7ed6b8164be66e180108d54 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 5 Jun 2020 12:45:52 -0700 Subject: [PATCH 05/40] Update _Dac38J84.py --- python/surf/devices/ti/_Dac38J84.py | 48 ++++++++++++++--------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/python/surf/devices/ti/_Dac38J84.py b/python/surf/devices/ti/_Dac38J84.py index cd34c694e6..1cb4f38ed5 100644 --- a/python/surf/devices/ti/_Dac38J84.py +++ b/python/surf/devices/ti/_Dac38J84.py @@ -377,54 +377,54 @@ def ClearAlarms(): @self.command(name="NcoSync", description="Special DAC Init procedure to sync NCO",) def NcoSync(): self.EnableTx.set(0x0) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.InitJesd.set(0x1) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.JesdRstN.set(0x0) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.JesdRstN.set(0x1) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.InitJesd.set(0x0) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.EnableTx.set(0x1) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout @self.command(name="Init", description="Initialization sequence for the DAC JESD core",) def Init(): self.writeBlocks(force=True) self.EnableTx.set(0) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.ClearAlarms() - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.DacReg[59].set( self.DacReg[59].value() ) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.DacReg[37].set( self.DacReg[37].value() ) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.DacReg[60].set( self.DacReg[60].value() | 0x0200 ) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.DacReg[60].set( self.DacReg[60].value() & 0xFDFF ) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.DacReg[62].set( self.DacReg[62].value() ) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.DacReg[76].set( self.DacReg[76].value() ) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.DacReg[77].set( self.DacReg[77].value() ) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.DacReg[75].set( self.DacReg[75].value() ) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.DacReg[77].set( self.DacReg[77].value() ) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.DacReg[78].set( self.DacReg[78].value() ) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.DacReg[0].set( self.DacReg[0].value() ) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.DacReg[74].set( (self.DacReg[74].value() & 0xFFE0) | 0x1E ) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.DacReg[74].set( (self.DacReg[74].value() & 0xFFE0) | 0x1E ) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.DacReg[74].set( (self.DacReg[74].value() & 0xFFE0) | 0x1F ) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.DacReg[74].set( (self.DacReg[74].value() & 0xFFE0) | 0x01 ) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout self.EnableTx.set(1) - time.sleep(0.100) # TODO: Optimize this timeout + time.sleep(0.010) # TODO: Optimize this timeout From b1bb7ead9e3126e80e227b971922206691a02492 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 5 Jun 2020 14:39:12 -0700 Subject: [PATCH 06/40] Update Code10b12bPkg.vhd ### Description - Adding more control symbols constants --- protocols/line-codes/rtl/Code10b12bPkg.vhd | 32 +++++++++++++++++----- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/protocols/line-codes/rtl/Code10b12bPkg.vhd b/protocols/line-codes/rtl/Code10b12bPkg.vhd index c60396cd74..120dbcbc49 100644 --- a/protocols/line-codes/rtl/Code10b12bPkg.vhd +++ b/protocols/line-codes/rtl/Code10b12bPkg.vhd @@ -19,20 +19,38 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; - library surf; use surf.StdRtlPkg.all; --use surf.TextUtilPkg.all; package Code10b12bPkg is - -- Delcare input constants for commas and other important K_CODES - constant K_28_3_C : slv(9 downto 0) := "0001111100"; -- 0x07C -> 0x8FC, 0x703 - constant K_28_11_C : slv(9 downto 0) := "0101111100"; -- 0x17C -> 0x2FC, 0xD03 - constant K_28_19_C : slv(9 downto 0) := "1001111100"; -- 0x27C -> 0x4FC, 0xB03 + ------------------------------------------------------------------------------------------------- + -- Control Symbols Constants + -- Note: None of these control symbols defined below are "natural commas" + ------------------------------------------------------------------------------------------------- + constant K_28_3_C : slv(9 downto 0) := b"00011_11100"; -- 0x07C -> 0x8FC, 0x703 + constant K_28_5_C : slv(9 downto 0) := b"00101_11100"; -- 0x0BC -> 0x683, 0x97C + constant K_28_6_C : slv(9 downto 0) := b"00110_11100"; -- 0x0DC -> 0x643, 0x9BC + constant K_28_9_C : slv(9 downto 0) := b"01001_11100"; -- 0x13C -> 0x583, 0xA7C + constant K_28_10_C : slv(9 downto 0) := b"01010_11100"; -- 0x15C -> 0xABC, 0x543 + constant K_28_11_C : slv(9 downto 0) := b"01011_11100"; -- 0x17C -> 0x2FC, 0xD03 + constant K_28_12_C : slv(9 downto 0) := b"01100_11100"; -- 0x19C -> 0x4C3, 0xB3C + constant K_28_13_C : slv(9 downto 0) := b"01101_11100"; -- 0x1BC -> 0x37C, 0xC83 + constant K_28_14_C : slv(9 downto 0) := b"01110_11100"; -- 0x1DC -> 0x3BC, 0xC43 + constant K_28_17_C : slv(9 downto 0) := b"10001_11100"; -- 0x23C -> 0x383, 0xC7C + constant K_28_18_C : slv(9 downto 0) := b"10010_11100"; -- 0x25C -> 0x343, 0xCBC + constant K_28_19_C : slv(9 downto 0) := b"10011_11100"; -- 0x27C -> 0x4FC, 0xB03 + constant K_28_20_C : slv(9 downto 0) := b"10100_11100"; -- 0x29C -> 0x2C3, 0xD3C + constant K_28_21_C : slv(9 downto 0) := b"10101_11100"; -- 0x2BC -> 0x57C, 0xA83 + constant K_28_22_C : slv(9 downto 0) := b"10110_11100"; -- 0x2DC -> 0x5BC, 0xA43 + constant K_28_25_C : slv(9 downto 0) := b"11001_11100"; -- 0x33C -> 0x67C, 0x983 + constant K_28_26_C : slv(9 downto 0) := b"11010_11100"; -- 0x35C -> 0x6BC, 0x943 - constant K_28_10_C : slv(9 downto 0) := "0101011100"; -- 0x15C -> 0xABC, 0x543 - constant K_28_21_C : slv(9 downto 0) := "1010111100"; -- 0x2BC -> 0x57C, 0xA83 + ------------------------------------------------------------------------------------------------- + -- [D7.7, D7.7] is a special case + ------------------------------------------------------------------------------------------------- + constant D_7_7_C : slv(9 downto 0) := b"00111_00111"; -- 0x0E7 -> 0x1C7, 0x1C7 ------------------------------------------------------------------------------------------------- -- Disparity types and helper functions From 9f34bf65713cf2527161bfc328f34dcff2d052a5 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 5 Jun 2020 15:08:18 -0700 Subject: [PATCH 07/40] addin outOfSync to SspDecoders --- protocols/ssp/rtl/SspDecoder10b12b.vhd | 2 ++ protocols/ssp/rtl/SspDecoder12b14b.vhd | 2 ++ protocols/ssp/rtl/SspDecoder8b10b.vhd | 2 ++ protocols/ssp/rtl/SspDeframer.vhd | 19 +++++++++++++------ 4 files changed, 19 insertions(+), 6 deletions(-) diff --git a/protocols/ssp/rtl/SspDecoder10b12b.vhd b/protocols/ssp/rtl/SspDecoder10b12b.vhd index 5f288d3f68..19fa7664b1 100644 --- a/protocols/ssp/rtl/SspDecoder10b12b.vhd +++ b/protocols/ssp/rtl/SspDecoder10b12b.vhd @@ -38,6 +38,7 @@ entity SspDecoder10b12b is validIn : in sl := '1'; dataOut : out slv(9 downto 0); validOut : out sl; + outOfSync : out sl; sof : out sl; eof : out sl; eofe : out sl; @@ -95,6 +96,7 @@ begin dataKIn => framedDataK, dataOut => dataOut, validOut => validOut, + outOfSync=> outOfSync, sof => sof, eof => eof, eofe => eofe); diff --git a/protocols/ssp/rtl/SspDecoder12b14b.vhd b/protocols/ssp/rtl/SspDecoder12b14b.vhd index c703efce32..ce469a7ec6 100644 --- a/protocols/ssp/rtl/SspDecoder12b14b.vhd +++ b/protocols/ssp/rtl/SspDecoder12b14b.vhd @@ -38,6 +38,7 @@ entity SspDecoder12b14b is validOut : out sl; dataOut : out slv(11 downto 0); valid : out sl; + outOfSync : out sl; sof : out sl; eof : out sl; eofe : out sl; @@ -93,6 +94,7 @@ begin dataKIn => framedDataK, validOut => validOut, dataOut => dataOut, + outOfSync=> outOfSync, sof => sof, eof => eof, eofe => eofe); diff --git a/protocols/ssp/rtl/SspDecoder8b10b.vhd b/protocols/ssp/rtl/SspDecoder8b10b.vhd index e83d34b66e..ba1a117ba2 100644 --- a/protocols/ssp/rtl/SspDecoder8b10b.vhd +++ b/protocols/ssp/rtl/SspDecoder8b10b.vhd @@ -38,6 +38,7 @@ entity SspDecoder8b10b is validIn : in sl := '1'; dataOut : out slv(15 downto 0); validOut : out sl; + outOfSync: out sl; sof : out sl; eof : out sl; eofe : out sl); @@ -95,6 +96,7 @@ begin decErrIn => decErr, dataOut => dataOut, validOut => validOut, + outOfSync=> outOfSync, sof => sof, eof => eof, eofe => eofe); diff --git a/protocols/ssp/rtl/SspDeframer.vhd b/protocols/ssp/rtl/SspDeframer.vhd index 6c840aff70..928a9fe6b1 100644 --- a/protocols/ssp/rtl/SspDeframer.vhd +++ b/protocols/ssp/rtl/SspDeframer.vhd @@ -19,7 +19,6 @@ use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; use IEEE.STD_LOGIC_ARITH.all; - library surf; use surf.StdRtlPkg.all; @@ -38,19 +37,21 @@ entity SspDeframer is SSP_EOF_CODE_G : slv; SSP_EOF_K_G : slv); port ( + -- Clock and Reset clk : in sl; rst : in sl := RST_POLARITY_G; + -- Input Interface dataKIn : in slv(K_SIZE_G-1 downto 0); dataIn : in slv(WORD_SIZE_G-1 downto 0); validIn : in sl; decErrIn : in sl := '0'; + -- Output Interface dataOut : out slv(WORD_SIZE_G-1 downto 0); validOut : out sl; + outOfSync: out sl; sof : out sl; eof : out sl; eofe : out sl); - - end entity SspDeframer; architecture rtl of SspDeframer is @@ -71,6 +72,7 @@ architecture rtl of SspDeframer is -- Output registers dataOut : slv(WORD_SIZE_G-1 downto 0); validOut : sl; + outOfSync: sl; sof : sl; eof : sl; eofe : sl; @@ -86,6 +88,7 @@ architecture rtl of SspDeframer is iEofe => '0', dataOut => (others => '0'), validOut => '0', + outOfSync => '0', sof => '0', eof => '0', eofe => '0'); @@ -100,8 +103,7 @@ begin begin v := r; --- v.iDataOut := dataIn; --- v.iValidOut := '0'; + v.outOfSync := '0'; if (validIn = '1') then @@ -131,7 +133,10 @@ begin v.iEof := '1'; v.iEofe := '1'; v.iValidOut := '1'; + v.outOfSync := '1'; end if; + else + v.outOfSync := '1'; end if; elsif (r.state = WAIT_EOF_S) then @@ -164,13 +169,15 @@ begin v.iValidOut := '0'; v.iEof := '1'; v.iEofe := '1'; + v.outOfSync := '1'; v.state := WAIT_SOF_S; end if; end if; if (decErrIn = '1') then - v.iEofe := '1'; + v.iEofe := '1'; + v.outOfSync := '1'; end if; end if; From 9c4d0f1ad4459af4f532154f1c4ad834e26865ff Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 5 Jun 2020 15:10:34 -0700 Subject: [PATCH 08/40] adding linkError to SelectIoRxGearboxAligner --- protocols/ssp/rtl/SspDeframer.vhd | 1 + xilinx/general/rtl/SelectIoRxGearboxAligner.vhd | 13 +++++++------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/protocols/ssp/rtl/SspDeframer.vhd b/protocols/ssp/rtl/SspDeframer.vhd index 928a9fe6b1..a33b8767db 100644 --- a/protocols/ssp/rtl/SspDeframer.vhd +++ b/protocols/ssp/rtl/SspDeframer.vhd @@ -205,6 +205,7 @@ begin rin <= v; dataOut <= r.dataOut; validOut <= r.validOut; + outOfSync<= r.outOfSync; sof <= r.sof; eof <= r.eof; eofe <= r.eofe; diff --git a/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd b/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd index 073836fdcf..840d85471c 100644 --- a/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd +++ b/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd @@ -37,11 +37,12 @@ entity SelectIoRxGearboxAligner is -- 64b/66b Interface (CODE_TYPE_G = "SCRAMBLER") rxHeaderValid : in sl; rxHeader : in slv(1 downto 0); - -- Gearbox Slip + -- Link Status and Gearbox Slip + linkError : in sl; bitSlip : out sl; -- IDELAY (DELAY_TYPE="VAR_LOAD") Interface dlyLoad : out sl; - dlyCfg : out slv(8 downto 0); -- Ultrascale: CNTVALUEIN=dlyCfg(8 downto 0), 7-series: CNTVALUEIN=dlyCfg(8 downto 4) + dlyCfg : out slv(8 downto 0); -- Ultrascale: CNTVALUEIN=dlyCfg(8 downto 0), 7-series: CNTVALUEIN=dlyCfg(8 downto 4) -- Configuration Interface enUsrDlyCfg : in sl := '0'; -- Enable User delay config usrDlyCfg : in slv(8 downto 0) := (others => '0'); -- User delay config @@ -107,8 +108,8 @@ begin severity failure; comb : process (bypFirstBerDet, enUsrDlyCfg, lineCodeDispErr, lineCodeErr, - lineCodeValid, lockingCntCfg, minEyeWidth, r, rst, rxHeader, - rxHeaderValid, usrDlyCfg) is + lineCodeValid, linkError, lockingCntCfg, minEyeWidth, r, + rst, rxHeader, rxHeaderValid, usrDlyCfg) is variable v : RegType; procedure slipProcedure is @@ -177,7 +178,7 @@ begin if (CODE_TYPE_G = "SCRAMBLER") then valid := rxHeaderValid; -- Check for bad header - if (rxHeaderValid = '1') and ((rxHeader = "00") or (rxHeader = "11")) then + if (rxHeaderValid = '1') and ((rxHeader = "00") or (rxHeader = "11")) or (linkError = '1') then v.errorDet := '1'; end if; @@ -185,7 +186,7 @@ begin elsif (CODE_TYPE_G = "LINE_CODE") then valid := lineCodeValid; -- Check for bad header - if (lineCodeValid = '1') and (uOr(lineCodeErr) = '1' or uOr(lineCodeDispErr) = '1') then + if (lineCodeValid = '1') and (uOr(lineCodeErr) = '1' or uOr(lineCodeDispErr) = '1') or (linkError = '1') then v.errorDet := '1'; end if; end if; From c05efa8edab47856baa08d7ab5b606faa3040630 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 5 Jun 2020 15:38:00 -0700 Subject: [PATCH 09/40] bug fix --- xilinx/general/rtl/SelectIoRxGearboxAligner.vhd | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd b/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd index 840d85471c..06f99d62b1 100644 --- a/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd +++ b/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd @@ -178,7 +178,7 @@ begin if (CODE_TYPE_G = "SCRAMBLER") then valid := rxHeaderValid; -- Check for bad header - if (rxHeaderValid = '1') and ((rxHeader = "00") or (rxHeader = "11")) or (linkError = '1') then + if (rxHeaderValid = '1') and ((rxHeader = "00") or (rxHeader = "11")) then v.errorDet := '1'; end if; @@ -186,11 +186,17 @@ begin elsif (CODE_TYPE_G = "LINE_CODE") then valid := lineCodeValid; -- Check for bad header - if (lineCodeValid = '1') and (uOr(lineCodeErr) = '1' or uOr(lineCodeDispErr) = '1') or (linkError = '1') then + if (lineCodeValid = '1') and (uOr(lineCodeErr) = '1' or uOr(lineCodeDispErr) = '1') then v.errorDet := '1'; end if; end if; + -- Check for physical link error + if (linkError = '1') then + valid := '1'; + v.errorDet := '1'; + end if; + -- State Machine case r.state is ---------------------------------------------------------------------- @@ -209,13 +215,13 @@ begin ---------------------------------------------------------------------- when SLIP_WAIT_S => -- Check the counter - if (r.slipWaitCnt = SLIP_WAIT_C-1) then + if (r.slipWaitCnt = SLIP_WAIT_C-1) or (r.enUsrDlyCfg = '1') then -- Reset the counter v.slipWaitCnt := 0; -- Check if eye scan completed - if (r.scanDone = '1') then + if (r.scanDone = '1') or (r.enUsrDlyCfg = '1') then -- Next state v.state := LOCKED_S; -- Check for armed mode From 72a3528a02e4e1e99697f33b15bd97df585b2d0f Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 5 Jun 2020 16:32:47 -0700 Subject: [PATCH 10/40] bug fix --- xilinx/general/rtl/SelectIoRxGearboxAligner.vhd | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd b/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd index 06f99d62b1..55cf96c1ea 100644 --- a/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd +++ b/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd @@ -191,12 +191,6 @@ begin end if; end if; - -- Check for physical link error - if (linkError = '1') then - valid := '1'; - v.errorDet := '1'; - end if; - -- State Machine case r.state is ---------------------------------------------------------------------- @@ -252,7 +246,7 @@ begin v.goodCnt := r.goodCnt + 1; else - -- Check if no bit errors detected yet during this IDELAY sweep + -- Check if no bit errors detected yet during this IDELAY sweep if (r.firstError = '0') and (bypFirstBerDet = '0') then -- Execute the slip procedure slipProcedure; @@ -289,7 +283,7 @@ begin -- Execute the slip procedure slipProcedure; - -- Check for not roll over and not + -- Check for not roll over and not elsif (r.goodCnt < lockingCntCfg) and (v.errorDet = '0') then -- Increment the counter v.goodCnt := r.goodCnt + 1; @@ -321,10 +315,10 @@ begin ---------------------------------------------------------------------- when LOCKED_S => -- Check for data - if (valid = '1') then + if (valid = '1') or (linkError = '1') then -- Check for bad header - if (v.errorDet = '1') then + if (v.errorDet = '1') or (linkError = '1') then -- Execute the slip procedure slipProcedure; @@ -347,7 +341,7 @@ begin v.dlyLoad(1) := '1'; end if; - -- Outputs + -- Outputs locked <= r.locked; bitSlip <= r.slip; dlyLoad <= r.dlyLoad(0); From c1cd5c30fbddcec16a896831a7b4310fbb19a89f Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 5 Jun 2020 18:26:51 -0700 Subject: [PATCH 11/40] Modify comments --- protocols/line-codes/rtl/Code10b12bPkg.vhd | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/protocols/line-codes/rtl/Code10b12bPkg.vhd b/protocols/line-codes/rtl/Code10b12bPkg.vhd index 120dbcbc49..393ccc8d9a 100644 --- a/protocols/line-codes/rtl/Code10b12bPkg.vhd +++ b/protocols/line-codes/rtl/Code10b12bPkg.vhd @@ -27,20 +27,23 @@ package Code10b12bPkg is ------------------------------------------------------------------------------------------------- -- Control Symbols Constants - -- Note: None of these control symbols defined below are "natural commas" ------------------------------------------------------------------------------------------------- + -- These symbols are commas, sequences that can be used for word alignment constant K_28_3_C : slv(9 downto 0) := b"00011_11100"; -- 0x07C -> 0x8FC, 0x703 + constant K_28_11_C : slv(9 downto 0) := b"01011_11100"; -- 0x17C -> 0x2FC, 0xD03 + constant K_28_19_C : slv(9 downto 0) := b"10011_11100"; -- 0x27C -> 0x4FC, 0xB03 + + -- These symbols are not commas but can be used to initiate control sequences + -- Technically any K.28.x character is a valid k-char but these are preffered constant K_28_5_C : slv(9 downto 0) := b"00101_11100"; -- 0x0BC -> 0x683, 0x97C constant K_28_6_C : slv(9 downto 0) := b"00110_11100"; -- 0x0DC -> 0x643, 0x9BC constant K_28_9_C : slv(9 downto 0) := b"01001_11100"; -- 0x13C -> 0x583, 0xA7C constant K_28_10_C : slv(9 downto 0) := b"01010_11100"; -- 0x15C -> 0xABC, 0x543 - constant K_28_11_C : slv(9 downto 0) := b"01011_11100"; -- 0x17C -> 0x2FC, 0xD03 constant K_28_12_C : slv(9 downto 0) := b"01100_11100"; -- 0x19C -> 0x4C3, 0xB3C constant K_28_13_C : slv(9 downto 0) := b"01101_11100"; -- 0x1BC -> 0x37C, 0xC83 constant K_28_14_C : slv(9 downto 0) := b"01110_11100"; -- 0x1DC -> 0x3BC, 0xC43 constant K_28_17_C : slv(9 downto 0) := b"10001_11100"; -- 0x23C -> 0x383, 0xC7C constant K_28_18_C : slv(9 downto 0) := b"10010_11100"; -- 0x25C -> 0x343, 0xCBC - constant K_28_19_C : slv(9 downto 0) := b"10011_11100"; -- 0x27C -> 0x4FC, 0xB03 constant K_28_20_C : slv(9 downto 0) := b"10100_11100"; -- 0x29C -> 0x2C3, 0xD3C constant K_28_21_C : slv(9 downto 0) := b"10101_11100"; -- 0x2BC -> 0x57C, 0xA83 constant K_28_22_C : slv(9 downto 0) := b"10110_11100"; -- 0x2DC -> 0x5BC, 0xA43 @@ -48,7 +51,7 @@ package Code10b12bPkg is constant K_28_26_C : slv(9 downto 0) := b"11010_11100"; -- 0x35C -> 0x6BC, 0x943 ------------------------------------------------------------------------------------------------- - -- [D7.7, D7.7] is a special case + -- D.7.7 constant helpful for testing ------------------------------------------------------------------------------------------------- constant D_7_7_C : slv(9 downto 0) := b"00111_00111"; -- 0x0E7 -> 0x1C7, 0x1C7 From 99198b5f13b7b12eed1ace5e077f6a13666e158e Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 5 Jun 2020 18:27:54 -0700 Subject: [PATCH 12/40] Fix typo --- protocols/line-codes/rtl/Code10b12bPkg.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/protocols/line-codes/rtl/Code10b12bPkg.vhd b/protocols/line-codes/rtl/Code10b12bPkg.vhd index 393ccc8d9a..c2e825c231 100644 --- a/protocols/line-codes/rtl/Code10b12bPkg.vhd +++ b/protocols/line-codes/rtl/Code10b12bPkg.vhd @@ -33,7 +33,7 @@ package Code10b12bPkg is constant K_28_11_C : slv(9 downto 0) := b"01011_11100"; -- 0x17C -> 0x2FC, 0xD03 constant K_28_19_C : slv(9 downto 0) := b"10011_11100"; -- 0x27C -> 0x4FC, 0xB03 - -- These symbols are not commas but can be used to initiate control sequences + -- These symbols are not commas but can be used for control sequences -- Technically any K.28.x character is a valid k-char but these are preffered constant K_28_5_C : slv(9 downto 0) := b"00101_11100"; -- 0x0BC -> 0x683, 0x97C constant K_28_6_C : slv(9 downto 0) := b"00110_11100"; -- 0x0DC -> 0x643, 0x9BC From d6fd335225a13a259ca19c20823fe7fe60a28056 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 8 Jun 2020 08:15:20 -0700 Subject: [PATCH 13/40] Update _Dac38J84.py --- python/surf/devices/ti/_Dac38J84.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/python/surf/devices/ti/_Dac38J84.py b/python/surf/devices/ti/_Dac38J84.py index 1cb4f38ed5..ec0207dba1 100644 --- a/python/surf/devices/ti/_Dac38J84.py +++ b/python/surf/devices/ti/_Dac38J84.py @@ -377,17 +377,17 @@ def ClearAlarms(): @self.command(name="NcoSync", description="Special DAC Init procedure to sync NCO",) def NcoSync(): self.EnableTx.set(0x0) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.010) self.InitJesd.set(0x1) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.010) self.JesdRstN.set(0x0) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.010) self.JesdRstN.set(0x1) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.010) self.InitJesd.set(0x0) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.010) self.EnableTx.set(0x1) - time.sleep(0.010) # TODO: Optimize this timeout + time.sleep(0.010) @self.command(name="Init", description="Initialization sequence for the DAC JESD core",) def Init(): From 82e0c1a752763a98a9d9c0dd40ea9f12a3e94b96 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 8 Jun 2020 08:38:41 -0700 Subject: [PATCH 14/40] adding SelectioDeser --- xilinx/7Series/general/rtl/SelectioDeser.vhd | 131 +++++++++++ .../7Series/general/rtl/SelectioDeserLane.vhd | 122 ++++++++++ .../UltraScale/general/rtl/SelectioDeser.vhd | 214 ++++++++++++++++++ .../general/rtl/SelectioDeserLane.vhd | 101 +++++++++ 4 files changed, 568 insertions(+) create mode 100644 xilinx/7Series/general/rtl/SelectioDeser.vhd create mode 100644 xilinx/7Series/general/rtl/SelectioDeserLane.vhd create mode 100644 xilinx/UltraScale/general/rtl/SelectioDeser.vhd create mode 100644 xilinx/UltraScale/general/rtl/SelectioDeserLane.vhd diff --git a/xilinx/7Series/general/rtl/SelectioDeser.vhd b/xilinx/7Series/general/rtl/SelectioDeser.vhd new file mode 100644 index 0000000000..aa078af033 --- /dev/null +++ b/xilinx/7Series/general/rtl/SelectioDeser.vhd @@ -0,0 +1,131 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: PLL and Deserialization +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +library unisim; +use unisim.vcomponents.all; + +entity SelectioDeser is + generic ( + TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; + NUM_LANE_G : positive := 1; + IODELAY_GROUP_G : string := "DESER_GROUP"; + REF_FREQ_G : real := 300.0; -- IDELAYCTRL's REFCLK (in units of Hz) + INPUT_BUFG_G : boolean := false; + FB_BUFG_G : boolean := false; + BANDWIDTH_G : string := "OPTIMIZED"; + CLKIN_PERIOD_G : real := 10.0; -- 100 MHz + DIVCLK_DIVIDE_G : positive := 1; + CLKFBOUT_MULT_G : positive := 10; -- 1 GHz = 100 MHz x 10 / 1 + CLKOUT0_DIVIDE_G : positive := 2); -- 500 MHz = 1 GHz/2 + port ( + -- SELECTIO Ports + rxP : in slv(NUM_LANE_G-1 downto 0); + rxN : in slv(NUM_LANE_G-1 downto 0); + pllClk : out sl; + -- Reference Clock and Reset + refClk : in sl; + refRst : in sl; + -- Deserialization Interface (deserClk domain) + deserClk : out sl; + deserRst : out sl; + deserData : out Slv8Array(NUM_LANE_G-1 downto 0); + dlyLoad : in slv(NUM_LANE_G-1 downto 0); + dlyCfg : in Slv9Array(NUM_LANE_G-1 downto 0); + -- AXI-Lite Interface (axilClk domain) + axilClk : in sl := '0'; + axilRst : in sl := '0'; + axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + axilWriteSlave : out AxiLiteWriteSlaveType); +end SelectioDeser; + +architecture mapping of SelectioDeser is + + signal clkx4 : sl := '0'; + signal clkx1 : sl := '0'; + + signal rstx1 : sl := '1'; + signal rstx4 : sl := '1'; + +begin + + pllClk <= clkx4; + deserClk <= clkx1; + deserRst <= rstx1; + + U_MMCM : entity surf.ClockManager7 + generic map( + TPD_G => TPD_G, + SIMULATION_G => SIMULATION_G, + TYPE_G => "MMCM", + BANDWIDTH_G => BANDWIDTH_G, + INPUT_BUFG_G => INPUT_BUFG_G, + FB_BUFG_G => FB_BUFG_G, + NUM_CLOCKS_G => 2, + CLKIN_PERIOD_G => CLKIN_PERIOD_G, + DIVCLK_DIVIDE_G => DIVCLK_DIVIDE_G, + CLKFBOUT_MULT_F_G => CLKFBOUT_MULT_F_G, + CLKOUT0_DIVIDE_F_G => CLKOUT0_DIVIDE_G, + CLKOUT1_DIVIDE_G => 4*integer(CLKOUT0_DIVIDE_G)) + port map( + clkIn => refClk, + rstIn => refRst, + -- Clock Outputs + clkOut(0) => clkx4, + clkOut(1) => clkx1, + -- Reset Outputs + rstOut(0) => rstx4, + rstOut(1) => rstx1, + -- AXI-Lite Port + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + + GEN_VEC : + for i in NUM_LANE_G-1 downto 0 generate + + U_Lane : entity surf.SelectioDeserLane + generic map ( + TPD_G => TPD_G) + port map ( + -- SELECTIO Ports + rxP => rxP(i), + rxN => rxN(i), + -- Clock and Reset Interface + clkx4 => clkx4, + clkx1 => clkx1, + rstx1 => rstx1, + -- Delay Configuration + dlyLoad => dlyLoad(i), + dlyCfg => dlyCfg(i), + -- Output + dataOut => deserData(i)); + + end generate GEN_VEC; + +end mapping; diff --git a/xilinx/7Series/general/rtl/SelectioDeserLane.vhd b/xilinx/7Series/general/rtl/SelectioDeserLane.vhd new file mode 100644 index 0000000000..2d172483b4 --- /dev/null +++ b/xilinx/7Series/general/rtl/SelectioDeserLane.vhd @@ -0,0 +1,122 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Wrapper for SelectioDeserLane +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; + +library unisim; +use unisim.vcomponents.all; + +entity SelectioDeserLane is + generic ( + TPD_G : time := 1 ns; + IODELAY_GROUP_G : string := "DESER_GROUP"; + REF_FREQ_G : real := 300.0); -- IDELAYCTRL's REFCLK (in units of Hz) + port ( + -- SELECTIO Ports + rxP : in sl; + rxN : in sl; + -- Clock and Reset Interface + clkx4 : in sl; + clkx1 : in sl; + rstx1 : in sl; + -- Delay Configuration + dlyLoad : in sl; + dlyCfg : in slv(8 downto 0); + -- Output + dataOut : out slv(7 downto 0)); +end SelectioDeserLane; + +architecture mapping of SelectioDeserLane is + + signal rx : sl; + signal rxDly : sl; + signal clkx4L : sl; + + attribute IODELAY_GROUP : string; + attribute IODELAY_GROUP of U_DELAY : label is IODELAY_GROUP_G; + +begin + + U_IBUFDS : IBUFDS + port map ( + I => rxP, + IB => rxN, + O => rx); + + U_DELAY : IDELAYE2 + generic map ( + REFCLK_FREQUENCY => REF_FREQ_G, + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_VALUE => 0, + DELAY_SRC => "IDATAIN", + IDELAY_TYPE => "VAR_LOAD") + port map( + DATAIN => '0', + IDATAIN => rx, + DATAOUT => rxDly, + C => clkx1, + CE => '0', + INC => '0', + LD => dlyLoad, + LDPIPEEN => '0', + REGRST => '0', + CINVCTRL => '0', + CNTVALUEIN => dlyCfg(8 downto 4)); + + U_ISERDES : ISERDESE2 + generic map ( + DATA_WIDTH => 8, + DATA_RATE => "DDR", + IOBDELAY => "IFD", + DYN_CLK_INV_EN => "FALSE", + INTERFACE_TYPE => "NETWORKING") + port map ( + D => '0', + DDLY => rxDly, + CE1 => '1', + CE2 => '1', + CLK => clkx4, + CLKB => clkx4L, + RST => clkx1, + CLKDIV => rstx1, + CLKDIVP => '0', + OCLK => '0', + OCLKB => '0', + DYNCLKSEL => '0', + DYNCLKDIVSEL => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + BITSLIP => '0', + O => open, + Q8 => dataOut(0), + Q7 => dataOut(1), + Q6 => dataOut(2), + Q5 => dataOut(3), + Q4 => dataOut(4), + Q3 => dataOut(5), + Q2 => dataOut(6), + Q1 => dataOut(7), + OFB => '0', + SHIFTOUT1 => open, + SHIFTOUT2 => open); + + clkx4L <= not(clkx4); + +end mapping; diff --git a/xilinx/UltraScale/general/rtl/SelectioDeser.vhd b/xilinx/UltraScale/general/rtl/SelectioDeser.vhd new file mode 100644 index 0000000000..20885bacfa --- /dev/null +++ b/xilinx/UltraScale/general/rtl/SelectioDeser.vhd @@ -0,0 +1,214 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: PLL and Deserialization +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +library unisim; +use unisim.vcomponents.all; + +entity SelectioDeser is + generic ( + TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; + NUM_LANE_G : positive := 1; + CLKIN_PERIOD_G : real := 10.0; -- 100 MHz + DIVCLK_DIVIDE_G : positive := 1; + CLKFBOUT_MULT_G : positive := 10; -- 1 GHz = 100 MHz x 10 / 1 + CLKOUT0_DIVIDE_G : positive := 2); -- 500 MHz = 1 GHz/2 + port ( + -- SELECTIO Ports + rxP : in slv(NUM_LANE_G-1 downto 0); + rxN : in slv(NUM_LANE_G-1 downto 0); + pllClk : out sl; + -- Reference Clock and Reset + refClk : in sl; + refRst : in sl; + -- Deserialization Interface (deserClk domain) + deserClk : out sl; + deserRst : out sl; + deserData : out Slv8Array(NUM_LANE_G-1 downto 0); + dlyLoad : in slv(NUM_LANE_G-1 downto 0); + dlyCfg : in Slv9Array(NUM_LANE_G-1 downto 0); + -- AXI-Lite Interface (axilClk domain) + axilClk : in sl := '0'; + axilRst : in sl := '0'; + axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + axilWriteSlave : out AxiLiteWriteSlaveType); +end SelectioDeser; + +architecture mapping of SelectioDeser is + + signal drpRdy : sl; + signal drpEn : sl; + signal drpWe : sl; + signal drpAddr : slv(6 downto 0); + signal drpDi : slv(15 downto 0); + signal drpDo : slv(15 downto 0); + + signal locked : sl := '0'; + signal clkFb : sl := '0'; + signal clkout0 : sl := '0'; + + signal clkx4 : sl := '0'; + signal clkx1 : sl := '0'; + signal reset : sl := '1'; + signal rstx1 : sl := '1'; + +begin + + pllClk <= clkx4; + deserClk <= clkx1; + deserRst <= rstx1; + + GEN_REAL : if (SIMULATION_G = false) generate + + U_AxiLiteToDrp : entity surf.AxiLiteToDrp + generic map ( + TPD_G => TPD_G, + COMMON_CLK_G => true, + EN_ARBITRATION_G => false, + TIMEOUT_G => 4096, + ADDR_WIDTH_G => 7, + DATA_WIDTH_G => 16) + port map ( + -- AXI-Lite Port + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave, + -- DRP Interface + drpClk => axilClk, + drpRst => axilRst, + drpRdy => drpRdy, + drpEn => drpEn, + drpWe => drpWe, + drpAddr => drpAddr, + drpDi => drpDi, + drpDo => drpDo); + + U_PLL : PLLE3_ADV + generic map ( + COMPENSATION => "INTERNAL", + STARTUP_WAIT => "FALSE", + CLKIN_PERIOD => CLKIN_PERIOD_G, + DIVCLK_DIVIDE => DIVCLK_DIVIDE_G, + CLKFBOUT_MULT => CLKFBOUT_MULT_G, + CLKOUT0_DIVIDE => CLKOUT0_DIVIDE_G) + port map ( + DCLK => axilClk, + DRDY => drpRdy, + DEN => drpEn, + DWE => drpWe, + DADDR => drpAddr, + DI => drpDi, + DO => drpDo, + PWRDWN => '0', + RST => refRst, + CLKIN => refClk, + CLKOUTPHYEN => '0', + CLKFBOUT => clkFb, + CLKFBIN => clkFb, + LOCKED => locked, + CLKOUT0 => clkout0, + CLKOUT1 => open); + + end generate GEN_REAL; + + GEN_SIM : if (SIMULATION_G = true) generate + + axilReadSlave <= AXI_LITE_READ_SLAVE_EMPTY_DECERR_C; + axilWriteSlave <= AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C; + + U_ClkRst : entity surf.ClkRst + generic map ( + CLK_PERIOD_G => (CLKIN_PERIOD_G*DIVCLK_DIVIDE_G*CLKOUT0_DIVIDE_G/CLKFBOUT_MULT_G)*(1.0 ns), + RST_START_DELAY_G => 0 ns, + RST_HOLD_TIME_G => 1000 ns) + port map ( + clkP => clkout0, + rstL => locked); + + end generate GEN_SIM; + + U_Bufg640 : BUFG + port map ( + I => clkout0, + O => clkx4); + + ------------------------------------------------------------------------------------------------------ + -- clkx1 is the ISERDESE3/OSERDESE3's CLKDIV port + -- Refer to "Figure 3-49: Sub-Optimal to Optimal Clocking Topologies for OSERDESE3" in UG949 (v2018.2) + -- https://www.xilinx.com/support/answers/67885.html + ------------------------------------------------------------------------------------------------------ + U_Bufg : BUFGCE_DIV + generic map ( + BUFGCE_DIVIDE => 4) + port map ( + I => clkout0, + CE => '1', + CLR => '0', + O => clkx1); + + U_reset : entity surf.RstSync + generic map ( + TPD_G => TPD_G, + IN_POLARITY_G => '0', + OUT_POLARITY_G => '1') + port map ( + clk => clkx1, + asyncRst => locked, + syncRst => reset); + + U_rstx1 : entity surf.RstPipeline + generic map ( + TPD_G => TPD_G) + port map ( + clk => clkx1, + rstIn => reset, + rstOut => rstx1); + + GEN_VEC : + for i in NUM_LANE_G-1 downto 0 generate + + U_Lane : entity surf.SelectioDeserLane + generic map ( + TPD_G => TPD_G) + port map ( + -- SELECTIO Ports + rxP => rxP(i), + rxN => rxN(i), + -- Clock and Reset Interface + clkx4 => clkx4, + clkx1 => clkx1, + rstx1 => rstx1, + -- Delay Configuration + dlyLoad => dlyLoad(i), + dlyCfg => dlyCfg(i), + -- Output + dataOut => deserData(i)); + + end generate GEN_VEC; + +end mapping; diff --git a/xilinx/UltraScale/general/rtl/SelectioDeserLane.vhd b/xilinx/UltraScale/general/rtl/SelectioDeserLane.vhd new file mode 100644 index 0000000000..b39277bbee --- /dev/null +++ b/xilinx/UltraScale/general/rtl/SelectioDeserLane.vhd @@ -0,0 +1,101 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Wrapper for SelectioDeserLane +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; + +library unisim; +use unisim.vcomponents.all; + +entity SelectioDeserLane is + generic ( + TPD_G : time := 1 ns); + port ( + -- SELECTIO Ports + rxP : in sl; + rxN : in sl; + -- Clock and Reset Interface + clkx4 : in sl; + clkx1 : in sl; + rstx1 : in sl; + -- Delay Configuration + dlyLoad : in sl; + dlyCfg : in slv(8 downto 0); + -- Output + dataOut : out slv(7 downto 0)); +end SelectioDeserLane; + +architecture mapping of SelectioDeserLane is + + signal rx : sl; + signal rxDly : sl; + signal clkx4L : sl; + +begin + + U_IBUFDS : IBUFDS + port map ( + I => rxP, + IB => rxN, + O => rx); + + U_DELAY : entity surf.Idelaye3Wrapper + generic map ( + DELAY_FORMAT => "COUNT", + SIM_DEVICE => "ULTRASCALE", + DELAY_VALUE => 0, + REFCLK_FREQUENCY => 300.0, -- IDELAYCTRL not used in COUNT mode + UPDATE_MODE => "ASYNC", + CASCADE => "NONE", + DELAY_SRC => "IDATAIN", + DELAY_TYPE => "VAR_LOAD") + port map( + DATAIN => '0', + IDATAIN => rx, + DATAOUT => rxDly, + CLK => clkx1, + RST => rstx1, + CE => '0', + INC => '0', + LOAD => dlyLoad, + EN_VTC => '0', + CASC_IN => '0', + CASC_RETURN => '0', + CNTVALUEIN => dlyCfg); + + U_ISERDES : ISERDESE3 + generic map ( + DATA_WIDTH => 8, + FIFO_ENABLE => "FALSE", + FIFO_SYNC_MODE => "FALSE", + SIM_DEVICE => "ULTRASCALE") + port map ( + D => rxDly, + Q => dataOut, + CLK => clkx4, + CLK_B => clkx4L, + CLKDIV => clkx1, + RST => rstx1, + FIFO_RD_CLK => '0', + FIFO_RD_EN => '0', + FIFO_EMPTY => open); + + clkx4L <= not(clkx4); + +end mapping; From a752c87081e69b9d551aa9ab92bd3d709a2af06b Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 8 Jun 2020 11:01:33 -0700 Subject: [PATCH 15/40] code polishing --- protocols/ssp/rtl/SspDecoder10b12b.vhd | 53 +++++++++------- protocols/ssp/rtl/SspDecoder12b14b.vhd | 53 +++++++++------- protocols/ssp/rtl/SspDecoder8b10b.vhd | 87 +++++++++++++++----------- 3 files changed, 111 insertions(+), 82 deletions(-) diff --git a/protocols/ssp/rtl/SspDecoder10b12b.vhd b/protocols/ssp/rtl/SspDecoder10b12b.vhd index 19fa7664b1..5b2e83530b 100644 --- a/protocols/ssp/rtl/SspDecoder10b12b.vhd +++ b/protocols/ssp/rtl/SspDecoder10b12b.vhd @@ -19,38 +19,40 @@ use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; use IEEE.STD_LOGIC_ARITH.all; - library surf; use surf.StdRtlPkg.all; use surf.Code10b12bPkg.all; entity SspDecoder10b12b is - generic ( TPD_G : time := 1 ns; RST_POLARITY_G : sl := '0'; RST_ASYNC_G : boolean := true); - port ( + -- Clock and Reset clk : in sl; rst : in sl := RST_POLARITY_G; - dataIn : in slv(11 downto 0); + -- Encoded Input validIn : in sl := '1'; - dataOut : out slv(9 downto 0); + dataIn : in slv(11 downto 0); + -- Framing Output validOut : out sl; - outOfSync : out sl; + dataOut : out slv(9 downto 0); + errorOut : out sl; sof : out sl; eof : out sl; eofe : out sl; + -- Decoder Monitoring + validDec : out sl; codeError : out sl; dispError : out sl); - end entity SspDecoder10b12b; architecture rtl of SspDecoder10b12b is - signal validDec : sl; + signal validDecInt : sl; signal codeErrorInt : sl; + signal dispErrorInt : sl; signal framedData : slv(9 downto 0); signal framedDataK : slv(0 downto 0); @@ -69,11 +71,13 @@ begin dataIn => dataIn, dataOut => framedData, dataKOut => framedDataK(0), - validOut => validDec, + validOut => validDecInt, codeError => codeErrorInt, - dispError => dispError); + dispError => dispErrorInt); + validDec <= validDecInt; codeError <= codeErrorInt; + dispError <= dispErrorInt; SspDeframer_1 : entity surf.SspDeframer generic map ( @@ -89,18 +93,21 @@ begin SSP_EOF_CODE_G => K_28_21_C, SSP_EOF_K_G => "1") port map ( - clk => clk, - rst => rst, - validIn => validDec, - dataIn => framedData, - dataKIn => framedDataK, - dataOut => dataOut, - validOut => validOut, - outOfSync=> outOfSync, - sof => sof, - eof => eof, - eofe => eofe); - - + -- Clock and Reset + clk => clk, + rst => rst, + -- Input Interface + validIn => validDecInt, + dataIn => framedData, + dataKIn => framedDataK, + decErrIn => codeErrorInt, + dispErrIn => dispErrorInt, + -- Output Interface + dataOut => dataOut, + validOut => validOut, + errorOut => errorOut, + sof => sof, + eof => eof, + eofe => eofe); end architecture rtl; diff --git a/protocols/ssp/rtl/SspDecoder12b14b.vhd b/protocols/ssp/rtl/SspDecoder12b14b.vhd index ce469a7ec6..5b8ae3ca8f 100644 --- a/protocols/ssp/rtl/SspDecoder12b14b.vhd +++ b/protocols/ssp/rtl/SspDecoder12b14b.vhd @@ -19,38 +19,40 @@ use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; use IEEE.STD_LOGIC_ARITH.all; - library surf; use surf.StdRtlPkg.all; use surf.Code12b14bPkg.all; entity SspDecoder12b14b is - generic ( TPD_G : time := 1 ns; RST_POLARITY_G : sl := '0'; RST_ASYNC_G : boolean := true); port ( + -- Clock and Reset clk : in sl; rst : in sl := RST_POLARITY_G; + -- Encoded Input validIn : in sl := '1'; dataIn : in slv(13 downto 0); + -- Framing Output validOut : out sl; dataOut : out slv(11 downto 0); - valid : out sl; - outOfSync : out sl; + errorOut : out sl; sof : out sl; eof : out sl; eofe : out sl; + -- Decoder Monitoring + validDec : out sl; codeError : out sl; dispError : out sl); - end entity SspDecoder12b14b; architecture rtl of SspDecoder12b14b is - signal validInt : sl; + signal validDecInt : sl; signal codeErrorInt : sl; + signal dispErrorInt : sl; signal framedData : slv(11 downto 0); signal framedDataK : slv(0 downto 0); @@ -67,11 +69,15 @@ begin rst => rst, validIn => validIn, dataIn => dataIn, - validOut => validInt, + validOut => validDecInt, dataOut => framedData, dataKOut => framedDataK(0), - codeError => codeError, - dispError => dispError); + codeError => codeErrorInt, + dispError => dispErrorInt); + + validDec <= validDecInt; + codeError <= codeErrorInt; + dispError <= dispErrorInt; SspDeframer_1 : entity surf.SspDeframer generic map ( @@ -87,18 +93,21 @@ begin SSP_EOF_CODE_G => K_120_1_C, SSP_EOF_K_G => "1") port map ( - clk => clk, - rst => rst, - validIn => validInt, - dataIn => framedData, - dataKIn => framedDataK, - validOut => validOut, - dataOut => dataOut, - outOfSync=> outOfSync, - sof => sof, - eof => eof, - eofe => eofe); - - + -- Clock and Reset + clk => clk, + rst => rst, + -- Input Interface + validIn => validDecInt, + dataIn => framedData, + dataKIn => framedDataK, + decErrIn => codeErrorInt, + dispErrIn => dispErrorInt, + -- Output Interface + validOut => validOut, + dataOut => dataOut, + errorOut => errorOut, + sof => sof, + eof => eof, + eofe => eofe); end architecture rtl; diff --git a/protocols/ssp/rtl/SspDecoder8b10b.vhd b/protocols/ssp/rtl/SspDecoder8b10b.vhd index ba1a117ba2..a9f69d94f3 100644 --- a/protocols/ssp/rtl/SspDecoder8b10b.vhd +++ b/protocols/ssp/rtl/SspDecoder8b10b.vhd @@ -19,39 +19,45 @@ use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; use IEEE.STD_LOGIC_ARITH.all; - library surf; use surf.StdRtlPkg.all; use surf.Code8b10bPkg.all; entity SspDecoder8b10b is - generic ( TPD_G : time := 1 ns; RST_POLARITY_G : sl := '0'; RST_ASYNC_G : boolean := true); - port ( - clk : in sl; - rst : in sl := RST_POLARITY_G; - dataIn : in slv(19 downto 0); - validIn : in sl := '1'; - dataOut : out slv(15 downto 0); - validOut : out sl; - outOfSync: out sl; - sof : out sl; - eof : out sl; - eofe : out sl); - + -- Clock and Reset + clk : in sl; + rst : in sl := RST_POLARITY_G; + -- Encoded Input + validIn : in sl := '1'; + dataIn : in slv(19 downto 0); + -- Framing Output + validOut : out sl; + dataOut : out slv(15 downto 0); + errorOut : out sl; + sof : out sl; + eof : out sl; + eofe : out sl; + -- Decoder Monitoring + validDec : out sl; + codeError : out sl; + dispError : out sl); end entity SspDecoder8b10b; architecture rtl of SspDecoder8b10b is - signal validDec : sl; - signal codeErr : slv(1 downto 0); - signal decErr : sl; - signal framedData : slv(15 downto 0); - signal framedDataK : slv(1 downto 0); + signal codeErrorVec : slv(1 downto 0); + signal dispErrorVec : slv(1 downto 0); + + signal validDecInt : sl; + signal codeErrorInt : sl; + signal dispErrorInt : sl; + signal framedData : slv(15 downto 0); + signal framedDataK : slv(1 downto 0); begin @@ -68,11 +74,16 @@ begin dataIn => dataIn, dataOut => framedData, dataKOut => framedDataK, - validOut => validDec, - codeErr => codeErr, - dispErr => open); + validOut => validDecInt, + codeErr => codeErrorVec, + dispErr => dispErrorVec); - decErr <= uor(codeErr); + validDec <= validDecInt; + codeError <= codeErrorInt; + dispError <= dispErrorInt; + + codeErrorInt <= uor(codeErrorVec); + dispErrorInt <= uor(dispErrorVec); SspDeframer_1 : entity surf.SspDeframer generic map ( @@ -88,19 +99,21 @@ begin SSP_EOF_CODE_G => D_10_2_C & K_29_7_C, SSP_EOF_K_G => "01") port map ( - clk => clk, - rst => rst, - dataIn => framedData, - dataKIn => framedDataK, - validIn => validDec, - decErrIn => decErr, - dataOut => dataOut, - validOut => validOut, - outOfSync=> outOfSync, - sof => sof, - eof => eof, - eofe => eofe); - - + -- Clock and Reset + clk => clk, + rst => rst, + -- Input Interface + validIn => validDecInt, + dataIn => framedData, + dataKIn => framedDataK, + decErrIn => codeErrorInt, + dispErrIn => dispErrorInt, + -- Output Interface + dataOut => dataOut, + validOut => validOut, + errorOut => errorOut, + sof => sof, + eof => eof, + eofe => eofe); end architecture rtl; From 38b0150466f2319c295ba19806779d1f092b6adc Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 8 Jun 2020 11:02:11 -0700 Subject: [PATCH 16/40] changing outOfSync to errorOut --- protocols/ssp/rtl/SspDeframer.vhd | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/protocols/ssp/rtl/SspDeframer.vhd b/protocols/ssp/rtl/SspDeframer.vhd index a33b8767db..f7723dfdc1 100644 --- a/protocols/ssp/rtl/SspDeframer.vhd +++ b/protocols/ssp/rtl/SspDeframer.vhd @@ -45,10 +45,11 @@ entity SspDeframer is dataIn : in slv(WORD_SIZE_G-1 downto 0); validIn : in sl; decErrIn : in sl := '0'; + dispErrIn: in sl := '0'; -- Unused -- Output Interface dataOut : out slv(WORD_SIZE_G-1 downto 0); validOut : out sl; - outOfSync: out sl; + errorOut : out sl; sof : out sl; eof : out sl; eofe : out sl); @@ -72,7 +73,7 @@ architecture rtl of SspDeframer is -- Output registers dataOut : slv(WORD_SIZE_G-1 downto 0); validOut : sl; - outOfSync: sl; + errorOut : sl; sof : sl; eof : sl; eofe : sl; @@ -88,7 +89,7 @@ architecture rtl of SspDeframer is iEofe => '0', dataOut => (others => '0'), validOut => '0', - outOfSync => '0', + errorOut => '0', sof => '0', eof => '0', eofe => '0'); @@ -103,7 +104,7 @@ begin begin v := r; - v.outOfSync := '0'; + v.errorOut := '0'; if (validIn = '1') then @@ -133,10 +134,10 @@ begin v.iEof := '1'; v.iEofe := '1'; v.iValidOut := '1'; - v.outOfSync := '1'; + v.errorOut := '1'; end if; else - v.outOfSync := '1'; + v.errorOut := '1'; end if; elsif (r.state = WAIT_EOF_S) then @@ -169,15 +170,15 @@ begin v.iValidOut := '0'; v.iEof := '1'; v.iEofe := '1'; - v.outOfSync := '1'; + v.errorOut := '1'; v.state := WAIT_SOF_S; end if; end if; if (decErrIn = '1') then - v.iEofe := '1'; - v.outOfSync := '1'; + v.iEofe := '1'; + v.errorOut := '1'; end if; end if; @@ -205,7 +206,7 @@ begin rin <= v; dataOut <= r.dataOut; validOut <= r.validOut; - outOfSync<= r.outOfSync; + errorOut <= r.errorOut; sof <= r.sof; eof <= r.eof; eofe <= r.eofe; From 5007a7ac16585b266615d2e937bc166c741d856e Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 8 Jun 2020 11:02:25 -0700 Subject: [PATCH 17/40] adding SspDecoderLane --- protocols/ssp/rtl/SspDecoderLane.vhd | 229 ++++++++++++++++++ .../general/rtl/SelectIoRxGearboxAligner.vhd | 110 +++++++-- 2 files changed, 319 insertions(+), 20 deletions(-) create mode 100644 protocols/ssp/rtl/SspDecoderLane.vhd diff --git a/protocols/ssp/rtl/SspDecoderLane.vhd b/protocols/ssp/rtl/SspDecoderLane.vhd new file mode 100644 index 0000000000..d886946c28 --- /dev/null +++ b/protocols/ssp/rtl/SspDecoderLane.vhd @@ -0,0 +1,229 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: PLL and Deserialization +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.Code10b12bPkg.all; + +entity SspDecoderLane is + generic ( + TPD_G : time := 1 ns; + DATA_WIDTH_G : positive := 10; + SIMULATION_G : boolean := false); + port ( + -- Clock and Reset Interface + clk : in sl; + rst : in sl; + -- Deserialization Interface + deserData : in slv(7 downto 0); + dlyLoad : out sl; + dlyCfg : out slv(8 downto 0); + -- Config/Status Interface + enUsrDlyCfg : in sl; + usrDlyCfg : in slv(8 downto 0); + minEyeWidth : in slv(7 downto 0); + lockingCntCfg : in slv(23 downto 0); + bypFirstBerDet : in sl; + polarity : in sl; + errorDet : out sl; + bitSlip : out sl; + locked : out sl; + -- SSP Frame Output + rxLinkUp : out sl; + rxValid : out sl; + rxData : out slv(DATA_WIDTH_G-1 downto 0); + rxSof : out sl; + rxEof : out sl; + rxEofe : out sl); +end SspDecoderLane; + +architecture mapping of SspDecoderLane is + + constant ENCODE_WIDTH_C : positive := ite(DATA_WIDTH_G = 16, 20, DATA_WIDTH_G+2); + + signal deserDataMask : slv(7 downto 0); + + signal reset : sl; + signal gearboxAligned : sl; + signal slip : sl; + signal validOut : sl; + + signal encodeValid : sl; + signal encodeData : slv(ENCODE_WIDTH_C-1 downto 0); + + signal decodeValid : sl; + signal decodeOutOfSync : sl; + signal decodeCodeErr : sl; + signal decodeDispErr : sl; + +begin + + assert ((DATA_WIDTH_G = 10) or (DATA_WIDTH_G = 12) or (DATA_WIDTH_G = 16)) + report "DATA_WIDTH_C must be either [10,12,16]" + severity failure; + + process(clk) + begin + if rising_edge(clk) then + bitSlip <= slip; + rxLinkUp <= gearboxAligned after TPD_G; + locked <= gearboxAligned after TPD_G; + end if; + end process; + + U_reset : entity surf.RstPipeline + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rstIn => rst, + rstOut => reset); + + deserDataMask <= deserData when(polarity = '0') else not(deserData); + + U_Gearbox : entity surf.Gearbox + generic map ( + TPD_G => TPD_G, + SLAVE_WIDTH_G => 8, + MASTER_WIDTH_G => ENCODE_WIDTH_C) + port map ( + clk => clk, + rst => reset, + slip => slip, + -- Slave Interface + slaveValid => '1', + slaveData => deserDataMask, + -- Master Interface + masterValid => encodeValid, + masterData => encodeData, + masterReady => '1'); + + U_GearboxAligner : entity surf.SelectIoRxGearboxAligner + generic map ( + TPD_G => TPD_G, + CODE_TYPE_G => "LINE_CODE", + SIMULATION_G => SIMULATION_G) + port map ( + -- Clock and Reset + clk => clk, + rst => reset, + -- Line-Code Interface (CODE_TYPE_G = "LINE_CODE") + lineCodeValid => decodeValid, + lineCodeErr => decodeCodeErr, + lineCodeDispErr => decodeDispErr, + linkOutOfSync => decodeOutOfSync, + -- 64b/66b Interface (CODE_TYPE_G = "SCRAMBLER") + rxHeaderValid => '0', + rxHeader => (others => '0'), + -- Link Status and Gearbox Slip + bitSlip => slip, + -- IDELAY (DELAY_TYPE="VAR_LOAD") Interface + dlyLoad => dlyLoad, + dlyCfg => dlyCfg, + -- Configuration Interface + enUsrDlyCfg => enUsrDlyCfg, + usrDlyCfg => usrDlyCfg, + bypFirstBerDet => bypFirstBerDet, + minEyeWidth => minEyeWidth, + lockingCntCfg => lockingCntCfg, + -- Status Interface + errorDet => errorDet, + locked => gearboxAligned); + + GEN_10B12B : if (DATA_WIDTH_G = 10) generate + U_Decoder : entity surf.SspDecoder10b12b + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false) + port map ( + -- Clock and Reset + clk => clk, + rst => reset, + -- Encoded Input + validIn => encodeValid, + dataIn => encodeData, + -- Framing Output + validOut => validOut, + dataOut => rxData, + errorOut => decodeOutOfSync, + sof => rxSof, + eof => rxEof, + eofe => rxEofe, + -- Decoder Monitoring + validDec => decodeValid, + codeError => decodeCodeErr, + dispError => decodeDispErr); + end generate; + + GEN_12B14B : if (DATA_WIDTH_G = 12) generate + U_Decoder : entity surf.SspDecoder12b14b + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false) + port map ( + -- Clock and Reset + clk => clk, + rst => reset, + -- Encoded Input + validIn => encodeValid, + dataIn => encodeData, + -- Framing Output + validOut => validOut, + dataOut => rxData, + errorOut => decodeOutOfSync, + sof => rxSof, + eof => rxEof, + eofe => rxEofe, + -- Decoder Monitoring + validDec => decodeValid, + codeError => decodeCodeErr, + dispError => decodeDispErr); + end generate; + + GEN_16B20B : if (DATA_WIDTH_G = 16) generate + U_Decoder : entity surf.SspDecoder8b10b + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false) + port map ( + -- Clock and Reset + clk => clk, + rst => reset, + -- Encoded Input + validIn => encodeValid, + dataIn => encodeData, + -- Framing Output + validOut => validOut, + dataOut => rxData, + errorOut => decodeOutOfSync, + sof => rxSof, + eof => rxEof, + eofe => rxEofe, + -- Decoder Monitoring + validDec => decodeValid, + codeError => decodeCodeErr, + dispError => decodeDispErr); + end generate; + + rxValid <= validOut and gearboxAligned; + +end mapping; diff --git a/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd b/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd index 55cf96c1ea..261134c891 100644 --- a/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd +++ b/xilinx/general/rtl/SelectIoRxGearboxAligner.vhd @@ -22,23 +22,22 @@ use surf.StdRtlPkg.all; entity SelectIoRxGearboxAligner is generic ( - TPD_G : time := 1 ns; - NUM_BYTES_G : positive := 1; - CODE_TYPE_G : string := "LINE_CODE"; -- or "SCRAMBLER" - SIMULATION_G : boolean := false); + TPD_G : time := 1 ns; + CODE_TYPE_G : string := "LINE_CODE"; -- or "SCRAMBLER" + SIMULATION_G : boolean := false); port ( -- Clock and Reset clk : in sl; rst : in sl; -- Line-Code Interface (CODE_TYPE_G = "LINE_CODE") lineCodeValid : in sl; - lineCodeErr : in slv(NUM_BYTES_G-1 downto 0); - lineCodeDispErr : in slv(NUM_BYTES_G-1 downto 0); + lineCodeErr : in sl; + lineCodeDispErr : in sl; + linkOutOfSync : in sl; -- 64b/66b Interface (CODE_TYPE_G = "SCRAMBLER") rxHeaderValid : in sl; rxHeader : in slv(1 downto 0); - -- Link Status and Gearbox Slip - linkError : in sl; + -- Gearbox Slip bitSlip : out sl; -- IDELAY (DELAY_TYPE="VAR_LOAD") Interface dlyLoad : out sl; @@ -63,6 +62,8 @@ architecture rtl of SelectIoRxGearboxAligner is SLIP_WAIT_S, LOCKING_S, EYE_SCAN_S, + BIT_WAIT_S, + BIT_ALIGN_S, LOCKED_S); type RegType is record @@ -73,7 +74,7 @@ architecture rtl of SelectIoRxGearboxAligner is dlyCache : slv(8 downto 0); slipWaitCnt : natural range 0 to SLIP_WAIT_C-1; goodCnt : slv(23 downto 0); - slip : sl; + bitSlip : sl; errorDet : sl; firstError : sl; armed : sl; @@ -90,7 +91,7 @@ architecture rtl of SelectIoRxGearboxAligner is dlyCache => (others => '0'), slipWaitCnt => 0, goodCnt => (others => '0'), - slip => '0', + bitSlip => '0', errorDet => '0', firstError => '0', armed => '0', @@ -108,7 +109,7 @@ begin severity failure; comb : process (bypFirstBerDet, enUsrDlyCfg, lineCodeDispErr, lineCodeErr, - lineCodeValid, linkError, lockingCntCfg, minEyeWidth, r, + lineCodeValid, linkOutOfSync, lockingCntCfg, minEyeWidth, r, rst, rxHeader, rxHeaderValid, usrDlyCfg) is variable v : RegType; @@ -125,7 +126,7 @@ begin v.dlyConfig := (others => '0'); -- Slip by 1-bit in the gearbox - v.slip := '1'; + v.bitSlip := '1'; -- Reset the flag v.firstError := '0'; @@ -168,7 +169,7 @@ begin eyescanCfg := '0' & minEyeWidth; -- Reset strobes - v.slip := '0'; + v.bitSlip := '0'; v.errorDet := '0'; -- Shift register @@ -186,7 +187,12 @@ begin elsif (CODE_TYPE_G = "LINE_CODE") then valid := lineCodeValid; -- Check for bad header - if (lineCodeValid = '1') and (uOr(lineCodeErr) = '1' or uOr(lineCodeDispErr) = '1') then + if (lineCodeValid = '1') and ((lineCodeErr = '1') or (lineCodeDispErr = '1')) then + v.errorDet := '1'; + end if; + -- Check for out-of-sync after locked + if (r.locked = '1') and (linkOutOfSync = '1') then + valid := '1'; v.errorDet := '1'; end if; end if; @@ -216,8 +222,19 @@ begin -- Check if eye scan completed if (r.scanDone = '1') or (r.enUsrDlyCfg = '1') then - -- Next state - v.state := LOCKED_S; + + -- 64b/66b Interface + if (CODE_TYPE_G = "SCRAMBLER") then + -- Next state + v.state := LOCKED_S; + + -- Line-Code Interface + elsif (CODE_TYPE_G = "LINE_CODE") then + -- Next state + v.state := BIT_ALIGN_S; + + end if; + -- Check for armed mode elsif (r.armed = '1') then -- Next state @@ -313,12 +330,65 @@ begin end if; end if; ---------------------------------------------------------------------- + when BIT_WAIT_S => + -- Check the counter + if (r.slipWaitCnt = SLIP_WAIT_C-1) then + + -- Reset the counter + v.slipWaitCnt := 0; + + -- Next state + v.state := BIT_ALIGN_S; + + else + -- Increment the counter + v.slipWaitCnt := r.slipWaitCnt + 1; + end if; + ---------------------------------------------------------------------- + when BIT_ALIGN_S => + -- Check for code error + if (valid = '1') and (v.errorDet = '1') then + + -- Reset the counter + v.slipWaitCnt := 0; + + -- Execute the slip procedure + slipProcedure; + + -- Check for out-of-sync flag + elsif (linkOutOfSync = '1') then + + -- Slip by 1-bit in the gearbox + v.bitSlip := '1'; + + -- Reset the counter + v.slipWaitCnt := 0; + + -- Next state + v.state := BIT_WAIT_S; + + -- Check the counter + elsif (r.slipWaitCnt = SLIP_WAIT_C-1) then + + -- Reset the counter + v.slipWaitCnt := 0; + + -- Next state + v.state := LOCKED_S; + + else + + -- Increment the counter + v.slipWaitCnt := r.slipWaitCnt + 1; + + end if; + ---------------------------------------------------------------------- when LOCKED_S => -- Check for data - if (valid = '1') or (linkError = '1') then + if (valid = '1') then -- Check for bad header - if (v.errorDet = '1') or (linkError = '1') then + if (v.errorDet = '1') then -- Execute the slip procedure slipProcedure; @@ -343,12 +413,12 @@ begin -- Outputs locked <= r.locked; - bitSlip <= r.slip; + bitSlip <= r.bitSlip; dlyLoad <= r.dlyLoad(0); errorDet <= r.errorDet; -- Check if using user delay configuration - if (enUsrDlyCfg = '1') then + if (r.enUsrDlyCfg = '1') then -- Force to user configuration dlyCfg <= usrDlyCfg; else From 42bc563ced5be5f8d70ff3485e84d63024e9d6b8 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 8 Jun 2020 12:12:20 -0700 Subject: [PATCH 18/40] bug fix --- xilinx/7Series/general/rtl/SelectioDeser.vhd | 24 +++++++++----------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/xilinx/7Series/general/rtl/SelectioDeser.vhd b/xilinx/7Series/general/rtl/SelectioDeser.vhd index aa078af033..0a4d001d24 100644 --- a/xilinx/7Series/general/rtl/SelectioDeser.vhd +++ b/xilinx/7Series/general/rtl/SelectioDeser.vhd @@ -33,7 +33,6 @@ entity SelectioDeser is REF_FREQ_G : real := 300.0; -- IDELAYCTRL's REFCLK (in units of Hz) INPUT_BUFG_G : boolean := false; FB_BUFG_G : boolean := false; - BANDWIDTH_G : string := "OPTIMIZED"; CLKIN_PERIOD_G : real := 10.0; -- 100 MHz DIVCLK_DIVIDE_G : positive := 1; CLKFBOUT_MULT_G : positive := 10; -- 1 GHz = 100 MHz x 10 / 1 @@ -77,18 +76,17 @@ begin U_MMCM : entity surf.ClockManager7 generic map( - TPD_G => TPD_G, - SIMULATION_G => SIMULATION_G, - TYPE_G => "MMCM", - BANDWIDTH_G => BANDWIDTH_G, - INPUT_BUFG_G => INPUT_BUFG_G, - FB_BUFG_G => FB_BUFG_G, - NUM_CLOCKS_G => 2, - CLKIN_PERIOD_G => CLKIN_PERIOD_G, - DIVCLK_DIVIDE_G => DIVCLK_DIVIDE_G, - CLKFBOUT_MULT_F_G => CLKFBOUT_MULT_F_G, - CLKOUT0_DIVIDE_F_G => CLKOUT0_DIVIDE_G, - CLKOUT1_DIVIDE_G => 4*integer(CLKOUT0_DIVIDE_G)) + TPD_G => TPD_G, + SIMULATION_G => SIMULATION_G, + TYPE_G => "PLL", + INPUT_BUFG_G => INPUT_BUFG_G, + FB_BUFG_G => FB_BUFG_G, + NUM_CLOCKS_G => 2, + CLKIN_PERIOD_G => CLKIN_PERIOD_G, + DIVCLK_DIVIDE_G => DIVCLK_DIVIDE_G, + CLKFBOUT_MULT_G => CLKFBOUT_MULT_G, + CLKOUT0_DIVIDE_G => CLKOUT0_DIVIDE_G, + CLKOUT1_DIVIDE_G => 4*CLKOUT0_DIVIDE_G) port map( clkIn => refClk, rstIn => refRst, From 002954d1772109d7953fa274450f0d4a90aa0335 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 8 Jun 2020 12:20:19 -0700 Subject: [PATCH 19/40] adding more SSP decoder wrappers --- protocols/ssp/rtl/SspDecoder10b12bWrapper.vhd | 136 +++++++++++ protocols/ssp/rtl/SspDecoder12b14bWrapper.vhd | 136 +++++++++++ protocols/ssp/rtl/SspDecoder8b10bWrapper.vhd | 136 +++++++++++ protocols/ssp/rtl/SspDecoderReg.vhd | 231 ++++++++++++++++++ 4 files changed, 639 insertions(+) create mode 100644 protocols/ssp/rtl/SspDecoder10b12bWrapper.vhd create mode 100644 protocols/ssp/rtl/SspDecoder12b14bWrapper.vhd create mode 100644 protocols/ssp/rtl/SspDecoder8b10bWrapper.vhd create mode 100644 protocols/ssp/rtl/SspDecoderReg.vhd diff --git a/protocols/ssp/rtl/SspDecoder10b12bWrapper.vhd b/protocols/ssp/rtl/SspDecoder10b12bWrapper.vhd new file mode 100644 index 0000000000..0dab87bda0 --- /dev/null +++ b/protocols/ssp/rtl/SspDecoder10b12bWrapper.vhd @@ -0,0 +1,136 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: SSP Decoder Wrapper +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +entity SspDecoder10b12bWrapper is + generic ( + TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; + NUM_LANE_G : positive := 1); + port ( + -- Deserialization Interface (deserClk domain) + deserClk : in sl; + deserRst : in sl; + deserData : in Slv8Array(NUM_LANE_G-1 downto 0); + dlyLoad : out slv(NUM_LANE_G-1 downto 0); + dlyCfg : out Slv9Array(NUM_LANE_G-1 downto 0); + -- SSP Frame Output + rxLinkUp : out slv(NUM_LANE_G-1 downto 0); + rxValid : out slv(NUM_LANE_G-1 downto 0); + rxData : out Slv10Array(NUM_LANE_G-1 downto 0); + rxSof : out slv(NUM_LANE_G-1 downto 0); + rxEof : out slv(NUM_LANE_G-1 downto 0); + rxEofe : out slv(NUM_LANE_G-1 downto 0); + -- AXI-Lite Interface (axilClk domain) + axilClk : in sl; + axilRst : in sl; + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType); +end SspDecoder10b12bWrapper; + +architecture mapping of SspDecoder10b12bWrapper is + + constant DATA_WIDTH_C : positive := 10; + + signal dlyConfig : Slv9Array(NUM_LANE_G-1 downto 0); + + signal enUsrDlyCfg : sl; + signal usrDlyCfg : slv(8 downto 0); + signal minEyeWidth : slv(7 downto 0); + signal lockingCntCfg : slv(23 downto 0); + signal bypFirstBerDet : sl; + signal polarity : slv(NUM_LANE_G-1 downto 0); + signal errorDet : slv(NUM_LANE_G-1 downto 0); + signal bitSlip : slv(NUM_LANE_G-1 downto 0); + signal locked : slv(NUM_LANE_G-1 downto 0); + +begin + + dlyCfg <= dlyConfig; + + GEN_VEC : + for i in NUM_LANE_G-1 downto 0 generate + + U_Lane : entity surf.SspDecoderLane + generic map ( + TPD_G => TPD_G, + DATA_WIDTH_G => DATA_WIDTH_C, + SIMULATION_G => SIMULATION_G) + port map ( + -- Clock and Reset Interface + clk => deserClk, + rst => deserRst, + -- Deserialization Interface + deserData => deserData(i), + dlyLoad => dlyLoad(i), + dlyCfg => dlyConfig(i), + -- Config/Status Interface + enUsrDlyCfg => enUsrDlyCfg, + usrDlyCfg => usrDlyCfg, + minEyeWidth => minEyeWidth, + lockingCntCfg => lockingCntCfg, + bypFirstBerDet => bypFirstBerDet, + polarity => polarity(i), + errorDet => errorDet(i), + bitSlip => bitSlip(i), + locked => locked(i), + -- SSP Frame Output + rxLinkUp => rxLinkUp(i), + rxValid => rxValid(i), + rxData => rxData(i), + rxSof => rxSof(i), + rxEof => rxEof(i), + rxEofe => rxEofe(i)); + + end generate GEN_VEC; + + U_Reg : entity surf.SspDecoderReg + generic map ( + TPD_G => TPD_G, + SIMULATION_G => SIMULATION_G, + DATA_WIDTH_G => DATA_WIDTH_C, + NUM_LANE_G => NUM_LANE_G) + port map ( + -- Deserialization Interface (deserClk domain) + deserClk => deserClk, + deserRst => deserRst, + dlyConfig => dlyConfig, + errorDet => errorDet, + bitSlip => bitSlip, + locked => locked, + enUsrDlyCfg => enUsrDlyCfg, + usrDlyCfg => usrDlyCfg, + minEyeWidth => minEyeWidth, + lockingCntCfg => lockingCntCfg, + bypFirstBerDet => bypFirstBerDet, + polarity => polarity, + -- AXI-Lite Interface (axilClk domain) + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + +end mapping; diff --git a/protocols/ssp/rtl/SspDecoder12b14bWrapper.vhd b/protocols/ssp/rtl/SspDecoder12b14bWrapper.vhd new file mode 100644 index 0000000000..1f067e0ea7 --- /dev/null +++ b/protocols/ssp/rtl/SspDecoder12b14bWrapper.vhd @@ -0,0 +1,136 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: SSP Decoder Wrapper +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +entity SspDecoder12b14bWrapper is + generic ( + TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; + NUM_LANE_G : positive := 1); + port ( + -- Deserialization Interface (deserClk domain) + deserClk : in sl; + deserRst : in sl; + deserData : in Slv8Array(NUM_LANE_G-1 downto 0); + dlyLoad : out slv(NUM_LANE_G-1 downto 0); + dlyCfg : out Slv9Array(NUM_LANE_G-1 downto 0); + -- SSP Frame Output + rxLinkUp : out slv(NUM_LANE_G-1 downto 0); + rxValid : out slv(NUM_LANE_G-1 downto 0); + rxData : out Slv12Array(NUM_LANE_G-1 downto 0); + rxSof : out slv(NUM_LANE_G-1 downto 0); + rxEof : out slv(NUM_LANE_G-1 downto 0); + rxEofe : out slv(NUM_LANE_G-1 downto 0); + -- AXI-Lite Interface (axilClk domain) + axilClk : in sl; + axilRst : in sl; + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType); +end SspDecoder12b14bWrapper; + +architecture mapping of SspDecoder12b14bWrapper is + + constant DATA_WIDTH_C : positive := 12; + + signal dlyConfig : Slv9Array(NUM_LANE_G-1 downto 0); + + signal enUsrDlyCfg : sl; + signal usrDlyCfg : slv(8 downto 0); + signal minEyeWidth : slv(7 downto 0); + signal lockingCntCfg : slv(23 downto 0); + signal bypFirstBerDet : sl; + signal polarity : slv(NUM_LANE_G-1 downto 0); + signal errorDet : slv(NUM_LANE_G-1 downto 0); + signal bitSlip : slv(NUM_LANE_G-1 downto 0); + signal locked : slv(NUM_LANE_G-1 downto 0); + +begin + + dlyCfg <= dlyConfig; + + GEN_VEC : + for i in NUM_LANE_G-1 downto 0 generate + + U_Lane : entity surf.SspDecoderLane + generic map ( + TPD_G => TPD_G, + DATA_WIDTH_G => DATA_WIDTH_C, + SIMULATION_G => SIMULATION_G) + port map ( + -- Clock and Reset Interface + clk => deserClk, + rst => deserRst, + -- Deserialization Interface + deserData => deserData(i), + dlyLoad => dlyLoad(i), + dlyCfg => dlyConfig(i), + -- Config/Status Interface + enUsrDlyCfg => enUsrDlyCfg, + usrDlyCfg => usrDlyCfg, + minEyeWidth => minEyeWidth, + lockingCntCfg => lockingCntCfg, + bypFirstBerDet => bypFirstBerDet, + polarity => polarity(i), + errorDet => errorDet(i), + bitSlip => bitSlip(i), + locked => locked(i), + -- SSP Frame Output + rxLinkUp => rxLinkUp(i), + rxValid => rxValid(i), + rxData => rxData(i), + rxSof => rxSof(i), + rxEof => rxEof(i), + rxEofe => rxEofe(i)); + + end generate GEN_VEC; + + U_Reg : entity surf.SspDecoderReg + generic map ( + TPD_G => TPD_G, + SIMULATION_G => SIMULATION_G, + DATA_WIDTH_G => DATA_WIDTH_C, + NUM_LANE_G => NUM_LANE_G) + port map ( + -- Deserialization Interface (deserClk domain) + deserClk => deserClk, + deserRst => deserRst, + dlyConfig => dlyConfig, + errorDet => errorDet, + bitSlip => bitSlip, + locked => locked, + enUsrDlyCfg => enUsrDlyCfg, + usrDlyCfg => usrDlyCfg, + minEyeWidth => minEyeWidth, + lockingCntCfg => lockingCntCfg, + bypFirstBerDet => bypFirstBerDet, + polarity => polarity, + -- AXI-Lite Interface (axilClk domain) + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + +end mapping; diff --git a/protocols/ssp/rtl/SspDecoder8b10bWrapper.vhd b/protocols/ssp/rtl/SspDecoder8b10bWrapper.vhd new file mode 100644 index 0000000000..f74524c3f3 --- /dev/null +++ b/protocols/ssp/rtl/SspDecoder8b10bWrapper.vhd @@ -0,0 +1,136 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: SSP Decoder Wrapper +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +entity SspDecoder8b10bWrapper is + generic ( + TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; + NUM_LANE_G : positive := 1); + port ( + -- Deserialization Interface (deserClk domain) + deserClk : in sl; + deserRst : in sl; + deserData : in Slv8Array(NUM_LANE_G-1 downto 0); + dlyLoad : out slv(NUM_LANE_G-1 downto 0); + dlyCfg : out Slv9Array(NUM_LANE_G-1 downto 0); + -- SSP Frame Output + rxLinkUp : out slv(NUM_LANE_G-1 downto 0); + rxValid : out slv(NUM_LANE_G-1 downto 0); + rxData : out Slv16Array(NUM_LANE_G-1 downto 0); + rxSof : out slv(NUM_LANE_G-1 downto 0); + rxEof : out slv(NUM_LANE_G-1 downto 0); + rxEofe : out slv(NUM_LANE_G-1 downto 0); + -- AXI-Lite Interface (axilClk domain) + axilClk : in sl; + axilRst : in sl; + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType); +end SspDecoder8b10bWrapper; + +architecture mapping of SspDecoder8b10bWrapper is + + constant DATA_WIDTH_C : positive := 16; + + signal dlyConfig : Slv9Array(NUM_LANE_G-1 downto 0); + + signal enUsrDlyCfg : sl; + signal usrDlyCfg : slv(8 downto 0); + signal minEyeWidth : slv(7 downto 0); + signal lockingCntCfg : slv(23 downto 0); + signal bypFirstBerDet : sl; + signal polarity : slv(NUM_LANE_G-1 downto 0); + signal errorDet : slv(NUM_LANE_G-1 downto 0); + signal bitSlip : slv(NUM_LANE_G-1 downto 0); + signal locked : slv(NUM_LANE_G-1 downto 0); + +begin + + dlyCfg <= dlyConfig; + + GEN_VEC : + for i in NUM_LANE_G-1 downto 0 generate + + U_Lane : entity surf.SspDecoderLane + generic map ( + TPD_G => TPD_G, + DATA_WIDTH_G => DATA_WIDTH_C, + SIMULATION_G => SIMULATION_G) + port map ( + -- Clock and Reset Interface + clk => deserClk, + rst => deserRst, + -- Deserialization Interface + deserData => deserData(i), + dlyLoad => dlyLoad(i), + dlyCfg => dlyConfig(i), + -- Config/Status Interface + enUsrDlyCfg => enUsrDlyCfg, + usrDlyCfg => usrDlyCfg, + minEyeWidth => minEyeWidth, + lockingCntCfg => lockingCntCfg, + bypFirstBerDet => bypFirstBerDet, + polarity => polarity(i), + errorDet => errorDet(i), + bitSlip => bitSlip(i), + locked => locked(i), + -- SSP Frame Output + rxLinkUp => rxLinkUp(i), + rxValid => rxValid(i), + rxData => rxData(i), + rxSof => rxSof(i), + rxEof => rxEof(i), + rxEofe => rxEofe(i)); + + end generate GEN_VEC; + + U_Reg : entity surf.SspDecoderReg + generic map ( + TPD_G => TPD_G, + SIMULATION_G => SIMULATION_G, + DATA_WIDTH_G => DATA_WIDTH_C, + NUM_LANE_G => NUM_LANE_G) + port map ( + -- Deserialization Interface (deserClk domain) + deserClk => deserClk, + deserRst => deserRst, + dlyConfig => dlyConfig, + errorDet => errorDet, + bitSlip => bitSlip, + locked => locked, + enUsrDlyCfg => enUsrDlyCfg, + usrDlyCfg => usrDlyCfg, + minEyeWidth => minEyeWidth, + lockingCntCfg => lockingCntCfg, + bypFirstBerDet => bypFirstBerDet, + polarity => polarity, + -- AXI-Lite Interface (axilClk domain) + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + +end mapping; diff --git a/protocols/ssp/rtl/SspDecoderReg.vhd b/protocols/ssp/rtl/SspDecoderReg.vhd new file mode 100644 index 0000000000..f54fd9fc88 --- /dev/null +++ b/protocols/ssp/rtl/SspDecoderReg.vhd @@ -0,0 +1,231 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: SSP Decoder Registers +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +entity SspDecoderReg is + generic ( + TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; + DATA_WIDTH_G : positive := 10; + NUM_LANE_G : positive := 1); + port ( + -- Deserialization Interface (deserClk domain) + deserClk : in sl; + deserRst : in sl; + dlyConfig : in Slv9Array(NUM_LANE_G-1 downto 0); + errorDet : in slv(NUM_LANE_G-1 downto 0); + bitSlip : in slv(NUM_LANE_G-1 downto 0); + locked : in slv(NUM_LANE_G-1 downto 0); + enUsrDlyCfg : out sl; + usrDlyCfg : out slv(8 downto 0); + minEyeWidth : out slv(7 downto 0); + lockingCntCfg : out slv(23 downto 0); + bypFirstBerDet : out sl; + polarity : out slv(NUM_LANE_G-1 downto 0); + -- AXI-Lite Interface (axilClk domain) + axilClk : in sl; + axilRst : in sl; + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType); +end SspDecoderReg; + +architecture mapping of SspDecoderReg is + + constant STATUS_SIZE_C : positive := 3*NUM_LANE_G; + constant STATUS_WIDTH_C : positive := 16; + + type RegType is record + enUsrDlyCfg : sl; + usrDlyCfg : slv(8 downto 0); + minEyeWidth : slv(7 downto 0); + lockingCntCfg : slv(23 downto 0); + bypFirstBerDet : sl; + polarity : slv(NUM_LANE_G-1 downto 0); + cntRst : sl; + rollOverEn : slv(STATUS_SIZE_C-1 downto 0); + axilReadSlave : AxiLiteReadSlaveType; + axilWriteSlave : AxiLiteWriteSlaveType; + end record; + + constant REG_INIT_C : RegType := ( + enUsrDlyCfg => ite(SIMULATION_G, '1', '0'), + usrDlyCfg => toSlv(219, 9), + minEyeWidth => toSlv(80, 8), + lockingCntCfg => ite(SIMULATION_G, x"00_0004", x"00_FFFF"), + bypFirstBerDet => '1', + polarity => (others => '0'), + cntRst => '1', + rollOverEn => (others => '0'), + axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, + axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal statusOut : slv(STATUS_SIZE_C-1 downto 0); + signal statusCnt : SlVectorArray(STATUS_SIZE_C-1 downto 0, STATUS_WIDTH_C-1 downto 0); + +begin + + comb : process (axilReadMaster, axilRst, axilWriteMaster, dlyConfig, r, + statusCnt, statusOut) is + variable v : RegType; + variable axilEp : AxiLiteEndPointType; + begin + -- Latch the current value + v := r; + + -- Reset the strobes + v.cntRst := '0'; + + -- Determine the transaction type + axiSlaveWaitTxn(axilEp, axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave); + + -- Map the read registers + for i in STATUS_SIZE_C-1 downto 0 loop + axiSlaveRegisterR(axilEp, toSlv((4*i), 12), 0, muxSlVectorArray(statusCnt, i)); + end loop; + axiSlaveRegisterR(axilEp, x"400", 0, statusOut); + + for i in NUM_LANE_G-1 downto 0 loop -- Address starts at 0x600 + axiSlaveRegisterR(axilEp, toSlv(1536+4*i, 12), 0, dlyConfig(i)); + end loop; + + axiSlaveRegisterR(axilEp, x"7FC", 0, toSlv(DATA_WIDTH_G, 8)); + axiSlaveRegisterR(axilEp, x"7FC", 8, toSlv(NUM_LANE_G, 8)); + + axiSlaveRegister (axilEp, x"800", 0, v.enUsrDlyCfg); + axiSlaveRegister (axilEp, x"804", 0, v.usrDlyCfg); + axiSlaveRegister (axilEp, x"808", 0, v.minEyeWidth); + axiSlaveRegister (axilEp, x"80C", 0, v.lockingCntCfg); + + axiSlaveRegister (axilEp, x"810", 0, v.bypFirstBerDet); + axiSlaveRegister (axilEp, x"814", 0, v.polarity); + + axiSlaveRegister (axilEp, x"FF8", 0, v.rollOverEn); + axiSlaveRegister (axilEp, x"FFC", 0, v.cntRst); + + -- Closeout the transaction + axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C); + + -- Synchronous Reset + if (axilRst = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + -- Outputs + axilWriteSlave <= r.axilWriteSlave; + axilReadSlave <= r.axilReadSlave; + + end process comb; + + seq : process (axilClk) is + begin + if (rising_edge(axilClk)) then + r <= rin after TPD_G; + end if; + end process seq; + + U_enUsrDlyCfg : entity surf.Synchronizer + generic map ( + TPD_G => TPD_G) + port map ( + clk => deserClk, + dataIn => r.enUsrDlyCfg, + dataOut => enUsrDlyCfg); + + U_usrDlyCfg : entity surf.SynchronizerFifo + generic map ( + TPD_G => TPD_G, + DATA_WIDTH_G => 9) + port map ( + wr_clk => axilClk, + din => r.usrDlyCfg, + rd_clk => deserClk, + dout => usrDlyCfg); + + U_minEyeWidth : entity surf.SynchronizerFifo + generic map ( + TPD_G => TPD_G, + DATA_WIDTH_G => 8) + port map ( + wr_clk => axilClk, + din => r.minEyeWidth, + rd_clk => deserClk, + dout => minEyeWidth); + + U_lockingCntCfg : entity surf.SynchronizerFifo + generic map ( + TPD_G => TPD_G, + DATA_WIDTH_G => 24) + port map ( + wr_clk => axilClk, + din => r.lockingCntCfg, + rd_clk => deserClk, + dout => lockingCntCfg); + + U_bypFirstBerDet : entity surf.Synchronizer + generic map ( + TPD_G => TPD_G) + port map ( + clk => deserClk, + dataIn => r.bypFirstBerDet, + dataOut => bypFirstBerDet); + + U_polarity : entity surf.SynchronizerVector + generic map ( + TPD_G => TPD_G, + WIDTH_G => NUM_LANE_G) + port map ( + clk => deserClk, + dataIn => r.polarity, + dataOut => polarity); + + U_SyncStatusVector : entity surf.SyncStatusVector + generic map ( + TPD_G => TPD_G, + COMMON_CLK_G => false, + OUT_POLARITY_G => '1', + CNT_RST_EDGE_G => false, + CNT_WIDTH_G => STATUS_WIDTH_C, + WIDTH_G => STATUS_SIZE_C) + port map ( + -- Input Status bit Signals (wrClk domain) + statusIn((2*NUM_LANE_G)+NUM_LANE_G-1 downto 2*NUM_LANE_G) => errorDet, + statusIn((1*NUM_LANE_G)+NUM_LANE_G-1 downto 1*NUM_LANE_G) => bitSlip, + statusIn((0*NUM_LANE_G)+NUM_LANE_G-1 downto 0*NUM_LANE_G) => locked, + -- Output Status bit Signals (rdClk domain) + statusOut => statusOut, + -- Status Bit Counters Signals (rdClk domain) + cntRstIn => r.cntRst, + rollOverEnIn => r.rollOverEn, + cntOut => statusCnt, + -- Clocks and Reset Ports + wrClk => deserClk, + rdClk => axilClk); + +end mapping; From 9de1bb671a7f06374be10eeb6fe111d941778a89 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 8 Jun 2020 13:11:17 -0700 Subject: [PATCH 20/40] vcs bug fix --- protocols/ssp/rtl/SspDecoderReg.vhd | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/protocols/ssp/rtl/SspDecoderReg.vhd b/protocols/ssp/rtl/SspDecoderReg.vhd index f54fd9fc88..5d22cf2a92 100644 --- a/protocols/ssp/rtl/SspDecoderReg.vhd +++ b/protocols/ssp/rtl/SspDecoderReg.vhd @@ -83,6 +83,7 @@ architecture mapping of SspDecoderReg is signal r : RegType := REG_INIT_C; signal rin : RegType; + signal statusIn : slv(STATUS_SIZE_C-1 downto 0); signal statusOut : slv(STATUS_SIZE_C-1 downto 0); signal statusCnt : SlVectorArray(STATUS_SIZE_C-1 downto 0, STATUS_WIDTH_C-1 downto 0); @@ -215,17 +216,19 @@ begin WIDTH_G => STATUS_SIZE_C) port map ( -- Input Status bit Signals (wrClk domain) - statusIn((2*NUM_LANE_G)+NUM_LANE_G-1 downto 2*NUM_LANE_G) => errorDet, - statusIn((1*NUM_LANE_G)+NUM_LANE_G-1 downto 1*NUM_LANE_G) => bitSlip, - statusIn((0*NUM_LANE_G)+NUM_LANE_G-1 downto 0*NUM_LANE_G) => locked, + statusIn => statusIn, -- Output Status bit Signals (rdClk domain) - statusOut => statusOut, + statusOut => statusOut, -- Status Bit Counters Signals (rdClk domain) - cntRstIn => r.cntRst, - rollOverEnIn => r.rollOverEn, - cntOut => statusCnt, + cntRstIn => r.cntRst, + rollOverEnIn => r.rollOverEn, + cntOut => statusCnt, -- Clocks and Reset Ports - wrClk => deserClk, - rdClk => axilClk); + wrClk => deserClk, + rdClk => axilClk); + + statusIn((2*NUM_LANE_G)+NUM_LANE_G-1 downto 2*NUM_LANE_G) <= errorDet; + statusIn((1*NUM_LANE_G)+NUM_LANE_G-1 downto 1*NUM_LANE_G) <= bitSlip; + statusIn((0*NUM_LANE_G)+NUM_LANE_G-1 downto 0*NUM_LANE_G) <= locked; end mapping; From 32cd5eb1c1c59b6a700c4db1448a908773f357ba Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 8 Jun 2020 13:29:11 -0700 Subject: [PATCH 21/40] adding SspDecoder.py --- python/surf/protocols/ssp/_SspDecoder.py | 153 +++++++++++++++++++++++ python/surf/protocols/ssp/__init__.py | 10 ++ 2 files changed, 163 insertions(+) create mode 100644 python/surf/protocols/ssp/_SspDecoder.py create mode 100644 python/surf/protocols/ssp/__init__.py diff --git a/python/surf/protocols/ssp/_SspDecoder.py b/python/surf/protocols/ssp/_SspDecoder.py new file mode 100644 index 0000000000..220780ff8c --- /dev/null +++ b/python/surf/protocols/ssp/_SspDecoder.py @@ -0,0 +1,153 @@ +#----------------------------------------------------------------------------- +# This file is part of the 'SLAC Firmware Standard Library'. It is subject to +# the license terms in the LICENSE.txt file found in the top-level directory +# of this distribution and at: +# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +# No part of the 'SLAC Firmware Standard Library', including this file, may be +# copied, modified, propagated, or distributed except according to the terms +# contained in the LICENSE.txt file. +#----------------------------------------------------------------------------- + +import pyrogue as pr + +class SspDecoder(pr.Device): + def __init__(self, numberLanes=1, **kwargs): + super().__init__(**kwargs) + + self.addRemoteVariables( + name = 'LockedCnt', + offset = 0*(numberLanes<<2), + bitSize = 16, + mode = 'RO', + number = numberLanes, + stride = 4, + pollInterval = 1, + ) + + self.addRemoteVariables( + name = 'BitSlipCnt', + offset = 1*(numberLanes<<2), + bitSize = 16, + mode = 'RO', + number = numberLanes, + stride = 4, + pollInterval = 1, + ) + + self.addRemoteVariables( + name = 'ErrorDetCnt', + offset = 2*(numberLanes<<2), + bitSize = 16, + mode = 'RO', + number = numberLanes, + stride = 4, + pollInterval = 1, + ) + + self.add(pr.RemoteVariable( + name = 'Locked', + offset = 0x400, + bitSize = 2, + mode = 'RO', + pollInterval = 1, + )) + + self.addRemoteVariables( + name = 'DlyConfig', + offset = 0x600, + bitSize = 9, + mode = 'RO', + number = numberLanes, + stride = 4, + pollInterval = 1, + ) + + self.add(pr.RemoteVariable( + name = 'DATA_WIDTH_G', + offset = 7FC, + bitSize = 8, + bitOffset = 0, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'NUM_LANE_G', + offset = 7FC, + bitSize = 8, + bitOffset = 8, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'EnUsrDlyCfg', + description = 'Enable User delay config', + offset = 0x800, + bitSize = 1, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'UsrDlyCfg', + description = 'User delay config', + offset = 0x804, + bitSize = 9, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'MinEyeWidth', + description = 'Sets the minimum eye width required for locking (units of IDELAY step)', + offset = 0x808, + bitSize = 8, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'LockingCntCfg', + description = 'Number of error-free event before state=LOCKED_S', + offset = 0x80C, + bitSize = 24, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'BypFirstBerDet', + description = 'Set to 0x1 if IDELAY full scale range > 2 Unit Intervals (UI) of serial rate (example: IDELAY range 2.5ns > 1 ns (1Gb/s) )', + offset = 0x810, + bitSize = 1, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'Polarity', + description = '1: Invert diff pair, 0: Non-inverted diff pair', + offset = 0x814, + bitSize = numberLanes, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'RollOverEn', + description = 'Rollover enable for status counters', + offset = 0xFF8, + bitSize = 7, + mode = 'RW', + )) + + self.add(pr.RemoteCommand( + name = 'CntRst', + description = 'Status counter reset', + offset = 0xFFC, + bitSize = 1, + function = lambda cmd: cmd.post(1), + hidden = False, + )) + + def hardReset(self): + self.CntRst() + + def softReset(self): + self.CntRst() + + def countReset(self): + self.CntRst() diff --git a/python/surf/protocols/ssp/__init__.py b/python/surf/protocols/ssp/__init__.py new file mode 100644 index 0000000000..2980fae092 --- /dev/null +++ b/python/surf/protocols/ssp/__init__.py @@ -0,0 +1,10 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## +from surf.protocols.ssp._SspDecoder import * From 326e2700a14403ab7b49f5ffdbe197b1f7e12ac8 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 8 Jun 2020 14:00:21 -0700 Subject: [PATCH 22/40] linter bug fix --- python/surf/protocols/ssp/_SspDecoder.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/python/surf/protocols/ssp/_SspDecoder.py b/python/surf/protocols/ssp/_SspDecoder.py index 220780ff8c..f507d8c2e0 100644 --- a/python/surf/protocols/ssp/_SspDecoder.py +++ b/python/surf/protocols/ssp/_SspDecoder.py @@ -64,7 +64,7 @@ def __init__(self, numberLanes=1, **kwargs): self.add(pr.RemoteVariable( name = 'DATA_WIDTH_G', - offset = 7FC, + offset = 0x7FC, bitSize = 8, bitOffset = 0, mode = 'RO', @@ -72,7 +72,7 @@ def __init__(self, numberLanes=1, **kwargs): self.add(pr.RemoteVariable( name = 'NUM_LANE_G', - offset = 7FC, + offset = 0x7FC, bitSize = 8, bitOffset = 8, mode = 'RO', From 3cdb152d9db2d4c708a08ce0044caef8a395bafe Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 9 Jun 2020 08:54:10 -0700 Subject: [PATCH 23/40] code clean up --- protocols/ssp/rtl/SspDecoderLane.vhd | 1 - 1 file changed, 1 deletion(-) diff --git a/protocols/ssp/rtl/SspDecoderLane.vhd b/protocols/ssp/rtl/SspDecoderLane.vhd index d886946c28..a022753807 100644 --- a/protocols/ssp/rtl/SspDecoderLane.vhd +++ b/protocols/ssp/rtl/SspDecoderLane.vhd @@ -19,7 +19,6 @@ use ieee.std_logic_unsigned.all; library surf; use surf.StdRtlPkg.all; -use surf.Code10b12bPkg.all; entity SspDecoderLane is generic ( From d8295054ccbc12d341d9f1fd1bc088dff8ec4e14 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 9 Jun 2020 09:49:16 -0700 Subject: [PATCH 24/40] renaming modules --- ...Wrapper.vhd => SspSelectIoDecoder10b12bWrapper.vhd} | 10 +++++----- ...Wrapper.vhd => SspSelectIoDecoder12b14bWrapper.vhd} | 10 +++++----- ...bWrapper.vhd => SspSelectIoDecoder8b10bWrapper.vhd} | 10 +++++----- .../{SspDecoderLane.vhd => SspSelectIoDecoderLane.vhd} | 6 +++--- .../{SspDecoderReg.vhd => SspSelectIoDecoderReg.vhd} | 0 .../ssp/{_SspDecoder.py => _SspSelectIoDecoderReg.py} | 2 +- python/surf/protocols/ssp/__init__.py | 2 +- 7 files changed, 20 insertions(+), 20 deletions(-) rename protocols/ssp/rtl/{SspDecoder10b12bWrapper.vhd => SspSelectIoDecoder10b12bWrapper.vhd} (95%) rename protocols/ssp/rtl/{SspDecoder12b14bWrapper.vhd => SspSelectIoDecoder12b14bWrapper.vhd} (95%) rename protocols/ssp/rtl/{SspDecoder8b10bWrapper.vhd => SspSelectIoDecoder8b10bWrapper.vhd} (95%) rename protocols/ssp/rtl/{SspDecoderLane.vhd => SspSelectIoDecoderLane.vhd} (98%) rename protocols/ssp/rtl/{SspDecoderReg.vhd => SspSelectIoDecoderReg.vhd} (100%) rename python/surf/protocols/ssp/{_SspDecoder.py => _SspSelectIoDecoderReg.py} (99%) diff --git a/protocols/ssp/rtl/SspDecoder10b12bWrapper.vhd b/protocols/ssp/rtl/SspSelectIoDecoder10b12bWrapper.vhd similarity index 95% rename from protocols/ssp/rtl/SspDecoder10b12bWrapper.vhd rename to protocols/ssp/rtl/SspSelectIoDecoder10b12bWrapper.vhd index 0dab87bda0..0dd1c23a06 100644 --- a/protocols/ssp/rtl/SspDecoder10b12bWrapper.vhd +++ b/protocols/ssp/rtl/SspSelectIoDecoder10b12bWrapper.vhd @@ -21,7 +21,7 @@ library surf; use surf.StdRtlPkg.all; use surf.AxiLitePkg.all; -entity SspDecoder10b12bWrapper is +entity SspSelectIoDecoder10b12bWrapper is generic ( TPD_G : time := 1 ns; SIMULATION_G : boolean := false; @@ -47,9 +47,9 @@ entity SspDecoder10b12bWrapper is axilReadSlave : out AxiLiteReadSlaveType; axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType); -end SspDecoder10b12bWrapper; +end SspSelectIoDecoder10b12bWrapper; -architecture mapping of SspDecoder10b12bWrapper is +architecture mapping of SspSelectIoDecoder10b12bWrapper is constant DATA_WIDTH_C : positive := 10; @@ -72,7 +72,7 @@ begin GEN_VEC : for i in NUM_LANE_G-1 downto 0 generate - U_Lane : entity surf.SspDecoderLane + U_Lane : entity surf.SspSelectIoDecoderLane generic map ( TPD_G => TPD_G, DATA_WIDTH_G => DATA_WIDTH_C, @@ -105,7 +105,7 @@ begin end generate GEN_VEC; - U_Reg : entity surf.SspDecoderReg + U_Reg : entity surf.SspSelectIoDecoderReg generic map ( TPD_G => TPD_G, SIMULATION_G => SIMULATION_G, diff --git a/protocols/ssp/rtl/SspDecoder12b14bWrapper.vhd b/protocols/ssp/rtl/SspSelectIoDecoder12b14bWrapper.vhd similarity index 95% rename from protocols/ssp/rtl/SspDecoder12b14bWrapper.vhd rename to protocols/ssp/rtl/SspSelectIoDecoder12b14bWrapper.vhd index 1f067e0ea7..d07ba232b3 100644 --- a/protocols/ssp/rtl/SspDecoder12b14bWrapper.vhd +++ b/protocols/ssp/rtl/SspSelectIoDecoder12b14bWrapper.vhd @@ -21,7 +21,7 @@ library surf; use surf.StdRtlPkg.all; use surf.AxiLitePkg.all; -entity SspDecoder12b14bWrapper is +entity SspSelectIoDecoder12b14bWrapper is generic ( TPD_G : time := 1 ns; SIMULATION_G : boolean := false; @@ -47,9 +47,9 @@ entity SspDecoder12b14bWrapper is axilReadSlave : out AxiLiteReadSlaveType; axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType); -end SspDecoder12b14bWrapper; +end SspSelectIoDecoder12b14bWrapper; -architecture mapping of SspDecoder12b14bWrapper is +architecture mapping of SspSelectIoDecoder12b14bWrapper is constant DATA_WIDTH_C : positive := 12; @@ -72,7 +72,7 @@ begin GEN_VEC : for i in NUM_LANE_G-1 downto 0 generate - U_Lane : entity surf.SspDecoderLane + U_Lane : entity surf.SspSelectIoDecoderLane generic map ( TPD_G => TPD_G, DATA_WIDTH_G => DATA_WIDTH_C, @@ -105,7 +105,7 @@ begin end generate GEN_VEC; - U_Reg : entity surf.SspDecoderReg + U_Reg : entity surf.SspSelectIoDecoderReg generic map ( TPD_G => TPD_G, SIMULATION_G => SIMULATION_G, diff --git a/protocols/ssp/rtl/SspDecoder8b10bWrapper.vhd b/protocols/ssp/rtl/SspSelectIoDecoder8b10bWrapper.vhd similarity index 95% rename from protocols/ssp/rtl/SspDecoder8b10bWrapper.vhd rename to protocols/ssp/rtl/SspSelectIoDecoder8b10bWrapper.vhd index f74524c3f3..272c598649 100644 --- a/protocols/ssp/rtl/SspDecoder8b10bWrapper.vhd +++ b/protocols/ssp/rtl/SspSelectIoDecoder8b10bWrapper.vhd @@ -21,7 +21,7 @@ library surf; use surf.StdRtlPkg.all; use surf.AxiLitePkg.all; -entity SspDecoder8b10bWrapper is +entity SspSelectIoDecoder8b10bWrapper is generic ( TPD_G : time := 1 ns; SIMULATION_G : boolean := false; @@ -47,9 +47,9 @@ entity SspDecoder8b10bWrapper is axilReadSlave : out AxiLiteReadSlaveType; axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType); -end SspDecoder8b10bWrapper; +end SspSelectIoDecoder8b10bWrapper; -architecture mapping of SspDecoder8b10bWrapper is +architecture mapping of SspSelectIoDecoder8b10bWrapper is constant DATA_WIDTH_C : positive := 16; @@ -72,7 +72,7 @@ begin GEN_VEC : for i in NUM_LANE_G-1 downto 0 generate - U_Lane : entity surf.SspDecoderLane + U_Lane : entity surf.SspSelectIoDecoderLane generic map ( TPD_G => TPD_G, DATA_WIDTH_G => DATA_WIDTH_C, @@ -105,7 +105,7 @@ begin end generate GEN_VEC; - U_Reg : entity surf.SspDecoderReg + U_Reg : entity surf.SspSelectIoDecoderReg generic map ( TPD_G => TPD_G, SIMULATION_G => SIMULATION_G, diff --git a/protocols/ssp/rtl/SspDecoderLane.vhd b/protocols/ssp/rtl/SspSelectIoDecoderLane.vhd similarity index 98% rename from protocols/ssp/rtl/SspDecoderLane.vhd rename to protocols/ssp/rtl/SspSelectIoDecoderLane.vhd index a022753807..1c2e8ce9a4 100644 --- a/protocols/ssp/rtl/SspDecoderLane.vhd +++ b/protocols/ssp/rtl/SspSelectIoDecoderLane.vhd @@ -20,7 +20,7 @@ use ieee.std_logic_unsigned.all; library surf; use surf.StdRtlPkg.all; -entity SspDecoderLane is +entity SspSelectIoDecoderLane is generic ( TPD_G : time := 1 ns; DATA_WIDTH_G : positive := 10; @@ -50,9 +50,9 @@ entity SspDecoderLane is rxSof : out sl; rxEof : out sl; rxEofe : out sl); -end SspDecoderLane; +end SspSelectIoDecoderLane; -architecture mapping of SspDecoderLane is +architecture mapping of SspSelectIoDecoderLane is constant ENCODE_WIDTH_C : positive := ite(DATA_WIDTH_G = 16, 20, DATA_WIDTH_G+2); diff --git a/protocols/ssp/rtl/SspDecoderReg.vhd b/protocols/ssp/rtl/SspSelectIoDecoderReg.vhd similarity index 100% rename from protocols/ssp/rtl/SspDecoderReg.vhd rename to protocols/ssp/rtl/SspSelectIoDecoderReg.vhd diff --git a/python/surf/protocols/ssp/_SspDecoder.py b/python/surf/protocols/ssp/_SspSelectIoDecoderReg.py similarity index 99% rename from python/surf/protocols/ssp/_SspDecoder.py rename to python/surf/protocols/ssp/_SspSelectIoDecoderReg.py index f507d8c2e0..efb184c663 100644 --- a/python/surf/protocols/ssp/_SspDecoder.py +++ b/python/surf/protocols/ssp/_SspSelectIoDecoderReg.py @@ -10,7 +10,7 @@ import pyrogue as pr -class SspDecoder(pr.Device): +class SspSelectIoDecoderReg(pr.Device): def __init__(self, numberLanes=1, **kwargs): super().__init__(**kwargs) diff --git a/python/surf/protocols/ssp/__init__.py b/python/surf/protocols/ssp/__init__.py index 2980fae092..b1037bfcde 100644 --- a/python/surf/protocols/ssp/__init__.py +++ b/python/surf/protocols/ssp/__init__.py @@ -7,4 +7,4 @@ ## may be copied, modified, propagated, or distributed except according to ## the terms contained in the LICENSE.txt file. ############################################################################## -from surf.protocols.ssp._SspDecoder import * +from surf.protocols.ssp._SspSelectIoDecoderReg import * From 3b2658373ad1cc85c5747b4e194cbef2d0e20903 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 9 Jun 2020 09:55:52 -0700 Subject: [PATCH 25/40] adding AxiLiteAsync in SspSelectIoDecoderReg.vhd --- protocols/ssp/rtl/SspSelectIoDecoderReg.vhd | 120 ++++++++------------ 1 file changed, 48 insertions(+), 72 deletions(-) diff --git a/protocols/ssp/rtl/SspSelectIoDecoderReg.vhd b/protocols/ssp/rtl/SspSelectIoDecoderReg.vhd index 5d22cf2a92..1ed85f6d21 100644 --- a/protocols/ssp/rtl/SspSelectIoDecoderReg.vhd +++ b/protocols/ssp/rtl/SspSelectIoDecoderReg.vhd @@ -64,8 +64,8 @@ architecture mapping of SspDecoderReg is polarity : slv(NUM_LANE_G-1 downto 0); cntRst : sl; rollOverEn : slv(STATUS_SIZE_C-1 downto 0); - axilReadSlave : AxiLiteReadSlaveType; - axilWriteSlave : AxiLiteWriteSlaveType; + readSlave : AxiLiteReadSlaveType; + writeSlave : AxiLiteWriteSlaveType; end record; constant REG_INIT_C : RegType := ( @@ -77,8 +77,8 @@ architecture mapping of SspDecoderReg is polarity => (others => '0'), cntRst => '1', rollOverEn => (others => '0'), - axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, - axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C); + readSlave => AXI_LITE_READ_SLAVE_INIT_C, + writeSlave => AXI_LITE_WRITE_SLAVE_INIT_C); signal r : RegType := REG_INIT_C; signal rin : RegType; @@ -87,10 +87,35 @@ architecture mapping of SspDecoderReg is signal statusOut : slv(STATUS_SIZE_C-1 downto 0); signal statusCnt : SlVectorArray(STATUS_SIZE_C-1 downto 0, STATUS_WIDTH_C-1 downto 0); + signal readMaster : AxiLiteReadMasterType; + signal readSlave : AxiLiteReadSlaveType; + signal writeMaster : AxiLiteWriteMasterType; + signal writeSlave : AxiLiteWriteSlaveType; + begin - comb : process (axilReadMaster, axilRst, axilWriteMaster, dlyConfig, r, - statusCnt, statusOut) is + U_AxiLiteAsync : entity surf.AxiLiteAsync + generic map ( + TPD_G => TPD_G, + NUM_ADDR_BITS_G => 12) + port map ( + -- Slave Interface + sAxiClk => axilClk, + sAxiClkRst => axilRst, + sAxiReadMaster => axilReadMaster, + sAxiReadSlave => axilReadSlave, + sAxiWriteMaster => axilWriteMaster, + sAxiWriteSlave => axilWriteSlave, + -- Master Interface + mAxiClk => deserClk, + mAxiClkRst => deserRst, + mAxiReadMaster => readMaster, + mAxiReadSlave => readSlave, + mAxiWriteMaster => writeMaster, + mAxiWriteSlave => writeSlave); + + comb : process (deserRst, dlyConfig, r, readMaster, statusCnt, statusOut, + writeMaster) is variable v : RegType; variable axilEp : AxiLiteEndPointType; begin @@ -101,7 +126,7 @@ begin v.cntRst := '0'; -- Determine the transaction type - axiSlaveWaitTxn(axilEp, axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave); + axiSlaveWaitTxn(axilEp, writeMaster, readMaster, v.writeSlave, v.readSlave); -- Map the read registers for i in STATUS_SIZE_C-1 downto 0 loop @@ -128,88 +153,39 @@ begin axiSlaveRegister (axilEp, x"FFC", 0, v.cntRst); -- Closeout the transaction - axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C); + axiSlaveDefault(axilEp, v.writeSlave, v.readSlave, AXI_RESP_DECERR_C); + + -- Outputs + writeSlave <= r.writeSlave; + readSlave <= r.readSlave; + enUsrDlyCfg <= r.enUsrDlyCfg; + usrDlyCfg <= r.usrDlyCfg; + minEyeWidth <= r.minEyeWidth; + lockingCntCfg <= r.lockingCntCfg; + bypFirstBerDet <= r.bypFirstBerDet; + polarity <= r.polarity; -- Synchronous Reset - if (axilRst = '1') then + if (deserRst = '1') then v := REG_INIT_C; end if; -- Register the variable for next clock cycle rin <= v; - -- Outputs - axilWriteSlave <= r.axilWriteSlave; - axilReadSlave <= r.axilReadSlave; - end process comb; - seq : process (axilClk) is + seq : process (deserClk) is begin - if (rising_edge(axilClk)) then + if (rising_edge(deserClk)) then r <= rin after TPD_G; end if; end process seq; - U_enUsrDlyCfg : entity surf.Synchronizer - generic map ( - TPD_G => TPD_G) - port map ( - clk => deserClk, - dataIn => r.enUsrDlyCfg, - dataOut => enUsrDlyCfg); - - U_usrDlyCfg : entity surf.SynchronizerFifo - generic map ( - TPD_G => TPD_G, - DATA_WIDTH_G => 9) - port map ( - wr_clk => axilClk, - din => r.usrDlyCfg, - rd_clk => deserClk, - dout => usrDlyCfg); - - U_minEyeWidth : entity surf.SynchronizerFifo - generic map ( - TPD_G => TPD_G, - DATA_WIDTH_G => 8) - port map ( - wr_clk => axilClk, - din => r.minEyeWidth, - rd_clk => deserClk, - dout => minEyeWidth); - - U_lockingCntCfg : entity surf.SynchronizerFifo - generic map ( - TPD_G => TPD_G, - DATA_WIDTH_G => 24) - port map ( - wr_clk => axilClk, - din => r.lockingCntCfg, - rd_clk => deserClk, - dout => lockingCntCfg); - - U_bypFirstBerDet : entity surf.Synchronizer - generic map ( - TPD_G => TPD_G) - port map ( - clk => deserClk, - dataIn => r.bypFirstBerDet, - dataOut => bypFirstBerDet); - - U_polarity : entity surf.SynchronizerVector - generic map ( - TPD_G => TPD_G, - WIDTH_G => NUM_LANE_G) - port map ( - clk => deserClk, - dataIn => r.polarity, - dataOut => polarity); - U_SyncStatusVector : entity surf.SyncStatusVector generic map ( TPD_G => TPD_G, - COMMON_CLK_G => false, + COMMON_CLK_G => true, OUT_POLARITY_G => '1', CNT_RST_EDGE_G => false, CNT_WIDTH_G => STATUS_WIDTH_C, @@ -225,7 +201,7 @@ begin cntOut => statusCnt, -- Clocks and Reset Ports wrClk => deserClk, - rdClk => axilClk); + rdClk => deserClk); statusIn((2*NUM_LANE_G)+NUM_LANE_G-1 downto 2*NUM_LANE_G) <= errorDet; statusIn((1*NUM_LANE_G)+NUM_LANE_G-1 downto 1*NUM_LANE_G) <= bitSlip; From 529837fb5ea6ec1c951fbfe7fd459ab8d8737b2a Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 9 Jun 2020 10:01:29 -0700 Subject: [PATCH 26/40] bug fix --- protocols/ssp/rtl/SspSelectIoDecoderReg.vhd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/protocols/ssp/rtl/SspSelectIoDecoderReg.vhd b/protocols/ssp/rtl/SspSelectIoDecoderReg.vhd index 1ed85f6d21..20ee463fb7 100644 --- a/protocols/ssp/rtl/SspSelectIoDecoderReg.vhd +++ b/protocols/ssp/rtl/SspSelectIoDecoderReg.vhd @@ -21,7 +21,7 @@ library surf; use surf.StdRtlPkg.all; use surf.AxiLitePkg.all; -entity SspDecoderReg is +entity SspSelectIoDecoderReg is generic ( TPD_G : time := 1 ns; SIMULATION_G : boolean := false; @@ -48,9 +48,9 @@ entity SspDecoderReg is axilReadSlave : out AxiLiteReadSlaveType; axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType); -end SspDecoderReg; +end SspSelectIoDecoderReg; -architecture mapping of SspDecoderReg is +architecture mapping of SspSelectIoDecoderReg is constant STATUS_SIZE_C : positive := 3*NUM_LANE_G; constant STATUS_WIDTH_C : positive := 16; From 870df500f09d30e9d6cbe0ea8e5c0c972d90093b Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 9 Jun 2020 12:54:46 -0700 Subject: [PATCH 27/40] cannot add .DCP as global with Vivado 2020.1 DFX or with use IP Integrator + custom RTL modules --- protocols/xvc-udp/ruckus.tcl | 2 -- 1 file changed, 2 deletions(-) diff --git a/protocols/xvc-udp/ruckus.tcl b/protocols/xvc-udp/ruckus.tcl index 66fcd05eba..7d3a8ad4b8 100644 --- a/protocols/xvc-udp/ruckus.tcl +++ b/protocols/xvc-udp/ruckus.tcl @@ -29,7 +29,6 @@ if { $::env(VIVADO_VERSION) >= 2018.3 } { if { [info exists ::env(USE_XVC_DEBUG)] != 1 || $::env(USE_XVC_DEBUG) == 0 } { loadSource -lib surf -path "$::DIR_PATH/dcp/${dirType}/Stub/images/UdpDebugBridge.dcp" - set_property IS_GLOBAL_INCLUDE {1} [get_files UdpDebugBridge.dcp] } elseif { $::env(USE_XVC_DEBUG) == -1 } { puts "Note: USE_XVC_DEBUG = -1" @@ -39,7 +38,6 @@ if { $::env(VIVADO_VERSION) >= 2018.3 } { } else { loadSource -lib surf -path "$::DIR_PATH/dcp/${dirType}/Impl/images/UdpDebugBridge.dcp" - set_property IS_GLOBAL_INCLUDE {1} [get_files UdpDebugBridge.dcp] } } else { From 98a7e29565020386f503c281ba2f969697953b68 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 9 Jun 2020 15:34:51 -0700 Subject: [PATCH 28/40] Update _ClinkSerialRx.py ### Description - Adding method for detecting response by setting _last to `None` before sending followed by polling for a value of _last. --- python/surf/protocols/clink/_ClinkSerialRx.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/python/surf/protocols/clink/_ClinkSerialRx.py b/python/surf/protocols/clink/_ClinkSerialRx.py index 899f6f6881..def11fd2f9 100644 --- a/python/surf/protocols/clink/_ClinkSerialRx.py +++ b/python/surf/protocols/clink/_ClinkSerialRx.py @@ -20,7 +20,7 @@ class ClinkSerialRx(rogue.interfaces.stream.Slave): def __init__(self): rogue.interfaces.stream.Slave.__init__(self) self._cur = [] - self._last = '' + self._last = None def _acceptFrame(self,frame): ba = bytearray(frame.getPayload()) @@ -30,10 +30,10 @@ def _acceptFrame(self,frame): c = chr(ba[i]) if c == '\n': - self._last = ''.join(self._cur) - print("Got Response: {}".format(self._last)) + print("Got Response: {}".format(''.join(self._cur))) self._cur = [] elif c == '\r': print("recvString: {}".format(''.join(self._cur))) + self._last = ''.join(self._cur) elif c != '': self._cur.append(c) From 999befef714289a95f27086d92420528fa556985 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 9 Jun 2020 16:57:05 -0700 Subject: [PATCH 29/40] renmaing SspSelectIoDecoder -> SspLowSpeedDecoder --- ...Wrapper.vhd => SspLowSpeedDecoder10b12bWrapper.vhd} | 10 +++++----- ...Wrapper.vhd => SspLowSpeedDecoder12b14bWrapper.vhd} | 10 +++++----- ...bWrapper.vhd => SspLowSpeedDecoder8b10bWrapper.vhd} | 10 +++++----- ...ectIoDecoderLane.vhd => SspLowSpeedDecoderLane.vhd} | 6 +++--- ...electIoDecoderReg.vhd => SspLowSpeedDecoderReg.vhd} | 6 +++--- 5 files changed, 21 insertions(+), 21 deletions(-) rename protocols/ssp/rtl/{SspSelectIoDecoder10b12bWrapper.vhd => SspLowSpeedDecoder10b12bWrapper.vhd} (95%) rename protocols/ssp/rtl/{SspSelectIoDecoder12b14bWrapper.vhd => SspLowSpeedDecoder12b14bWrapper.vhd} (95%) rename protocols/ssp/rtl/{SspSelectIoDecoder8b10bWrapper.vhd => SspLowSpeedDecoder8b10bWrapper.vhd} (95%) rename protocols/ssp/rtl/{SspSelectIoDecoderLane.vhd => SspLowSpeedDecoderLane.vhd} (98%) rename protocols/ssp/rtl/{SspSelectIoDecoderReg.vhd => SspLowSpeedDecoderReg.vhd} (98%) diff --git a/protocols/ssp/rtl/SspSelectIoDecoder10b12bWrapper.vhd b/protocols/ssp/rtl/SspLowSpeedDecoder10b12bWrapper.vhd similarity index 95% rename from protocols/ssp/rtl/SspSelectIoDecoder10b12bWrapper.vhd rename to protocols/ssp/rtl/SspLowSpeedDecoder10b12bWrapper.vhd index 0dd1c23a06..64a6fe65b2 100644 --- a/protocols/ssp/rtl/SspSelectIoDecoder10b12bWrapper.vhd +++ b/protocols/ssp/rtl/SspLowSpeedDecoder10b12bWrapper.vhd @@ -21,7 +21,7 @@ library surf; use surf.StdRtlPkg.all; use surf.AxiLitePkg.all; -entity SspSelectIoDecoder10b12bWrapper is +entity SspLowSpeedDecoder10b12bWrapper is generic ( TPD_G : time := 1 ns; SIMULATION_G : boolean := false; @@ -47,9 +47,9 @@ entity SspSelectIoDecoder10b12bWrapper is axilReadSlave : out AxiLiteReadSlaveType; axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType); -end SspSelectIoDecoder10b12bWrapper; +end SspLowSpeedDecoder10b12bWrapper; -architecture mapping of SspSelectIoDecoder10b12bWrapper is +architecture mapping of SspLowSpeedDecoder10b12bWrapper is constant DATA_WIDTH_C : positive := 10; @@ -72,7 +72,7 @@ begin GEN_VEC : for i in NUM_LANE_G-1 downto 0 generate - U_Lane : entity surf.SspSelectIoDecoderLane + U_Lane : entity surf.SspLowSpeedDecoderLane generic map ( TPD_G => TPD_G, DATA_WIDTH_G => DATA_WIDTH_C, @@ -105,7 +105,7 @@ begin end generate GEN_VEC; - U_Reg : entity surf.SspSelectIoDecoderReg + U_Reg : entity surf.SspLowSpeedDecoderReg generic map ( TPD_G => TPD_G, SIMULATION_G => SIMULATION_G, diff --git a/protocols/ssp/rtl/SspSelectIoDecoder12b14bWrapper.vhd b/protocols/ssp/rtl/SspLowSpeedDecoder12b14bWrapper.vhd similarity index 95% rename from protocols/ssp/rtl/SspSelectIoDecoder12b14bWrapper.vhd rename to protocols/ssp/rtl/SspLowSpeedDecoder12b14bWrapper.vhd index d07ba232b3..a444ed38fb 100644 --- a/protocols/ssp/rtl/SspSelectIoDecoder12b14bWrapper.vhd +++ b/protocols/ssp/rtl/SspLowSpeedDecoder12b14bWrapper.vhd @@ -21,7 +21,7 @@ library surf; use surf.StdRtlPkg.all; use surf.AxiLitePkg.all; -entity SspSelectIoDecoder12b14bWrapper is +entity SspLowSpeedDecoder12b14bWrapper is generic ( TPD_G : time := 1 ns; SIMULATION_G : boolean := false; @@ -47,9 +47,9 @@ entity SspSelectIoDecoder12b14bWrapper is axilReadSlave : out AxiLiteReadSlaveType; axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType); -end SspSelectIoDecoder12b14bWrapper; +end SspLowSpeedDecoder12b14bWrapper; -architecture mapping of SspSelectIoDecoder12b14bWrapper is +architecture mapping of SspLowSpeedDecoder12b14bWrapper is constant DATA_WIDTH_C : positive := 12; @@ -72,7 +72,7 @@ begin GEN_VEC : for i in NUM_LANE_G-1 downto 0 generate - U_Lane : entity surf.SspSelectIoDecoderLane + U_Lane : entity surf.SspLowSpeedDecoderLane generic map ( TPD_G => TPD_G, DATA_WIDTH_G => DATA_WIDTH_C, @@ -105,7 +105,7 @@ begin end generate GEN_VEC; - U_Reg : entity surf.SspSelectIoDecoderReg + U_Reg : entity surf.SspLowSpeedDecoderReg generic map ( TPD_G => TPD_G, SIMULATION_G => SIMULATION_G, diff --git a/protocols/ssp/rtl/SspSelectIoDecoder8b10bWrapper.vhd b/protocols/ssp/rtl/SspLowSpeedDecoder8b10bWrapper.vhd similarity index 95% rename from protocols/ssp/rtl/SspSelectIoDecoder8b10bWrapper.vhd rename to protocols/ssp/rtl/SspLowSpeedDecoder8b10bWrapper.vhd index 272c598649..c6d4279239 100644 --- a/protocols/ssp/rtl/SspSelectIoDecoder8b10bWrapper.vhd +++ b/protocols/ssp/rtl/SspLowSpeedDecoder8b10bWrapper.vhd @@ -21,7 +21,7 @@ library surf; use surf.StdRtlPkg.all; use surf.AxiLitePkg.all; -entity SspSelectIoDecoder8b10bWrapper is +entity SspLowSpeedDecoder8b10bWrapper is generic ( TPD_G : time := 1 ns; SIMULATION_G : boolean := false; @@ -47,9 +47,9 @@ entity SspSelectIoDecoder8b10bWrapper is axilReadSlave : out AxiLiteReadSlaveType; axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType); -end SspSelectIoDecoder8b10bWrapper; +end SspLowSpeedDecoder8b10bWrapper; -architecture mapping of SspSelectIoDecoder8b10bWrapper is +architecture mapping of SspLowSpeedDecoder8b10bWrapper is constant DATA_WIDTH_C : positive := 16; @@ -72,7 +72,7 @@ begin GEN_VEC : for i in NUM_LANE_G-1 downto 0 generate - U_Lane : entity surf.SspSelectIoDecoderLane + U_Lane : entity surf.SspLowSpeedDecoderLane generic map ( TPD_G => TPD_G, DATA_WIDTH_G => DATA_WIDTH_C, @@ -105,7 +105,7 @@ begin end generate GEN_VEC; - U_Reg : entity surf.SspSelectIoDecoderReg + U_Reg : entity surf.SspLowSpeedDecoderReg generic map ( TPD_G => TPD_G, SIMULATION_G => SIMULATION_G, diff --git a/protocols/ssp/rtl/SspSelectIoDecoderLane.vhd b/protocols/ssp/rtl/SspLowSpeedDecoderLane.vhd similarity index 98% rename from protocols/ssp/rtl/SspSelectIoDecoderLane.vhd rename to protocols/ssp/rtl/SspLowSpeedDecoderLane.vhd index 1c2e8ce9a4..0d26acb0c0 100644 --- a/protocols/ssp/rtl/SspSelectIoDecoderLane.vhd +++ b/protocols/ssp/rtl/SspLowSpeedDecoderLane.vhd @@ -20,7 +20,7 @@ use ieee.std_logic_unsigned.all; library surf; use surf.StdRtlPkg.all; -entity SspSelectIoDecoderLane is +entity SspLowSpeedDecoderLane is generic ( TPD_G : time := 1 ns; DATA_WIDTH_G : positive := 10; @@ -50,9 +50,9 @@ entity SspSelectIoDecoderLane is rxSof : out sl; rxEof : out sl; rxEofe : out sl); -end SspSelectIoDecoderLane; +end SspLowSpeedDecoderLane; -architecture mapping of SspSelectIoDecoderLane is +architecture mapping of SspLowSpeedDecoderLane is constant ENCODE_WIDTH_C : positive := ite(DATA_WIDTH_G = 16, 20, DATA_WIDTH_G+2); diff --git a/protocols/ssp/rtl/SspSelectIoDecoderReg.vhd b/protocols/ssp/rtl/SspLowSpeedDecoderReg.vhd similarity index 98% rename from protocols/ssp/rtl/SspSelectIoDecoderReg.vhd rename to protocols/ssp/rtl/SspLowSpeedDecoderReg.vhd index 20ee463fb7..b2e9fbabc7 100644 --- a/protocols/ssp/rtl/SspSelectIoDecoderReg.vhd +++ b/protocols/ssp/rtl/SspLowSpeedDecoderReg.vhd @@ -21,7 +21,7 @@ library surf; use surf.StdRtlPkg.all; use surf.AxiLitePkg.all; -entity SspSelectIoDecoderReg is +entity SspLowSpeedDecoderReg is generic ( TPD_G : time := 1 ns; SIMULATION_G : boolean := false; @@ -48,9 +48,9 @@ entity SspSelectIoDecoderReg is axilReadSlave : out AxiLiteReadSlaveType; axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType); -end SspSelectIoDecoderReg; +end SspLowSpeedDecoderReg; -architecture mapping of SspSelectIoDecoderReg is +architecture mapping of SspLowSpeedDecoderReg is constant STATUS_SIZE_C : positive := 3*NUM_LANE_G; constant STATUS_WIDTH_C : positive := 16; From 80a250d6a85e262fe13fc8aa28b2766566eacfd9 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 9 Jun 2020 16:57:57 -0700 Subject: [PATCH 30/40] renmaing SspSelectIoDecoder -> SspLowSpeedDecoder --- .../{_SspSelectIoDecoderReg.py => _SspLowSpeedDecoderReg.py} | 2 +- python/surf/protocols/ssp/__init__.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) rename python/surf/protocols/ssp/{_SspSelectIoDecoderReg.py => _SspLowSpeedDecoderReg.py} (99%) diff --git a/python/surf/protocols/ssp/_SspSelectIoDecoderReg.py b/python/surf/protocols/ssp/_SspLowSpeedDecoderReg.py similarity index 99% rename from python/surf/protocols/ssp/_SspSelectIoDecoderReg.py rename to python/surf/protocols/ssp/_SspLowSpeedDecoderReg.py index efb184c663..f8f72b2794 100644 --- a/python/surf/protocols/ssp/_SspSelectIoDecoderReg.py +++ b/python/surf/protocols/ssp/_SspLowSpeedDecoderReg.py @@ -10,7 +10,7 @@ import pyrogue as pr -class SspSelectIoDecoderReg(pr.Device): +class SspLowSpeedDecoderReg(pr.Device): def __init__(self, numberLanes=1, **kwargs): super().__init__(**kwargs) diff --git a/python/surf/protocols/ssp/__init__.py b/python/surf/protocols/ssp/__init__.py index b1037bfcde..10ea398be8 100644 --- a/python/surf/protocols/ssp/__init__.py +++ b/python/surf/protocols/ssp/__init__.py @@ -7,4 +7,4 @@ ## may be copied, modified, propagated, or distributed except according to ## the terms contained in the LICENSE.txt file. ############################################################################## -from surf.protocols.ssp._SspSelectIoDecoderReg import * +from surf.protocols.ssp._SspLowSpeedDecoderReg import * From 79f6038eb09ba66b92ade5c42b78f986be21bdd6 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 12 Jun 2020 10:39:00 -0700 Subject: [PATCH 31/40] update to SspLowSpeedDecoderReg.py --- python/surf/protocols/ssp/_SspLowSpeedDecoderReg.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/python/surf/protocols/ssp/_SspLowSpeedDecoderReg.py b/python/surf/protocols/ssp/_SspLowSpeedDecoderReg.py index f8f72b2794..3fe4e6b6a1 100644 --- a/python/surf/protocols/ssp/_SspLowSpeedDecoderReg.py +++ b/python/surf/protocols/ssp/_SspLowSpeedDecoderReg.py @@ -68,6 +68,7 @@ def __init__(self, numberLanes=1, **kwargs): bitSize = 8, bitOffset = 0, mode = 'RO', + disp = '{:d}', )) self.add(pr.RemoteVariable( @@ -76,6 +77,7 @@ def __init__(self, numberLanes=1, **kwargs): bitSize = 8, bitOffset = 8, mode = 'RO', + disp = '{:d}', )) self.add(pr.RemoteVariable( From c58960685043323abcd6c8877806bd15b9f1bf55 Mon Sep 17 00:00:00 2001 From: Matt Weaver Date: Fri, 12 Jun 2020 13:17:53 -0700 Subject: [PATCH 32/40] Add interrupt holdoff. --- axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd b/axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd index 236462f3db..c3f69af1b9 100644 --- a/axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd +++ b/axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd @@ -174,6 +174,9 @@ architecture rtl of AxiStreamDmaV2Desc is intReqCount : slv(31 downto 0); interrupt : sl; + intHoldoff : slv(15 downto 0); + intHoldoffCount : slv(15 downto 0); + end record RegType; constant REG_INIT_C : RegType := ( @@ -235,7 +238,9 @@ architecture rtl of AxiStreamDmaV2Desc is rdMemAddr => (others => '0'), intReqEn => '0', intReqCount => (others => '0'), - interrupt => '0'); + interrupt => '0', + intHoldoff => toSlv(10000,16), -- ~20 kHz + intHoldoffCount => (others => '0') ); signal r : RegType := REG_INIT_C; signal rin : RegType; @@ -429,6 +434,8 @@ begin axiSlaveRegister(regCon, x"080", 0, v.forceInt); + axiSlaveRegister(regCon, x"084", 0, v.intHoldoff); + -- End transaction block axiSlaveDefault(regCon, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C); @@ -688,7 +695,7 @@ begin end loop; -- Drive interrupt, avoid false firings during ack - if (r.intReqCount /= 0 or r.forceInt = '1') and r.intSwAckReq = '0' then + if ((r.intReqCount /= 0 and r.intHoldoffCount > r.intHoldoff) or r.forceInt = '1') and r.intSwAckReq = '0' then v.interrupt := r.intEnable; else v.interrupt := '0'; @@ -724,6 +731,12 @@ begin v.forceInt := '0'; end if; + if r.intSwAckReq = '1' then + v.intHoldoffCount := (others=>'0'); + elsif uAnd(r.intHoldoffCount)='0' then + v.intHoldoffCount := r.intHoldoffCount+1; + end if; + ---------------------------------------------------------- -- Read Descriptor Requests ---------------------------------------------------------- From 4952afc02845855038f1ae006f3d8faa14a2c071 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 12 Jun 2020 13:26:39 -0700 Subject: [PATCH 33/40] Update AxiStreamDmaV2Desc.vhd Updating to Version Number = 0x3 --- axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd b/axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd index c3f69af1b9..b4d0930725 100644 --- a/axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd +++ b/axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd @@ -383,7 +383,7 @@ begin axiSlaveRegister(regCon, x"000", 0, v.enable); axiSlaveRegisterR(regCon, x"000", 8, r.enableCnt); -- Count the number of times enable transitions from 0->1 axiSlaveRegisterR(regCon, x"000", 16, '1'); -- Legacy DESC_128_EN_C constant (always 0x1 now) - axiSlaveRegisterR(regCon, x"000", 24, toSlv(2, 8)); -- Version 2 = 2, Version1 = 0 + axiSlaveRegisterR(regCon, x"000", 24, toSlv(3, 8)); -- Version Number for aes-stream-driver to case on axiSlaveRegister(regCon, x"004", 0, v.intEnable); axiSlaveRegister(regCon, x"008", 0, v.contEn); axiSlaveRegister(regCon, x"00C", 0, v.dropEn); From 64bb3f2264164cac7dff80cb3efe36f68b78ec48 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 12 Jun 2020 13:42:32 -0700 Subject: [PATCH 34/40] Update JesdRxReg.vhd ### Description - Connecting axilWriteResp to axiSlaveWriteResponse() - Connecting axilReadResp to axiSlaveReadResponse() --- protocols/jesd204b/rtl/JesdRxReg.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/protocols/jesd204b/rtl/JesdRxReg.vhd b/protocols/jesd204b/rtl/JesdRxReg.vhd index f32619b9fa..a335345a49 100644 --- a/protocols/jesd204b/rtl/JesdRxReg.vhd +++ b/protocols/jesd204b/rtl/JesdRxReg.vhd @@ -229,7 +229,7 @@ begin when others => axilWriteResp := AXI_RESP_DECERR_C; end case; - axiSlaveWriteResponse(v.axilWriteSlave); + axiSlaveWriteResponse(v.axilWriteSlave, axilWriteResp); end if; if (axilStatus.readEnable = '1') then @@ -288,7 +288,7 @@ begin when others => axilReadResp := AXI_RESP_DECERR_C; end case; - axiSlaveReadResponse(v.axilReadSlave); + axiSlaveReadResponse(v.axilReadSlave, axilReadResp); end if; -- Reset From edcfe72e19e99b4b1f2362051a79b85952f5c99b Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 12 Jun 2020 13:44:04 -0700 Subject: [PATCH 35/40] Update JesdTxReg.vhd ### Description - Connecting axilWriteResp to axiSlaveWriteResponse() - Connecting axilReadResp to axiSlaveReadResponse() --- protocols/jesd204b/rtl/JesdTxReg.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/protocols/jesd204b/rtl/JesdTxReg.vhd b/protocols/jesd204b/rtl/JesdTxReg.vhd index e02953f631..7580c75c76 100644 --- a/protocols/jesd204b/rtl/JesdTxReg.vhd +++ b/protocols/jesd204b/rtl/JesdTxReg.vhd @@ -259,7 +259,7 @@ begin when others => axilWriteResp := AXI_RESP_DECERR_C; end case; - axiSlaveWriteResponse(v.axilWriteSlave); + axiSlaveWriteResponse(v.axilWriteSlave, axilWriteResp); end if; if (axilStatus.readEnable = '1') then @@ -321,7 +321,7 @@ begin when others => axilReadResp := AXI_RESP_DECERR_C; end case; - axiSlaveReadResponse(v.axilReadSlave); + axiSlaveReadResponse(v.axilReadSlave, axilReadResp); end if; -- Reset From 23de68ad1fb159d5233ffbcd884d6ebdc510e0e8 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 12 Jun 2020 14:54:32 -0700 Subject: [PATCH 36/40] Delete SaciSlave2.vhd ### Description - Removing SaciSlave2 because identical to SaciSlave --- protocols/saci/sim/SaciSlave2.vhd | 166 ------------------------------ 1 file changed, 166 deletions(-) delete mode 100644 protocols/saci/sim/SaciSlave2.vhd diff --git a/protocols/saci/sim/SaciSlave2.vhd b/protocols/saci/sim/SaciSlave2.vhd deleted file mode 100644 index 7f1171b532..0000000000 --- a/protocols/saci/sim/SaciSlave2.vhd +++ /dev/null @@ -1,166 +0,0 @@ -------------------------------------------------------------------------------- --- Title : SACI Protocol: https://confluence.slac.stanford.edu/x/YYcRDQ -------------------------------------------------------------------------------- --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: Slave module for SACI interface. -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library IEEE; -use IEEE.std_logic_1164.all; -use ieee.numeric_std.all; - -library surf; -use surf.StdRtlPkg.all; - -entity SaciSlave2 is - - generic ( - TPD_G : time := 1 ns); - - port ( - rstL : in sl; -- ASIC global reset - - -- Serial Interface - saciClk : in sl; - saciSelL : in sl; -- chipSelect - saciCmd : in sl; - saciRsp : out sl; - - -- Silly reset hack to get saciSelL | rst onto dedicated reset bar - rstOutL : out sl; - rstInL : in sl; - - -- Detector (Parallel) Interface - exec : out sl; - ack : in sl; - readL : out sl; - cmd : out slv(6 downto 0); - addr : out slv(11 downto 0); - wrData : out slv(31 downto 0); - rdData : in slv(31 downto 0)); - -end entity SaciSlave2; - -architecture rtl of SaciSlave2 is - - type StateType is (WAIT_START_S, SHIFT_IN_S); - - type RegType is record - shiftReg : slv(54 downto 0); - state : StateType; - exec : sl; - readL : sl; - end record RegType; - - signal r, rin : RegType; - signal saciCmdFall : sl; - - procedure shiftInLeft ( - i : in sl; - v : inout slv) is - begin - v := v(v'high-1 downto v'low) & i; - end procedure shiftInLeft; - -begin - - -- Chip select also functions as async reset - rstOutL <= rstL and not saciSelL; - - - -- Clock in serial input on falling edge - fall : process (saciClk, rstInL) is - begin - if (rstInL = '0') then - saciCmdFall <= '0' after TPD_G; - elsif (falling_edge(saciClk)) then - saciCmdFall <= saciCmd after TPD_G; - end if; - end process fall; - - - seq : process (saciClk, rstInL) is - begin - if (rstInL = '0') then - r.shiftReg <= (others => '0') after TPD_G; - r.state <= WAIT_START_S after TPD_G; - r.exec <= '0' after TPD_G; - r.readL <= '0' after TPD_G; - elsif (rising_edge(saciClk)) then - r <= rin after TPD_G; - end if; - end process seq; - - comb : process (r, saciCmdFall, ack, rdData, saciSelL) is - variable v : RegType; - begin - v := r; - - shiftInLeft(saciCmdFall, v.shiftReg); - - -- Main state machine - case (r.state) is - - when WAIT_START_S => - - -- Shift data out and look for next start bit - if (r.shiftReg(0) = '1') then - v.state := SHIFT_IN_S; - end if; - - when SHIFT_IN_S => - -- Wait for start bit to shift all the way in then assert exec and readL - if (r.shiftReg(52) = '1') then - v.exec := '1'; - v.readL := r.shiftReg(51); - end if; - - if (r.exec = '1') then - v.shiftReg := r.shiftReg; -- Pause shifting when exec high - v.readL := r.readL; - end if; - - if (ack = '1') then - v.exec := '0'; - v.state := WAIT_START_S; - if (r.shiftReg(52) = '1') then - v.shiftReg(32 downto 1) := (others => '0'); -- write - else - v.shiftReg(32 downto 1) := rdData; -- read - end if; - end if; - - - when others => - v.shiftReg := (others => '0'); - v.state := WAIT_START_S; - v.exec := '0'; - v.readL := '0'; - - end case; - - - rin <= v; - - -- Assign outputs from registers - exec <= r.exec; - readL <= r.readL; - saciRsp <= r.shiftReg(54); -- 52 = start, 51 = r/w at time of exec - cmd <= r.shiftReg(51 downto 45); - addr <= r.shiftReg(44 downto 33); - wrData <= r.shiftReg(32 downto 1); - - end process comb; - - -end architecture rtl; - From d8b9e48d21e41ee1632247afe95fe6e0fe445b46 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Sun, 14 Jun 2020 13:17:30 -0700 Subject: [PATCH 37/40] Update RssiAxiLiteRegItf.vhd ### Description - Connecting axilWriteResp to axiSlaveWriteResponse() - Connecting axilReadResp to axiSlaveReadResponse() --- protocols/rssi/v1/rtl/RssiAxiLiteRegItf.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/protocols/rssi/v1/rtl/RssiAxiLiteRegItf.vhd b/protocols/rssi/v1/rtl/RssiAxiLiteRegItf.vhd index fa6286e624..6a66fbc5b4 100644 --- a/protocols/rssi/v1/rtl/RssiAxiLiteRegItf.vhd +++ b/protocols/rssi/v1/rtl/RssiAxiLiteRegItf.vhd @@ -247,7 +247,7 @@ begin when others => axilWriteResp := AXI_RESP_DECERR_C; end case; - axiSlaveWriteResponse(v.axilWriteSlave); + axiSlaveWriteResponse(v.axilWriteSlave, axilWriteResp); end if; if (axilStatus.readEnable = '1') then @@ -314,7 +314,7 @@ begin when others => axilReadResp := AXI_RESP_DECERR_C; end case; - axiSlaveReadResponse(v.axilReadSlave); + axiSlaveReadResponse(v.axilReadSlave, axilReadResp); end if; -- Map to chksumEn From 49a5a2b9f6d526260d05ced88700e4bb8ebf2801 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 15 Jun 2020 08:29:29 -0700 Subject: [PATCH 38/40] connecting the AXI-Lite responses --- axi/axi-stream/rtl/AxiStreamScatterGather.vhd | 21 +++++++++------- axi/dma/rtl/v1/AxiStreamDma.vhd | 21 ++++++++-------- protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd | 24 ++++++++++--------- protocols/ssi/rtl/SsiPrbsTx.vhd | 4 ++-- 4 files changed, 39 insertions(+), 31 deletions(-) diff --git a/axi/axi-stream/rtl/AxiStreamScatterGather.vhd b/axi/axi-stream/rtl/AxiStreamScatterGather.vhd index 03b47c1974..438fc3fd7e 100644 --- a/axi/axi-stream/rtl/AxiStreamScatterGather.vhd +++ b/axi/axi-stream/rtl/AxiStreamScatterGather.vhd @@ -181,10 +181,12 @@ begin comb : process (axiRst, axilReadMaster, axilWriteMaster, r, sSsiMaster, txFifoRdData, txFifoValid, txRamRdData) is - variable v : RegType; - variable mDataLow : integer; - variable mDataHigh : integer; - variable axilStatus : AxiLiteStatusType; + variable v : RegType; + variable mDataLow : integer; + variable mDataHigh : integer; + variable axilWriteResp : slv(1 downto 0); + variable axilReadResp : slv(1 downto 0); + variable axilStatus : AxiLiteStatusType; begin v := r; @@ -305,8 +307,11 @@ begin ---------------------------------------------------------------------------------------------- axiSlaveWaitTxn(axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave, axilStatus); + axilWriteResp := ite(axilWriteMaster.awaddr(1 downto 0) = "00", AXI_RESP_OK_C, AXI_RESP_DECERR_C); + axilReadResp := ite(axilReadMaster.araddr(1 downto 0) = "00", AXI_RESP_OK_C, AXI_RESP_DECERR_C); + if (axilStatus.writeEnable = '1') then - axiSlaveWriteResponse(v.axilWriteSlave); + axiSlaveWriteResponse(v.axilWriteSlave, AXI_RESP_DECERR_C); end if; if (axilStatus.readEnable = '1') then @@ -337,10 +342,10 @@ begin v.axilReadSlave.rdata(r.badWords'range) := r.badWords; when X"28" => v.axilReadSlave.rdata(r.badWordCount'range) := r.badWordCount; - - when others => null; + when others => + axilReadResp := AXI_RESP_DECERR_C; end case; - axiSlaveReadResponse(v.axilReadSlave); + axiSlaveReadResponse(v.axilReadSlave, axilReadResp); end if; ---------------------------------------------------------------------------------------------- diff --git a/axi/dma/rtl/v1/AxiStreamDma.vhd b/axi/dma/rtl/v1/AxiStreamDma.vhd index 0f64a2c5bb..af885040f9 100644 --- a/axi/dma/rtl/v1/AxiStreamDma.vhd +++ b/axi/dma/rtl/v1/AxiStreamDma.vhd @@ -297,8 +297,10 @@ begin -- Local Register Space ------------------------------------- process (axiRst, ib, intReadMasters, intWriteMasters, ob, popFifoValid, r) is - variable v : RegType; - variable axiStatus : AxiLiteStatusType; + variable v : RegType; + variable axiWriteResp : slv(1 downto 0); + variable axiReadResp : slv(1 downto 0); + variable axiStatus : AxiLiteStatusType; begin v := r; @@ -306,6 +308,9 @@ begin axiSlaveWaitTxn(intWriteMasters(0), intReadMasters(0), v.axiWriteSlave, v.axiReadSlave, axiStatus); + axiWriteResp := ite(intWriteMasters(0).awaddr(1 downto 0) = "00", AXI_RESP_OK_C, AXI_RESP_DECERR_C); + axiReadResp := ite(intReadMasters(0).araddr(1 downto 0) = "00", AXI_RESP_OK_C, AXI_RESP_DECERR_C); + -- Write if (axiStatus.writeEnable = '1') then @@ -328,10 +333,9 @@ begin when x"20" => v.swCache := intWriteMasters(0).wdata(3 downto 0); when others => - null; + axiWriteResp := AXI_RESP_DECERR_C; end case; - - axiSlaveWriteResponse(v.axiWriteSlave); + axiSlaveWriteResponse(v.axiWriteSlave, axiWriteResp); end if; -- Read @@ -361,12 +365,9 @@ begin when x"20" => v.axiReadSlave.rdata(3 downto 0) := r.swCache; when others => - null; + axiReadResp := AXI_RESP_DECERR_C; end case; - - -- Send Axi Response - axiSlaveReadResponse(v.axiReadSlave); - + axiSlaveReadResponse(v.axiReadSlave, axiReadResp); end if; v.interrupt := (ib.intPending or ob.intPending) and r.intEnable; diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd index 62c55a22b6..0a5e53a627 100644 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd @@ -618,13 +618,18 @@ begin -- Async process (axilRst, axilReadMaster, axilWriteMaster, r, rxStatusSync, txStatusSync) is - variable v : RegType; - variable axiStatus : AxiLiteStatusType; + variable v : RegType; + variable axiStatus : AxiLiteStatusType; + variable axilWriteResp : slv(1 downto 0); + variable axilReadResp : slv(1 downto 0); begin v := r; axiSlaveWaitTxn(axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave, axiStatus); + axilWriteResp := ite(axilWriteMaster.awaddr(1 downto 0) = "00", AXI_RESP_OK_C, AXI_RESP_DECERR_C); + axilReadResp := ite(axilReadMaster.araddr(1 downto 0) = "00", AXI_RESP_OK_C, AXI_RESP_DECERR_C); + -- Write if (axiStatus.writeEnable = '1') then @@ -647,11 +652,10 @@ begin v.autoStatus := axilWriteMaster.wdata(0); when X"18" => v.flowCntlDis := ite(WRITE_EN_G, axilWriteMaster.wdata(0), '0'); - when others => null; + when others => + axilWriteResp := AXI_RESP_DECERR_C; end case; - - -- Send Axi response - axiSlaveWriteResponse(v.axilWriteSlave); + axiSlaveWriteResponse(v.axilWriteSlave, axilWriteResp); end if; -- Read @@ -734,12 +738,10 @@ begin v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := rxStatusSync.rxOpCodeCount; when X"80" => v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := rxStatusSync.remLinkReadyCnt; - - when others => null; + when others => + axilReadResp := AXI_RESP_DECERR_C; end case; - - -- Send Axi Response - axiSlaveReadResponse(v.axilReadSlave); + axiSlaveReadResponse(v.axilReadSlave, axilReadResp); end if; -- Reset diff --git a/protocols/ssi/rtl/SsiPrbsTx.vhd b/protocols/ssi/rtl/SsiPrbsTx.vhd index 822c3db463..0986775b89 100644 --- a/protocols/ssi/rtl/SsiPrbsTx.vhd +++ b/protocols/ssi/rtl/SsiPrbsTx.vhd @@ -182,7 +182,7 @@ begin when others => axilWriteResp := AXI_RESP_DECERR_C; end case; - axiSlaveWriteResponse(v.axilWriteSlave); + axiSlaveWriteResponse(v.axilWriteSlave, axilWriteResp); end if; if (axilStatus.readEnable = '1') then @@ -220,7 +220,7 @@ begin when others => axilReadResp := AXI_RESP_DECERR_C; end case; - axiSlaveReadResponse(v.axilReadSlave); + axiSlaveReadResponse(v.axilReadSlave, axilReadResp); end if; -- Check for delay between AXI triggers From 85378e9fb1170dbb01bef3f1745122bb555f8d83 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 15 Jun 2020 10:23:50 -0700 Subject: [PATCH 39/40] renaming modules --- .../rtl/{SelectioDeser.vhd => SelectioDeser7Series.vhd} | 8 ++++---- ...SelectioDeserLane.vhd => SelectioDeserLane7Series.vhd} | 8 ++++---- ...ectioDeserLane.vhd => SelectioDeserLaneUltraScale.vhd} | 8 ++++---- .../{SelectioDeser.vhd => SelectioDeserUltraScale.vhd} | 8 ++++---- 4 files changed, 16 insertions(+), 16 deletions(-) rename xilinx/7Series/general/rtl/{SelectioDeser.vhd => SelectioDeser7Series.vhd} (96%) rename xilinx/7Series/general/rtl/{SelectioDeserLane.vhd => SelectioDeserLane7Series.vhd} (95%) rename xilinx/UltraScale/general/rtl/{SelectioDeserLane.vhd => SelectioDeserLaneUltraScale.vhd} (94%) rename xilinx/UltraScale/general/rtl/{SelectioDeser.vhd => SelectioDeserUltraScale.vhd} (97%) diff --git a/xilinx/7Series/general/rtl/SelectioDeser.vhd b/xilinx/7Series/general/rtl/SelectioDeser7Series.vhd similarity index 96% rename from xilinx/7Series/general/rtl/SelectioDeser.vhd rename to xilinx/7Series/general/rtl/SelectioDeser7Series.vhd index 0a4d001d24..55dbb1c9a6 100644 --- a/xilinx/7Series/general/rtl/SelectioDeser.vhd +++ b/xilinx/7Series/general/rtl/SelectioDeser7Series.vhd @@ -24,7 +24,7 @@ use surf.AxiLitePkg.all; library unisim; use unisim.vcomponents.all; -entity SelectioDeser is +entity SelectioDeser7Series is generic ( TPD_G : time := 1 ns; SIMULATION_G : boolean := false; @@ -58,9 +58,9 @@ entity SelectioDeser is axilReadSlave : out AxiLiteReadSlaveType; axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; axilWriteSlave : out AxiLiteWriteSlaveType); -end SelectioDeser; +end SelectioDeser7Series; -architecture mapping of SelectioDeser is +architecture mapping of SelectioDeser7Series is signal clkx4 : sl := '0'; signal clkx1 : sl := '0'; @@ -107,7 +107,7 @@ begin GEN_VEC : for i in NUM_LANE_G-1 downto 0 generate - U_Lane : entity surf.SelectioDeserLane + U_Lane : entity surf.SelectioDeserLane7Series generic map ( TPD_G => TPD_G) port map ( diff --git a/xilinx/7Series/general/rtl/SelectioDeserLane.vhd b/xilinx/7Series/general/rtl/SelectioDeserLane7Series.vhd similarity index 95% rename from xilinx/7Series/general/rtl/SelectioDeserLane.vhd rename to xilinx/7Series/general/rtl/SelectioDeserLane7Series.vhd index 2d172483b4..9cba499076 100644 --- a/xilinx/7Series/general/rtl/SelectioDeserLane.vhd +++ b/xilinx/7Series/general/rtl/SelectioDeserLane7Series.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: Wrapper for SelectioDeserLane +-- Description: Wrapper for SelectioDeser ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the @@ -23,7 +23,7 @@ use surf.StdRtlPkg.all; library unisim; use unisim.vcomponents.all; -entity SelectioDeserLane is +entity SelectioDeserLane7Series is generic ( TPD_G : time := 1 ns; IODELAY_GROUP_G : string := "DESER_GROUP"; @@ -41,9 +41,9 @@ entity SelectioDeserLane is dlyCfg : in slv(8 downto 0); -- Output dataOut : out slv(7 downto 0)); -end SelectioDeserLane; +end SelectioDeserLane7Series; -architecture mapping of SelectioDeserLane is +architecture mapping of SelectioDeserLane7Series is signal rx : sl; signal rxDly : sl; diff --git a/xilinx/UltraScale/general/rtl/SelectioDeserLane.vhd b/xilinx/UltraScale/general/rtl/SelectioDeserLaneUltraScale.vhd similarity index 94% rename from xilinx/UltraScale/general/rtl/SelectioDeserLane.vhd rename to xilinx/UltraScale/general/rtl/SelectioDeserLaneUltraScale.vhd index b39277bbee..10c4976413 100644 --- a/xilinx/UltraScale/general/rtl/SelectioDeserLane.vhd +++ b/xilinx/UltraScale/general/rtl/SelectioDeserLaneUltraScale.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: Wrapper for SelectioDeserLane +-- Description: Wrapper for SelectioDeser ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the @@ -23,7 +23,7 @@ use surf.StdRtlPkg.all; library unisim; use unisim.vcomponents.all; -entity SelectioDeserLane is +entity SelectioDeserLaneUltraScale is generic ( TPD_G : time := 1 ns); port ( @@ -39,9 +39,9 @@ entity SelectioDeserLane is dlyCfg : in slv(8 downto 0); -- Output dataOut : out slv(7 downto 0)); -end SelectioDeserLane; +end SelectioDeserLaneUltraScale; -architecture mapping of SelectioDeserLane is +architecture mapping of SelectioDeserLaneUltraScale is signal rx : sl; signal rxDly : sl; diff --git a/xilinx/UltraScale/general/rtl/SelectioDeser.vhd b/xilinx/UltraScale/general/rtl/SelectioDeserUltraScale.vhd similarity index 97% rename from xilinx/UltraScale/general/rtl/SelectioDeser.vhd rename to xilinx/UltraScale/general/rtl/SelectioDeserUltraScale.vhd index 20885bacfa..f26dde2395 100644 --- a/xilinx/UltraScale/general/rtl/SelectioDeser.vhd +++ b/xilinx/UltraScale/general/rtl/SelectioDeserUltraScale.vhd @@ -24,7 +24,7 @@ use surf.AxiLitePkg.all; library unisim; use unisim.vcomponents.all; -entity SelectioDeser is +entity SelectioDeserUltraScale is generic ( TPD_G : time := 1 ns; SIMULATION_G : boolean := false; @@ -54,9 +54,9 @@ entity SelectioDeser is axilReadSlave : out AxiLiteReadSlaveType; axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; axilWriteSlave : out AxiLiteWriteSlaveType); -end SelectioDeser; +end SelectioDeserUltraScale; -architecture mapping of SelectioDeser is +architecture mapping of SelectioDeserUltraScale is signal drpRdy : sl; signal drpEn : sl; @@ -192,7 +192,7 @@ begin GEN_VEC : for i in NUM_LANE_G-1 downto 0 generate - U_Lane : entity surf.SelectioDeserLane + U_Lane : entity surf.SelectioDeserLaneUltraScale generic map ( TPD_G => TPD_G) port map ( From 2a4cb55f7931cf27d2ae9a82b48dd91ed8c92cab Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 15 Jun 2020 10:24:55 -0700 Subject: [PATCH 40/40] removing white space --- protocols/ssp/rtl/SspLowSpeedDecoderReg.vhd | 4 ++-- xilinx/7Series/general/rtl/SelectioDeser7Series.vhd | 2 +- xilinx/7Series/general/rtl/SelectioDeserLane7Series.vhd | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/protocols/ssp/rtl/SspLowSpeedDecoderReg.vhd b/protocols/ssp/rtl/SspLowSpeedDecoderReg.vhd index b2e9fbabc7..78ece5f304 100644 --- a/protocols/ssp/rtl/SspLowSpeedDecoderReg.vhd +++ b/protocols/ssp/rtl/SspLowSpeedDecoderReg.vhd @@ -193,9 +193,9 @@ begin port map ( -- Input Status bit Signals (wrClk domain) statusIn => statusIn, - -- Output Status bit Signals (rdClk domain) + -- Output Status bit Signals (rdClk domain) statusOut => statusOut, - -- Status Bit Counters Signals (rdClk domain) + -- Status Bit Counters Signals (rdClk domain) cntRstIn => r.cntRst, rollOverEnIn => r.rollOverEn, cntOut => statusCnt, diff --git a/xilinx/7Series/general/rtl/SelectioDeser7Series.vhd b/xilinx/7Series/general/rtl/SelectioDeser7Series.vhd index 55dbb1c9a6..b015d8f5a3 100644 --- a/xilinx/7Series/general/rtl/SelectioDeser7Series.vhd +++ b/xilinx/7Series/general/rtl/SelectioDeser7Series.vhd @@ -30,7 +30,7 @@ entity SelectioDeser7Series is SIMULATION_G : boolean := false; NUM_LANE_G : positive := 1; IODELAY_GROUP_G : string := "DESER_GROUP"; - REF_FREQ_G : real := 300.0; -- IDELAYCTRL's REFCLK (in units of Hz) + REF_FREQ_G : real := 300.0; -- IDELAYCTRL's REFCLK (in units of Hz) INPUT_BUFG_G : boolean := false; FB_BUFG_G : boolean := false; CLKIN_PERIOD_G : real := 10.0; -- 100 MHz diff --git a/xilinx/7Series/general/rtl/SelectioDeserLane7Series.vhd b/xilinx/7Series/general/rtl/SelectioDeserLane7Series.vhd index 9cba499076..c360c6f59f 100644 --- a/xilinx/7Series/general/rtl/SelectioDeserLane7Series.vhd +++ b/xilinx/7Series/general/rtl/SelectioDeserLane7Series.vhd @@ -27,7 +27,7 @@ entity SelectioDeserLane7Series is generic ( TPD_G : time := 1 ns; IODELAY_GROUP_G : string := "DESER_GROUP"; - REF_FREQ_G : real := 300.0); -- IDELAYCTRL's REFCLK (in units of Hz) + REF_FREQ_G : real := 300.0); -- IDELAYCTRL's REFCLK (in units of Hz) port ( -- SELECTIO Ports rxP : in sl;