diff --git a/axi/axi-lite/rtl/AxiLitePkg.vhd b/axi/axi-lite/rtl/AxiLitePkg.vhd index d0c8650889..8021a11e25 100644 --- a/axi/axi-lite/rtl/AxiLitePkg.vhd +++ b/axi/axi-lite/rtl/AxiLitePkg.vhd @@ -853,18 +853,45 @@ package body AxiLitePkg is -- Generate evenly distributed address map function genAxiLiteConfig (num : positive; base : slv(31 downto 0); - baseBot : integer range 0 to 32; - addrBits : integer range 0 to 32) + baseBot : integer range 1 to 32; + addrBits : integer range 0 to 31) return AxiLiteCrossbarMasterConfigArray is variable retConf : AxiLiteCrossbarMasterConfigArray(num-1 downto 0); variable addr : slv(31 downto 0); begin - + + ------------------------------------------------------------------------------------------- + -- Note: These asserts only work in synthesis (not simulation) + -- https://forums.xilinx.com/t5/Synthesis/VHDL-assert-statement-within-function/td-p/413463 + ------------------------------------------------------------------------------------------- + + -- Compare the baseBot to addrBits + assert (baseBot > addrBits) + report "AxiLitePkg.genAxiLiteConfig(): (baseBot > addrBits) condition not meet" + & lf & "num = " & integer'image(num) + & lf & "base = 0x" & hstr(base) + & lf & "baseBot = " & integer'image(baseBot) + & lf & "addrBits = " & integer'image(addrBits) + severity error; + + -- Check that there is enough bits for the number of buses + assert (2**(baseBot-addrBits) >= num) + report "AxiLitePkg.genAxiLiteConfig(): (2**(baseBot-addrBits) >= num) condition not meet" + & lf & "num = " & integer'image(num) + & lf & "base = 0x" & hstr(base) + & lf & "baseBot = " & integer'image(baseBot) + & lf & "addrBits = " & integer'image(addrBits) + severity error; + + ------------------------------------------------------------------------------------------- -- Init + ------------------------------------------------------------------------------------------- addr := base; addr(baseBot-1 downto 0) := (others => '0'); + ------------------------------------------------------------------------------------------- -- Generate records + ------------------------------------------------------------------------------------------- for i in 0 to num-1 loop addr(baseBot-1 downto addrBits) := toSlv(i, baseBot-addrBits); retConf(i).baseAddr := addr; diff --git a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd index fd943ae733..00c2f33ab9 100644 --- a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd +++ b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd @@ -2,7 +2,7 @@ -- File : GigEthGthUltraScale.vhd -- Company : SLAC National Accelerator Laboratory -- Created : 2016-02-07 --- Last update: 2018-04-05 +-- Last update: 2018-07-24 ------------------------------------------------------------------------------- -- Description: 1000BASE-X Ethernet for Gth7 ------------------------------------------------------------------------------- @@ -64,6 +64,53 @@ end GigEthGthUltraScale; architecture mapping of GigEthGthUltraScale is + component GigEthGthUltraScaleCore + port ( + --------------------- + -- Transceiver Interface + --------------------- + gtrefclk : in std_logic; -- Very high quality clock for GT transceiver. + txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD. + txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD. + rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA. + rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA. + resetdone : out std_logic; -- The GT transceiver has completed its reset cycle + cplllock : out std_logic; -- The GT transceiver has completed its reset cycle + mmcm_reset : out std_logic; + txoutclk : out std_logic; + rxoutclk : out std_logic; + userclk : in std_logic; + userclk2 : in std_logic; + rxuserclk : in std_logic; + rxuserclk2 : in std_logic; + pma_reset : in std_logic; -- transceiver PMA reset signal + mmcm_locked : in std_logic; -- MMCM Locked + independent_clock_bufg : in std_logic; + ----------------- + -- GMII Interface + ----------------- + gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC. + gmii_tx_en : in std_logic; -- Transmit control signal from client MAC. + gmii_tx_er : in std_logic; -- Transmit control signal from client MAC. + gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC. + gmii_rx_dv : out std_logic; -- Received control signal to client MAC. + gmii_rx_er : out std_logic; -- Received control signal to client MAC. + gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII. + -------------------------------------------- + -- Management: Alternative to MDIO Interface + -------------------------------------------- + configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface. + an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed + an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV) + an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0 + --------------- + -- General IO's + --------------- + status_vector : out std_logic_vector(15 downto 0); -- Core status. + reset : in std_logic; -- Asynchronous reset for entire core. + signal_detect : in std_logic); -- Input from PMD to indicate presence of optical input. + end component; + signal config : GigEthConfigType; signal status : GigEthStatusType; @@ -157,7 +204,7 @@ begin ------------------ -- 1000BASE-X core ------------------ - U_GigEthGthUltraScaleCore : entity work.GigEthGthUltraScaleCore + U_GigEthGthUltraScaleCore : GigEthGthUltraScaleCore port map ( -- Clocks and Resets gtrefclk => sysClk125, -- Used as CPLL clock reference diff --git a/protocols/packetizer/rtl/AxiStreamPacketizer2.vhd b/protocols/packetizer/rtl/AxiStreamPacketizer2.vhd index a85584ffd3..35f8f6625d 100644 --- a/protocols/packetizer/rtl/AxiStreamPacketizer2.vhd +++ b/protocols/packetizer/rtl/AxiStreamPacketizer2.vhd @@ -2,7 +2,7 @@ -- File : AxiStreamPacketizer2.vhd -- Company : SLAC National Accelerator Laboratory -- Created : 2017-05-02 --- Last update: 2018-06-13 +-- Last update: 2018-08-01 ------------------------------------------------------------------------------- -- Description: Formats an AXI-Stream for a transport link. -- Sideband fields are placed into the data stream in a header. @@ -78,6 +78,7 @@ architecture rtl of AxiStreamPacketizer2 is crcDataWidth : slv(2 downto 0); crcInit : slv(31 downto 0); crcRem : slv(31 downto 0); + crcIn : slv(63 downto 0); crcReset : sl; tailCrcReady : sl; inputAxisSlave : AxiStreamSlaveType; @@ -99,6 +100,7 @@ architecture rtl of AxiStreamPacketizer2 is crcDataWidth => (others => '1'), crcInit => (others => '1'), crcRem => (others => '1'), + crcIn => (others => '1'), crcReset => '0', tailCrcReady => toSl(not CRC_HEAD_TAIL_C), inputAxisSlave => AXI_STREAM_SLAVE_INIT_C, @@ -187,7 +189,6 @@ begin doutb(48 downto 17) => ramCrcRem); ramAddrr <= inputAxisMaster.tDest(ADDR_WIDTH_C-1 downto 0) when (TDEST_BITS_G > 0) else (others => '0'); - crcIn <= endianSwap(rin.outputAxisMaster.tData(63 downto 0)); GEN_CRC : if (CRC_EN_C) generate @@ -412,8 +413,21 @@ begin v.outputAxisMaster.tKeep := x"00FF"; v.outputAxisMaster.tStrb := v.outputAxisMaster.tKeep; + if (r.state /= TAIL_S) then + v.crcIn := v.outputAxisMaster.tData(63 downto 0); + else + v.crcIn := + makePacketizer2TailTdata( + CRC_MODE_C => CRC_MODE_G, + eof => r.eof, + tuser => r.tUserLast, + bytes => r.lastByteCount, + crc => crcOut); + end if; + -- Combinatorial outputs before the reset inputAxisSlave <= v.inputAxisSlave; + crcIn <= endianSwap(v.crcIn); -- Reset if (axisRst = '1') then diff --git a/protocols/packetizer/rtl/AxiStreamPacketizer2Pkg.vhd b/protocols/packetizer/rtl/AxiStreamPacketizer2Pkg.vhd index 6d0380c9ad..8a58a2a60d 100644 --- a/protocols/packetizer/rtl/AxiStreamPacketizer2Pkg.vhd +++ b/protocols/packetizer/rtl/AxiStreamPacketizer2Pkg.vhd @@ -40,7 +40,7 @@ package AxiStreamPacketizer2Pkg is subtype PACKETIZER2_HDR_TID_FIELD_C is natural range 31 downto 24; subtype PACKETIZER2_HDR_SEQ_FIELD_C is natural range 47 downto 32; -- BIT62:BIT48 unused - constant PACKETIZER2_HDR_SOF_BIT_C : integer := 63; + constant PACKETIZER2_HDR_SOF_BIT_C : integer := 63; --------------------------------------------------------------- --------------------------------------------------------------- @@ -92,6 +92,14 @@ package AxiStreamPacketizer2Pkg is seq : slv(15 downto 0) := (others => '0')) return AxiStreamMasterType; + function makePacketizer2TailTdata ( + CRC_MODE_C : string; + eof : sl := '1'; + tuser : slv(7 downto 0) := (others => '0'); + bytes : slv(3 downto 0) := "1000"; -- Default 8 bytes + crc : slv(31 downto 0) := (others => '0')) + return slv; + function makePacketizer2Tail ( CRC_MODE_C : string; valid : sl := '0'; @@ -145,6 +153,24 @@ package body AxiStreamPacketizer2Pkg is return ret; end function makePacketizer2Header; + function makePacketizer2TailTdata ( + CRC_MODE_C : string; + eof : sl := '1'; + tuser : slv(7 downto 0) := (others => '0'); + bytes : slv(3 downto 0) := "1000"; + crc : slv(31 downto 0) := (others => '0')) + return slv + is + variable ret : slv(63 downto 0); + begin + ret := (others => '0'); + ret(PACKETIZER2_TAIL_EOF_BIT_C) := eof; + ret(PACKETIZER2_TAIL_TUSER_FIELD_C) := tuser; + ret(PACKETIZER2_TAIL_BYTES_FIELD_C) := bytes; + ret(PACKETIZER2_TAIL_CRC_FIELD_C) := ite((CRC_MODE_C /= "NONE"), crc, x"00000000"); + return ret; + end function makePacketizer2TailTdata; + function makePacketizer2Tail ( CRC_MODE_C : string; valid : sl := '0'; @@ -156,13 +182,16 @@ package body AxiStreamPacketizer2Pkg is is variable ret : AxiStreamMasterType; begin - ret := axiStreamMasterInit(PACKETIZER2_AXIS_CFG_C); - ret.tValid := valid; - ret.tData(PACKETIZER2_TAIL_EOF_BIT_C) := eof; - ret.tData(PACKETIZER2_TAIL_TUSER_FIELD_C) := tuser; - ret.tData(PACKETIZER2_TAIL_BYTES_FIELD_C) := bytes; - ret.tData(PACKETIZER2_TAIL_CRC_FIELD_C) := ite((CRC_MODE_C /= "NONE"), crc, x"00000000"); - ret.tLast := '1'; + ret := axiStreamMasterInit(PACKETIZER2_AXIS_CFG_C); + ret.tValid := valid; + ret.tLast := '1'; + ret.tData(63 downto 0) := + makePacketizer2TailTdata( + CRC_MODE_C => CRC_MODE_C, + eof => eof, + tuser => tuser, + bytes => bytes, + crc => crc); return ret; end function makePacketizer2Tail; diff --git a/protocols/rssi/rtl/RssiCore.vhd b/protocols/rssi/rtl/RssiCore.vhd index e16ea6d57e..1f38332ce4 100644 --- a/protocols/rssi/rtl/RssiCore.vhd +++ b/protocols/rssi/rtl/RssiCore.vhd @@ -64,6 +64,8 @@ entity RssiCore is TSP_AXIS_CONFIG_G : AxiStreamConfigType := ssiAxiStreamConfig(16, TKEEP_NORMAL_C); -- Generic RSSI parameters + BYP_TX_BUFFER_G : boolean := false; + BYP_RX_BUFFER_G : boolean := false; -- Version and connection ID INIT_SEQ_N_G : natural := 16#80#; @@ -121,14 +123,11 @@ architecture rtl of RssiCore is constant BUFFER_ADDR_WIDTH_C : positive := (SEGMENT_ADDR_SIZE_G+WINDOW_ADDR_SIZE_G); - constant RX_FIFO_ADDR_WIDTH_C : positive := BUFFER_ADDR_WIDTH_C+1; -- 2 x total MAX buffering - constant RX_FIFO_PAUSE_THRESH_C : positive := (2**RX_FIFO_ADDR_WIDTH_C) - (2**(SEGMENT_ADDR_SIZE_G+1)); -- pause threshold = FIFO_FULL - (2 x segment buffers) - constant RX_FIFO_BUSY_THRESH_C : positive := (2**(SEGMENT_ADDR_SIZE_G+1)); -- busy threshold = (2 x segment buffers) + constant FIFO_ADDR_WIDTH_C : positive := ite((SEGMENT_ADDR_SIZE_G < 7), 9, SEGMENT_ADDR_SIZE_G+2); -- min. 4 segment buffering + constant FIFO_PAUSE_THRESH_C : positive := (2**FIFO_ADDR_WIDTH_C) - (2**(SEGMENT_ADDR_SIZE_G+1)); -- pause threshold = FIFO_FULL - (2 x segment buffers) + constant FIFO_BUSY_THRESH_C : positive := (2**SEGMENT_ADDR_SIZE_G); -- busy threshold = (1 x segment buffers) - constant TX_FIFO_ADDR_WIDTH_C : positive := ite((SEGMENT_ADDR_SIZE_G < 7), 9, SEGMENT_ADDR_SIZE_G+2); -- min. 4 segment buffering - constant TX_FIFO_PAUSE_THRESH_C : positive := (2**TX_FIFO_ADDR_WIDTH_C) - (2**(SEGMENT_ADDR_SIZE_G+1)); -- pause threshold = FIFO_FULL - (2 x segment buffers) - - signal s_fifoWrCnt : slv(RX_FIFO_ADDR_WIDTH_C-1 downto 0); + signal s_fifoWrCnt : slv(FIFO_ADDR_WIDTH_C-1 downto 0); signal s_localBusy : sl; -- RSSI Parameters @@ -643,25 +642,25 @@ begin ----------------------------------------------- -- Tx buffer RAM - TxBuffer_INST : entity work.SimpleDualPortRam - generic map ( - TPD_G => TPD_G, - DATA_WIDTH_G => RSSI_WORD_WIDTH_C*8, - ADDR_WIDTH_G => BUFFER_ADDR_WIDTH_C - ) - port map ( - -- Port A - Write only - clka => clk_i, - wea => s_txWrBuffWe, - addra => s_txWrBuffAddr, - dina => s_txWrBuffData, - - -- Port B - Read only - clkb => clk_i, - rstb => rst_i, - addrb => s_txRdBuffAddr, - doutb => s_txRdBuffData); - + GEN_TX : if (BYP_TX_BUFFER_G = false) generate + U_Buffer : entity work.SimpleDualPortRam + generic map ( + TPD_G => TPD_G, + DATA_WIDTH_G => RSSI_WORD_WIDTH_C*8, + ADDR_WIDTH_G => BUFFER_ADDR_WIDTH_C) + port map ( + -- Port A - Write only + clka => clk_i, + wea => s_txWrBuffWe, + addra => s_txWrBuffAddr, + dina => s_txWrBuffData, + -- Port B - Read only + clkb => clk_i, + rstb => rst_i, + addrb => s_txRdBuffAddr, + doutb => s_txRdBuffData); + end generate; + tx_Chksum_INST : entity work.RssiChksum generic map ( TPD_G => TPD_G, @@ -722,25 +721,25 @@ begin appSsiSlave_i => s_mAppSsiSlave); -- Rx buffer RAM - RxBuffer_INST : entity work.SimpleDualPortRam - generic map ( - TPD_G => TPD_G, - DATA_WIDTH_G => RSSI_WORD_WIDTH_C*8, - ADDR_WIDTH_G => BUFFER_ADDR_WIDTH_C - ) - port map ( - -- Port A - Write only - clka => clk_i, - wea => s_rxWrBuffWe, - addra => s_rxWrBuffAddr, - dina => s_rxWrBuffData, - - -- Port B - Read only - clkb => clk_i, - rstb => rst_i, - addrb => s_rxRdBuffAddr, - doutb => s_rxRdBuffData); - + GEN_RX : if (BYP_RX_BUFFER_G = false) generate + U_Buffer : entity work.SimpleDualPortRam + generic map ( + TPD_G => TPD_G, + DATA_WIDTH_G => RSSI_WORD_WIDTH_C*8, + ADDR_WIDTH_G => BUFFER_ADDR_WIDTH_C) + port map ( + -- Port A - Write only + clka => clk_i, + wea => s_rxWrBuffWe, + addra => s_rxWrBuffAddr, + dina => s_rxWrBuffData, + -- Port B - Read only + clkb => clk_i, + rstb => rst_i, + addrb => s_rxRdBuffAddr, + doutb => s_rxRdBuffData); + end generate; + -- Acknowledge valid packet s_rxAck <= s_rxValidSeg and s_rxFlags.ack and s_connActive; @@ -793,9 +792,9 @@ begin PIPE_STAGES_G => 1, CASCADE_SIZE_G => 1, CASCADE_PAUSE_SEL_G => 0, - FIFO_ADDR_WIDTH_G => RX_FIFO_ADDR_WIDTH_C, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_C, FIFO_FIXED_THRESH_G => true, - FIFO_PAUSE_THRESH_G => RX_FIFO_PAUSE_THRESH_C, + FIFO_PAUSE_THRESH_G => FIFO_PAUSE_THRESH_C, SLAVE_AXI_CONFIG_G => RSSI_AXIS_CONFIG_C, MASTER_AXI_CONFIG_G => APP_AXIS_CONFIG_G) port map ( @@ -812,7 +811,7 @@ begin mAxisSlave => monSlaves(1), mTLastTUser => open); - s_localBusy <= '1' when((s_fifoWrCnt >= RX_FIFO_BUSY_THRESH_C) and (s_connActive = '1')) else '0'; + s_localBusy <= '1' when((s_fifoWrCnt >= FIFO_BUSY_THRESH_C) and (s_connActive = '1')) else '0'; mAppAxisMaster_o <= monMasters(1); monSlaves(1) <= mAppAxisSlave_i; @@ -829,9 +828,9 @@ begin PIPE_STAGES_G => 1, CASCADE_SIZE_G => 1, CASCADE_PAUSE_SEL_G => 0, - FIFO_ADDR_WIDTH_G => TX_FIFO_ADDR_WIDTH_C, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_C, FIFO_FIXED_THRESH_G => true, - FIFO_PAUSE_THRESH_G => TX_FIFO_PAUSE_THRESH_C, + FIFO_PAUSE_THRESH_G => FIFO_PAUSE_THRESH_C, SLAVE_AXI_CONFIG_G => RSSI_AXIS_CONFIG_C, MASTER_AXI_CONFIG_G => TSP_AXIS_CONFIG_G) port map ( diff --git a/protocols/rssi/rtl/RssiCoreWrapper.vhd b/protocols/rssi/rtl/RssiCoreWrapper.vhd index 23662d239d..9fe0d9def6 100644 --- a/protocols/rssi/rtl/RssiCoreWrapper.vhd +++ b/protocols/rssi/rtl/RssiCoreWrapper.vhd @@ -38,6 +38,8 @@ entity RssiCoreWrapper is APP_STREAMS_G : positive := 1; APP_STREAM_ROUTES_G : Slv8Array := (0 => "--------"); APP_ILEAVE_EN_G : boolean := false; + BYP_TX_BUFFER_G : boolean := false; + BYP_RX_BUFFER_G : boolean := false; -- AXIS Configurations APP_AXIS_CONFIG_G : AxiStreamConfigArray := (0 => ssiAxiStreamConfig(8, TKEEP_NORMAL_C)); TSP_AXIS_CONFIG_G : AxiStreamConfigType := ssiAxiStreamConfig(16, TKEEP_NORMAL_C); @@ -213,6 +215,8 @@ begin RETRANSMIT_ENABLE_G => RETRANSMIT_ENABLE_G, WINDOW_ADDR_SIZE_G => WINDOW_ADDR_SIZE_G, SEGMENT_ADDR_SIZE_G => SEGMENT_ADDR_SIZE_G, + BYP_TX_BUFFER_G => BYP_TX_BUFFER_G, + BYP_RX_BUFFER_G => BYP_RX_BUFFER_G, -- AXIS Configurations APP_AXIS_CONFIG_G => CONV_AXIS_CONFIG_C, TSP_AXIS_CONFIG_G => TSP_AXIS_CONFIG_G,