diff --git a/axi/axi-lite/rtl/AxiDualPortRam.vhd b/axi/axi-lite/rtl/AxiDualPortRam.vhd index 4874b936b8..3055c98229 100644 --- a/axi/axi-lite/rtl/AxiDualPortRam.vhd +++ b/axi/axi-lite/rtl/AxiDualPortRam.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiDualPortRam.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-12-17 --- Last update: 2018-03-09 ------------------------------------------------------------------------------- -- Description: A wrapper of StdLib DualPortRam that places an AxiLite -- interface on the read/write port. @@ -252,7 +250,11 @@ begin v.axiReadSlave.rdata := (others => '0'); -- Multiplex read data onto axi bus - decAddrInt := conv_integer(axiReadMaster.araddr(AXI_DEC_ADDR_RANGE_C)); + if (DATA_WIDTH_G <= 32) then + decAddrInt := 0; + else + decAddrInt := conv_integer(axiReadMaster.araddr(AXI_DEC_ADDR_RANGE_C)); + end if; v.axiReadSlave.rdata := axiDout((decAddrInt+1)*32-1 downto decAddrInt*32); -- Set axiAddr to read address by default @@ -266,7 +268,11 @@ begin if (axiStatus.writeEnable = '1') then if (AXI_WR_EN_G) then v.axiAddr := axiWriteMaster.awaddr(AXI_RAM_ADDR_RANGE_C); - decAddrInt := conv_integer(axiWriteMaster.awaddr(AXI_DEC_ADDR_RANGE_C)); + if (DATA_WIDTH_G <= 32) then + decAddrInt := conv_integer(axiWriteMaster.awaddr(AXI_RAM_ADDR_RANGE_C)); + else + decAddrInt := conv_integer(axiWriteMaster.awaddr(AXI_DEC_ADDR_RANGE_C)); + end if; v.axiWrStrobe((decAddrInt+1)*4-1 downto decAddrInt*4) := axiWriteMaster.wstrb; end if; diff --git a/axi/axi-lite/rtl/AxiLiteAsync.vhd b/axi/axi-lite/rtl/AxiLiteAsync.vhd index e4aef9fe1d..39fc027abf 100644 --- a/axi/axi-lite/rtl/AxiLiteAsync.vhd +++ b/axi/axi-lite/rtl/AxiLiteAsync.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLiteAsync.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-04-02 --- Last update: 2017-11-07 ------------------------------------------------------------------------------- -- Description: -- Asynchronous bridge for AXI Lite bus. Allows AXI transactions to cross diff --git a/axi/axi-lite/rtl/AxiLiteCrossbar.vhd b/axi/axi-lite/rtl/AxiLiteCrossbar.vhd index 9f486a43cf..452391dac6 100644 --- a/axi/axi-lite/rtl/AxiLiteCrossbar.vhd +++ b/axi/axi-lite/rtl/AxiLiteCrossbar.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLiteCrossbar.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-09-24 --- Last update: 2017-11-13 ------------------------------------------------------------------------------- -- Description: Wrapper around Xilinx generated Main AXI Crossbar for HPS Front End ------------------------------------------------------------------------------- diff --git a/axi/axi-lite/rtl/AxiLiteFifoPop.vhd b/axi/axi-lite/rtl/AxiLiteFifoPop.vhd index 6c64039ba3..37366dee1d 100644 --- a/axi/axi-lite/rtl/AxiLiteFifoPop.vhd +++ b/axi/axi-lite/rtl/AxiLiteFifoPop.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLiteFifoPop.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-04-02 --- Last update: 2016-04-26 ------------------------------------------------------------------------------- -- Description: -- Supports reading of general purpose FIFOs from the AxiLite bus. diff --git a/axi/axi-lite/rtl/AxiLiteFifoPush.vhd b/axi/axi-lite/rtl/AxiLiteFifoPush.vhd index 8266d6b0a4..e2dcdf0757 100644 --- a/axi/axi-lite/rtl/AxiLiteFifoPush.vhd +++ b/axi/axi-lite/rtl/AxiLiteFifoPush.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLiteFifoPush.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-04-02 --- Last update: 2016-04-26 ------------------------------------------------------------------------------- -- Description: -- Supports writing of general purpose FIFOs from the AxiLite bus. diff --git a/axi/axi-lite/rtl/AxiLiteFifoPushPop.vhd b/axi/axi-lite/rtl/AxiLiteFifoPushPop.vhd index d5dc1974f6..f264909329 100644 --- a/axi/axi-lite/rtl/AxiLiteFifoPushPop.vhd +++ b/axi/axi-lite/rtl/AxiLiteFifoPushPop.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLiteFifoPush.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-04-02 --- Last update: 2016-04-26 ------------------------------------------------------------------------------- -- Description: -- Supports reading of general purpose FIFOs from the AxiLite bus. diff --git a/axi/axi-lite/rtl/AxiLiteMaster.vhd b/axi/axi-lite/rtl/AxiLiteMaster.vhd index de95f638a3..ad37f79fe5 100644 --- a/axi/axi-lite/rtl/AxiLiteMaster.vhd +++ b/axi/axi-lite/rtl/AxiLiteMaster.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLiteMaster.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-09 --- Last update: 2016-03-09 ------------------------------------------------------------------------------- -- Description: AXI-Lite Master module controlled via REQ/ACK interface ------------------------------------------------------------------------------- @@ -22,17 +20,16 @@ use ieee.std_logic_unsigned.all; use work.StdRtlPkg.all; use work.AxiLitePkg.all; -use work.AxiLiteMasterPkg.all; entity AxiLiteMaster is generic ( -- General Config TPD_G : time := 1 ns); port ( - axilClk : in sl; - axilRst : in sl; - req : in AxiLiteMasterReqType; - ack : out AxiLiteMasterAckType; + axilClk : in sl; + axilRst : in sl; + req : in AxiLiteReqType; + ack : out AxiLiteAckType; axilWriteMaster : out AxiLiteWriteMasterType; axilWriteSlave : in AxiLiteWriteSlaveType; axilReadMaster : out AxiLiteReadMasterType; @@ -46,14 +43,14 @@ architecture rtl of AxiLiteMaster is type StateType is (S_IDLE_C, S_WRITE_C, S_WRITE_AXI_C, S_READ_C, S_READ_AXI_C); type RegType is record - ack : AxiLiteMasterAckType; + ack : AxiLiteAckType; state : StateType; axilWriteMaster : AxiLiteWriteMasterType; axilReadMaster : AxiLiteReadMasterType; end record RegType; constant REG_INIT_C : RegType := ( - ack => AXI_LITE_MASTER_ACK_INIT_C, + ack => AXI_LITE_ACK_INIT_C, state => S_IDLE_C, axilWriteMaster => AXI_LITE_WRITE_MASTER_INIT_C, axilReadMaster => AXI_LITE_READ_MASTER_INIT_C); @@ -82,7 +79,7 @@ begin v.axilReadMaster := AXI_LITE_READ_MASTER_INIT_C; if (req.request = '0') then - v.ack := AXI_LITE_MASTER_ACK_INIT_C; + v.ack := AXI_LITE_ACK_INIT_C; end if; -- Frame is starting diff --git a/axi/axi-lite/rtl/AxiLiteMasterPkg.vhd b/axi/axi-lite/rtl/AxiLiteMasterPkg.vhd deleted file mode 100644 index a79e060a06..0000000000 --- a/axi/axi-lite/rtl/AxiLiteMasterPkg.vhd +++ /dev/null @@ -1,51 +0,0 @@ -------------------------------------------------------------------------------- --- File : AxiLiteMasterPkg.vhd --- Company : SLAC National Accelerator Laboratory --- Created : 2016-03-08 --- Last update: 2016-03-09 -------------------------------------------------------------------------------- --- Description: AxiLiteMaster Support Package -------------------------------------------------------------------------------- --- This file is part of SLAC Firmware Standard Library. It is subject to --- the license terms in the LICENSE.txt file found in the top-level directory --- of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of SLAC Firmware Standard Library, including this file, may be --- copied, modified, propagated, or distributed except according to the terms --- contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.StdRtlPkg.all; - -package AxiLiteMasterPkg is - - type AxiLiteMasterReqType is record - request : sl; - rnw : sl; - address : slv(31 downto 0); - wrData : slv(31 downto 0); - end record AxiLiteMasterReqType; - - constant AXI_LITE_MASTER_REQ_INIT_C : AxiLiteMasterReqType := ( - request => '0', - rnw => '1', - address => (others => '0'), - wrData => (others => '0')); - - type AxiLiteMasterAckType is record - done : sl; - resp : slv(1 downto 0); - rdData : slv(31 downto 0); - end record AxiLiteMasterAckType; - - constant AXI_LITE_MASTER_ACK_INIT_C : AxiLiteMasterAckType := ( - done => '0', - resp => (others => '0'), - rdData => (others => '0')); - - -end package AxiLiteMasterPkg; - diff --git a/axi/axi-lite/rtl/AxiLitePkg.vhd b/axi/axi-lite/rtl/AxiLitePkg.vhd index 8021a11e25..3bf0bd90bc 100644 --- a/axi/axi-lite/rtl/AxiLitePkg.vhd +++ b/axi/axi-lite/rtl/AxiLitePkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLitePkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-04-02 --- Last update: 2018-01-29 ------------------------------------------------------------------------------- -- Description: AXI-Lite Package File ------------------------------------------------------------------------------- @@ -206,6 +204,33 @@ package AxiLitePkg is axiWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, axiStatus => AXI_LITE_STATUS_INIT_C); + ---------------------------------------------------------------------------------- + -- Constants for endpoint abstractions (migrated from legacy AxiLiteMasterPkg.vhd) + ---------------------------------------------------------------------------------- + type AxiLiteReqType is record + request : sl; + rnw : sl; + address : slv(31 downto 0); + wrData : slv(31 downto 0); + end record AxiLiteReqType; + + constant AXI_LITE_REQ_INIT_C : AxiLiteReqType := ( + request => '0', + rnw => '1', + address => (others => '0'), + wrData => (others => '0')); + + type AxiLiteAckType is record + done : sl; + resp : slv(1 downto 0); + rdData : slv(31 downto 0); + end record AxiLiteAckType; + + constant AXI_LITE_ACK_INIT_C : AxiLiteAckType := ( + done => '0', + resp => (others => '0'), + rdData => (others => '0')); + ------------------------------------------------------------------------------------------------- -- Crossbar Config Generic Types ------------------------------------------------------------------------------------------------- @@ -332,6 +357,13 @@ package AxiLitePkg is variable axiWriteSlave : in AxiLiteWriteSlaveType; variable axiReadSlave : in AxiLiteReadSlaveType); + procedure axiSlaveRegisterLegacy ( + variable ep : inout AxiLiteEndpointType; + addr : in slv; + offset : in integer; + reg : inout slv; + constVal : in slv := "X"); + procedure axiSlaveRegister ( variable ep : inout AxiLiteEndpointType; addr : in slv; @@ -388,8 +420,8 @@ package AxiLitePkg is -- Generate evenly distributed address map function genAxiLiteConfig (num : positive; base : slv(31 downto 0); - baseBot : integer range 0 to 32; - addrBits : integer range 0 to 32) + baseBot : integer range 1 to 32; + addrBits : integer range 0 to 31) return AxiLiteCrossbarMasterConfigArray; @@ -437,9 +469,9 @@ package body AxiLitePkg is return AxiLiteWriteSlaveType is begin return (awready => '1', - wready => '1', - bresp => bresp, - bvalid => '1'); + wready => '1', + bresp => bresp, + bvalid => '1'); end function axiLiteWriteSlaveEmptyInit; function axiReadMasterInit (constant config : AxiLiteCrossbarMasterConfigType) return AxiLiteReadMasterType is @@ -681,10 +713,7 @@ package body AxiLitePkg is ep.axiStatus); end procedure; - - - - procedure axiSlaveRegister ( + procedure axiSlaveRegisterLegacy ( variable ep : inout AxiLiteEndpointType; addr : in slv; offset : in integer; @@ -732,10 +761,27 @@ package body AxiLitePkg is axiSlaveWriteResponse(ep.axiWriteSlave); end if; end if; + + end procedure; - if (REG_HIGH_BIT_C < reg'high) then - axiSlaveRegister(ep, slv(unsigned(NORMAL_ADDR_C)+4), 0, reg(reg'high downto REG_HIGH_BIT_C+1), "X"); - end if; + procedure axiSlaveRegister ( + variable ep : inout AxiLiteEndpointType; + addr : in slv; + offset : in integer; + reg : inout slv; + constVal : in slv := "X") + is + variable highbit : integer; + begin + + for i in ((reg'length-1)/32) downto 0 loop + if i = ((reg'length-1)/32) then + highbit := ((reg'length-1) mod 32) + (32*i) + reg'low; + else + highbit := 31 + (32*i) + reg'low; + end if; + axiSlaveRegisterLegacy(ep, slv(unsigned(addr)+(4*i)), offset, reg(highbit downto (32*i)+reg'low), constVal); + end loop; end procedure; @@ -748,7 +794,9 @@ package body AxiLitePkg is variable regTmp : slv(reg'length-1 downto 0); begin regTmp := reg; - axiSlaveRegister(ep, addr, offset, regTmp, "X"); + if (ep.axiStatus.readEnable = '1') then + axiSlaveRegister(ep, addr, offset, regTmp, "X"); + end if; end procedure; procedure axiSlaveRegister ( @@ -796,18 +844,11 @@ package body AxiLitePkg is addr : in slv; regs : in slv32Array) is - constant ADDR_BITS_C : integer := log2(regs'length); - variable addrLocal : slv(addr'length-1 downto 0) := addr; - variable tmp : slv(31 downto 0); begin - -- Select regs word based on araddr - tmp := regs(to_integer(unsigned(ep.axiReadMaster.araddr(ADDR_BITS_C+2-1 downto 2)))); - - addrLocal := addr; - addrLocal(ADDR_BITS_C+2-1 downto 2) := (others => '-'); - addrLocal(1 downto 0) := "00"; --- print("MULTI! - Addr: " & hstr(addrLocal)); - axiSlaveRegister(ep, addrLocal, 0, tmp); + for i in regs'range loop + axiSlaveRegisterR(ep, slv(unsigned(addr) + to_unsigned(i*4, addr'length)), 0, regs(i)); + end loop; + end procedure; procedure axiWrDetect ( @@ -859,7 +900,7 @@ package body AxiLitePkg is variable retConf : AxiLiteCrossbarMasterConfigArray(num-1 downto 0); variable addr : slv(31 downto 0); begin - + ------------------------------------------------------------------------------------------- -- Note: These asserts only work in synthesis (not simulation) -- https://forums.xilinx.com/t5/Synthesis/VHDL-assert-statement-within-function/td-p/413463 @@ -867,20 +908,20 @@ package body AxiLitePkg is -- Compare the baseBot to addrBits assert (baseBot > addrBits) - report "AxiLitePkg.genAxiLiteConfig(): (baseBot > addrBits) condition not meet" - & lf & "num = " & integer'image(num) + report "AxiLitePkg.genAxiLiteConfig(): (baseBot > addrBits) condition not meet" + & lf & "num = " & integer'image(num) & lf & "base = 0x" & hstr(base) - & lf & "baseBot = " & integer'image(baseBot) - & lf & "addrBits = " & integer'image(addrBits) + & lf & "baseBot = " & integer'image(baseBot) + & lf & "addrBits = " & integer'image(addrBits) severity error; -- Check that there is enough bits for the number of buses assert (2**(baseBot-addrBits) >= num) - report "AxiLitePkg.genAxiLiteConfig(): (2**(baseBot-addrBits) >= num) condition not meet" - & lf & "num = " & integer'image(num) + report "AxiLitePkg.genAxiLiteConfig(): (2**(baseBot-addrBits) >= num) condition not meet" + & lf & "num = " & integer'image(num) & lf & "base = 0x" & hstr(base) - & lf & "baseBot = " & integer'image(baseBot) - & lf & "addrBits = " & integer'image(addrBits) + & lf & "baseBot = " & integer'image(baseBot) + & lf & "addrBits = " & integer'image(addrBits) severity error; ------------------------------------------------------------------------------------------- @@ -957,9 +998,9 @@ package body AxiLitePkg is print(debug, "AxiLitePkg::axiLiteBusSimWrite(addr:" & hstr(addr) & ", data: " & hstr(dataTmp) & ")"); if (axilWriteSlave.bresp = AXI_RESP_SLVERR_C) then - report "AxiLitePkg::axiLiteBusSimWrite(): - BRESP = SLAVE_ERROR" severity warning; + report "AxiLitePkg::axiLiteBusSimWrite( addr:" & hstr(addr) & "): - BRESP = SLAVE_ERROR" severity warning; elsif (axilWriteSlave.bresp = AXI_RESP_DECERR_C) then - report "AxiLitePkg::axiLiteBusSimWrite(): BRESP = DECODE_ERROR" severity warning; + report "AxiLitePkg::axiLiteBusSimWrite( addr:" & hstr(addr) & "): BRESP = DECODE_ERROR" severity warning; end if; @@ -1008,9 +1049,9 @@ package body AxiLitePkg is -- Done. Check for errors if (axilReadSlave.rresp = AXI_RESP_SLVERR_C) then - report "AxiLitePkg::axiLiteBusSimRead(): - RRESP = SLAVE_ERROR" severity warning; + report "AxiLitePkg::axiLiteBusSimRead( addr:" & hstr(addr) & "): RRESP = SLAVE_ERROR" severity warning; elsif (axilReadSlave.rresp = AXI_RESP_DECERR_C) then - report "AxiLitePkg::axiLiteBusSimRead(): RRESP = DECODE_ERROR" severity warning; + report "AxiLitePkg::axiLiteBusSimRead( addr:" & hstr(addr) & "): RRESP = DECODE_ERROR" severity warning; else dataTmp := axilReadSlave.rdata; print(debug, "AxiLitePkg::axiLiteBusSimRead( addr:" & hstr(addr) & ", data: " & hstr(axilReadSlave.rdata) & ")"); diff --git a/axi/axi-lite/rtl/AxiLiteRingBuffer.vhd b/axi/axi-lite/rtl/AxiLiteRingBuffer.vhd index 553e5ce4b2..41cdb1a3bf 100644 --- a/axi/axi-lite/rtl/AxiLiteRingBuffer.vhd +++ b/axi/axi-lite/rtl/AxiLiteRingBuffer.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLiteRingBuffer.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-02 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Wrapper for simple BRAM based ring buffer with AXI-Lite interface ------------------------------------------------------------------------------- diff --git a/axi/axi-lite/rtl/AxiLiteSlave.vhd b/axi/axi-lite/rtl/AxiLiteSlave.vhd new file mode 100644 index 0000000000..658c4ff0b1 --- /dev/null +++ b/axi/axi-lite/rtl/AxiLiteSlave.vhd @@ -0,0 +1,155 @@ +------------------------------------------------------------------------------- +-- File : AxiLiteSlave.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: AXI-Lite Slave module controlled via REQ/ACK interface +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.StdRtlPkg.all; +use work.AxiLitePkg.all; + +entity AxiLiteSlave is + generic ( + TPD_G : time := 1 ns); + port ( + axilClk : in sl; + axilRst : in sl; + req : out AxiLiteReqType; + ack : in AxiLiteAckType; + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType; + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType); +end entity AxiLiteSlave; + +architecture rtl of AxiLiteSlave is + + type StateType is ( + IDLE_S, + ACK_S); + + type RegType is record + toggle : sl; + req : AxiLiteReqType; + axilWriteSlave : AxiLiteWriteSlaveType; + axilReadSlave : AxiLiteReadSlaveType; + state : StateType; + end record; + + constant REG_INIT_C : RegType := ( + toggle => '0', + req => AXI_LITE_REQ_INIT_C, + axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, + axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, + state => IDLE_S); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + +begin + + comb : process (ack, axilReadMaster, axilRst, axilWriteMaster, r) is + variable v : RegType; + variable axiStatus : AxiLiteStatusType; + variable axiResp : slv(1 downto 0); + begin + -- Latch the current value + v := r; + + -- Determine the transaction type + axiSlaveWaitTxn(axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave, axiStatus); + + -- State Machine + case (r.state) is + ---------------------------------------------------------------------- + when IDLE_S => + -- Check if done deasserted + if (ack.done = '0') then + -- Toggle the transaction select (prevent locking up in read or write direction) + v.toggle := not(r.toggle); + -- Check for a write request + if (axiStatus.writeEnable = '1') and (r.toggle = '0') then + -- Start the write request + v.req.request := '1'; + v.req.rnw := '0'; + v.req.address := axilWriteMaster.awaddr; + v.req.wrData := axilWriteMaster.wdata; + -- Next state + v.state := ACK_S; + -- Check for a read request + elsif (axiStatus.readEnable = '1') and (r.toggle = '1') then + -- Start the read request + v.req.request := '1'; + v.req.rnw := '1'; + v.req.address := axilReadMaster.araddr; + -- Next state + v.state := ACK_S; + end if; + end if; + ---------------------------------------------------------------------- + when ACK_S => + -- Check for the acknowledgment + if (ack.done = '1') then + -- Reset the flag + v.req.request := '0'; + -- Check for bus errors + if (ack.resp = 0) then + -- Return good transaction + axiResp := AXI_RESP_OK_C; + else + -- Return bad transaction + axiResp := AXI_RESP_SLVERR_C; + end if; + -- Check for a write request + if (r.req.rnw = '0') then + -- Send AXI-Lite response + axiSlaveWriteResponse(v.axilWriteSlave, axiResp); + -- Check for a read request + elsif (axiStatus.readEnable = '1') then + -- Set the read bus + v.axilReadSlave.rdata := ack.rdData; + -- Send AXI-Lite Response + axiSlaveReadResponse(v.axilReadSlave, axiResp); + end if; + -- Next state + v.state := IDLE_S; + end if; + ---------------------------------------------------------------------- + end case; + + -- Outputs + axilReadSlave <= r.axilReadSlave; + axilWriteSlave <= r.axilWriteSlave; + req <= r.req; + + -- Synchronous Reset + if (axilRst = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (axilClk) is + begin + if (rising_edge(axilClk)) then + r <= rin after TPD_G; + end if; + end process seq; + +end rtl; diff --git a/axi/axi-lite/rtl/AxiLiteWriteFilter.vhd b/axi/axi-lite/rtl/AxiLiteWriteFilter.vhd index 9f20bdca73..6b4ebbb801 100644 --- a/axi/axi-lite/rtl/AxiLiteWriteFilter.vhd +++ b/axi/axi-lite/rtl/AxiLiteWriteFilter.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLiteWriteFilter.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-13 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Module for filtering write access ------------------------------------------------------------------------------- diff --git a/axi/axi-lite/rtl/AxiVersion.vhd b/axi/axi-lite/rtl/AxiVersion.vhd index 5932ed7e89..0e960a1ce5 100644 --- a/axi/axi-lite/rtl/AxiVersion.vhd +++ b/axi/axi-lite/rtl/AxiVersion.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiVersion.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-05-20 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Creates AXI accessible registers containing configuration -- information. @@ -202,12 +200,7 @@ begin axiSlaveRegisterR(axilEp, x"400", userValues); axiSlaveRegisterR(axilEp, x"500", 0, DEVICE_ID_G); - -- axiSlaveRegisterR(axilEp, x"600", 0, BUILD_INFO_C.gitHash);-- axiSlaveRegisterR() Broken, only first 32-bit show up in software - axiSlaveRegisterR(axilEp, x"600", 0, BUILD_INFO_C.gitHash(31 downto 0)); - axiSlaveRegisterR(axilEp, x"604", 0, BUILD_INFO_C.gitHash(63 downto 32)); - axiSlaveRegisterR(axilEp, x"608", 0, BUILD_INFO_C.gitHash(95 downto 64)); - axiSlaveRegisterR(axilEp, x"60C", 0, BUILD_INFO_C.gitHash(127 downto 96)); - axiSlaveRegisterR(axilEp, x"610", 0, BUILD_INFO_C.gitHash(159 downto 128)); + axiSlaveRegisterR(axilEp, x"600", 0, BUILD_INFO_C.gitHash); axiSlaveRegisterR(axilEp, x"700", 0, dnaValue); axiSlaveRegisterR(axilEp, x"800", BUILD_STRING_ROM_C); diff --git a/axi/axi-lite/rtl/AxiVersionLegacy.vhd b/axi/axi-lite/rtl/AxiVersionLegacy.vhd index a13d024caf..8f8245ea9f 100644 --- a/axi/axi-lite/rtl/AxiVersionLegacy.vhd +++ b/axi/axi-lite/rtl/AxiVersionLegacy.vhd @@ -201,12 +201,7 @@ begin axiSlaveRegisterR(axilEp, X"02C", 0, r.upTimeCnt); axiSlaveRegisterR(axilEp, X"030", 0, DEVICE_ID_G); --- axiSlaveRegisterR(axilEp, X"100", 0, BUILD_INFO_C.gitHash(63 downto 32)); - axiSlaveRegisterR(axilEp, X"100", 0, BUILD_INFO_C.gitHash(31 downto 0)); - axiSlaveRegisterR(axilEp, x"104", 0, BUILD_INFO_C.gitHash(63 downto 32)); - axiSlaveRegisterR(axilEp, x"108", 0, BUILD_INFO_C.gitHash(95 downto 64)); - axiSlaveRegisterR(axilEp, x"10C", 0, BUILD_INFO_C.gitHash(127 downto 96)); - axiSlaveRegisterR(axilEp, x"110", 0, BUILD_INFO_C.gitHash(159 downto 128)); + axiSlaveRegisterR(axilEp, X"100", 0, BUILD_INFO_C.gitHash(63 downto 32)); axiSlaveRegisterR(axilEp, X"400", userValues); axiSlaveRegisterR(axilEp, X"800", BUILD_STRING_ROM_C); diff --git a/axi/axi-lite/tb/AxiLiteAsyncTb.vhd b/axi/axi-lite/tb/AxiLiteAsyncTb.vhd index 6a089972b7..9f2048daa2 100644 --- a/axi/axi-lite/tb/AxiLiteAsyncTb.vhd +++ b/axi/axi-lite/tb/AxiLiteAsyncTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLiteAsyncTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-05-11 --- Last update: 2016-05-11 ------------------------------------------------------------------------------- -- Description: Testbench for design "AxiLiteAsync" ------------------------------------------------------------------------------- diff --git a/axi/axi-lite/tb/AxiLiteWriteFilterTb.vhd b/axi/axi-lite/tb/AxiLiteWriteFilterTb.vhd index 5411655646..371b65c98c 100644 --- a/axi/axi-lite/tb/AxiLiteWriteFilterTb.vhd +++ b/axi/axi-lite/tb/AxiLiteWriteFilterTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLiteWriteFilterTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-13 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Testbench for design "AxiLiteAsync" ------------------------------------------------------------------------------- diff --git a/axi/axi-lite/tb/AxiVersionTb.vhd b/axi/axi-lite/tb/AxiVersionTb.vhd new file mode 100644 index 0000000000..807537968a --- /dev/null +++ b/axi/axi-lite/tb/AxiVersionTb.vhd @@ -0,0 +1,100 @@ +------------------------------------------------------------------------------- +-- File : AxiVersionTb.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Simulation Testbed for testing the AxiVersionTb module +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +use work.StdRtlPkg.all; +use work.AxiLitePkg.all; +use work.BuildInfoPkg.all; + +entity AxiVersionTb is end AxiVersionTb; + +architecture testbed of AxiVersionTb is + + constant GET_BUILD_INFO_C : BuildInfoRetType := toBuildInfo(BUILD_INFO_C); + constant MOD_BUILD_INFO_C : BuildInfoRetType := ( + buildString => GET_BUILD_INFO_C.buildString, + fwVersion => GET_BUILD_INFO_C.fwVersion, + gitHash => x"1111_2222_3333_4444_5555_6666_7777_8888_9999_AAAA"); -- Force githash + constant SIM_BUILD_INFO_C : slv(2239 downto 0) := toSlv(MOD_BUILD_INFO_C); + + constant CLK_PERIOD_G : time := 10 ns; + constant TPD_G : time := CLK_PERIOD_G/4; + + signal axilClk : sl := '0'; + signal axilRst : sl := '0'; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + +begin + + -------------------- + -- Clocks and Resets + -------------------- + U_axilClk : entity work.ClkRst + generic map ( + CLK_PERIOD_G => CLK_PERIOD_G, + RST_START_DELAY_G => 0 ns, + RST_HOLD_TIME_G => 1000 ns) + port map ( + clkP => axilClk, + rst => axilRst); + + ----------------------- + -- Module to be tested + ----------------------- + U_Version : entity work.AxiVersion + generic map ( + TPD_G => TPD_G, + BUILD_INFO_G => SIM_BUILD_INFO_C) + port map ( + -- AXI-Lite Interface + axiClk => axilClk, + axiRst => axilRst, + axiReadMaster => axilReadMaster, + axiReadSlave => axilReadSlave, + axiWriteMaster => axilWriteMaster, + axiWriteSlave => axilWriteSlave); + + --------------------------------- + -- AXI-Lite Register Transactions + --------------------------------- + test : process is + variable debugData : slv(31 downto 0) := (others => '0'); + begin + debugData := x"1111_1111"; + ------------------------------------------ + -- Wait for the AXI-Lite reset to complete + ------------------------------------------ + wait until axilRst = '1'; + wait until axilRst = '0'; + + axiLiteBusSimRead (axilClk, axilReadMaster, axilReadSlave, x"0000_0600", debugData, true); + axiLiteBusSimRead (axilClk, axilReadMaster, axilReadSlave, x"0000_0604", debugData, true); + axiLiteBusSimRead (axilClk, axilReadMaster, axilReadSlave, x"0000_0608", debugData, true); + axiLiteBusSimRead (axilClk, axilReadMaster, axilReadSlave, x"0000_060C", debugData, true); + axiLiteBusSimRead (axilClk, axilReadMaster, axilReadSlave, x"0000_0610", debugData, true); + + + axiLiteBusSimWrite (axilClk, axilWriteMaster, axilWriteSlave, x"0000_0000", x"1234_5678", true); + + end process test; + +end testbed; diff --git a/axi/axi-stream/rtl/AxiStreamBytePacker.vhd b/axi/axi-stream/rtl/AxiStreamBytePacker.vhd index 93fa9fe42c..236be4936c 100644 --- a/axi/axi-stream/rtl/AxiStreamBytePacker.vhd +++ b/axi/axi-stream/rtl/AxiStreamBytePacker.vhd @@ -1,7 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamBytePacker.vhd.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-13 ------------------------------------------------------------------------------- -- Description: -- Byte packer for AXI-Stream. @@ -81,7 +80,7 @@ begin -- Register input and compute size v.inMaster := sAxisMaster; - v.inTop := getTKeep(sAxisMaster.tKeep(MAX_IN_BYTE_C downto 0))-1; + v.inTop := getTKeep(sAxisMaster.tKeep(MAX_IN_BYTE_C downto 0),SLAVE_CONFIG_G)-1; -- Pending output from current if r.curMaster.tValid = '1' then diff --git a/axi/axi-stream/rtl/AxiStreamDeMux.vhd b/axi/axi-stream/rtl/AxiStreamDeMux.vhd index f45087feb6..1da9cb399e 100644 --- a/axi/axi-stream/rtl/AxiStreamDeMux.vhd +++ b/axi/axi-stream/rtl/AxiStreamDeMux.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamDeMux.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-25 --- Last update: 2017-04-07 ------------------------------------------------------------------------------- -- Description: -- Block to connect a single incoming AXI stream to multiple outgoing AXI diff --git a/axi/axi-stream/rtl/AxiStreamFifo.vhd b/axi/axi-stream/rtl/AxiStreamFifo.vhd index 032f30610e..6bb7317253 100644 --- a/axi/axi-stream/rtl/AxiStreamFifo.vhd +++ b/axi/axi-stream/rtl/AxiStreamFifo.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamFifo.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-25 --- Last update: 2016-08-31 ------------------------------------------------------------------------------- -- Description: -- Block to serve as an async FIFO for AXI Streams. This block also allows the @@ -79,7 +77,7 @@ entity AxiStreamFifo is mAxisRst : in sl; mAxisMaster : out AxiStreamMasterType; mAxisSlave : in AxiStreamSlaveType; - mTLastTUser : out slv(127 downto 0)); -- when VALID_THOLD_G /= 1, used to look ahead at tLast's tUser + mTLastTUser : out slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0)); -- when VALID_THOLD_G /= 1, used to look ahead at tLast's tUser end AxiStreamFifo; architecture rtl of AxiStreamFifo is @@ -139,7 +137,7 @@ architecture rtl of AxiStreamFifo is if KEEP_MODE_C = TKEEP_NORMAL_C then assignSlv(i, retValue, din.tKeep(KEEP_BITS_C-1 downto 0)); elsif KEEP_MODE_C = TKEEP_COMP_C then - assignSlv(i, retValue, toSlv(getTKeep(din.tKeep(DATA_BYTES_C-1 downto 1)), KEEP_BITS_C)); -- Assume lsb is present + assignSlv(i, retValue, toSlv(getTKeep(din.tKeep(DATA_BYTES_C-1 downto 1),FIFO_AXIS_CONFIG_C), KEEP_BITS_C)); -- Assume lsb is present end if; -- Pack user bits @@ -198,7 +196,7 @@ architecture rtl of AxiStreamFifo is -- Get keep bits if KEEP_MODE_C = TKEEP_NORMAL_C then assignRecord(i, din, master.tKeep(KEEP_BITS_C-1 downto 0)); - byteCnt := getTKeep(master.tKeep); + byteCnt := getTKeep(master.tKeep,MASTER_AXI_CONFIG_G); elsif KEEP_MODE_C = TKEEP_COMP_C then byteCnt := conv_integer(din((KEEP_BITS_C+i)-1 downto i))+1; master.tKeep := genTKeep(byteCnt); diff --git a/axi/axi-stream/rtl/AxiStreamFifoV2.vhd b/axi/axi-stream/rtl/AxiStreamFifoV2.vhd index 3d2c0b1f88..41d1384199 100644 --- a/axi/axi-stream/rtl/AxiStreamFifoV2.vhd +++ b/axi/axi-stream/rtl/AxiStreamFifoV2.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamFifoV2.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-09-02 --- Last update: 2016-11-30 ------------------------------------------------------------------------------- -- Description: -- Block to serve as an async FIFO for AXI Streams. This block also allows the diff --git a/axi/axi-stream/rtl/AxiStreamFlush.vhd b/axi/axi-stream/rtl/AxiStreamFlush.vhd index df9223564a..bd1d5d8662 100644 --- a/axi/axi-stream/rtl/AxiStreamFlush.vhd +++ b/axi/axi-stream/rtl/AxiStreamFlush.vhd @@ -1,160 +1,158 @@ -------------------------------------------------------------------------------- --- File : AxiStreamFlush.vhd --- Company : SLAC National Accelerator Laboratory --- Created : 2016-06-16 --- Last update: 2016-06-16 -------------------------------------------------------------------------------- --- Description: --- Block to flush AXI Stream frames, being mindfull of frame boundaries. --- This module is designed to feed into an AxiStreamFifo using pause to determine --- backpressure situations. -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -use work.StdRtlPkg.all; -use work.AxiStreamPkg.all; -use work.SsiPkg.all; - -entity AxiStreamFlush is - generic ( - TPD_G : time := 1 ns; - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C; - SSI_EN_G : boolean := false); - port ( - - -- Clock and reset - axisClk : in sl; - axisRst : in sl; - - -- Flush enable - flushEn : in sl; - - -- Slave Port - sAxisMaster : in AxiStreamMasterType; - sAxisSlave : out AxiStreamSlaveType; - - -- Master Port - mAxisMaster : out AxiStreamMasterType; - mAxisCtrl : in AxiStreamCtrlType); -end AxiStreamFlush; - -architecture rtl of AxiStreamFlush is - - type StateType is ( IDLE_S, MOVE_S, FLUSH_S ); - - type RegType is record - state : StateType; - obMaster : AxiStreamMasterType; - ibSlave : AxiStreamSlaveType; - end record RegType; - - constant REG_INIT_C : RegType := ( - state => IDLE_S, - obMaster => axiStreamMasterInit(AXIS_CONFIG_G), - ibSlave => AXI_STREAM_SLAVE_INIT_C - ); - - signal r : RegType := REG_INIT_C; - signal rin : RegType; - -begin - - comb : process (mAxisCtrl, sAxisMaster, axisRst, flushEn, r) is - variable v : RegType; - begin - -- Latch the current value - v := r; - - -- Reset strobing signals - v.ibSlave.tReady := '0'; - v.obMaster := AXI_STREAM_MASTER_INIT_C; - - case r.state is - - -- Wait for frame - when IDLE_S => - if sAxisMaster.tValid = '1' then - - -- Flush is enabled - if flushEn = '1' then - v.state := FLUSH_S; - - -- Allow backpressure when flush is disabled - elsif mAxisCtrl.pause = '0' then - v.state := MOVE_S; - end if; - end if; - - -- Moving data - when MOVE_S => - v.ibSlave.tReady := not mAxisCtrl.pause; - - v.obMaster := sAxisMaster; - v.obMaster.tValid := sAxisMaster.tValid and not mAxisCtrl.pause; - - -- Flush is asserted, terminate frame - if flushEn = '1' then - v.obMaster.tValid := '1'; - v.obMaster.tLast := '1'; - - -- Set EOFE if enabled - if SSI_EN_G then - ssiSetUserEofe ( AXIS_CONFIG_G, v.obMaster, '1'); - end if; - - v.state := FLUSH_S; - - elsif sAxisMaster.tValid = '1' and sAxisMaster.tLast = '1' then - v.state := IDLE_S; - end if; - - -- Flushing data - when FLUSH_S => - v.ibSlave.tReady := '1'; - - -- Dump until we see tlast - if sAxisMaster.tValid = '1' and sAxisMaster.tLast = '1' then - v.state := IDLE_S; - end if; - - when others => - v.state := IDLE_S; - - end case; - - -- Combinatorial outputs before the reset - sAxisSlave <= v.ibSlave; - - -- Reset - if axisRst = '1' then - v := REG_INIT_C; - end if; - - -- Register the variable for next clock cycle - rin <= v; - - -- Registered Outputs - mAxisMaster <= r.obMaster; - - end process comb; - - seq : process (axisClk) is - begin - if (rising_edge(axisClk)) then - r <= rin after TPD_G; - end if; - end process seq; - -end rtl; +------------------------------------------------------------------------------- +-- File : AxiStreamFlush.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Block to flush AXI Stream frames, being mindfull of frame boundaries. +-- This module is designed to feed into an AxiStreamFifo using pause to determine +-- backpressure situations. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +use work.StdRtlPkg.all; +use work.AxiStreamPkg.all; +use work.SsiPkg.all; + +entity AxiStreamFlush is + generic ( + TPD_G : time := 1 ns; + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C; + SSI_EN_G : boolean := false); + port ( + + -- Clock and reset + axisClk : in sl; + axisRst : in sl; + + -- Flush enable + flushEn : in sl; + + -- Slave Port + sAxisMaster : in AxiStreamMasterType; + sAxisSlave : out AxiStreamSlaveType; + + -- Master Port + mAxisMaster : out AxiStreamMasterType; + mAxisCtrl : in AxiStreamCtrlType); +end AxiStreamFlush; + +architecture rtl of AxiStreamFlush is + + type StateType is ( IDLE_S, MOVE_S, FLUSH_S ); + + type RegType is record + state : StateType; + obMaster : AxiStreamMasterType; + ibSlave : AxiStreamSlaveType; + end record RegType; + + constant REG_INIT_C : RegType := ( + state => IDLE_S, + obMaster => axiStreamMasterInit(AXIS_CONFIG_G), + ibSlave => AXI_STREAM_SLAVE_INIT_C + ); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + +begin + + comb : process (mAxisCtrl, sAxisMaster, axisRst, flushEn, r) is + variable v : RegType; + begin + -- Latch the current value + v := r; + + -- Reset strobing signals + v.ibSlave.tReady := '0'; + v.obMaster := AXI_STREAM_MASTER_INIT_C; + + case r.state is + + -- Wait for frame + when IDLE_S => + if sAxisMaster.tValid = '1' then + + -- Flush is enabled + if flushEn = '1' then + v.state := FLUSH_S; + + -- Allow backpressure when flush is disabled + elsif mAxisCtrl.pause = '0' then + v.state := MOVE_S; + end if; + end if; + + -- Moving data + when MOVE_S => + v.ibSlave.tReady := not mAxisCtrl.pause; + + v.obMaster := sAxisMaster; + v.obMaster.tValid := sAxisMaster.tValid and not mAxisCtrl.pause; + + -- Flush is asserted, terminate frame + if flushEn = '1' then + v.obMaster.tValid := '1'; + v.obMaster.tLast := '1'; + + -- Set EOFE if enabled + if SSI_EN_G then + ssiSetUserEofe ( AXIS_CONFIG_G, v.obMaster, '1'); + end if; + + v.state := FLUSH_S; + + elsif sAxisMaster.tValid = '1' and sAxisMaster.tLast = '1' then + v.state := IDLE_S; + end if; + + -- Flushing data + when FLUSH_S => + v.ibSlave.tReady := '1'; + + -- Dump until we see tlast + if sAxisMaster.tValid = '1' and sAxisMaster.tLast = '1' then + v.state := IDLE_S; + end if; + + when others => + v.state := IDLE_S; + + end case; + + -- Combinatorial outputs before the reset + sAxisSlave <= v.ibSlave; + + -- Reset + if axisRst = '1' then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + -- Registered Outputs + mAxisMaster <= r.obMaster; + + end process comb; + + seq : process (axisClk) is + begin + if (rising_edge(axisClk)) then + r <= rin after TPD_G; + end if; + end process seq; + +end rtl; diff --git a/axi/axi-stream/rtl/AxiStreamGearboxPack.vhd b/axi/axi-stream/rtl/AxiStreamGearboxPack.vhd index 7fe818391f..b85fc473d5 100644 --- a/axi/axi-stream/rtl/AxiStreamGearboxPack.vhd +++ b/axi/axi-stream/rtl/AxiStreamGearboxPack.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamGearboxPack -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-29 --- Last update: 2016-07-13 ------------------------------------------------------------------------------- -- Description: AXI stream Packer Module ------------------------------------------------------------------------------- diff --git a/axi/axi-stream/rtl/AxiStreamGearboxUnpack.vhd b/axi/axi-stream/rtl/AxiStreamGearboxUnpack.vhd index eedc76e870..ab33568a60 100644 --- a/axi/axi-stream/rtl/AxiStreamGearboxUnpack.vhd +++ b/axi/axi-stream/rtl/AxiStreamGearboxUnpack.vhd @@ -1,7 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamGearboxUnpack.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-09-26 ------------------------------------------------------------------------------- -- Description: Takes 8 80-bit (5x16) ADC frames and reformats them into -- 7 80 bit (5x14) frames. diff --git a/axi/axi-stream/rtl/AxiStreamMon.vhd b/axi/axi-stream/rtl/AxiStreamMon.vhd index a035f37a65..2de91aebce 100644 --- a/axi/axi-stream/rtl/AxiStreamMon.vhd +++ b/axi/axi-stream/rtl/AxiStreamMon.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamMon.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-07-14 --- Last update: 2017-11-16 ------------------------------------------------------------------------------- -- Description: AXI Stream Monitor Module ------------------------------------------------------------------------------- @@ -55,7 +53,7 @@ architecture rtl of AxiStreamMon is armed : sl; frameSent : sl; tValid : sl; - tKeep : slv(15 downto 0); + tKeep : slv(AXI_STREAM_MAX_TKEEP_WIDTH_C-1 downto 0); updated : sl; updateStat : sl; timer : natural range 0 to TIMEOUT_C; @@ -177,7 +175,11 @@ begin -- Check if last cycle had data moving if r.tValid = '1' then -- Update the accumulator - v.accum := r.accum + getTKeep(r.tKeep); + if (AXIS_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then + v.accum := r.accum + conv_integer(r.tKeep(bitSize(AXIS_CONFIG_G.TDATA_BYTES_C)-1 downto 0)); + else + v.accum := r.accum + getTKeep(r.tKeep, AXIS_CONFIG_G); + end if; end if; -- Increment the timer @@ -194,7 +196,11 @@ begin if r.tValid = '0' then v.accum := (others => '0'); else - v.accum := toSlv(getTKeep(r.tKeep), 40); + if (AXIS_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then + v.accum := resize(r.tKeep(bitSize(AXIS_CONFIG_G.TDATA_BYTES_C)-1 downto 0), 40); + else + v.accum := toSlv(getTKeep(r.tKeep, AXIS_CONFIG_G), 40); + end if; end if; end if; diff --git a/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd b/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd index 7fd2ecbf8e..cfbf15201b 100644 --- a/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd +++ b/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamMonAxiL.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-07-14 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AXI Stream Monitor Module ------------------------------------------------------------------------------- @@ -36,8 +34,8 @@ entity AxiStreamMonAxiL is -- AXIS Stream Interface axisClk : in sl; axisRst : in sl; - axisMaster : in AxiStreamMasterArray(AXIS_NUM_SLOTS_G-1 downto 0); - axisSlave : in AxiStreamSlaveArray(AXIS_NUM_SLOTS_G-1 downto 0); + axisMasters : in AxiStreamMasterArray(AXIS_NUM_SLOTS_G-1 downto 0); + axisSlaves : in AxiStreamSlaveArray(AXIS_NUM_SLOTS_G-1 downto 0); -- AXI lite slave port for register access axilClk : in std_logic; axilRst : in std_logic; @@ -110,8 +108,8 @@ begin -- AXIS Stream Interface axisClk => axisClk, axisRst => axisReset, - axisMaster => axisMaster(i), - axisSlave => axisSlave(i), + axisMaster => axisMasters(i), + axisSlave => axisSlaves(i), -- Status Interface statusClk => axilClk, statusRst => r.rstCnt, diff --git a/axi/axi-stream/rtl/AxiStreamMux.vhd b/axi/axi-stream/rtl/AxiStreamMux.vhd index 96598b703f..6f69cf125c 100644 --- a/axi/axi-stream/rtl/AxiStreamMux.vhd +++ b/axi/axi-stream/rtl/AxiStreamMux.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamMux.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-25 --- Last update: 2017-12-14 ------------------------------------------------------------------------------- -- Description: -- Block to connect multiple incoming AXI streams into a single encoded diff --git a/axi/axi-stream/rtl/AxiStreamPipeline.vhd b/axi/axi-stream/rtl/AxiStreamPipeline.vhd index 2af8d71b2e..9389282b1c 100644 --- a/axi/axi-stream/rtl/AxiStreamPipeline.vhd +++ b/axi/axi-stream/rtl/AxiStreamPipeline.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamPipeline.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-01 --- Last update: 2016-09-06 ------------------------------------------------------------------------------- -- Description: This module is used to sync a AxiStream bus -- either as a pass through or with pipeline register stages. diff --git a/axi/axi-stream/rtl/AxiStreamPkg.vhd b/axi/axi-stream/rtl/AxiStreamPkg.vhd index 70ff6d9de3..69214f440d 100644 --- a/axi/axi-stream/rtl/AxiStreamPkg.vhd +++ b/axi/axi-stream/rtl/AxiStreamPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-24 --- Last update: 2017-02-09 ------------------------------------------------------------------------------- -- Description: AXI Stream Package File ------------------------------------------------------------------------------- @@ -21,18 +19,22 @@ use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use work.StdRtlPkg.all; +-- use work.TextUtilPkg.all; package AxiStreamPkg is + constant AXI_STREAM_MAX_TDATA_WIDTH_C : positive := 512; -- Units of bits + constant AXI_STREAM_MAX_TKEEP_WIDTH_C : positive := (AXI_STREAM_MAX_TDATA_WIDTH_C/8); -- Units of bytes + type AxiStreamMasterType is record tValid : sl; - tData : slv(127 downto 0); - tStrb : slv(15 downto 0); - tKeep : slv(15 downto 0); + tData : slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0); + tStrb : slv(AXI_STREAM_MAX_TKEEP_WIDTH_C-1 downto 0); + tKeep : slv(AXI_STREAM_MAX_TKEEP_WIDTH_C-1 downto 0); tLast : sl; tDest : slv(7 downto 0); tId : slv(7 downto 0); - tUser : slv(127 downto 0); + tUser : slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0); end record AxiStreamMasterType; constant AXI_STREAM_MASTER_INIT_C : AxiStreamMasterType := ( @@ -70,7 +72,7 @@ package AxiStreamPkg is type AxiStreamConfigType is record TSTRB_EN_C : boolean; - TDATA_BYTES_C : natural range 1 to 16; + TDATA_BYTES_C : natural range 1 to AXI_STREAM_MAX_TKEEP_WIDTH_C; TDEST_BITS_C : natural range 0 to 8; TID_BITS_C : natural range 0 to 8; TKEEP_MODE_C : TkeepModeType; @@ -167,10 +169,10 @@ package AxiStreamPkg is function ite(i : boolean; t : TUserModeType; e : TUserModeType) return TUserModeType; function ite(i : boolean; t : TKeepModeType; e : TKeepModeType) return TKeepModeType; - function genTKeep (bytes : integer range 0 to 16) return slv; + function genTKeep (bytes : natural range 0 to AXI_STREAM_MAX_TKEEP_WIDTH_C) return slv; function genTKeep (constant config : AxiStreamConfigType) return slv; - function getTKeep (tKeep : slv) return natural; + function getTKeep (tKeep : slv; axisConfig : AxiStreamConfigType) return natural; end package AxiStreamPkg; @@ -210,7 +212,7 @@ package body AxiStreamPkg is begin if bytePos = -1 then - ret := getTKeep(axisMaster.tKeep)-1; + ret := getTKeep(axisMaster.tKeep, axisConfig)-1; if (ret > axisConfig.TDATA_BYTES_C) then ret := axisConfig.TDATA_BYTES_C-1; end if; @@ -236,7 +238,7 @@ package body AxiStreamPkg is pos := axiStreamGetUserPos(axisConfig, axisMaster, bytePos); - ret := ite(axisConfig.TUSER_BITS_C>0, + ret := ite(axisConfig.TUSER_BITS_C > 0, axisMaster.tUser((axisConfig.TUSER_BITS_C*pos)+axisConfig.TUSER_BITS_C-1 downto ((axisConfig.TUSER_BITS_C*pos))), "0"); @@ -329,27 +331,14 @@ package body AxiStreamPkg is if (i) then return t; else return e; end if; end function ite; - function genTKeep (bytes : integer range 0 to 16) return slv is + function genTKeep (bytes : natural range 0 to AXI_STREAM_MAX_TKEEP_WIDTH_C) return slv is + variable retVar : slv(AXI_STREAM_MAX_TKEEP_WIDTH_C-1 downto 0); begin - case bytes is - when 0 => return X"0000"; - when 1 => return X"0001"; - when 2 => return X"0003"; - when 3 => return X"0007"; - when 4 => return X"000F"; - when 5 => return X"001F"; - when 6 => return X"003F"; - when 7 => return X"007F"; - when 8 => return X"00FF"; - when 9 => return X"01FF"; - when 10 => return X"03FF"; - when 11 => return X"07FF"; - when 12 => return X"0FFF"; - when 13 => return X"1FFF"; - when 14 => return X"3FFF"; - when 15 => return X"7FFF"; - when 16 => return X"FFFF"; - end case; + retVar := (others => '0'); + if bytes /= 0 then + retVar(bytes-1 downto 0) := (others => '1'); + end if; + return retVar; end function genTKeep; function genTKeep (constant config : AxiStreamConfigType) return slv is @@ -357,30 +346,29 @@ package body AxiStreamPkg is return genTKeep(config.TDATA_BYTES_C); end function genTKeep; - function getTKeep (tKeep : slv) return natural is - variable tKeepFull : slv(15 downto 0); + function getTKeep (tKeep : slv; axisConfig : AxiStreamConfigType) return natural is + variable tKeepFull : slv(AXI_STREAM_MAX_TKEEP_WIDTH_C-1 downto 0); + variable retVar : natural; + variable i : natural; begin - tKeepFull := resize(tKeep, 16); - case tKeepFull is - when X"0000" => return 0; - when X"0001" => return 1; - when X"0003" => return 2; - when X"0007" => return 3; - when X"000F" => return 4; - when X"001F" => return 5; - when X"003F" => return 6; - when X"007F" => return 7; - when X"00FF" => return 8; - when X"01FF" => return 9; - when X"03FF" => return 10; - when X"07FF" => return 11; - when X"0FFF" => return 12; - when X"1FFF" => return 13; - when X"3FFF" => return 14; - when X"7FFF" => return 15; - when X"FFFF" => return 16; - when others => return 0; - end case; + retVar := 0; + tKeepFull := resize(tKeep, AXI_STREAM_MAX_TKEEP_WIDTH_C); + for i in 0 to axisConfig.TDATA_BYTES_C-1 loop + -- report "AxiStreamPkg::genTKeep( i:" & integer'image(i) & ")" severity warning; + ---------------------------------------------------- + -- Confirmed in simulation the for loop ordering is: + ---------------------------------------------------- + -- Warning: AxiStreamPkg::genTKeep( i:0) + -- Warning: AxiStreamPkg::genTKeep( i:1) + -- Warning: AxiStreamPkg::genTKeep( i:2) + -- ..................................... + -- ..................................... + ---------------------------------------------------- + if (tKeepFull(i) = '1') then + retVar := (i+1); + end if; + end loop; + return retVar; end function getTKeep; procedure axiStreamSimSendTxn ( @@ -389,11 +377,11 @@ package body AxiStreamPkg is signal master : out AxiStreamMasterType; signal slave : in AxiStreamSlaveType; tData : in slv; - tKeep : in slv := "X"; - tLast : in sl := '0'; - tDest : in slv(7 downto 0) := X"00"; - tId : in slv(7 downto 0) := X"00"; - tUser : in slv(127 downto 0) := (others => '0')) is + tKeep : in slv := "X"; + tLast : in sl := '0'; + tDest : in slv(7 downto 0) := X"00"; + tId : in slv(7 downto 0) := X"00"; + tUser : in slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0) := (others => '0')) is begin -- Wait for rising edge wait until clk = '1'; @@ -401,9 +389,9 @@ package body AxiStreamPkg is -- Set the bus master <= axiStreamMasterInit(CONFIG_C); master.tValid <= '1'; - master.tData <= resize(tdata, 128); + master.tData <= resize(tdata, AXI_STREAM_MAX_TDATA_WIDTH_C); if (tKeep /= "X") then - master.tKeep <= resize(tkeep, 16); + master.tKeep <= resize(tkeep, AXI_STREAM_MAX_TKEEP_WIDTH_C); end if; master.tLast <= tlast; master.tDest <= tDest; @@ -423,7 +411,7 @@ package body AxiStreamPkg is signal master : in AxiStreamMasterType; signal slave : out AxiStreamSlaveType; tData : out slv; - tKeep : out slv(15 downto 0); + tKeep : out slv(AXI_STREAM_MAX_TKEEP_WIDTH_C-1 downto 0); tLast : out sl; tDest : out slv(7 downto 0); tId : out slv(7 downto 0); @@ -579,16 +567,16 @@ package body AxiStreamPkg is size := size + c.TDATA_BYTES_C*8; -- Keep - size := size + ite( (c.TKEEP_MODE_C = TKEEP_NORMAL_C), c.TDATA_BYTES_C, -- TKEEP_NORMAL_C - ite( (c.TKEEP_MODE_C = TKEEP_COMP_C), bitSize(c.TDATA_BYTES_C-1), -- TKEEP_COMP_C - ite( (c.TKEEP_MODE_C = TKEEP_COUNT_C), 5, -- TKEEP_COUNT_C - 0))); -- TKEEP_FIXED_C + size := size + ite((c.TKEEP_MODE_C = TKEEP_NORMAL_C), c.TDATA_BYTES_C, -- TKEEP_NORMAL_C + ite((c.TKEEP_MODE_C = TKEEP_COMP_C), bitSize(c.TDATA_BYTES_C-1), -- TKEEP_COMP_C + ite((c.TKEEP_MODE_C = TKEEP_COUNT_C), bitSize(AXI_STREAM_MAX_TKEEP_WIDTH_C), -- TKEEP_COUNT_C + 0))); -- TKEEP_FIXED_C -- User bits size := size + ite(c.TUSER_MODE_C = TUSER_FIRST_LAST_C, c.TUSER_BITS_C*2, - ite(c.TUSER_MODE_C = TUSER_LAST_C, c.TUSER_BITS_C, - ite(c.TUSER_MODE_C = TUSER_NORMAL_C, c.TDATA_BYTES_C * c.TUSER_BITS_C, - 0))); -- TUSER_NONE_C + ite(c.TUSER_MODE_C = TUSER_LAST_C, c.TUSER_BITS_C, + ite(c.TUSER_MODE_C = TUSER_NORMAL_C, c.TDATA_BYTES_C * c.TUSER_BITS_C, + 0))); -- TUSER_NONE_C size := size + ite(c.TSTRB_EN_C, c.TDATA_BYTES_C, 0); -- Strobe bits size := size + c.TDEST_BITS_C; @@ -615,9 +603,9 @@ package body AxiStreamPkg is assignSlv(i, retValue, din.tKeep(c.TDATA_BYTES_C-1 downto 0)); elsif c.TKEEP_MODE_C = TKEEP_COMP_C then -- Assume lsb is present - assignSlv(i, retValue, toSlv(getTKeep(din.tKeep(c.TDATA_BYTES_C-1 downto 1)), bitSize(c.TDATA_BYTES_C-1))); + assignSlv(i, retValue, toSlv(getTKeep(din.tKeep(c.TDATA_BYTES_C-1 downto 1), c), bitSize(c.TDATA_BYTES_C-1))); elsif c.TKEEP_MODE_C = TKEEP_COUNT_C then - assignSlv(i, retValue, din.tKeep(4 downto 0)); + assignSlv(i, retValue, din.tKeep(bitSize(AXI_STREAM_MAX_TKEEP_WIDTH_C)-1 downto 0)); end if; -- TKEEP_FIXED_C uses 0 bits @@ -679,7 +667,7 @@ package body AxiStreamPkg is assignRecord(i, din, keep); master.tKeep := genTKeep(conv_integer(keep)+1); elsif c.TKEEP_MODE_C = TKEEP_COUNT_C then - assignRecord(i, din, master.tKeep(4 downto 0)); + assignRecord(i, din, master.tKeep(bitSize(AXI_STREAM_MAX_TKEEP_WIDTH_C)-1 downto 0)); else -- KEEP_MODE_C = TKEEP_FIXED_C master.tKeep := genTKeep(c.TDATA_BYTES_C); end if; diff --git a/axi/axi-stream/rtl/AxiStreamPrbsFlowCtrl.vhd b/axi/axi-stream/rtl/AxiStreamPrbsFlowCtrl.vhd index 6910bba633..38f36c3a7c 100644 --- a/axi/axi-stream/rtl/AxiStreamPrbsFlowCtrl.vhd +++ b/axi/axi-stream/rtl/AxiStreamPrbsFlowCtrl.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamPrbsFlowCtrl.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-10-27 --- Last update: 2017-10-27 ------------------------------------------------------------------------------- -- Description: Generates pseudo-random back pressure ------------------------------------------------------------------------------- diff --git a/axi/axi-stream/rtl/AxiStreamRepeater.vhd b/axi/axi-stream/rtl/AxiStreamRepeater.vhd new file mode 100644 index 0000000000..ddb9c89e6d --- /dev/null +++ b/axi/axi-stream/rtl/AxiStreamRepeater.vhd @@ -0,0 +1,180 @@ +------------------------------------------------------------------------------- +-- File : AxiStreamRepeater.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Block to connect a single incoming AXI stream to multiple outgoing AXI +-- streams +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +use work.StdRtlPkg.all; +use work.AxiStreamPkg.all; + +entity AxiStreamRepeater is + generic ( + TPD_G : time := 1 ns; + NUM_MASTERS_G : positive := 2; + INCR_AXIS_ID_G : boolean := false; -- true = overwrites the TID with a counter that increments after each TLAST (help with frame alignment down stream) + INPUT_PIPE_STAGES_G : natural := 0; + OUTPUT_PIPE_STAGES_G : natural := 0); + port ( + -- Clock and reset + axisClk : in sl; + axisRst : in sl; + -- Slave + sAxisMaster : in AxiStreamMasterType; + sAxisSlave : out AxiStreamSlaveType; + -- Masters + mAxisMasters : out AxiStreamMasterArray(NUM_MASTERS_G-1 downto 0); + mAxisSlaves : in AxiStreamSlaveArray(NUM_MASTERS_G-1 downto 0)); +end AxiStreamRepeater; + +architecture structure of AxiStreamRepeater is + + type RegType is record + tId : slv(7 downto 0); + slave : AxiStreamSlaveType; + masters : AxiStreamMasterArray(NUM_MASTERS_G-1 downto 0); + end record RegType; + + constant REG_INIT_C : RegType := ( + tId => (others => '0'), + slave => AXI_STREAM_SLAVE_INIT_C, + masters => (others => AXI_STREAM_MASTER_INIT_C)); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal inputAxisMaster : AxiStreamMasterType; + signal inputAxisSlave : AxiStreamSlaveType; + signal outputAxisMasters : AxiStreamMasterArray(NUM_MASTERS_G-1 downto 0); + signal outputAxisSlaves : AxiStreamSlaveArray(NUM_MASTERS_G-1 downto 0); + +begin + + ----------------- + -- Input pipeline + ----------------- + U_Input : entity work.AxiStreamPipeline + generic map ( + TPD_G => TPD_G, + PIPE_STAGES_G => INPUT_PIPE_STAGES_G) + port map ( + axisClk => axisClk, + axisRst => axisRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + mAxisMaster => inputAxisMaster, + mAxisSlave => inputAxisSlave); + + comb : process (axisRst, inputAxisMaster, outputAxisSlaves, r) is + variable v : RegType; + variable i : natural; + variable tValid : sl; + begin + -- Latch the current value + v := r; + + -- Reset strobing signals + v.slave.tReady := '0'; + tValid := '0'; + + -- Loop through the output lanes + for i in (NUM_MASTERS_G-1) downto 0 loop + + -- Check if the data was accepted + if outputAxisSlaves(i).tReady = '1' then + -- Reset the flag + v.masters(i).tValid := '0'; + end if; + + -- Check if the flag was not reset + if (v.masters(i).tValid = '1') then + -- Not ready to move data + tValid := '1'; + end if; + + end loop; + + -- Check if ready to move data + if (inputAxisMaster.tValid = '1') and (tValid = '0') then + + -- Accept the data + v.slave.tReady := '1'; + + -- Loop through the output lanes + for i in (NUM_MASTERS_G-1) downto 0 loop + + -- Move the data + v.masters(i) := inputAxisMaster; + + -- Checking if overriding TID + if(INCR_AXIS_ID_G)then + v.masters(i).tId := r.tId; + end if; + + end loop; + + -- Check for the end of the frame + if (inputAxisMaster.tLast = '1') then + -- Increment the counter + v.tId := r.tId + 1; + end if; + + end if; + + -- Outputs + inputAxisSlave <= v.slave; + outputAxisMasters <= r.masters; + + -- Reset + if (axisRst = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (axisClk) is + begin + if (rising_edge(axisClk)) then + r <= rin after TPD_G; + end if; + end process seq; + + ------------------ + -- Output pipeline + ------------------ + GEN_VEC : + for i in (NUM_MASTERS_G-1) downto 0 generate + + U_Output : entity work.AxiStreamPipeline + generic map ( + TPD_G => TPD_G, + PIPE_STAGES_G => OUTPUT_PIPE_STAGES_G) + port map ( + axisClk => axisClk, + axisRst => axisRst, + sAxisMaster => outputAxisMasters(i), + sAxisSlave => outputAxisSlaves(i), + mAxisMaster => mAxisMasters(i), + mAxisSlave => mAxisSlaves(i)); + + end generate GEN_VEC; + +end structure; diff --git a/axi/axi-stream/rtl/AxiStreamResize.vhd b/axi/axi-stream/rtl/AxiStreamResize.vhd index 983d372db6..4dafd3fdcb 100644 --- a/axi/axi-stream/rtl/AxiStreamResize.vhd +++ b/axi/axi-stream/rtl/AxiStreamResize.vhd @@ -1,244 +1,242 @@ -------------------------------------------------------------------------------- --- File : AxiStreamResize.vhd --- Company : SLAC National Accelerator Laboratory --- Created : 2016-06-16 --- Last update: 2016-06-16 -------------------------------------------------------------------------------- --- Description: --- Block to resize AXI Streams. Re-sizing is always little endian. --- Resizer should not be used when interleaving tDests -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -use work.StdRtlPkg.all; -use work.AxiStreamPkg.all; - -entity AxiStreamResize is - generic ( - - -- General Configurations - TPD_G : time := 1 ns; - READY_EN_G : boolean := true; - - -- AXI Stream Port Configurations - SLAVE_AXI_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C; - MASTER_AXI_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C - ); - port ( - - -- Clock and reset - axisClk : in sl; - axisRst : in sl; - - -- Slave Port - sAxisMaster : in AxiStreamMasterType; - sAxisSlave : out AxiStreamSlaveType; - - -- Master Port - mAxisMaster : out AxiStreamMasterType; - mAxisSlave : in AxiStreamSlaveType - ); -end AxiStreamResize; - -architecture rtl of AxiStreamResize is - - constant SLV_BYTES_C : integer := SLAVE_AXI_CONFIG_G.TDATA_BYTES_C; - constant MST_BYTES_C : integer := MASTER_AXI_CONFIG_G.TDATA_BYTES_C; - - constant SLV_USER_C : integer := SLAVE_AXI_CONFIG_G.TUSER_BITS_C; - constant MST_USER_C : integer := MASTER_AXI_CONFIG_G.TUSER_BITS_C; - - constant COUNT_C : integer := ite(SLV_BYTES_C > MST_BYTES_C, SLV_BYTES_C / MST_BYTES_C, MST_BYTES_C / SLV_BYTES_C); - - type RegType is record - count : slv(bitSize(COUNT_C)-1 downto 0); - obMaster : AxiStreamMasterType; - ibSlave : AxiStreamSlaveType; - end record RegType; - - constant REG_INIT_C : RegType := ( - count => (others => '0'), - obMaster => axiStreamMasterInit(MASTER_AXI_CONFIG_G), - ibSlave => AXI_STREAM_SLAVE_INIT_C - ); - - signal r : RegType := REG_INIT_C; - signal rin : RegType; - -begin - - -- Make sure data widths are appropriate. - assert ((SLV_BYTES_C >= MST_BYTES_C and SLV_BYTES_C mod MST_BYTES_C = 0) or - (MST_BYTES_C >= SLV_BYTES_C and MST_BYTES_C mod SLV_BYTES_C = 0)) - report "Data widths must be even number multiples of each other" severity failure; - - -- When going from a large bus to a small bus, ready is neccessary - assert (SLV_BYTES_C <= MST_BYTES_C or READY_EN_G = true) - report "READY_EN_G must be true if slave width is great than master" severity failure; - - comb : process (mAxisSlave, sAxisMaster, r) is - variable v : RegType; - variable ibM : AxiStreamMasterType; - variable idx : integer; -- index version of counter - variable byteCnt : integer; -- Number of valid bytes in incoming bus - variable bytes : integer; -- byte version of counter - begin - v := r; - idx := conv_integer(r.count); - bytes := (idx+1) * MST_BYTES_C; - if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - byteCnt := conv_integer(sAxisMaster.tKeep(4 downto 0)); - else - byteCnt := getTKeep(sAxisMaster.tKeep); - end if; - - -- Init ready - v.ibSlave.tReady := '0'; - - -- Choose ready source and clear valid - if READY_EN_G = false or mAxisSlave.tReady = '1' then - v.obMaster.tValid := '0'; - end if; - - -- Inbound data with normalized user bits (8 user bits) - ibM := sAxisMaster; - ibM.tUser := (others=>'0'); - if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - ibM.tKeep := genTKeep(byteCnt); - end if; - - for i in 0 to 15 loop - ibM.tUser((i*8)+(SLV_USER_C-1) downto (i*8)) := sAxisMaster.tUser((i*SLV_USER_C)+(SLV_USER_C-1) downto (i*SLV_USER_C)); - end loop; - - -- Pipeline advance - if v.obMaster.tValid = '0' then - - -- Increasing size - if MST_BYTES_C > SLV_BYTES_C then - v.ibSlave.tReady := '1'; - - -- init when count = 0 - if (r.count = 0) then - v.obMaster := axiStreamMasterInit(MASTER_AXI_CONFIG_G); - v.obMaster.tKeep := (others=>'0'); - v.obMaster.tStrb := (others=>'0'); - end if; - - v.obMaster.tData((SLV_BYTES_C*8*idx)+((SLV_BYTES_C*8)-1) downto (SLV_BYTES_C*8*idx)) := ibM.tData((SLV_BYTES_C*8)-1 downto 0); - v.obMaster.tUser((SLV_BYTES_C*8*idx)+((SLV_BYTES_C*8)-1) downto (SLV_BYTES_C*8*idx)) := ibM.tUser((SLV_BYTES_C*8)-1 downto 0); - v.obMaster.tStrb((SLV_BYTES_C*idx)+(SLV_BYTES_C-1) downto (SLV_BYTES_C*idx)) := ibM.tStrb(SLV_BYTES_C-1 downto 0); - v.obMaster.tKeep((SLV_BYTES_C*idx)+(SLV_BYTES_C-1) downto (SLV_BYTES_C*idx)) := ibM.tKeep(SLV_BYTES_C-1 downto 0); - - v.obMaster.tId := ibM.tId; - v.obMaster.tDest := ibM.tDest; - v.obMaster.tLast := ibM.tLast; - - -- Determine if we move data - if ibM.tValid = '1' then - if r.count = (COUNT_C-1) or ibM.tLast = '1' then - v.obMaster.tValid := '1'; - v.count := (others => '0'); - else - v.count := r.count + 1; - end if; - end if; - - -- Decreasing size - else - - v.obMaster := axiStreamMasterInit(MASTER_AXI_CONFIG_G); - - v.obMaster.tData((MST_BYTES_C*8)-1 downto 0) := ibM.tData((MST_BYTES_C*8*idx)+((MST_BYTES_C*8)-1) downto (MST_BYTES_C*8*idx)); - v.obMaster.tUser((MST_BYTES_C*8)-1 downto 0) := ibM.tUser((MST_BYTES_C*8*idx)+((MST_BYTES_C*8)-1) downto (MST_BYTES_C*8*idx)); - v.obMaster.tStrb(MST_BYTES_C-1 downto 0) := ibM.tStrb((MST_BYTES_C*idx)+(MST_BYTES_C-1) downto (MST_BYTES_C*idx)); - v.obMaster.tKeep(MST_BYTES_C-1 downto 0) := ibM.tKeep((MST_BYTES_C*idx)+(MST_BYTES_C-1) downto (MST_BYTES_C*idx)); - - v.obMaster.tId := ibM.tId; - v.obMaster.tDest := ibM.tDest; - - -- Determine if we move data - if ibM.tValid = '1' then - if (r.count = (COUNT_C-1)) or ((bytes >= byteCnt) and (ibM.tLast = '1')) then - v.count := (others => '0'); - v.ibSlave.tReady := '1'; - v.obMaster.tLast := ibM.tLast; - else - v.count := r.count + 1; - v.ibSlave.tReady := '0'; - v.obMaster.tLast := '0'; - end if; - end if; - - -- Drop transfers with no tKeep bits set, except on tLast - v.obMaster.tValid := ibM.tValid and (uOr(v.obMaster.tKeep(COUNT_C-1 downto 0)) or v.obMaster.tLast); - - end if; - end if; - - -- Resize disabled - if SLV_BYTES_C = MST_BYTES_C then - sAxisSlave <= mAxisSlave; - mAxisMaster <= sAxisMaster; - - -- Check for TKEEP_COUNT_C mode on either side - if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) or (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - - -- Check for TKEEP_COUNT_C mode on slave side only - if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) and (MASTER_AXI_CONFIG_G.TKEEP_MODE_C /= TKEEP_COUNT_C) then - mAxisMaster.tkeep <= genTKeep(conv_integer(sAxisMaster.tkeep(4 downto 0))); - - -- Check for TKEEP_COUNT_C mode on master side only - elsif (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C /= TKEEP_COUNT_C) and (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - mAxisMaster.tkeep <= toSlv(getTKeep(sAxisMaster.tKeep) ,16); - - -- Else both sides are TKEEP_COUNT_C mode - else - NULL; - end if; - end if; - - else - sAxisSlave <= v.ibSlave; - - -- Outbound data with proper user bits - mAxisMaster <= r.obMaster; - mAxisMaster.tUser <= (others=>'0'); - if (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - mAxisMaster.tKeep <= toSlv(getTKeep(r.obMaster.tKeep) ,16); - end if; - - for i in 0 to 15 loop - mAxisMaster.tUser((i*MST_USER_C)+(MST_USER_C-1) downto (i*MST_USER_C)) <= r.obMaster.tUser((i*8)+(MST_USER_C-1) downto (i*8)); - end loop; - end if; - - rin <= v; - - end process comb; - - seq : process (axisClk) is - begin - if (rising_edge(axisClk)) then - if axisRst = '1' or (SLV_BYTES_C = MST_BYTES_C) then - r <= REG_INIT_C after TPD_G; - else - r <= rin after TPD_G; - end if; - end if; - end process seq; - -end rtl; - +------------------------------------------------------------------------------- +-- File : AxiStreamResize.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Block to resize AXI Streams. Re-sizing is always little endian. +-- Resizer should not be used when interleaving tDests +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +use work.StdRtlPkg.all; +use work.AxiStreamPkg.all; + +entity AxiStreamResize is + generic ( + + -- General Configurations + TPD_G : time := 1 ns; + READY_EN_G : boolean := true; + + -- AXI Stream Port Configurations + SLAVE_AXI_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C; + MASTER_AXI_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C + ); + port ( + + -- Clock and reset + axisClk : in sl; + axisRst : in sl; + + -- Slave Port + sAxisMaster : in AxiStreamMasterType; + sAxisSlave : out AxiStreamSlaveType; + + -- Master Port + mAxisMaster : out AxiStreamMasterType; + mAxisSlave : in AxiStreamSlaveType + ); +end AxiStreamResize; + +architecture rtl of AxiStreamResize is + + constant SLV_BYTES_C : integer := SLAVE_AXI_CONFIG_G.TDATA_BYTES_C; + constant MST_BYTES_C : integer := MASTER_AXI_CONFIG_G.TDATA_BYTES_C; + + constant SLV_USER_C : integer := SLAVE_AXI_CONFIG_G.TUSER_BITS_C; + constant MST_USER_C : integer := MASTER_AXI_CONFIG_G.TUSER_BITS_C; + + constant COUNT_C : integer := ite(SLV_BYTES_C > MST_BYTES_C, SLV_BYTES_C / MST_BYTES_C, MST_BYTES_C / SLV_BYTES_C); + + type RegType is record + count : slv(bitSize(COUNT_C)-1 downto 0); + obMaster : AxiStreamMasterType; + ibSlave : AxiStreamSlaveType; + end record RegType; + + constant REG_INIT_C : RegType := ( + count => (others => '0'), + obMaster => axiStreamMasterInit(MASTER_AXI_CONFIG_G), + ibSlave => AXI_STREAM_SLAVE_INIT_C + ); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + +begin + + -- Make sure data widths are appropriate. + assert ((SLV_BYTES_C >= MST_BYTES_C and SLV_BYTES_C mod MST_BYTES_C = 0) or + (MST_BYTES_C >= SLV_BYTES_C and MST_BYTES_C mod SLV_BYTES_C = 0)) + report "Data widths must be even number multiples of each other" severity failure; + + -- When going from a large bus to a small bus, ready is necessary + assert (SLV_BYTES_C <= MST_BYTES_C or READY_EN_G = true) + report "READY_EN_G must be true if slave width is great than master" severity failure; + + comb : process (mAxisSlave, sAxisMaster, r) is + variable v : RegType; + variable ibM : AxiStreamMasterType; + variable idx : integer; -- index version of counter + variable byteCnt : integer; -- Number of valid bytes in incoming bus + variable bytes : integer; -- byte version of counter + begin + v := r; + idx := conv_integer(r.count); + bytes := (idx+1) * MST_BYTES_C; + if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then + byteCnt := conv_integer(sAxisMaster.tKeep(bitSize(SLAVE_AXI_CONFIG_G.TDATA_BYTES_C)-1 downto 0)); + else + byteCnt := getTKeep(sAxisMaster.tKeep,SLAVE_AXI_CONFIG_G); + end if; + + -- Init ready + v.ibSlave.tReady := '0'; + + -- Choose ready source and clear valid + if READY_EN_G = false or mAxisSlave.tReady = '1' then + v.obMaster.tValid := '0'; + end if; + + -- Inbound data with normalized user bits (8 user bits) + ibM := sAxisMaster; + ibM.tUser := (others=>'0'); + if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then + ibM.tKeep := genTKeep(byteCnt); + end if; + + for i in 0 to AXI_STREAM_MAX_TKEEP_WIDTH_C-1 loop + ibM.tUser((i*8)+(SLV_USER_C-1) downto (i*8)) := sAxisMaster.tUser((i*SLV_USER_C)+(SLV_USER_C-1) downto (i*SLV_USER_C)); + end loop; + + -- Pipeline advance + if v.obMaster.tValid = '0' then + + -- Increasing size + if MST_BYTES_C > SLV_BYTES_C then + v.ibSlave.tReady := '1'; + + -- init when count = 0 + if (r.count = 0) then + v.obMaster := axiStreamMasterInit(MASTER_AXI_CONFIG_G); + v.obMaster.tKeep := (others=>'0'); + v.obMaster.tStrb := (others=>'0'); + end if; + + v.obMaster.tData((SLV_BYTES_C*8*idx)+((SLV_BYTES_C*8)-1) downto (SLV_BYTES_C*8*idx)) := ibM.tData((SLV_BYTES_C*8)-1 downto 0); + v.obMaster.tUser((SLV_BYTES_C*8*idx)+((SLV_BYTES_C*8)-1) downto (SLV_BYTES_C*8*idx)) := ibM.tUser((SLV_BYTES_C*8)-1 downto 0); + v.obMaster.tStrb((SLV_BYTES_C*idx)+(SLV_BYTES_C-1) downto (SLV_BYTES_C*idx)) := ibM.tStrb(SLV_BYTES_C-1 downto 0); + v.obMaster.tKeep((SLV_BYTES_C*idx)+(SLV_BYTES_C-1) downto (SLV_BYTES_C*idx)) := ibM.tKeep(SLV_BYTES_C-1 downto 0); + + v.obMaster.tId := ibM.tId; + v.obMaster.tDest := ibM.tDest; + v.obMaster.tLast := ibM.tLast; + + -- Determine if we move data + if ibM.tValid = '1' then + if r.count = (COUNT_C-1) or ibM.tLast = '1' then + v.obMaster.tValid := '1'; + v.count := (others => '0'); + else + v.count := r.count + 1; + end if; + end if; + + -- Decreasing size + else + + v.obMaster := axiStreamMasterInit(MASTER_AXI_CONFIG_G); + + v.obMaster.tData((MST_BYTES_C*8)-1 downto 0) := ibM.tData((MST_BYTES_C*8*idx)+((MST_BYTES_C*8)-1) downto (MST_BYTES_C*8*idx)); + v.obMaster.tUser((MST_BYTES_C*8)-1 downto 0) := ibM.tUser((MST_BYTES_C*8*idx)+((MST_BYTES_C*8)-1) downto (MST_BYTES_C*8*idx)); + v.obMaster.tStrb(MST_BYTES_C-1 downto 0) := ibM.tStrb((MST_BYTES_C*idx)+(MST_BYTES_C-1) downto (MST_BYTES_C*idx)); + v.obMaster.tKeep(MST_BYTES_C-1 downto 0) := ibM.tKeep((MST_BYTES_C*idx)+(MST_BYTES_C-1) downto (MST_BYTES_C*idx)); + + v.obMaster.tId := ibM.tId; + v.obMaster.tDest := ibM.tDest; + + -- Determine if we move data + if ibM.tValid = '1' then + if (r.count = (COUNT_C-1)) or ((bytes >= byteCnt) and (ibM.tLast = '1')) then + v.count := (others => '0'); + v.ibSlave.tReady := '1'; + v.obMaster.tLast := ibM.tLast; + else + v.count := r.count + 1; + v.ibSlave.tReady := '0'; + v.obMaster.tLast := '0'; + end if; + end if; + + -- Drop transfers with no tKeep bits set, except on tLast + v.obMaster.tValid := ibM.tValid and (uOr(v.obMaster.tKeep(COUNT_C-1 downto 0)) or v.obMaster.tLast); + + end if; + end if; + + -- Resize disabled + if SLV_BYTES_C = MST_BYTES_C then + sAxisSlave <= mAxisSlave; + mAxisMaster <= sAxisMaster; + + -- Check for TKEEP_COUNT_C mode on either side + if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) or (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then + + -- Check for TKEEP_COUNT_C mode on slave side only + if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) and (MASTER_AXI_CONFIG_G.TKEEP_MODE_C /= TKEEP_COUNT_C) then + mAxisMaster.tkeep <= genTKeep(conv_integer(sAxisMaster.tkeep(bitSize(SLAVE_AXI_CONFIG_G.TDATA_BYTES_C)-1 downto 0))); + + -- Check for TKEEP_COUNT_C mode on master side only + elsif (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C /= TKEEP_COUNT_C) and (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then + mAxisMaster.tkeep <= toSlv(getTKeep(sAxisMaster.tKeep,SLAVE_AXI_CONFIG_G),AXI_STREAM_MAX_TKEEP_WIDTH_C); + + -- Else both sides are TKEEP_COUNT_C mode + else + NULL; + end if; + end if; + + else + sAxisSlave <= v.ibSlave; + + -- Outbound data with proper user bits + mAxisMaster <= r.obMaster; + mAxisMaster.tUser <= (others=>'0'); + if (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then + mAxisMaster.tKeep <= toSlv(getTKeep(r.obMaster.tKeep,MASTER_AXI_CONFIG_G), AXI_STREAM_MAX_TKEEP_WIDTH_C); + end if; + + for i in 0 to AXI_STREAM_MAX_TKEEP_WIDTH_C-1 loop + mAxisMaster.tUser((i*MST_USER_C)+(MST_USER_C-1) downto (i*MST_USER_C)) <= r.obMaster.tUser((i*8)+(MST_USER_C-1) downto (i*8)); + end loop; + end if; + + rin <= v; + + end process comb; + + seq : process (axisClk) is + begin + if (rising_edge(axisClk)) then + if axisRst = '1' or (SLV_BYTES_C = MST_BYTES_C) then + r <= REG_INIT_C after TPD_G; + else + r <= rin after TPD_G; + end if; + end if; + end process seq; + +end rtl; + diff --git a/axi/axi-stream/rtl/AxiStreamScatterGather.vhd b/axi/axi-stream/rtl/AxiStreamScatterGather.vhd index 5d1baef391..f572831ce9 100644 --- a/axi/axi-stream/rtl/AxiStreamScatterGather.vhd +++ b/axi/axi-stream/rtl/AxiStreamScatterGather.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamScatterGather.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-03-01 --- Last update: 2015-04-08 ------------------------------------------------------------------------------- -- Description: Takes 6 APV bursts with 128 channels of data each and -- transforms them into 128 "MultiSamples" with 6 samples each. diff --git a/axi/axi-stream/rtl/AxiStreamShift.vhd b/axi/axi-stream/rtl/AxiStreamShift.vhd index 524036635c..7483e46938 100644 --- a/axi/axi-stream/rtl/AxiStreamShift.vhd +++ b/axi/axi-stream/rtl/AxiStreamShift.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamShift.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-25 --- Last update: 2016-10-27 ------------------------------------------------------------------------------- -- Description: -- Block to shift data bytes within an AXI stream. Both left and right shifting @@ -257,9 +255,9 @@ begin end case; -- Mask off the unused tStrb and tKeep bits - if (AXIS_CONFIG_G.TDATA_BYTES_C /= 16) then - v.master.tKeep(15 downto AXIS_CONFIG_G.TDATA_BYTES_C) := (others => '0'); - v.master.tStrb(15 downto AXIS_CONFIG_G.TDATA_BYTES_C) := (others => '0'); + if (AXIS_CONFIG_G.TDATA_BYTES_C /= AXI_STREAM_MAX_TKEEP_WIDTH_C) then + v.master.tKeep(AXI_STREAM_MAX_TKEEP_WIDTH_C-1 downto AXIS_CONFIG_G.TDATA_BYTES_C) := (others => '0'); + v.master.tStrb(AXI_STREAM_MAX_TKEEP_WIDTH_C-1 downto AXIS_CONFIG_G.TDATA_BYTES_C) := (others => '0'); end if; -- Combinatorial outputs before the reset diff --git a/axi/axi-stream/rtl/AxiStreamTap.vhd b/axi/axi-stream/rtl/AxiStreamTap.vhd index 84f1eb4bb1..ce93ad7d5b 100644 --- a/axi/axi-stream/rtl/AxiStreamTap.vhd +++ b/axi/axi-stream/rtl/AxiStreamTap.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamTap.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-25 --- Last update: 2016-09-06 ------------------------------------------------------------------------------- -- Description: -- Block to extract and re-isnert a destination from an interleaved stream. diff --git a/axi/axi-stream/tb/AxiStreamBytePackerTb.vhd b/axi/axi-stream/tb/AxiStreamBytePackerTb.vhd index 661dd222ce..5c26503586 100755 --- a/axi/axi-stream/tb/AxiStreamBytePackerTb.vhd +++ b/axi/axi-stream/tb/AxiStreamBytePackerTb.vhd @@ -1,6 +1,5 @@ ------------------------------------------------------------------------------- -- File : AxiStreamBytePackerTb.vhd --- Created : 2017-11-13 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for AxiStreamBytePacker ------------------------------------------------------------------------------- diff --git a/axi/axi-stream/tb/AxiStreamFlushTb.vhd b/axi/axi-stream/tb/AxiStreamFlushTb.vhd index 52d67373e1..4ec9a5ffb4 100644 --- a/axi/axi-stream/tb/AxiStreamFlushTb.vhd +++ b/axi/axi-stream/tb/AxiStreamFlushTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamFlushTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-25 --- Last update: 2015-08-25 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the AxiStreamFlush module ------------------------------------------------------------------------------- diff --git a/axi/axi-stream/tb/AxiStreamMuxTb.vhd b/axi/axi-stream/tb/AxiStreamMuxTb.vhd index 3a003ad21d..f7eec19eb8 100644 --- a/axi/axi-stream/tb/AxiStreamMuxTb.vhd +++ b/axi/axi-stream/tb/AxiStreamMuxTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamMuxTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-25 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the SsiFifo module ------------------------------------------------------------------------------- diff --git a/axi/axi-stream/tb/AxiStreamPipelineTb.vhd b/axi/axi-stream/tb/AxiStreamPipelineTb.vhd index aad66f49f1..b45248e9fe 100644 --- a/axi/axi-stream/tb/AxiStreamPipelineTb.vhd +++ b/axi/axi-stream/tb/AxiStreamPipelineTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamPipelineTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-02 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the AxiStreamPipelineTb module ------------------------------------------------------------------------------- @@ -30,8 +28,8 @@ architecture testbed of AxiStreamPipelineTb is constant CLK_PERIOD_C : time := 4 ns; constant TPD_C : time := CLK_PERIOD_C/4; constant PIPE_STAGES_C : natural := 1; - constant MAX_CNT_C : slv(127 downto 0) := x"000000000000000019999997E241C000"; - -- constant MAX_CNT_C : slv(127 downto 0) := x"000000000000000000000000000000FF"; + constant MAX_CNT_C : slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0) := resize(x"000000000000000019999997E241C000",AXI_STREAM_MAX_TDATA_WIDTH_C); + -- constant MAX_CNT_C : slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0) := resize(x"000000000000000000000000000000FF",AXI_STREAM_MAX_TDATA_WIDTH_C); constant PRBS_TAPS_C : NaturalArray := (0 => 31, 1 => 6, 2 => 2, 3 => 1); type RegType is record @@ -39,14 +37,14 @@ architecture testbed of AxiStreamPipelineTb is failed : sl; wrPbrs : slv(31 downto 0); wrSof : sl; - wrPkt : slv(127 downto 0); - wrCnt : slv(127 downto 0); - wrSize : slv(127 downto 0); + wrPkt : slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0); + wrCnt : slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0); + wrSize : slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0); rdPbrs : slv(31 downto 0); rdSof : sl; - rdPkt : slv(127 downto 0); - rdCnt : slv(127 downto 0); - rdSize : slv(127 downto 0); + rdPkt : slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0); + rdCnt : slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0); + rdSize : slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0); sAxisMaster : AxiStreamMasterType; mAxisSlave : AxiStreamSlaveType; end record RegType; diff --git a/axi/axi-stream/tb/fifo_tb.vhd b/axi/axi-stream/tb/fifo_tb.vhd index 5c4c1e7354..aadd8712fe 100644 --- a/axi/axi-stream/tb/fifo_tb.vhd +++ b/axi/axi-stream/tb/fifo_tb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : fifo_tb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-02 --- Last update: 2016-09-06 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for FIFO module ------------------------------------------------------------------------------- diff --git a/axi/axi-stream/tb/rogue_tb.vhd b/axi/axi-stream/tb/rogue_tb.vhd index e8b325b35b..677402fd01 100644 --- a/axi/axi-stream/tb/rogue_tb.vhd +++ b/axi/axi-stream/tb/rogue_tb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : rogue_tb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-02 --- Last update: 2016-09-06 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for ROGUE module ------------------------------------------------------------------------------- diff --git a/axi/axi-stream/tb/stream_tb.vhd b/axi/axi-stream/tb/stream_tb.vhd index ad7c52be62..7d3a27c602 100644 --- a/axi/axi-stream/tb/stream_tb.vhd +++ b/axi/axi-stream/tb/stream_tb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : stream_tb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-02 --- Last update: 2016-09-06 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for STREAM module ------------------------------------------------------------------------------- diff --git a/axi/axi-stream/tb/vcs_tb.vhd b/axi/axi-stream/tb/vcs_tb.vhd index f86c2ab824..a23bcf1978 100644 --- a/axi/axi-stream/tb/vcs_tb.vhd +++ b/axi/axi-stream/tb/vcs_tb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : vcs_tb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-02 --- Last update: 2018-01-22 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for VCS module ------------------------------------------------------------------------------- diff --git a/axi/axi4/rtl/AxiMemTester.vhd b/axi/axi4/rtl/AxiMemTester.vhd index 463b60c838..baa4bbf0de 100644 --- a/axi/axi4/rtl/AxiMemTester.vhd +++ b/axi/axi4/rtl/AxiMemTester.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiMemTester.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-07-28 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: General Purpose AXI4 memory tester ------------------------------------------------------------------------------- @@ -58,10 +56,12 @@ architecture rtl of AxiMemTester is constant STOP_C : slv(AXI_CONFIG_G.ADDR_WIDTH_C-1 downto 0) := STOP_ADDR_G(AXI_CONFIG_G.ADDR_WIDTH_C-1 downto 0); constant STOP_ADDR_C : slv(AXI_CONFIG_G.ADDR_WIDTH_C-1 downto 0) := STOP_C(AXI_CONFIG_G.ADDR_WIDTH_C-1 downto 12) & x"000"; - constant DATA_BITS_C : natural := 8*AXI_CONFIG_G.DATA_BYTES_C; - constant AXI_LEN_C : slv(7 downto 0) := getAxiLen(AXI_CONFIG_G, BURST_LEN_G); + constant DATA_BITS_C : natural := 8*AXI_CONFIG_G.DATA_BYTES_C; + constant AXI_LEN_C : slv(7 downto 0) := getAxiLen(AXI_CONFIG_G, BURST_LEN_G); constant PRBS_TAPS_C : NaturalArray := (0 => (DATA_BITS_C-1), 1 => (DATA_BITS_C/2), 2 => (DATA_BITS_C/4)); + + constant DATA_SYNC_BITS_C : natural := ite(DATA_BITS_C<1024, DATA_BITS_C, 1024); function GenSeed return slv is variable retVar : slv(DATA_BITS_C-1 downto 0); @@ -97,6 +97,8 @@ architecture rtl of AxiMemTester is len : slv(7 downto 0); address : slv(63 downto 0); randomData : slv(DATA_BITS_C-1 downto 0); + rData : slv(DATA_BITS_C-1 downto 0); + rPattern : slv(DATA_BITS_C-1 downto 0); state : StateType; axiWriteMaster : AxiWriteMasterType; axiReadMaster : AxiReadMasterType; @@ -115,6 +117,8 @@ architecture rtl of AxiMemTester is len => AXI_LEN_C, address => (others => '0'), randomData => PRBS_SEED_C, + rData => (others => '0'), + rPattern => (others => '0'), state => IDLE_S, axiWriteMaster => AXI_WRITE_MASTER_INIT_C, axiReadMaster => AXI_READ_MASTER_INIT_C); @@ -126,6 +130,13 @@ architecture rtl of AxiMemTester is signal error : sl; signal wTimer : slv(31 downto 0); signal rTimer : slv(31 downto 0); + signal wErrResp : sl; + signal rErrResp : sl; + signal rErrData : sl; + signal rDataIn : slv(DATA_SYNC_BITS_C-1 downto 0); + signal rPatternIn : slv(DATA_SYNC_BITS_C-1 downto 0); + signal rDataOut : slv(1023 downto 0); + signal rPatternOut : slv(1023 downto 0); type RegLiteType is record memReady : sl; @@ -264,6 +275,9 @@ begin ---------------------------------------------------------------------- when READ_DATA_S => if (v.axiReadMaster.arvalid = '0') and (axiReadSlave.rvalid = '1') then + -- Save data for AXIL access + v.rData := axiReadSlave.rdata(DATA_BITS_C-1 downto 0); + v.rPattern := r.randomData(DATA_BITS_C-1 downto 0); -- Compare the data if r.randomData(DATA_BITS_C-1 downto 0) /= axiReadSlave.rdata(DATA_BITS_C-1 downto 0) then -- Set the flag @@ -395,9 +409,53 @@ begin -- Read Ports (rd_clk domain) rd_clk => axilClk, dout => rTimer); - + + Sync_4 : entity work.Synchronizer + generic map ( + TPD_G => TPD_G) + port map ( + clk => axilClk, + dataIn => r.wErrResp, + dataOut => wErrResp); + + Sync_5 : entity work.Synchronizer + generic map ( + TPD_G => TPD_G) + port map ( + clk => axilClk, + dataIn => r.rErrResp, + dataOut => rErrResp); + + Sync_6 : entity work.Synchronizer + generic map ( + TPD_G => TPD_G) + port map ( + clk => axilClk, + dataIn => r.rErrData, + dataOut => rErrData); + + rDataIn <= r.rData(DATA_SYNC_BITS_C-1 downto 0); + Sync_7 : entity work.SynchronizerVector + generic map ( + TPD_G => TPD_G, + WIDTH_G => DATA_SYNC_BITS_C) + port map ( + clk => axilClk, + dataIn => rDataIn, + dataOut => rDataOut(DATA_SYNC_BITS_C-1 downto 0)); + + rPatternIn <= r.rPattern(DATA_SYNC_BITS_C-1 downto 0); + Sync_8 : entity work.SynchronizerVector + generic map ( + TPD_G => TPD_G, + WIDTH_G => DATA_SYNC_BITS_C) + port map ( + clk => axilClk, + dataIn => rPatternIn, + dataOut => rPatternOut(DATA_SYNC_BITS_C-1 downto 0)); + combLite : process (axilReadMaster, axilRst, axilWriteMaster, done, error, - rLite, rTimer, wTimer) is + rLite, rTimer, wTimer, wErrResp, rErrResp, rErrData, rDataOut, rPatternOut) is variable v : RegLiteType; variable regCon : AxiLiteEndPointType; begin @@ -426,6 +484,13 @@ begin axiSlaveRegisterR(regCon, x"120", 0, toSlv(AXI_CONFIG_G.ADDR_WIDTH_C, 32)); axiSlaveRegisterR(regCon, x"124", 0, toSlv(AXI_CONFIG_G.DATA_BYTES_C, 32)); axiSlaveRegisterR(regCon, x"128", 0, toSlv(AXI_CONFIG_G.ID_BITS_C, 32)); + axiSlaveRegisterR(regCon, x"12C", 0, wErrResp); + axiSlaveRegisterR(regCon, x"12C", 1, rErrResp); + axiSlaveRegisterR(regCon, x"12C", 2, rErrData); + for i in 0 to 31 loop + axiSlaveRegisterR(regCon, x"130"+toSlv(i*4,12), 0, rDataOut(31+i*32 downto 0+i*32)); + axiSlaveRegisterR(regCon, x"1B0"+toSlv(i*4,12), 0, rPatternOut(31+i*32 downto 0+i*32)); + end loop; -- Closeout the transaction axiSlaveDefault(regCon, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C); diff --git a/axi/axi4/rtl/AxiPkg.vhd b/axi/axi4/rtl/AxiPkg.vhd index 42bb8e0e7f..38faa0a4f9 100644 --- a/axi/axi4/rtl/AxiPkg.vhd +++ b/axi/axi4/rtl/AxiPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-04-02 --- Last update: 2017-12-12 ------------------------------------------------------------------------------- -- Description: AXI4 Package File ------------------------------------------------------------------------------- @@ -447,10 +445,18 @@ package body AxiPkg is begin tempSlv := (others => '0'); - tempSlv(AxiConfig.LEN_BITS_C+addrLsb downto addrLsb) - := axiRead.arlen(AxiConfig.LEN_BITS_C-1 downto 0) + toSlv(1, AxiConfig.LEN_BITS_C+1); + if (AxiConfig.DATA_BYTES_C>1) then - tempSlv := tempSlv - axiRead.araddr(addrLsb-1 downto 0); + tempSlv(AxiConfig.LEN_BITS_C+addrLsb downto addrLsb) + := axiRead.arlen(AxiConfig.LEN_BITS_C-1 downto 0) + toSlv(1, AxiConfig.LEN_BITS_C+1); + + tempSlv := tempSlv - axiRead.araddr(addrLsb-1 downto 0); + + else + + tempSlv(AxiConfig.LEN_BITS_C downto 0) := axiRead.arlen(AxiConfig.LEN_BITS_C-1 downto 0) + toSlv(1, AxiConfig.LEN_BITS_C+1); + + end if; return(tempSlv); end function getAxiReadBytes; diff --git a/axi/axi4/rtl/AxiRam.vhd b/axi/axi4/rtl/AxiRam.vhd new file mode 100644 index 0000000000..9838160a93 --- /dev/null +++ b/axi/axi4/rtl/AxiRam.vhd @@ -0,0 +1,413 @@ +------------------------------------------------------------------------------- +-- File : AxiRam.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: General AXI RAM Module +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.StdRtlPkg.all; +use work.AxiPkg.all; + +entity AxiRam is + generic ( + TPD_G : time := 1 ns; + SYNTH_MODE_G : string := "inferred"; + MEMORY_TYPE_G : string := "block"; + READ_LATENCY_G : natural range 0 to 2 := 2; + AXI_CONFIG_G : AxiConfigType := axiConfig(16, 8, 4, 8)); + port ( + -- Clock and Reset + axiClk : in sl; + axiRst : in sl; + -- Slave Write Interface + sAxiWriteMaster : in AxiWriteMasterType; + sAxiWriteSlave : out AxiWriteSlaveType; + -- Slave Read Interface + sAxiReadMaster : in AxiReadMasterType; + sAxiReadSlave : out AxiReadSlaveType); +end AxiRam; + +architecture structure of AxiRam is + + constant DATA_BYTES_C : positive := AXI_CONFIG_G.DATA_BYTES_C; + constant DATA_WIDTH_C : positive := 8*DATA_BYTES_C; + constant OFFSET_C : positive := ite(DATA_BYTES_C = 1, 0, log2(DATA_BYTES_C)); + constant ADDR_WIDTH_C : positive := AXI_CONFIG_G.ADDR_WIDTH_C-OFFSET_C; + + type WrStateType is ( + WR_ADDR_S, + WR_DATA_S, + WR_BLOWOFF_S); + + type RdStateType is ( + RD_ADDR_S, + RD_PIPELINE_S, + RD_DATA_S); + + type RegType is record + -- Write Signals + wrData : slv(DATA_WIDTH_C-1 downto 0); + wrAddr : slv(ADDR_WIDTH_C-1 downto 0); + wstrb : slv(DATA_BYTES_C-1 downto 0); + wid : slv(31 downto 0); + awlen : slv(7 downto 0); + sAxiWriteSlave : AxiWriteSlaveType; + wrState : WrStateType; + -- Read Signals + rdAddr : slv(ADDR_WIDTH_C-1 downto 0); + rid : slv(31 downto 0); + arlen : slv(7 downto 0); + sAxiReadSlave : AxiReadSlaveType; + rdEn : slv(1 downto 0); + rdLat : slv(1 downto 0); + rdState : RdStateType; + end record; + + constant REG_INIT_C : RegType := ( + -- Write Signals + wrData => (others => '0'), + wrAddr => (others => '0'), + wstrb => (others => '0'), + wid => (others => '0'), + awlen => (others => '0'), + sAxiWriteSlave => AXI_WRITE_SLAVE_INIT_C, + wrState => WR_ADDR_S, + -- Read Signals + rdAddr => (others => '0'), + rid => (others => '0'), + arlen => (others => '0'), + sAxiReadSlave => AXI_READ_SLAVE_INIT_C, + rdEn => (others => '0'), + rdLat => (others => '0'), + rdState => RD_ADDR_S); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + + signal wrEn : sl; + signal wrData : slv(DATA_WIDTH_C-1 downto 0); + signal wrAddr : slv(ADDR_WIDTH_C-1 downto 0); + signal wstrb : slv(DATA_BYTES_C-1 downto 0); + + signal rdEn : slv(1 downto 0); + signal rdData : slv(DATA_WIDTH_C-1 downto 0); + signal rdAddr : slv(ADDR_WIDTH_C-1 downto 0); + +begin + + assert (SYNTH_MODE_G /= "inferred") or + ((SYNTH_MODE_G = "inferred") and (READ_LATENCY_G > 0)) + report "AxiRam: Inferred SimpleDualPortRam does not support zero latency reads" severity failure; + + GEN_XPM : if (SYNTH_MODE_G = "xpm") generate + U_RAM : entity work.SimpleDualPortRamXpm + generic map ( + TPD_G => TPD_G, + COMMON_CLK_G => true, + MEMORY_TYPE_G => MEMORY_TYPE_G, + READ_LATENCY_G => READ_LATENCY_G, + DATA_WIDTH_G => DATA_WIDTH_C, + BYTE_WR_EN_G => true, + BYTE_WIDTH_G => 8, + ADDR_WIDTH_G => ADDR_WIDTH_C) + port map ( + -- Port A + ena => wrEn, + clka => axiClk, + addra => wrAddr, + dina => wrData, + wea => wstrb, + -- Read Interface + enb => rdEn(0), + clkb => axiClk, + addrb => rdAddr, + doutb => rdData, + regceb => rdEn(1)); + end generate; + + GEN_ALTERA : if (SYNTH_MODE_G = "altera_mf") generate + U_RAM : entity work.SimpleDualPortRamAlteraMf + generic map ( + TPD_G => TPD_G, + COMMON_CLK_G => true, + MEMORY_TYPE_G => MEMORY_TYPE_G, + READ_LATENCY_G => READ_LATENCY_G, + DATA_WIDTH_G => DATA_WIDTH_C, + BYTE_WR_EN_G => true, + BYTE_WIDTH_G => 8, + ADDR_WIDTH_G => ADDR_WIDTH_C) + port map ( + -- Port A + ena => wrEn, + clka => axiClk, + addra => wrAddr, + dina => wrData, + wea => wstrb, + -- Read Interface + enb => rdEn(0), + clkb => axiClk, + addrb => rdAddr, + doutb => rdData, + regceb => rdEn(1)); + end generate; + + GEN_INFERRED : if (SYNTH_MODE_G = "inferred") generate + U_RAM : entity work.SimpleDualPortRam + generic map ( + TPD_G => TPD_G, + BRAM_EN_G => ite(READ_LATENCY_G = 0, false, true), + DOB_REG_G => ite(READ_LATENCY_G = 2, true, false), + BYTE_WR_EN_G => true, + DATA_WIDTH_G => DATA_WIDTH_C, + BYTE_WIDTH_G => 8, + ADDR_WIDTH_G => ADDR_WIDTH_C) + port map ( + -- Port A + ena => wrEn, + clka => axiClk, + addra => wrAddr, + dina => wrData, + weaByte => wstrb, + -- Read Interface + enb => rdEn(0), + clkb => axiClk, + addrb => rdAddr, + doutb => rdData, + regceb => rdEn(1)); + end generate; + + comb : process (axiRst, r, rdData, sAxiReadMaster, sAxiWriteMaster) is + variable v : RegType; + begin + -- Latch the current value + v := r; + + ---------------------------------------------------------------------- + -- AXI Write Logic -- + ---------------------------------------------------------------------- + + -- Reset the strobes + v.wstrb := (others => '0'); + v.sAxiWriteSlave.awready := '0'; + v.sAxiWriteSlave.wready := '0'; + if (sAxiWriteMaster.bready = '1') then + v.sAxiWriteSlave.bvalid := '0'; + end if; + + -- Write State Machine + case (r.wrState) is + ---------------------------------------------------------------------- + when WR_ADDR_S => + -- Wait for the Address transaction + if (sAxiWriteMaster.awvalid = '1') then + -- Accept the transaction + v.sAxiWriteSlave.awready := '1'; + -- Slave the channel ID + v.wid := sAxiWriteMaster.awid; + -- Save the address + v.wrAddr := sAxiWriteMaster.awaddr((ADDR_WIDTH_C-1)+OFFSET_C downto OFFSET_C); + -- Pre-decrement (registered output) + v.wrAddr := v.wrAddr - 1; + -- latch the length + v.awlen := sAxiWriteMaster.awlen; + -- Next State + v.wrState := WR_DATA_S; + end if; + ---------------------------------------------------------------------- + when WR_DATA_S => + -- Check if ready to move data + if (sAxiWriteMaster.wvalid = '1') and (r.sAxiWriteSlave.bvalid = '0') then + -- Accept the data + v.sAxiWriteSlave.wready := '1'; + -- Increment the address + v.wrAddr := r.wrAddr + 1; + -- Write the data to RAM + v.wstrb := sAxiWriteMaster.wstrb(DATA_BYTES_C-1 downto 0); + v.wrData := sAxiWriteMaster.wdata(DATA_WIDTH_C-1 downto 0); + -- Decrement the counter + v.awlen := r.awlen - 1; + -- Check for last transfer + if (sAxiWriteMaster.wlast = '1') or (r.awlen = 0) then + v.sAxiWriteSlave.bvalid := '1'; + v.sAxiWriteSlave.bid := r.wid; + -- Check alignment + if (sAxiWriteMaster.wlast = '1') and (r.awlen = 0) then + -- Access OK + v.sAxiWriteSlave.bresp := "00"; + -- Next State + v.wrState := WR_ADDR_S; + else + -- Slave Error + v.sAxiWriteSlave.bresp := "10"; + -- Check for last transfer + if (sAxiWriteMaster.wlast = '1') then + -- Next State + v.wrState := WR_ADDR_S; + else + -- Next State + v.wrState := WR_BLOWOFF_S; + end if; + end if; + end if; + end if; + ---------------------------------------------------------------------- + when WR_BLOWOFF_S => + -- Blow off the data + v.sAxiWriteSlave.wready := '1'; + -- Check for last transfer + if (sAxiWriteMaster.wvalid = '1') and (sAxiWriteMaster.wlast = '1') then + -- Next State + v.wrState := WR_ADDR_S; + end if; + ---------------------------------------------------------------------- + end case; + + -- Outputs + wrEn <= uOr(r.wstrb); + wstrb <= r.wstrb; + wrAddr <= r.wrAddr; + wrData <= r.wrData; + + -------------------------- + -- sAxiWriteSlave's Outputs + -------------------------- + -- Write address channel + sAxiWriteSlave.awready <= v.sAxiWriteSlave.awready; + -- Write data channel + sAxiWriteSlave.wready <= v.sAxiWriteSlave.wready; + -- Write ack channel + sAxiWriteSlave.bresp <= r.sAxiWriteSlave.bresp; + sAxiWriteSlave.bvalid <= r.sAxiWriteSlave.bvalid; + sAxiWriteSlave.bid <= r.sAxiWriteSlave.bid; + + ---------------------------------------------------------------------- + -- AXI Read Logic -- + ---------------------------------------------------------------------- + + -- Reset the strobes + v.sAxiReadSlave.arready := '0'; + if (sAxiReadMaster.rready = '1') then + v.sAxiReadSlave.rvalid := '0'; + v.sAxiReadSlave.rlast := '0'; + end if; + + -- Write State Machine + case (r.rdState) is + ---------------------------------------------------------------------- + when RD_ADDR_S => + -- Wait for the Address transaction + if (sAxiReadMaster.arvalid = '1') then + -- Accept the transaction + v.sAxiReadSlave.arready := '1'; + -- Slave the channel ID + v.rid := sAxiReadMaster.arid; + -- Save the address + v.rdAddr := sAxiReadMaster.araddr((ADDR_WIDTH_C-1)+OFFSET_C downto OFFSET_C); + -- Enable RAM reads + v.rdEn := "11"; + -- latch the length + v.arlen := sAxiReadMaster.arlen; + -- Check the read latency + if (READ_LATENCY_G = 0) then + -- Next State + v.rdState := RD_DATA_S; + else + -- Next State + v.rdState := RD_PIPELINE_S; + end if; + end if; + ---------------------------------------------------------------------- + when RD_PIPELINE_S => + -- Enable RAM reads + v.rdEn := "11"; + -- Increment the address + v.rdAddr := r.rdAddr + 1; + -- Check if RAM pipeline is filled + if (r.rdLat = READ_LATENCY_G-1) then + -- Reset the counter + v.rdLat := (others => '0'); + -- Next State + v.rdState := RD_DATA_S; + else + -- Increment the counter + v.rdLat := r.rdLat + 1; + end if; + ---------------------------------------------------------------------- + when RD_DATA_S => + -- Hold the pipeline + v.rdEn := "00"; + -- Check if ready to move data + if (v.sAxiReadSlave.rvalid = '0') then + -- Accept the data from the rate + v.rdEn := "11"; + -- Forward the data + v.sAxiReadSlave.rvalid := '1'; + v.sAxiReadSlave.rdata(DATA_WIDTH_C-1 downto 0) := rdData; + v.sAxiReadSlave.rid := r.rid; + -- Increment the address + v.rdAddr := r.rdAddr + 1; + -- Decrement the counter + v.arlen := r.arlen - 1; + -- Check for last transfer + if (r.arlen = 0) then + -- Set the last transfer flag + v.sAxiReadSlave.rlast := '1'; + -- Next State + v.rdState := RD_ADDR_S; + end if; + end if; + ---------------------------------------------------------------------- + end case; + + -- Outputs + rdAddr <= r.rdAddr; + if (READ_LATENCY_G = 0) then + rdEn <= "11"; + else + rdEn <= r.rdEn; + end if; + + -------------------------- + -- sAxiReadSlave's Outputs + -------------------------- + -- Read Address channel + sAxiReadSlave.arready <= v.sAxiReadSlave.arready; + -- Read data channel + sAxiReadSlave.rdata <= r.sAxiReadSlave.rdata; + sAxiReadSlave.rlast <= r.sAxiReadSlave.rlast; + sAxiReadSlave.rvalid <= r.sAxiReadSlave.rvalid; + sAxiReadSlave.rid <= r.sAxiReadSlave.rid; + sAxiReadSlave.rresp <= r.sAxiReadSlave.rresp; + + -- Reset + if (axiRst = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (axiClk) is + begin + if (rising_edge(axiClk)) then + r <= rin after TPD_G; + end if; + end process seq; + +end structure; diff --git a/axi/axi4/rtl/AxiReadEmulate.vhd b/axi/axi4/rtl/AxiReadEmulate.vhd index 1440209983..a1265fae3b 100644 --- a/axi/axi4/rtl/AxiReadEmulate.vhd +++ b/axi/axi4/rtl/AxiReadEmulate.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiReadEmulate.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-04-02 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: AXI4 Read Emulation Module ------------------------------------------------------------------------------- diff --git a/axi/axi4/rtl/AxiReadPathFifo.vhd b/axi/axi4/rtl/AxiReadPathFifo.vhd index 563d06e518..07feebed6e 100644 --- a/axi/axi4/rtl/AxiReadPathFifo.vhd +++ b/axi/axi4/rtl/AxiReadPathFifo.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiReadPathFifo.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-25 --- Last update: 2014-05-01 ------------------------------------------------------------------------------- -- Description: FIFO for AXI write path transactions. ------------------------------------------------------------------------------- diff --git a/axi/axi4/rtl/AxiReadPathMux.vhd b/axi/axi4/rtl/AxiReadPathMux.vhd index 6849310fd4..647cc2c904 100644 --- a/axi/axi4/rtl/AxiReadPathMux.vhd +++ b/axi/axi4/rtl/AxiReadPathMux.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiReadPathMux.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-25 --- Last update: 2018-03-11 ------------------------------------------------------------------------------- -- Description: Block to connect multiple incoming AXI write path interfaces. ------------------------------------------------------------------------------- @@ -114,7 +112,7 @@ begin when S_IDLE_C => v.master.arvalid := '0'; - -- Aribrate between requesters + -- Arbitrate between requesters if r.addrValid = '0' then arbitrate(addrRequests, r.addrAckNum, v.addrAckNum, v.addrValid, v.addrAcks); end if; @@ -186,7 +184,7 @@ begin mAxiReadMaster <= r.master; -- Readies are direct - -- Assign combinatoral outputs before reset + -- Assign combinatorial outputs before reset for i in 0 to (NUM_SLAVES_G-1) loop sAxiReadSlaves(i).arready <= v.slaves(i).arready; end loop; diff --git a/axi/axi4/rtl/AxiResize.vhd b/axi/axi4/rtl/AxiResize.vhd new file mode 100644 index 0000000000..6d1860cd53 --- /dev/null +++ b/axi/axi4/rtl/AxiResize.vhd @@ -0,0 +1,379 @@ +------------------------------------------------------------------------------- +-- File : AxiResize.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Block to resize AXI. Re-sizing is always little endian. +-- +-- Disclaimer: This module doesn't support the following: +-- Narrow write transfers +-- Unaligned transfers +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +use work.StdRtlPkg.all; +use work.AxiPkg.all; + +entity AxiResize is + generic ( + -- General Configurations + TPD_G : time := 1 ns; + -- AXI Stream Port Configurations + SLAVE_AXI_CONFIG_G : AxiConfigType := AXI_CONFIG_INIT_C; + MASTER_AXI_CONFIG_G : AxiConfigType := AXI_CONFIG_INIT_C); + port ( + -- Clock and reset + axiClk : in sl; + axiRst : in sl; + -- Slave Port + sAxiReadMaster : in AxiReadMasterType; + sAxiReadSlave : out AxiReadSlaveType; + sAxiWriteMaster : in AxiWriteMasterType; + sAxiWriteSlave : out AxiWriteSlaveType; + -- Master Port + mAxiReadMaster : out AxiReadMasterType; + mAxiReadSlave : in AxiReadSlaveType; + mAxiWriteMaster : out AxiWriteMasterType; + mAxiWriteSlave : in AxiWriteSlaveType); +end AxiResize; + +architecture rtl of AxiResize is + + constant SLV_BYTES_C : integer := SLAVE_AXI_CONFIG_G.DATA_BYTES_C; + constant MST_BYTES_C : integer := MASTER_AXI_CONFIG_G.DATA_BYTES_C; + constant MAX_BYTES_C : integer := maximum(SLV_BYTES_C, MST_BYTES_C); + constant COUNT_C : integer := ite(SLV_BYTES_C > MST_BYTES_C, SLV_BYTES_C / MST_BYTES_C, MST_BYTES_C / SLV_BYTES_C); + constant BIT_CNT_C : integer := bitSize(COUNT_C); + constant SHIFT_C : integer := log2(COUNT_C); + + type RegType is record + rdCount : slv(BIT_CNT_C-1 downto 0); + rdMaster : AxiReadMasterType; + rdSlave : AxiReadSlaveType; + wrCount : slv(BIT_CNT_C-1 downto 0); + wrMaster : AxiWriteMasterType; + wrSlave : AxiWriteSlaveType; + end record RegType; + + constant REG_INIT_C : RegType := ( + rdCount => (others => '0'), + rdMaster => axiReadMasterInit(MASTER_AXI_CONFIG_G), + rdSlave => AXI_READ_SLAVE_INIT_C, + wrCount => (others => '0'), + wrMaster => axiWriteMasterInit(MASTER_AXI_CONFIG_G), + wrSlave => AXI_WRITE_SLAVE_INIT_C); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + +begin + + -- Make sure data widths are appropriate. + assert ((SLV_BYTES_C >= MST_BYTES_C and SLV_BYTES_C mod MST_BYTES_C = 0) or + (MST_BYTES_C >= SLV_BYTES_C and MST_BYTES_C mod SLV_BYTES_C = 0)) + report "Data widths must be even number multiples of each other" severity failure; + + GEN_RESIZE : if (SLV_BYTES_C /= MST_BYTES_C) generate + + comb : process (axiRst, mAxiReadSlave, mAxiWriteSlave, r, sAxiReadMaster, + sAxiWriteMaster) is + variable v : RegType; + variable ibRdM : AxiReadSlaveType; + variable ibWrM : AxiWriteMasterType; + variable rdIdx : integer; -- index version of counter + variable wrIdx : integer; -- index version of counter + variable rdByteCnt : integer; -- Number of valid bytes in incoming bus + variable wrByteCnt : integer; -- Number of valid bytes in incoming bus + variable rdBytes : integer; -- byte version of counter + variable wrBytes : integer; -- byte version of counter + variable arlen : slv(7 downto 0); + variable awlen : slv(7 downto 0); + begin + -- Latch the current value + v := r; + + ---------------------------------------------------------------------- + -- AXI Read Resizing Logic -- + ---------------------------------------------------------------------- + + -- Update the indexes + rdIdx := conv_integer(r.rdCount); + + -- Update the number of bytes + rdBytes := (rdIdx+1) * SLV_BYTES_C; + + -- Update the byte counter pointer + rdByteCnt := MST_BYTES_C; + + -- Initialize the ready signal + v.rdMaster.rready := '0'; + + -- Valid/Ready Handshaking for the data channel + if (sAxiReadMaster.rready = '1') then + v.rdSlave.rvalid := '0'; + end if; + + -- Inbound data + ibRdM := mAxiReadSlave; + + -- Pipeline advance + if (v.rdSlave.rvalid = '0') then + + -- Increasing size + if SLV_BYTES_C > MST_BYTES_C then + -- Accept the data + v.rdMaster.rready := '1'; + + -- Initialize when rdCount = 0 + if (r.rdCount = 0) then + v.rdSlave := AXI_READ_SLAVE_INIT_C; + end if; + + v.rdSlave.rdata((MST_BYTES_C*8*rdIdx)+((MST_BYTES_C*8)-1) downto (MST_BYTES_C*8*rdIdx)) := ibRdM.rdata((MST_BYTES_C*8)-1 downto 0); + + v.rdSlave.rid := ibRdM.rid; + v.rdSlave.rresp := ibRdM.rresp; + v.rdSlave.rlast := ibRdM.rlast; + + -- Determine if we move data + if (ibRdM.rvalid = '1') then + if r.rdCount = (COUNT_C-1) or ibRdM.rlast = '1' then + v.rdSlave.rvalid := '1'; + v.rdCount := (others => '0'); + else + v.rdCount := r.rdCount + 1; + end if; + end if; + + -- Decreasing size + else + + v.rdSlave := AXI_READ_SLAVE_INIT_C; + + v.rdSlave.rdata((SLV_BYTES_C*8)-1 downto 0) := ibRdM.rdata((SLV_BYTES_C*8*rdIdx)+((SLV_BYTES_C*8)-1) downto (SLV_BYTES_C*8*rdIdx)); + + v.rdSlave.rid := ibRdM.rid; + v.rdSlave.rresp := ibRdM.rresp; + + -- Determine if we move data + if (ibRdM.rvalid = '1') then + if (r.rdCount = (COUNT_C-1)) or ((rdBytes >= rdByteCnt) and (ibRdM.rlast = '1')) then + v.rdCount := (others => '0'); + v.rdMaster.rready := '1'; + v.rdSlave.rlast := ibRdM.rlast; + else + v.rdCount := r.rdCount + 1; + v.rdMaster.rready := '0'; + v.rdSlave.rlast := '0'; + end if; + end if; + + -- Drop transfers, except on tLast + v.rdSlave.rvalid := ibRdM.rvalid or v.rdSlave.rlast; + + end if; + end if; + + if MST_BYTES_C > SLV_BYTES_C then + arlen(7 downto 7-SHIFT_C+1) := (others => '0'); + arlen(7-SHIFT_C downto 0) := sAxiReadMaster.arlen(7 downto SHIFT_C); + else + arlen(7 downto SHIFT_C) := sAxiReadMaster.arlen(7-SHIFT_C downto 0); + arlen(SHIFT_C-1 downto 0) := (others => '1'); + end if; + + --------------------------- + -- mAxiReadMaster's Outputs + --------------------------- + -- Read Address channel + mAxiReadMaster.arvalid <= sAxiReadMaster.arvalid; + mAxiReadMaster.araddr <= sAxiReadMaster.araddr; + mAxiReadMaster.arid <= sAxiReadMaster.arid; + mAxiReadMaster.arlen <= arlen; + mAxiReadMaster.arsize <= toSlv(log2(MASTER_AXI_CONFIG_G.DATA_BYTES_C), 3); + mAxiReadMaster.arburst <= sAxiReadMaster.arburst; + mAxiReadMaster.arlock <= sAxiReadMaster.arlock; + mAxiReadMaster.arprot <= sAxiReadMaster.arprot; + mAxiReadMaster.arcache <= sAxiReadMaster.arcache; + mAxiReadMaster.arqos <= sAxiReadMaster.arqos; + mAxiReadMaster.arregion <= sAxiReadMaster.arregion; + -- Read data channel + mAxiReadMaster.rready <= v.rdMaster.rready; + + -------------------------- + -- sAxiReadSlave's Outputs + -------------------------- + -- Read Address channel + sAxiReadSlave.arready <= mAxiReadSlave.arready; + -- Read data channel + sAxiReadSlave.rdata <= r.rdSlave.rdata; + sAxiReadSlave.rlast <= r.rdSlave.rlast; + sAxiReadSlave.rvalid <= r.rdSlave.rvalid; + sAxiReadSlave.rid <= r.rdSlave.rid; + sAxiReadSlave.rresp <= r.rdSlave.rresp; + + ---------------------------------------------------------------------- + -- AXI Write Resizing Logic -- + ---------------------------------------------------------------------- + + -- Update the indexes + wrIdx := conv_integer(r.wrCount); + + -- Update the number of bytes + wrBytes := (wrIdx+1) * MST_BYTES_C; + + -- Update the byte counter pointer + wrByteCnt := conv_integer(onesCount(sAxiWriteMaster.wstrb(SLV_BYTES_C-1 downto 0))); + + -- Initialize the ready signal + v.wrSlave.wready := '0'; + + -- Valid/Ready Handshaking for the data channel + if (mAxiWriteSlave.wready = '1') then + v.wrMaster.wvalid := '0'; + end if; + + -- Inbound data + ibWrM := sAxiWriteMaster; + + -- Pipeline advance + if (v.wrMaster.wvalid = '0') then + + -- Increasing size + if MST_BYTES_C > SLV_BYTES_C then + -- Accept the data + v.wrSlave.wready := '1'; + + -- Initialize when wrCount = 0 + if (r.wrCount = 0) then + v.wrMaster := axiWriteMasterInit(MASTER_AXI_CONFIG_G); + v.wrMaster.wstrb := (others => '0'); + end if; + + v.wrMaster.wdata((SLV_BYTES_C*8*wrIdx)+((SLV_BYTES_C*8)-1) downto (SLV_BYTES_C*8*wrIdx)) := ibWrM.wdata((SLV_BYTES_C*8)-1 downto 0); + v.wrMaster.wstrb((SLV_BYTES_C*wrIdx)+(SLV_BYTES_C-1) downto (SLV_BYTES_C*wrIdx)) := ibWrM.wstrb(SLV_BYTES_C-1 downto 0); + + v.wrMaster.wid := ibWrM.wid; --- The WID signal is implemented only in AXI3 + v.wrMaster.wlast := ibWrM.wlast; + + -- Determine if we move data + if (ibWrM.wvalid = '1') then + if r.wrCount = (COUNT_C-1) or ibWrM.wlast = '1' then + v.wrMaster.wvalid := '1'; + v.wrCount := (others => '0'); + else + v.wrCount := r.wrCount + 1; + end if; + end if; + + -- Decreasing size + else + + v.wrMaster := axiWriteMasterInit(MASTER_AXI_CONFIG_G); + + v.wrMaster.wdata((MST_BYTES_C*8)-1 downto 0) := ibWrM.wdata((MST_BYTES_C*8*wrIdx)+((MST_BYTES_C*8)-1) downto (MST_BYTES_C*8*wrIdx)); + v.wrMaster.wstrb(MST_BYTES_C-1 downto 0) := ibWrM.wstrb((MST_BYTES_C*wrIdx)+(MST_BYTES_C-1) downto (MST_BYTES_C*wrIdx)); + + v.wrMaster.wid := ibWrM.wid; -- The WID signal is implemented only in AXI3 + + -- Determine if we move data + if (ibWrM.wvalid = '1') then + if (r.wrCount = (COUNT_C-1)) or ((wrBytes >= wrByteCnt) and (ibWrM.wlast = '1')) then + v.wrCount := (others => '0'); + v.wrSlave.wready := '1'; + v.wrMaster.wlast := ibWrM.wlast; + else + v.wrCount := r.wrCount + 1; + v.wrSlave.wready := '0'; + v.wrMaster.wlast := '0'; + end if; + end if; + + -- Drop transfers with no wstrb bits set, except on wlast + v.wrMaster.wvalid := ibWrM.wvalid and (uOr(v.wrMaster.wstrb(COUNT_C-1 downto 0)) or v.wrMaster.wlast); + + end if; + end if; + + if MST_BYTES_C > SLV_BYTES_C then + awlen(7 downto 7-SHIFT_C+1) := (others => '0'); + awlen(7-SHIFT_C downto 0) := sAxiWriteMaster.awlen(7 downto SHIFT_C); + else + awlen(7 downto SHIFT_C) := sAxiWriteMaster.awlen(7-SHIFT_C downto 0); + awlen(SHIFT_C-1 downto 0) := (others => '1'); + end if; + + ---------------------------- + -- mAxiWriteMaster's Outputs + ---------------------------- + -- Write address channel + mAxiWriteMaster.awvalid <= sAxiWriteMaster.awvalid; + mAxiWriteMaster.awaddr <= sAxiWriteMaster.awaddr; + mAxiWriteMaster.awid <= sAxiWriteMaster.awid; + mAxiWriteMaster.awlen <= awlen; + mAxiWriteMaster.awsize <= toSlv(log2(MASTER_AXI_CONFIG_G.DATA_BYTES_C), 3); + mAxiWriteMaster.awburst <= sAxiWriteMaster.awburst; + mAxiWriteMaster.awlock <= sAxiWriteMaster.awlock; + mAxiWriteMaster.awprot <= sAxiWriteMaster.awprot; + mAxiWriteMaster.awcache <= sAxiWriteMaster.awcache; + mAxiWriteMaster.awqos <= sAxiWriteMaster.awqos; + mAxiWriteMaster.awregion <= sAxiWriteMaster.awregion; + -- Write data channel + mAxiWriteMaster.wdata <= r.wrMaster.wdata; + mAxiWriteMaster.wlast <= r.wrMaster.wlast; + mAxiWriteMaster.wvalid <= r.wrMaster.wvalid; + mAxiWriteMaster.wid <= r.wrMaster.wid; + mAxiWriteMaster.wstrb <= r.wrMaster.wstrb; + -- Write ack channel + mAxiWriteMaster.bready <= sAxiWriteMaster.bready; + + -------------------------- + -- sAxiWriteSlave's Outputs + -------------------------- + -- Write address channel + sAxiWriteSlave.awready <= mAxiWriteSlave.awready; + -- Write data channel + sAxiWriteSlave.wready <= v.wrSlave.wready; + -- Write ack channel + sAxiWriteSlave.bresp <= mAxiWriteSlave.bresp; + sAxiWriteSlave.bvalid <= mAxiWriteSlave.bvalid; + sAxiWriteSlave.bid <= mAxiWriteSlave.bid; + + -- Reset + if (axiRst = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (axiClk) is + begin + if (rising_edge(axiClk)) then + r <= rin after TPD_G; + end if; + end process seq; + + end generate; + + BYP_RESIZE : if (SLV_BYTES_C = MST_BYTES_C) generate + mAxiReadMaster <= sAxiReadMaster; + sAxiReadSlave <= mAxiReadSlave; + mAxiWriteMaster <= sAxiWriteMaster; + sAxiWriteSlave <= mAxiWriteSlave; + end generate; + +end rtl; diff --git a/axi/axi4/rtl/AxiWriteEmulate.vhd b/axi/axi4/rtl/AxiWriteEmulate.vhd index f691fc8890..f3578a207e 100644 --- a/axi/axi4/rtl/AxiWriteEmulate.vhd +++ b/axi/axi4/rtl/AxiWriteEmulate.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiWriteEmulate.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-04-02 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: AXI4 Write Emulation Module ------------------------------------------------------------------------------- diff --git a/axi/axi4/rtl/AxiWritePathFifo.vhd b/axi/axi4/rtl/AxiWritePathFifo.vhd index 5c903164ca..0b9934bf97 100644 --- a/axi/axi4/rtl/AxiWritePathFifo.vhd +++ b/axi/axi4/rtl/AxiWritePathFifo.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiWritePathFifo.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-25 --- Last update: 2014-05-01 ------------------------------------------------------------------------------- -- Description: -- FIFO for AXI write path transactions. diff --git a/axi/axi4/rtl/AxiWritePathMux.vhd b/axi/axi4/rtl/AxiWritePathMux.vhd index b4d0be84c6..240a80f6fc 100644 --- a/axi/axi4/rtl/AxiWritePathMux.vhd +++ b/axi/axi4/rtl/AxiWritePathMux.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiWritePathMux.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-25 --- Last update: 2018-03-11 ------------------------------------------------------------------------------- -- Description: -- Block to connect multiple incoming AXI write path interfaces. diff --git a/axi/axi4/tb/AxiPkgTb.vhd b/axi/axi4/tb/AxiPkgTb.vhd index 31835b65f7..f793909e49 100644 --- a/axi/axi4/tb/AxiPkgTb.vhd +++ b/axi/axi4/tb/AxiPkgTb.vhd @@ -1,3 +1,12 @@ +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; diff --git a/axi/axi4/tb/AxiRamTb.vhd b/axi/axi4/tb/AxiRamTb.vhd new file mode 100644 index 0000000000..ca9b99ce7f --- /dev/null +++ b/axi/axi4/tb/AxiRamTb.vhd @@ -0,0 +1,152 @@ +------------------------------------------------------------------------------- +-- File : AxiRamTb.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Simulation Testbed for testing the AxiRamTb module +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +use work.StdRtlPkg.all; +use work.AxiPkg.all; +use work.AxiLitePkg.all; + +entity AxiRamTb is end AxiRamTb; + +architecture testbed of AxiRamTb is + + constant CLK_PERIOD_C : time := 10 ns; + constant TPD_G : time := CLK_PERIOD_C/4; + + constant AXI_CONFIG_C : AxiConfigType := ( + ADDR_WIDTH_C => 16, + DATA_BYTES_C => 8, + ID_BITS_C => 4, + LEN_BITS_C => 8); + + constant START_ADDR_C : slv(AXI_CONFIG_C.ADDR_WIDTH_C-1 downto 0) := (others => '0'); + constant STOP_ADDR_C : slv(AXI_CONFIG_C.ADDR_WIDTH_C-1 downto 0) := (others => '1'); + + signal clk : sl := '0'; + signal rst : sl := '0'; + signal rstL : sl := '1'; + + signal memReady : sl := '0'; + signal memError : sl := '0'; + signal memReadyDly : sl := '0'; + signal memErrorDly : sl := '0'; + + signal axiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + signal axiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; + signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; + signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; + +begin + + --------------------------- + -- Generate clock and reset + --------------------------- + U_ClkRst : entity work.ClkRst + generic map ( + CLK_PERIOD_G => CLK_PERIOD_C, + RST_START_DELAY_G => 0 ns, -- Wait this long into simulation before asserting reset + RST_HOLD_TIME_G => 1000 ns) -- Hold reset for this long) + port map ( + clkP => clk, + clkN => open, + rst => rst, + rstL => rstL); + + ------------- + -- AXI Memory + ------------- + U_MEM : entity work.AxiRam + generic map ( + TPD_G => TPD_G, + ------------------------------ + -- Select Either XPM or inferred + ------------------------------ + SYNTH_MODE_G => "inferred", + -- SYNTH_MODE_G => "xpm", + ------------------------------ + -- LUT RAM + ------------------------------ + -- MEMORY_TYPE_G => "distributed", + -- READ_LATENCY_G => 0, + ------------------------------ + -- BRAM + ------------------------------ + MEMORY_TYPE_G => "block", + READ_LATENCY_G => 2, + ------------------------------ + AXI_CONFIG_G => AXI_CONFIG_C) + port map ( + -- Clock and Reset + axiClk => clk, + axiRst => rst, + -- Slave Write Interface + sAxiWriteMaster => axiWriteMaster, + sAxiWriteSlave => axiWriteSlave, + -- Slave Read Interface + sAxiReadMaster => axiReadMaster, + sAxiReadSlave => axiReadSlave); + + ---------------- + -- Memory Tester + ---------------- + U_AxiMemTester : entity work.AxiMemTester + generic map ( + TPD_G => TPD_G, + START_ADDR_G => START_ADDR_C, + STOP_ADDR_G => STOP_ADDR_C, + AXI_CONFIG_G => AXI_CONFIG_C) + port map ( + -- AXI-Lite Interface + axilClk => clk, + axilRst => rst, + axilReadMaster => AXI_LITE_READ_MASTER_INIT_C, + axilReadSlave => open, + axilWriteMaster => AXI_LITE_WRITE_MASTER_INIT_C, + axilWriteSlave => open, + memReady => memReady, + memError => memError, + -- DDR Memory Interface + axiClk => clk, + axiRst => rst, + start => rstL, + axiWriteMaster => axiWriteMaster, + axiWriteSlave => axiWriteSlave, + axiReadMaster => axiReadMaster, + axiReadSlave => axiReadSlave); + + --------------------- + -- Report the Results + --------------------- + process(clk) + begin + if rising_edge(clk) then + memErrorDly <= memError after TPD_G; + memReadyDly <= memReady after TPD_G; + if (memErrorDly = '1') then + assert false + report "Simulation Failed!" severity failure; + end if; + if (memReadyDly = '1') then + assert false + report "Simulation Passed!" severity failure; + end if; + end if; + end process; + +end testbed; diff --git a/axi/bridge/rtl/AxiLiteToDrp.vhd b/axi/bridge/rtl/AxiLiteToDrp.vhd index 3797d090fa..c591b2288d 100644 --- a/axi/bridge/rtl/AxiLiteToDrp.vhd +++ b/axi/bridge/rtl/AxiLiteToDrp.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLiteToDrp.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-02-10 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AXI-Lite to Xilinx DRP Bridge ------------------------------------------------------------------------------- diff --git a/axi/bridge/rtl/AxiLiteToIpBus.vhd b/axi/bridge/rtl/AxiLiteToIpBus.vhd new file mode 100644 index 0000000000..bef6b83188 --- /dev/null +++ b/axi/bridge/rtl/AxiLiteToIpBus.vhd @@ -0,0 +1,168 @@ +------------------------------------------------------------------------------- +-- File : AxiLiteToIpBus.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: AXI-Lite to IP Bus Bridge +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.StdRtlPkg.all; +use work.AxiLitePkg.all; + +entity AxiLiteToIpBus is + generic ( + TPD_G : time := 1 ns); + port ( + -- Clock and Reset + clk : in sl; + rst : in sl; + -- AXI-Lite Slave Interface + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType; + -- IP Bus Master Interface + ipbRdata : in slv(31 downto 0); + ipbAck : in sl; + ipbErr : in sl; + ipbAddr : out slv(31 downto 0); + ipbWdata : out slv(31 downto 0); + ipbStrobe : out sl; + ipbWrite : out sl); +end AxiLiteToIpBus; + +architecture rtl of AxiLiteToIpBus is + + type StateType is ( + IDLE_S, + WAIT_S); + + type RegType is record + ipbAddr : slv(31 downto 0); + ipbWdata : slv(31 downto 0); + ipbStrobe : sl; + ipbWrite : sl; + ack : AxiLiteAckType; + state : StateType; + end record; + + constant REG_INIT_C : RegType := ( + ipbAddr => (others => '0'), + ipbWdata => (others => '0'), + ipbStrobe => '0', + ipbWrite => '0', + ack => AXI_LITE_ACK_INIT_C, + state => IDLE_S); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal req : AxiLiteReqType; + signal ack : AxiLiteAckType; + +begin + + U_AxiLiteSlave : entity work.AxiLiteSlave + generic map ( + TPD_G => TPD_G) + port map ( + req => req, + ack => ack, + axilClk => clk, + axilRst => rst, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave); + + comb : process (ipbAck, ipbErr, ipbRdata, r, req, rst) is + variable v : RegType; + variable i : natural; + begin + -- Latch the current value + v := r; + + -- State Machine + case (r.state) is + ---------------------------------------------------------------------- + when IDLE_S => + -- Reset strobes + v.ack.done := '0'; + -- Check if ready for next transaction + if (r.ack.done = '0') then + -- Check for new transaction + if (req.request = '1') then + -- Check for 32-bit word misalignment + if (req.address(1 downto 0) /= 0) then + -- Send the Bus Error response + v.ack.done := '1'; + v.ack.resp := AXI_RESP_SLVERR_C; + else + -- Setup the Master IP Bus request + v.ipbAddr := "00" & req.address(31 downto 2); -- Convert from byte address to 32-bit word address + v.ipbWdata := req.wrData; + v.ipbStrobe := '1'; + v.ipbWrite := not(req.rnw); + -- Next state + v.state := WAIT_S; + end if; + end if; + end if; + ---------------------------------------------------------------------- + when WAIT_S => + -- Check for IP bus ACK + if (ipbAck = '1') then + -- Reset the false + v.ipbStrobe := '0'; + -- Send the Bus response + v.ack.done := '1'; + v.ack.rdData := ipbRdata; + -- Check for bus error + if (ipbErr = '1') then + v.ack.resp := AXI_RESP_SLVERR_C; + else + v.ack.resp := AXI_RESP_OK_C; + end if; + -- Next state + v.state := IDLE_S; + end if; + ---------------------------------------------------------------------- + end case; + + -- Outputs + ack <= v.ack; + ipbAddr <= r.ipbAddr; + ipbWdata <= r.ipbWdata; + ipbStrobe <= r.ipbStrobe; + ipbWrite <= r.ipbWrite; + + -- Reset + if (rst = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (clk) is + begin + if (rising_edge(clk)) then + r <= rin after TPD_G; + end if; + end process seq; + +end rtl; diff --git a/axi/bridge/rtl/AxiToAxiLite.vhd b/axi/bridge/rtl/AxiToAxiLite.vhd index d190bcf984..03d7a498a1 100644 --- a/axi/bridge/rtl/AxiToAxiLite.vhd +++ b/axi/bridge/rtl/AxiToAxiLite.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiToAxiLite.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-03-06 --- Last update: 2017-11-03 ------------------------------------------------------------------------------- -- Description: AXI4-to-AXI-Lite bridge -- diff --git a/axi/bridge/rtl/IpBusToAxiLite.vhd b/axi/bridge/rtl/IpBusToAxiLite.vhd new file mode 100644 index 0000000000..f9bf52a212 --- /dev/null +++ b/axi/bridge/rtl/IpBusToAxiLite.vhd @@ -0,0 +1,163 @@ +------------------------------------------------------------------------------- +-- File : IpBusToAxiLite.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: IP Bus to AXI-Lite Bridge +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.StdRtlPkg.all; +use work.AxiLitePkg.all; + +entity IpBusToAxiLite is + generic ( + TPD_G : time := 1 ns); + port ( + -- Clock and Reset + clk : in sl; + rst : in sl; + -- IP Bus Slave Interface + ipbAddr : in slv(31 downto 0); + ipbWdata : in slv(31 downto 0); + ipbStrobe : in sl; + ipbWrite : in sl; + ipbRdata : out slv(31 downto 0); + ipbAck : out sl; + ipbErr : out sl; + -- AXI-Lite Master Interface + axilReadMaster : out AxiLiteReadMasterType; + axilReadSlave : in AxiLiteReadSlaveType; + axilWriteMaster : out AxiLiteWriteMasterType; + axilWriteSlave : in AxiLiteWriteSlaveType); +end IpBusToAxiLite; + +architecture rtl of IpBusToAxiLite is + + type StateType is ( + IDLE_S, + WAIT_S); + + type RegType is record + ipbRdata : slv(31 downto 0); + ipbAck : sl; + ipbErr : sl; + req : AxiLiteReqType; + state : StateType; + end record; + + constant REG_INIT_C : RegType := ( + ipbRdata => (others => '0'), + ipbAck => '0', + ipbErr => '0', + req => AXI_LITE_REQ_INIT_C, + state => IDLE_S); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal ack : AxiLiteAckType; + +begin + + U_AxiLiteMaster : entity work.AxiLiteMaster + generic map ( + TPD_G => TPD_G) + port map ( + req => r.req, + ack => ack, + axilClk => clk, + axilRst => rst, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave); + + comb : process (ack, ipbAddr, ipbStrobe, ipbWdata, ipbWrite, r, rst) is + variable v : RegType; + variable i : natural; + begin + -- Latch the current value + v := r; + + -- Reset strobes + v.ipbAck := '0'; + v.ipbErr := '0'; + + -- State Machine + case (r.state) is + ---------------------------------------------------------------------- + when IDLE_S => + -- Check if ready for next transaction + if (ack.done = '0') and (r.ipbAck = '0') then + -- Check for new transaction + if (ipbStrobe = '1') then + -- Check for invalid address range + if (ipbAddr(31 downto 30) /= 0) then + -- Send the IP Bus Error response + v.ipbAck := '1'; + v.ipbErr := '1'; + else + -- Setup the AXI-Lite Master request + v.req.request := '1'; + v.req.rnw := not(ipbWrite); + v.req.address := ipbAddr(29 downto 0) & "00"; -- Convert from 32-bit word address to byte address + v.req.wrData := ipbWdata; + -- Next state + v.state := WAIT_S; + end if; + end if; + end if; + ---------------------------------------------------------------------- + when WAIT_S => + -- Wait for DONE to set + if (ack.done = '1') then + -- Reset the flag + v.req.request := '0'; + -- Send the IP Bus response + v.ipbAck := '1'; + v.ipbRdata := ack.rdData; + -- Check for bus error + if (ack.resp /= 0) then + v.ipbErr := '1'; + end if; + -- Next state + v.state := IDLE_S; + end if; + ---------------------------------------------------------------------- + end case; + + -- Outputs + ipbRdata <= r.ipbRdata; + ipbAck <= r.ipbAck; + ipbErr <= r.ipbErr; + + -- Reset + if (rst = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (clk) is + begin + if (rising_edge(clk)) then + r <= rin after TPD_G; + end if; + end process seq; + +end rtl; diff --git a/axi/bridge/rtl/SlvArraytoAxiLite.vhd b/axi/bridge/rtl/SlvArraytoAxiLite.vhd index 26df352bf3..431cf2576a 100644 --- a/axi/bridge/rtl/SlvArraytoAxiLite.vhd +++ b/axi/bridge/rtl/SlvArraytoAxiLite.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SlvArraytoAxiLite.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-07-21 --- Last update: 2017-10-24 ------------------------------------------------------------------------------- -- Description: SLV array to AXI-Lite Master Bridge ------------------------------------------------------------------------------- @@ -22,7 +20,6 @@ use ieee.std_logic_unsigned.all; use work.StdRtlPkg.all; use work.AxiLitePkg.all; -use work.AxiLiteMasterPkg.all; entity SlvArraytoAxiLite is generic ( @@ -54,7 +51,7 @@ architecture rtl of SlvArraytoAxiLite is cnt : natural range 0 to SIZE_G-1; valid : slv(SIZE_G-1 downto 0); inSlv : Slv32Array(SIZE_G-1 downto 0); - req : AxiLiteMasterReqType; + req : AxiLiteReqType; state : StateType; end record; @@ -62,14 +59,14 @@ architecture rtl of SlvArraytoAxiLite is cnt => 0, valid => (others => '0'), inSlv => (others => (others => '0')), - req => AXI_LITE_MASTER_REQ_INIT_C, + req => AXI_LITE_REQ_INIT_C, state => IDLE_S); signal r : RegType := REG_INIT_C; signal rin : RegType; signal inSlv : Slv32Array(SIZE_G-1 downto 0); - signal ack : AxiLiteMasterAckType; + signal ack : AxiLiteAckType; -- attribute dont_touch : string; -- attribute dont_touch of r : signal is "true"; @@ -92,7 +89,7 @@ begin dout => inSlv(i)); end generate GEN_VEC; - AxiLiteMaster : entity work.AxiLiteMaster + U_AxiLiteMaster : entity work.AxiLiteMaster generic map ( TPD_G => TPD_G) port map ( diff --git a/axi/bridge/ruckus.tcl b/axi/bridge/ruckus.tcl index 10548569b1..cdcd2f7367 100644 --- a/axi/bridge/ruckus.tcl +++ b/axi/bridge/ruckus.tcl @@ -4,5 +4,5 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Load Source Code loadSource -dir "$::DIR_PATH/rtl" -# # Load Simulation -# loadSource -sim_only -dir "$::DIR_PATH/tb" +# Load Simulation +loadSource -sim_only -dir "$::DIR_PATH/tb" diff --git a/axi/bridge/tb/AxiLiteIpBusBridgeTb.vhd b/axi/bridge/tb/AxiLiteIpBusBridgeTb.vhd new file mode 100644 index 0000000000..29372f0e3f --- /dev/null +++ b/axi/bridge/tb/AxiLiteIpBusBridgeTb.vhd @@ -0,0 +1,179 @@ +------------------------------------------------------------------------------- +-- File : AxiLiteIpBusBridgeTb.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Simulation Testbed for testing the AxiLiteIpBusBridgeTb module +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +use work.StdRtlPkg.all; +use work.AxiLitePkg.all; +use work.BuildInfoPkg.all; + +entity AxiLiteIpBusBridgeTb is end AxiLiteIpBusBridgeTb; + +architecture testbed of AxiLiteIpBusBridgeTb is + + constant GET_BUILD_INFO_C : BuildInfoRetType := toBuildInfo(BUILD_INFO_C); + constant MOD_BUILD_INFO_C : BuildInfoRetType := ( + buildString => GET_BUILD_INFO_C.buildString, + fwVersion => GET_BUILD_INFO_C.fwVersion, + gitHash => x"1111_2222_3333_4444_5555_6666_7777_8888_9999_AAAA"); -- create a fake githash + constant SIM_BUILD_INFO_C : slv(2239 downto 0) := toSlv(MOD_BUILD_INFO_C); + + constant CLK_PERIOD_G : time := 10 ns; + constant TPD_G : time := CLK_PERIOD_G/4; + + signal axilClk : sl := '0'; + signal axilRst : sl := '0'; + + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + + signal ipbRdata : slv(31 downto 0) := (others => '0'); + signal ipbAck : sl := '0'; + signal ipbErr : sl := '0'; + signal ipbAddr : slv(31 downto 0) := (others => '0'); + signal ipbWdata : slv(31 downto 0) := (others => '0'); + signal ipbStrobe : sl := '0'; + signal ipbWrite : sl := '0'; + + signal regWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal regWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal regReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal regReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + +begin + + -------------------- + -- Clocks and Resets + -------------------- + U_axilClk : entity work.ClkRst + generic map ( + CLK_PERIOD_G => CLK_PERIOD_G, + RST_START_DELAY_G => 0 ns, + RST_HOLD_TIME_G => 1000 ns) + port map ( + clkP => axilClk, + rst => axilRst); + + -------------------------------------------- + -- Simulation AXI-Lite Register Transactions + -------------------------------------------- + test : process is + variable debugData : slv(31 downto 0) := (others => '0'); + begin + debugData := x"1111_1111"; + ------------------------------------------ + -- Wait for the AXI-Lite reset to complete + ------------------------------------------ + wait until axilRst = '1'; + wait until axilRst = '0'; + + -- Read the GIT hash + axiLiteBusSimRead (axilClk, axilReadMaster, axilReadSlave, x"0000_0600", debugData, true); + axiLiteBusSimRead (axilClk, axilReadMaster, axilReadSlave, x"0000_0604", debugData, true); + axiLiteBusSimRead (axilClk, axilReadMaster, axilReadSlave, x"0000_0608", debugData, true); + axiLiteBusSimRead (axilClk, axilReadMaster, axilReadSlave, x"0000_060C", debugData, true); + axiLiteBusSimRead (axilClk, axilReadMaster, axilReadSlave, x"0000_0610", debugData, true); + + -- Write to the scratch pad + axiLiteBusSimWrite (axilClk, axilWriteMaster, axilWriteSlave, x"0000_0004", x"1234_5678", true); + + -- Write to a read-only register to test error bus response path + axiLiteBusSimWrite (axilClk, axilWriteMaster, axilWriteSlave, x"0000_0000", x"1234_5678", true); + + --------------------------------------------------------------------------------- + -- Here's the expected output: + --------------------------------------------------------------------------------- + -- AxiLitePkg::axiLiteBusSimRead( addr:00000600, data: 9999AAAA) + -- AxiLitePkg::axiLiteBusSimRead( addr:00000604, data: 77778888) + -- AxiLitePkg::axiLiteBusSimRead( addr:00000608, data: 55556666) + -- AxiLitePkg::axiLiteBusSimRead( addr:0000060C, data: 33334444) + -- AxiLitePkg::axiLiteBusSimRead( addr:00000610, data: 11112222) + -- AxiLitePkg::axiLiteBusSimWrite(addr:00000004, data: 12345678) + -- AxiLitePkg::axiLiteBusSimWrite(addr:00000000, data: 12345678) + -- Warning: AxiLitePkg::axiLiteBusSimWrite( addr:00000000): - BRESP = SLAVE_ERROR + --------------------------------------------------------------------------------- + + end process test; + + ---------------------------- + -- Axi-Lite to IP bus Bridge + ---------------------------- + U_AxiLiteToIpBus : entity work.AxiLiteToIpBus + generic map ( + TPD_G => TPD_G) + port map ( + -- Clock and Reset + clk => axilClk, + rst => axilRst, + -- AXI-Lite Slave Interface + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave, + -- IP Bus Master Interface + ipbRdata => ipbRdata, + ipbAck => ipbAck, + ipbErr => ipbErr, + ipbAddr => ipbAddr, + ipbWdata => ipbWdata, + ipbStrobe => ipbStrobe, + ipbWrite => ipbWrite); + + ---------------------------- + -- IP Bus to Axi-Lite Bridge + ---------------------------- + U_IpBusToAxiLite : entity work.IpBusToAxiLite + generic map ( + TPD_G => TPD_G) + port map ( + -- Clock and Reset + clk => axilClk, + rst => axilRst, + -- IP Bus Slave Interface + ipbAddr => ipbAddr, + ipbWdata => ipbWdata, + ipbStrobe => ipbStrobe, + ipbWrite => ipbWrite, + ipbRdata => ipbRdata, + ipbAck => ipbAck, + ipbErr => ipbErr, + -- AXI-Lite Master Interface + axilReadMaster => regReadMaster, + axilReadSlave => regReadSlave, + axilWriteMaster => regWriteMaster, + axilWriteSlave => regWriteSlave); + + -------------------------- + -- Example Register Module + -------------------------- + U_Version : entity work.AxiVersion + generic map ( + TPD_G => TPD_G, + BUILD_INFO_G => SIM_BUILD_INFO_C) + port map ( + -- AXI-Lite Interface + axiClk => axilClk, + axiRst => axilRst, + axiReadMaster => regReadMaster, + axiReadSlave => regReadSlave, + axiWriteMaster => regWriteMaster, + axiWriteSlave => regWriteSlave); + +end testbed; diff --git a/axi/dma/rtl/AxiDmaPkg.vhd b/axi/dma/rtl/AxiDmaPkg.vhd index 1ecc840719..e2d1caad6f 100644 --- a/axi/dma/rtl/AxiDmaPkg.vhd +++ b/axi/dma/rtl/AxiDmaPkg.vhd @@ -1,7 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamDmaRead.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-05-06 -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: @@ -46,6 +45,7 @@ package AxiDmaPkg is drop : sl; address : slv(63 downto 0); maxSize : slv(31 downto 0); + prot : slv(2 downto 0); end record; -- Initialization constants @@ -53,8 +53,8 @@ package AxiDmaPkg is request => '0', drop => '0', address => (others=>'0'), - maxSize => (others=>'0') - ); + maxSize => (others=>'0'), + prot => (others=>'0')); -- Array type AxiWriteDmaReqArray is array (natural range<>) of AxiWriteDmaReqType; @@ -107,6 +107,7 @@ package AxiDmaPkg is lastUser : slv(7 downto 0); dest : slv(7 downto 0); id : slv(7 downto 0); + prot : slv(2 downto 0); end record; -- Initialization constants @@ -117,8 +118,8 @@ package AxiDmaPkg is firstUser => (others=>'0'), lastUser => (others=>'0'), dest => (others=>'0'), - id => (others=>'0') - ); + id => (others=>'0'), + prot => (others=>'0')); -- Array type AxiReadDmaReqArray is array (natural range<>) of AxiReadDmaReqType; @@ -183,7 +184,7 @@ package AxiDmaPkg is dropEn : sl; maxSize : slv(31 downto 0); contEn : sl; - buffId : slv(15 downto 0); + buffId : slv(31 downto 0); end record; constant AXI_WRITE_DMA_DESC_ACK_INIT_C : AxiWriteDmaDescAckType := ( @@ -197,7 +198,7 @@ package AxiDmaPkg is type AxiWriteDmaDescAckArray is array (natural range<>) of AxiWriteDmaDescAckType; - constant AXI_WRITE_DMA_DESC_ACK_SIZE_C : integer := 114; + constant AXI_WRITE_DMA_DESC_ACK_SIZE_C : integer := 130; function toSlv (r : AxiWriteDmaDescAckType ) return slv; function toAxiWriteDmaDescAck (din : slv; valid : sl) return AxiWriteDmaDescAckType; @@ -209,14 +210,14 @@ package AxiDmaPkg is type AxiWriteDmaDescRetType is record valid : sl; - buffId : slv(15 downto 0); + buffId : slv(31 downto 0); firstUser : slv(7 downto 0); lastUser : slv(7 downto 0); size : slv(31 downto 0); continue : sl; result : slv(2 downto 0); dest : slv(7 downto 0); - id : slv(7 downto 0); + id : slv(7 downto 0); -- TID end record; constant AXI_WRITE_DMA_DESC_RET_INIT_C : AxiWriteDmaDescRetType := ( @@ -233,7 +234,7 @@ package AxiDmaPkg is type AxiWriteDmaDescRetArray is array (natural range<>) of AxiWriteDmaDescRetType; - constant AXI_WRITE_DMA_DESC_RET_SIZE_C : integer := 84; + constant AXI_WRITE_DMA_DESC_RET_SIZE_C : integer := 100; function toSlv (r : AxiWriteDmaDescRetType ) return slv; function toAxiWriteDmaDescRet (din : slv; valid : sl) return AxiWriteDmaDescRetType; @@ -252,8 +253,8 @@ package AxiDmaPkg is firstUser : slv(7 downto 0); contEn : sl; dropEn : sl; - id : slv(7 downto 0); - buffId : slv(15 downto 0); + id : slv(7 downto 0); -- TID + buffId : slv(31 downto 0); overflow : sl; end record; @@ -273,7 +274,7 @@ package AxiDmaPkg is type AxiWriteDmaTrackArray is array (natural range<>) of AxiWriteDmaTrackType; - constant AXI_WRITE_DMA_TRACK_SIZE_C : integer := 172; + constant AXI_WRITE_DMA_TRACK_SIZE_C : integer := 188; function toSlv (r : AxiWriteDmaTrackType ) return slv; function toAxiWriteDmaTrack (din : slv ) return AxiWriteDmaTrackType; @@ -286,7 +287,7 @@ package AxiDmaPkg is type AxiReadDmaDescReqType is record valid : sl; address : slv(63 downto 0); - buffId : slv(15 downto 0); + buffId : slv(31 downto 0); firstUser : slv(7 downto 0); lastUser : slv(7 downto 0); size : slv(31 downto 0); @@ -303,13 +304,13 @@ package AxiDmaPkg is lastUser => (others=>'0'), size => (others=>'0'), continue => '0', - id => (others=>'0'), + id => (others=>'0'), -- TID dest => (others=>'0') ); type AxiReadDmaDescReqArray is array (natural range<>) of AxiReadDmaDescReqType; - constant AXI_READ_DMA_DESC_REQ_SIZE_C : integer := 145; + constant AXI_READ_DMA_DESC_REQ_SIZE_C : integer := 161; function toSlv (r : AxiReadDmaDescReqType ) return slv; function toAxiReadDmaDescReq (din : slv; valid : sl) return AxiReadDmaDescReqType; @@ -321,7 +322,7 @@ package AxiDmaPkg is type AxiReadDmaDescRetType is record valid : sl; - buffId : slv(15 downto 0); + buffId : slv(31 downto 0); result : slv(2 downto 0); end record; @@ -333,7 +334,7 @@ package AxiDmaPkg is type AxiReadDmaDescRetArray is array (natural range<>) of AxiReadDmaDescRetType; - constant AXI_READ_DMA_DESC_RET_SIZE_C : integer := 19; + constant AXI_READ_DMA_DESC_RET_SIZE_C : integer := 35; function toSlv (r : AxiReadDmaDescRetType ) return slv; function toAxiReadDmaDescRet (din : slv; valid : sl) return AxiReadDmaDescRetType; diff --git a/axi/dma/rtl/AxiStreamDma.vhd b/axi/dma/rtl/AxiStreamDma.vhd index a9a41b9424..4e4bdf3140 100644 --- a/axi/dma/rtl/AxiStreamDma.vhd +++ b/axi/dma/rtl/AxiStreamDma.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamDma.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-25 --- Last update: 2017-05-03 ------------------------------------------------------------------------------- -- Description: -- Generic AXI Stream DMA block for frame at a time transfers. diff --git a/axi/dma/rtl/AxiStreamDmaRead.vhd b/axi/dma/rtl/AxiStreamDmaRead.vhd index d1626aa3d8..c14896b7bc 100644 --- a/axi/dma/rtl/AxiStreamDmaRead.vhd +++ b/axi/dma/rtl/AxiStreamDmaRead.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamDmaRead.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-25 --- Last update: 2018-03-09 ------------------------------------------------------------------------------- -- Description: -- Block to transfer a single AXI Stream frame from memory using an AXI @@ -235,6 +233,8 @@ begin v.rMaster.arlen := resize(r.reqSize(ADDR_LSB_C+AXI_CONFIG_G.LEN_BITS_C-1 downto ADDR_LSB_C)-1, 8); end if; end if; + -- Update the Protection control + v.rMaster.arprot := r.dmaReq.prot; -- There is enough room in the FIFO for a burst if (pause = '0') then -- Set the flag @@ -327,8 +327,8 @@ begin if (v.size = 0) then -- Terminate the frame v.sMaster.tLast := '1'; - v.sMaster.tKeep := genTKeep(conv_integer(r.size(4 downto 0))); - v.sMaster.tStrb := genTKeep(conv_integer(r.size(4 downto 0))); + v.sMaster.tKeep := genTKeep(conv_integer(r.size(bitSize(AXI_STREAM_MAX_TKEEP_WIDTH_C)-1 downto 0))); + v.sMaster.tStrb := genTKeep(conv_integer(r.size(bitSize(AXI_STREAM_MAX_TKEEP_WIDTH_C)-1 downto 0))); -- Check for first transfer if (r.first = '1') then -- Compensate the tKeep and tStrb via shift module diff --git a/axi/dma/rtl/AxiStreamDmaRingPkg.vhd b/axi/dma/rtl/AxiStreamDmaRingPkg.vhd index 54c0dfc5fe..8c91e34811 100644 --- a/axi/dma/rtl/AxiStreamDmaRingPkg.vhd +++ b/axi/dma/rtl/AxiStreamDmaRingPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamDmaRingPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-03-08 --- Last update: 2016-08-02 ------------------------------------------------------------------------------- -- Description: AxiStreamDmaRingPkg Support Package ------------------------------------------------------------------------------- diff --git a/axi/dma/rtl/AxiStreamDmaRingRead.vhd b/axi/dma/rtl/AxiStreamDmaRingRead.vhd index 6bc36534c5..1e971c747c 100644 --- a/axi/dma/rtl/AxiStreamDmaRingRead.vhd +++ b/axi/dma/rtl/AxiStreamDmaRingRead.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamDmaRingRead.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-29 --- Last update: 2018-03-09 ------------------------------------------------------------------------------- -- Description: AXI Stream to DMA Ring Buffer Read Module ------------------------------------------------------------------------------- @@ -24,7 +22,6 @@ use work.StdRtlPkg.all; use work.AxiStreamPkg.all; use work.SsiPkg.all; use work.AxiLitePkg.all; -use work.AxiLiteMasterPkg.all; use work.AxiPkg.all; use work.AxiDmaPkg.all; use work.AxiStreamDmaRingPkg.all; @@ -91,7 +88,7 @@ architecture rtl of AxiStreamDmaRingRead is endAddr : slv(63 downto 0); mode : slv(31 downto 0); state : StateType; - axilReq : AxiLiteMasterReqType; + axilReq : AxiLiteReqType; dmaReq : AxiReadDmaReqType; intStatusSlave : AxiStreamSlaveType; end record RegType; @@ -101,7 +98,7 @@ architecture rtl of AxiStreamDmaRingRead is endAddr => (others => '0'), mode => (others => '0'), state => START_LOW_S, - axilReq => AXI_LITE_MASTER_REQ_INIT_C, + axilReq => AXI_LITE_REQ_INIT_C, dmaReq => AXI_READ_DMA_REQ_INIT_C, intStatusSlave => AXI_STREAM_SLAVE_INIT_C); @@ -110,7 +107,7 @@ architecture rtl of AxiStreamDmaRingRead is signal intStatusMaster : AxiStreamMasterType; - signal axilAck : AxiLiteMasterAckType; + signal axilAck : AxiLiteAckType; signal dmaAck : AxiReadDmaAckType; diff --git a/axi/dma/rtl/AxiStreamDmaRingWrite.vhd b/axi/dma/rtl/AxiStreamDmaRingWrite.vhd index 8cc3e0e1d8..6725ecec34 100644 --- a/axi/dma/rtl/AxiStreamDmaRingWrite.vhd +++ b/axi/dma/rtl/AxiStreamDmaRingWrite.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamDmaRingWrite.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-29 --- Last update: 2017-02-20 ------------------------------------------------------------------------------- -- Description: AXI Stream to DMA Ring Buffer Write Module ------------------------------------------------------------------------------- diff --git a/axi/dma/rtl/AxiStreamDmaV2.vhd b/axi/dma/rtl/AxiStreamDmaV2.vhd index d19db944c9..b518c3872a 100644 --- a/axi/dma/rtl/AxiStreamDmaV2.vhd +++ b/axi/dma/rtl/AxiStreamDmaV2.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamDmaV2.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-02-02 --- Last update: 2018-01-10 ------------------------------------------------------------------------------- -- Description: -- Generic AXI Stream DMA block for frame at a time transfers. @@ -139,7 +137,7 @@ begin AXI_CONFIG_G => AXI_DESC_CONFIG_G, DESC_AWIDTH_G => DESC_AWIDTH_G, DESC_ARB_G => DESC_ARB_G, - ACK_WAIT_BVALID_G => true) + ACK_WAIT_BVALID_G => false) port map ( -- Clock/Reset axiClk => axiClk, @@ -214,7 +212,7 @@ begin AXI_CONFIG_G => AXI_DMA_CONFIG_G, PIPE_STAGES_G => WR_PIPE_STAGES_G, BURST_BYTES_G => BURST_BYTES_G, - ACK_WAIT_BVALID_G => true) + ACK_WAIT_BVALID_G => false) port map ( axiClk => axiClk, axiRst => axiReset(i), diff --git a/axi/dma/rtl/AxiStreamDmaV2Desc.vhd b/axi/dma/rtl/AxiStreamDmaV2Desc.vhd index a7beb4c74e..e005af169f 100644 --- a/axi/dma/rtl/AxiStreamDmaV2Desc.vhd +++ b/axi/dma/rtl/AxiStreamDmaV2Desc.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamDmaV2Desc.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-02-02 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: -- Descriptor manager for AXI DMA read and write engines. @@ -30,14 +28,30 @@ use work.ArbiterPkg.all; entity AxiStreamDmaV2Desc is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + + -- Number of read & write DMA engines to support for each descriptor engine CHAN_COUNT_G : integer range 1 to 16 := 1; - AXIL_BASE_ADDR_G : slv(31 downto 0) := x"00000000"; - AXI_READY_EN_G : boolean := false; + + -- Base address of descriptor registers & FIFOs + AXIL_BASE_ADDR_G : slv(31 downto 0) := x"00000000"; + + -- Support ready handshaking for output AXI transactions. If false user + -- must provide an AXI FIFO at the output with SLAVE_READY_EN_G = False + AXI_READY_EN_G : boolean := false; + + -- Configuration of AXI bus, must be 64 bits or 128 bits wide AXI_CONFIG_G : AxiConfigType := AXI_CONFIG_INIT_C; - DESC_AWIDTH_G : integer range 4 to 12 := 12; - DESC_ARB_G : boolean := true; - ACK_WAIT_BVALID_G : boolean := true); + + -- Number of descriptor entries in write FIFO and return ring buffers + DESC_AWIDTH_G : integer range 4 to 32 := 12; + + -- Choose between one-clock arbitration for return descritors or count and check selection + DESC_ARB_G : boolean := true; + + -- Set to true to wait for bvalid status return before moving on to next descriptor DMA + ACK_WAIT_BVALID_G : boolean := true); + port ( -- Clock/Reset axiClk : in sl; @@ -72,8 +86,9 @@ end AxiStreamDmaV2Desc; architecture rtl of AxiStreamDmaV2Desc is - constant CROSSBAR_CONN_C : slv(15 downto 0) := x"FFFF"; - + -- Descriptor width, 64-bits or 128-bits + constant DESC_128_EN_C : boolean := AXI_CONFIG_G.DATA_BYTES_C >= 16; + constant CB_COUNT_C : integer := 2; constant LOC_INDEX_C : natural := 0; @@ -88,22 +103,23 @@ architecture rtl of AxiStreamDmaV2Desc is LOC_INDEX_C => ( baseAddr => LOC_BASE_ADDR_C, addrBits => LOC_NUM_BITS_C, - connectivity => CROSSBAR_CONN_C), + connectivity => x"FFFF"), ADDR_INDEX_C => ( baseAddr => ADDR_BASE_ADDR_C, addrBits => ADDR_NUM_BITS_C, - connectivity => CROSSBAR_CONN_C)); + connectivity => x"FFFF")); - signal intReadMasters : AxiLiteReadMasterArray(CB_COUNT_C-1 downto 0); - signal intReadSlaves : AxiLiteReadSlaveArray(CB_COUNT_C-1 downto 0); - signal intWriteMasters : AxiLiteWriteMasterArray(CB_COUNT_C-1 downto 0); - signal intWriteSlaves : AxiLiteWriteSlaveArray(CB_COUNT_C-1 downto 0); + constant CHAN_SIZE_C : integer := bitSize(CHAN_COUNT_G-1); + constant RET_COUNT_C : integer := CHAN_COUNT_G*2; + constant RET_SIZE_C : integer := bitSize(RET_COUNT_C-1); - type DescStateType is (IDLE_S, WRITE_S, READ_S, WAIT_S); + constant RD_FIFO_CNT_C : integer := ite(DESC_128_EN_C,4,2); + constant RD_FIFO_BITS_C : integer := RD_FIFO_CNT_C * 32; - constant CHAN_SIZE_C : integer := bitSize(CHAN_COUNT_G-1); - constant DESC_COUNT_C : integer := CHAN_COUNT_G*2; - constant DESC_SIZE_C : integer := bitSize(DESC_COUNT_C-1); + constant WR_FIFO_CNT_C : integer := ite(DESC_128_EN_C,2,1); + constant WR_FIFO_BITS_C : integer := WR_FIFO_CNT_C * 32; + + type DescStateType is (IDLE_S, WRITE_S, READ_S, WAIT_S); type RegType is record @@ -123,13 +139,14 @@ architecture rtl of AxiStreamDmaV2Desc is axiWriteMaster : AxiWriteMasterType; -- Configuration - buffBaseAddr : slv(63 downto 32); -- For buffer entries + buffBaseAddr : slv(31 downto 0); -- For buffer entries wrBaseAddr : slv(63 downto 0); -- For wr ring buffer rdBaseAddr : slv(63 downto 0); -- For rd ring buffer - maxSize : slv(23 downto 0); + maxSize : slv(31 downto 0); contEn : sl; dropEn : sl; enable : sl; + forceInt : sl; intEnable : sl; online : slv(CHAN_COUNT_G-1 downto 0); acknowledge : slv(CHAN_COUNT_G-1 downto 0); @@ -142,8 +159,8 @@ architecture rtl of AxiStreamDmaV2Desc is -- FIFOs fifoDin : slv(31 downto 0); - wrFifoWr : sl; - rdFifoWr : slv(1 downto 0); + wrFifoWr : slv(WR_FIFO_CNT_C-1 downto 0); + rdFifoWr : slv(RD_FIFO_CNT_C-1 downto 0); addrFifoSel : sl; wrFifoRd : sl; wrFifoValidDly : slv(1 downto 0); @@ -162,11 +179,11 @@ architecture rtl of AxiStreamDmaV2Desc is wrReqMissed : slv(31 downto 0); -- Desc Return - descRetList : slv(DESC_COUNT_C-1 downto 0); + descRetList : slv(RET_COUNT_C-1 downto 0); descState : DescStateType; - descRetCnt : natural range 0 to DESC_COUNT_C-1; - descRetNum : slv(DESC_SIZE_C-1 downto 0); - descRetAcks : slv(DESC_COUNT_C-1 downto 0); + descRetCnt : natural range 0 to RET_COUNT_C-1; + descRetNum : slv(RET_SIZE_C-1 downto 0); + descRetAcks : slv(RET_COUNT_C-1 downto 0); wrIndex : slv(DESC_AWIDTH_G-1 downto 0); wrMemAddr : slv(63 downto 0); rdIndex : slv(DESC_AWIDTH_G-1 downto 0); @@ -192,6 +209,7 @@ architecture rtl of AxiStreamDmaV2Desc is contEn => '0', dropEn => '0', enable => '0', + forceInt => '0', intEnable => '0', online => (others => '0'), acknowledge => (others => '0'), @@ -202,7 +220,7 @@ architecture rtl of AxiStreamDmaV2Desc is buffRdCache => (others => '0'), buffWrCache => (others => '0'), fifoDin => (others => '0'), - wrFifoWr => '0', + wrFifoWr => (others => '0'), rdFifoWr => (others => '0'), addrFifoSel => '0', wrFifoRd => '0', @@ -235,10 +253,10 @@ architecture rtl of AxiStreamDmaV2Desc is signal r : RegType := REG_INIT_C; signal rin : RegType; signal pause : sl; - signal rdFifoValid : slv(1 downto 0); - signal rdFifoDout : slv(63 downto 0); - signal wrFifoValid : sl; - signal wrFifoDout : slv(15 downto 0); + signal rdFifoValid : slv(RD_FIFO_CNT_C-1 downto 0); + signal rdFifoDout : slv(RD_FIFO_BITS_C-1 downto 0); + signal wrFifoValid : slv(WR_FIFO_CNT_C-1 downto 0); + signal wrFifoDout : slv(WR_FIFO_BITS_C-1 downto 0); signal addrRamDout : slv(31 downto 0); signal addrRamAddr : slv(DESC_AWIDTH_G-1 downto 0); signal intSwAckEn : sl; @@ -247,6 +265,11 @@ architecture rtl of AxiStreamDmaV2Desc is signal invalidCount : sl; signal diffCnt : slv(31 downto 0); + signal intReadMasters : AxiLiteReadMasterArray(CB_COUNT_C-1 downto 0); + signal intReadSlaves : AxiLiteReadSlaveArray(CB_COUNT_C-1 downto 0); + signal intWriteMasters : AxiLiteWriteMasterArray(CB_COUNT_C-1 downto 0); + signal intWriteSlaves : AxiLiteWriteSlaveArray(CB_COUNT_C-1 downto 0); + -- attribute dont_touch : string; -- attribute dont_touch of r : signal is "true"; -- attribute dont_touch of intSwAckEn : signal is "true"; @@ -258,108 +281,119 @@ begin ----------------------------------------- -- Crossbar ----------------------------------------- - U_AxiCrossbar : entity work.AxiLiteCrossbar - generic map ( - TPD_G => TPD_G, - NUM_SLAVE_SLOTS_G => 1, - NUM_MASTER_SLOTS_G => CB_COUNT_C, - DEC_ERROR_RESP_G => AXI_RESP_OK_C, - MASTERS_CONFIG_G => AXI_CROSSBAR_MASTERS_CONFIG_C) - port map ( - axiClk => axiClk, - axiClkRst => axiRst, - sAxiWriteMasters(0) => axilWriteMaster, - sAxiWriteSlaves(0) => axilWriteSlave, - sAxiReadMasters(0) => axilReadMaster, - sAxiReadSlaves(0) => axilReadSlave, - mAxiWriteMasters => intWriteMasters, - mAxiWriteSlaves => intWriteSlaves, - mAxiReadMasters => intReadMasters, - mAxiReadSlaves => intReadSlaves); + U_CbEn: if DESC_128_EN_C = False generate + U_AxiCrossbar : entity work.AxiLiteCrossbar + generic map ( + TPD_G => TPD_G, + NUM_SLAVE_SLOTS_G => 1, + NUM_MASTER_SLOTS_G => CB_COUNT_C, + DEC_ERROR_RESP_G => AXI_RESP_OK_C, + MASTERS_CONFIG_G => AXI_CROSSBAR_MASTERS_CONFIG_C) + port map ( + axiClk => axiClk, + axiClkRst => axiRst, + sAxiWriteMasters(0) => axilWriteMaster, + sAxiWriteSlaves(0) => axilWriteSlave, + sAxiReadMasters(0) => axilReadMaster, + sAxiReadSlaves(0) => axilReadSlave, + mAxiWriteMasters => intWriteMasters, + mAxiWriteSlaves => intWriteSlaves, + mAxiReadMasters => intReadMasters, + mAxiReadSlaves => intReadSlaves); + end generate; + + U_CbDis: if DESC_128_EN_C = True generate + intWriteMasters(0) <= axilWriteMaster; + axilWriteSlave <= intWriteSlaves(0); + intReadMasters(0) <= axilReadMaster; + axilReadSlave <= intReadSlaves(0); + + intWriteMasters(1) <= AXI_LITE_WRITE_MASTER_INIT_C; + intReadMasters(1) <= AXI_LITE_READ_MASTER_INIT_C; + end generate; ----------------------------------------- - -- Write Free List FIFO + -- Write Free List FIFOs ----------------------------------------- - U_DescFifo : entity work.Fifo - generic map ( - TPD_G => TPD_G, - GEN_SYNC_FIFO_G => true, - FWFT_EN_G => true, - DATA_WIDTH_G => 16, - ADDR_WIDTH_G => DESC_AWIDTH_G) - port map ( - rst => r.fifoReset, - wr_clk => axiClk, - wr_en => r.wrFifoWr, - din => r.fifoDin(15 downto 0), - rd_clk => axiClk, - rd_en => r.wrFifoRd, - dout => wrFifoDout, - valid => wrFifoValid); + U_DescGen: for i in 0 to WR_FIFO_CNT_C-1 generate + U_DescFifo : entity work.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => 32, + ADDR_WIDTH_G => DESC_AWIDTH_G) + port map ( + rst => r.fifoReset, + wr_clk => axiClk, + wr_en => r.wrFifoWr(i), + din => r.fifoDin, + rd_clk => axiClk, + rd_en => r.wrFifoRd, + dout => wrFifoDout((i*32)+31 downto i*32), + valid => wrFifoValid(i)); + end generate; ----------------------------------------- -- Read Transaction FIFOs ----------------------------------------- - U_RdLowFifo : entity work.Fifo - generic map ( - TPD_G => TPD_G, - GEN_SYNC_FIFO_G => true, - FWFT_EN_G => true, - DATA_WIDTH_G => 32, - ADDR_WIDTH_G => DESC_AWIDTH_G) - port map ( - rst => r.fifoReset, - wr_clk => axiClk, - wr_en => r.rdFifoWr(0), - din => r.fifoDin, - rd_clk => axiClk, - rd_en => r.rdFifoRd, - dout => rdFifoDout(31 downto 0), - valid => rdFifoValid(0)); - - U_RdHighFifo : entity work.Fifo - generic map ( - TPD_G => TPD_G, - GEN_SYNC_FIFO_G => true, - FWFT_EN_G => true, - DATA_WIDTH_G => 32, - ADDR_WIDTH_G => DESC_AWIDTH_G) - port map ( - rst => r.fifoReset, - wr_clk => axiClk, - wr_en => r.rdFifoWr(1), - din => r.fifoDin, - rd_clk => axiClk, - rd_en => r.rdFifoRd, - dout => rdFifoDout(63 downto 32), - valid => rdFifoValid(1)); + U_RdFifoGen: for i in 0 to RD_FIFO_CNT_C-1 generate + U_RdFifo : entity work.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => 32, + ADDR_WIDTH_G => DESC_AWIDTH_G) + port map ( + rst => r.fifoReset, + wr_clk => axiClk, + wr_en => r.rdFifoWr(i), + din => r.fifoDin, + rd_clk => axiClk, + rd_en => r.rdFifoRd, + dout => rdFifoDout((i*32)+31 downto i*32), + valid => rdFifoValid(i)); + end generate; ----------------------------------------- - -- Address RAM + -- Address RAM, only used for width=64 ----------------------------------------- - U_AddrRam : entity work.AxiDualPortRam - generic map ( - TPD_G => TPD_G, - REG_EN_G => true, - BRAM_EN_G => true, - COMMON_CLK_G => true, - ADDR_WIDTH_G => DESC_AWIDTH_G, - DATA_WIDTH_G => 32) - port map ( - axiClk => axiClk, - axiRst => axiRst, - axiReadMaster => intReadMasters(ADDR_INDEX_C), - axiReadSlave => intReadSlaves(ADDR_INDEX_C), - axiWriteMaster => intWriteMasters(ADDR_INDEX_C), - axiWriteSlave => intWriteSlaves(ADDR_INDEX_C), - clk => axiClk, - rst => axiRst, - addr => addrRamAddr, - dout => addrRamDout); + U_AddrEnGen: if DESC_128_EN_C = false generate + U_AddrRam : entity work.AxiDualPortRam + generic map ( + TPD_G => TPD_G, + REG_EN_G => true, + BRAM_EN_G => true, + COMMON_CLK_G => true, + ADDR_WIDTH_G => DESC_AWIDTH_G, + DATA_WIDTH_G => 32) + port map ( + axiClk => axiClk, + axiRst => axiRst, + axiReadMaster => intReadMasters(ADDR_INDEX_C), + axiReadSlave => intReadSlaves(ADDR_INDEX_C), + axiWriteMaster => intWriteMasters(ADDR_INDEX_C), + axiWriteSlave => intWriteSlaves(ADDR_INDEX_C), + clk => axiClk, + rst => axiRst, + addr => addrRamAddr, + dout => addrRamDout); + end generate; + + U_AddrDisGen: if DESC_128_EN_C = true generate + addrRamDout <= (others=>'0'); + intWriteSlaves(ADDR_INDEX_C) <= AXI_LITE_WRITE_SLAVE_INIT_C; + intReadSlaves(ADDR_INDEX_C) <= AXI_LITE_READ_SLAVE_INIT_C; + end generate; addrRamAddr <= wrFifoDout(DESC_AWIDTH_G-1 downto 0) when r.addrFifoSel = '0' else rdFifoDout(DESC_AWIDTH_G+3 downto 4); + ----------------------------------------- + -- Interrupt ACK Counter + ----------------------------------------- + -- Check for invalid count U_DspComparator : entity work.DspComparator generic map ( @@ -382,9 +416,9 @@ begin ibValid => r.intSwAckReq, ain => r.intReqCount, bin => r.intAckCount, - add => '0', -- '0' = subtract - obValid => intDiffValid, -- sync'd up with U_DspComparator - pOut => diffCnt); -- a - b <--> r.intReqCount - r.intAckCount + add => '0', -- '0' = subtract + obValid => intDiffValid, -- sync'd up with U_DspComparator + pOut => diffCnt); -- a - b <--> r.intReqCount - r.intAckCount -- Both DSPs are done intSwAckEn <= intDiffValid and intCompValid; @@ -403,7 +437,6 @@ begin variable v : RegType; variable wrReqList : slv(CHAN_COUNT_G-1 downto 0); - --variable descRetList : slv(DESC_COUNT_C-1 downto 0); variable descRetValid : sl; variable descIndex : natural; variable dmaRdReq : AxiReadDmaDescReqType; @@ -415,9 +448,9 @@ begin v := r; -- Clear one shot signals - v.rdFifoWr := "00"; + v.rdFifoWr := (others=>'0'); v.rdFifoRd := '0'; - v.wrFifoWr := '0'; + v.wrFifoWr := (others=>'0'); v.wrFifoRd := '0'; v.acknowledge := (others => '0'); @@ -429,8 +462,8 @@ begin axiSlaveWaitTxn(regCon, intWriteMasters(LOC_INDEX_C), intReadMasters(LOC_INDEX_C), v.axilWriteSlave, v.axilReadSlave); axiSlaveRegister(regCon, x"000", 0, v.enable); + axiSlaveRegisterR(regCon, x"000", 16, toSl(DESC_128_EN_C)); axiSlaveRegisterR(regCon, x"000", 24, toSlv(2, 8)); -- Version 2 = 2, Version1 = 0 - axiSlaveRegister(regCon, x"004", 0, v.intEnable); axiSlaveRegister(regCon, x"008", 0, v.contEn); axiSlaveRegister(regCon, x"00C", 0, v.dropEn); @@ -439,12 +472,14 @@ begin axiSlaveRegister(regCon, x"018", 0, v.rdBaseAddr(31 downto 0)); axiSlaveRegister(regCon, x"01C", 0, v.rdBaseAddr(63 downto 32)); axiSlaveRegister(regCon, x"020", 0, v.fifoReset); - axiSlaveRegister(regCon, x"024", 0, v.buffBaseAddr(63 downto 32)); + axiSlaveRegister(regCon, x"024", 0, v.buffBaseAddr); axiSlaveRegister(regCon, x"028", 0, v.maxSize); axiSlaveRegister(regCon, x"02C", 0, v.online); axiSlaveRegister(regCon, x"030", 0, v.acknowledge); axiSlaveRegisterR(regCon, x"034", 0, toSlv(CHAN_COUNT_G, 8)); + axiSlaveRegisterR(regCon, x"034", 8, toSlv(AXI_CONFIG_G.ADDR_WIDTH_C, 8)); + axiSlaveRegisterR(regCon, x"034", 16,toSlv(AXI_CONFIG_G.DATA_BYTES_C, 8)); axiSlaveRegisterR(regCon, x"038", 0, toSlv(DESC_AWIDTH_G, 8)); axiSlaveRegister(regCon, x"03C", 0, v.descWrCache); axiSlaveRegister(regCon, x"03C", 8, v.buffWrCache); @@ -457,7 +492,7 @@ begin axiWrDetect(regCon, x"044", v.rdFifoWr(1)); axiSlaveRegister(regCon, x"048", 0, v.fifoDin); - axiWrDetect(regCon, x"048", v.wrFifoWr); + axiWrDetect(regCon, x"048", v.wrFifoWr(0)); axiSlaveRegister(regCon, x"04C", 0, v.intAckCount(15 downto 0)); axiSlaveRegister(regCon, x"04C", 17, v.intEnable); @@ -469,6 +504,19 @@ begin axiSlaveRegisterR(regCon, x"05C", 0, r.wrReqMissed); + if DESC_128_EN_C then + axiSlaveRegister(regCon, x"060", 0, v.fifoDin); + axiWrDetect(regCon, x"064", v.rdFifoWr(2)); + + axiSlaveRegister(regCon, x"064", 0, v.fifoDin); + axiWrDetect(regCon, x"064", v.rdFifoWr(3)); + + axiSlaveRegister(regCon, x"070", 0, v.fifoDin); + axiWrDetect(regCon, x"070", v.wrFifoWr(1)); + end if; + + axiSlaveRegister(regCon, x"080", 0, v.forceInt); + -- End transaction block axiSlaveDefault(regCon, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C); @@ -484,7 +532,7 @@ begin v.wrAddr := (others => '1'); v.wrAddrValid := '0'; else - v.wrFifoValidDly := (wrFifoValid and (not r.addrFifoSel)) & r.wrFifoValidDly(1); + v.wrFifoValidDly := (uAnd(wrFifoValid) and (not r.addrFifoSel)) & r.wrFifoValidDly(1); if r.wrFifoValidDly(0) = '1' then v.wrAddr := addrRamDout; v.wrAddrValid := '1'; @@ -497,7 +545,7 @@ begin v.rdAddr := (others => '1'); v.rdAddrValid := '0'; else - v.rdFifoValidDly := (rdFifoValid(0) and rdFifoValid(1) and r.addrFifoSel) & r.rdFifoValidDly(1); + v.rdFifoValidDly := (uAnd(rdFifoValid) and r.addrFifoSel) & r.rdFifoValidDly(1); if r.rdFifoValidDly(0) = '1' then v.rdAddr := addrRamDout; v.rdAddrValid := '1'; @@ -547,18 +595,29 @@ begin if r.enable = '0' then v.wrReqMissed := (others => '0'); - elsif wrReqList /= 0 and wrFifoValid = '0' then + elsif wrReqList /= 0 and uAnd(wrFifoValid) = '0' then v.wrReqMissed := r.wrReqMissed + 1; end if; -- Valid arbitration result else for i in 0 to CHAN_COUNT_G-1 loop - v.dmaWrDescAck(i).address := r.buffBaseAddr & r.wrAddr; - v.dmaWrDescAck(i).dropEn := r.dropEn; - v.dmaWrDescAck(i).contEn := r.contEn; - v.dmaWrDescAck(i).buffId(11 downto 0) := wrFifoDout(11 downto 0); - v.dmaWrDescAck(i).maxSize(23 downto 0) := r.maxSize; + + if DESC_128_EN_C then + v.dmaWrDescAck(i).address(63 downto 40) := r.buffBaseAddr(31 downto 8); + v.dmaWrDescAck(i).address(39 downto 4) := wrFifoDout(63 downto 28); + v.dmaWrDescAck(i).address(3 downto 0) := (others=>'0'); + else + v.dmaWrDescAck(i).address(63 downto 32) := r.buffBaseAddr; + v.dmaWrDescAck(i).address(31 downto 0) := r.wrAddr; + end if; + + v.dmaWrDescAck(i).dropEn := r.dropEn; + v.dmaWrDescAck(i).contEn := r.contEn; + v.dmaWrDescAck(i).maxSize := r.maxSize; + + v.dmaWrDescAck(i).buffId(27 downto 0) := wrFifoDout(27 downto 0); + end loop; v.dmaWrDescAck(conv_integer(r.wrReqNum)).valid := '1'; @@ -567,7 +626,6 @@ begin end if; - -------------------------------------- -- Read/Write Descriptor Returns -------------------------------------- @@ -589,8 +647,13 @@ begin end if; -- Generate descriptor ring addresses - v.wrMemAddr := r.wrBaseAddr + (r.wrIndex & "000"); - v.rdMemAddr := r.rdBaseAddr + (r.rdIndex & "000"); + if DESC_128_EN_C then + v.wrMemAddr := r.wrBaseAddr + (r.wrIndex & "0000"); + v.rdMemAddr := r.rdBaseAddr + (r.rdIndex & "0000"); + else + v.wrMemAddr := r.wrBaseAddr + (r.wrIndex & "000"); + v.rdMemAddr := r.rdBaseAddr + (r.rdIndex & "000"); + end if; -- State machine case r.descState is @@ -610,7 +673,7 @@ begin arbitrate(v.descRetList, r.descRetNum, v.descRetNum, descRetValid, v.descRetAcks); else -- Check the counter - if (r.descRetCnt = (DESC_COUNT_C-1)) then + if (r.descRetCnt = (RET_COUNT_C-1)) then -- Reset the counter v.descRetCnt := 0; else @@ -620,7 +683,7 @@ begin -- Check for valid if (v.descRetList(r.descRetCnt) = '1') then descRetValid := '1'; - v.descRetNum := toSlv(r.descRetCnt, DESC_SIZE_C); + v.descRetNum := toSlv(r.descRetCnt, RET_SIZE_C); else descRetValid := '0'; end if; @@ -639,7 +702,7 @@ begin ---------------------------------------------------------------------- when WRITE_S => if CHAN_COUNT_G > 1 then - descIndex := conv_integer(r.descRetNum(DESC_SIZE_C-1 downto 1)); + descIndex := conv_integer(r.descRetNum(RET_SIZE_C-1 downto 1)); else descIndex := 0; end if; @@ -650,20 +713,39 @@ begin -- Write data channel v.axiWriteMaster.wlast := '1'; - v.axiWriteMaster.wstrb := resize(x"FF", 128); - - -- Descriptor data - v.axiWriteMaster.wdata(63 downto 56) := dmaWrDescRet(descIndex).dest; - v.axiWriteMaster.wdata(55 downto 32) := dmaWrDescRet(descIndex).size(23 downto 0); - v.axiWriteMaster.wdata(31 downto 24) := dmaWrDescRet(descIndex).firstUser; - v.axiWriteMaster.wdata(23 downto 16) := dmaWrDescRet(descIndex).lastUser; - v.axiWriteMaster.wdata(15 downto 4) := dmaWrDescRet(descIndex).buffId(11 downto 0); - v.axiWriteMaster.wdata(3) := dmaWrDescRet(descIndex).continue; - v.axiWriteMaster.wdata(2 downto 0) := dmaWrDescRet(descIndex).result; - - -- Encoded channel into upper destination bits - if CHAN_COUNT_G > 1 then - v.axiWriteMaster.wdata(63 downto 64-CHAN_SIZE_C) := toSlv(descIndex, CHAN_SIZE_C); + + -- Descriptor data, 128-bits + if DESC_128_EN_C then + v.axiWriteMaster.wdata(127) := '1'; + v.axiWriteMaster.wdata(126 downto 108) := (others=>'0'); + v.axiWriteMaster.wdata(107 downto 104) := toSlv(descIndex,4); -- Channel + v.axiWriteMaster.wdata(103 downto 96) := dmaWrDescRet(descIndex).dest; + v.axiWriteMaster.wdata(95 downto 64) := dmaWrDescRet(descIndex).size; + v.axiWriteMaster.wdata(63 downto 32) := dmaWrDescRet(descIndex).buffId; + v.axiWriteMaster.wdata(31 downto 24) := dmaWrDescRet(descIndex).firstUser; + v.axiWriteMaster.wdata(23 downto 16) := dmaWrDescRet(descIndex).lastUser; + v.axiWriteMaster.wdata(15 downto 4) := (others=>'0'); + v.axiWriteMaster.wdata(3) := dmaWrDescRet(descIndex).continue; + v.axiWriteMaster.wdata(2 downto 0) := dmaWrDescRet(descIndex).result; + + v.axiWriteMaster.wstrb := resize(x"FFFF", 128); + + -- Descriptor data, 64-bits + else + v.axiWriteMaster.wdata(63 downto 56) := dmaWrDescRet(descIndex).dest; + v.axiWriteMaster.wdata(55 downto 32) := dmaWrDescRet(descIndex).size(23 downto 0); + v.axiWriteMaster.wdata(31 downto 24) := dmaWrDescRet(descIndex).firstUser; + v.axiWriteMaster.wdata(23 downto 16) := dmaWrDescRet(descIndex).lastUser; + v.axiWriteMaster.wdata(15 downto 4) := dmaWrDescRet(descIndex).buffId(11 downto 0); + v.axiWriteMaster.wdata(3) := dmaWrDescRet(descIndex).continue; + v.axiWriteMaster.wdata(2 downto 0) := dmaWrDescRet(descIndex).result; + + v.axiWriteMaster.wstrb := resize(x"FF", 128); + + -- Encoded channel into upper destination bits + if CHAN_COUNT_G > 1 then + v.axiWriteMaster.wdata(63 downto 64-CHAN_SIZE_C) := toSlv(descIndex, CHAN_SIZE_C); + end if; end if; v.axiWriteMaster.awvalid := '1'; @@ -676,7 +758,7 @@ begin ---------------------------------------------------------------------- when READ_S => if CHAN_COUNT_G > 1 then - descIndex := conv_integer(r.descRetNum(DESC_SIZE_C-1 downto 1)); + descIndex := conv_integer(r.descRetNum(RET_SIZE_C-1 downto 1)); else descIndex := 0; end if; @@ -687,14 +769,28 @@ begin -- Write data channel v.axiWriteMaster.wlast := '1'; - v.axiWriteMaster.wstrb := resize(x"FF", 128); - -- Descriptor data - v.axiWriteMaster.wdata(63 downto 32) := x"00000001"; - v.axiWriteMaster.wdata(31 downto 16) := (others => '0'); - v.axiWriteMaster.wdata(15 downto 4) := dmaRdDescRet(descIndex).buffId(11 downto 0); - v.axiWriteMaster.wdata(3) := '0'; - v.axiWriteMaster.wdata(2 downto 0) := dmaRdDescRet(descIndex).result; + -- Descriptor data, 128-bits + if DESC_128_EN_C then + v.axiWriteMaster.wdata(127) := '1'; + v.axiWriteMaster.wdata(126 downto 64) := (others => '0'); + v.axiWriteMaster.wdata(63 downto 32) := dmaWrDescRet(descIndex).buffId; + v.axiWriteMaster.wdata(31 downto 3) := (others => '0'); + v.axiWriteMaster.wdata(2 downto 0) := dmaWrDescRet(descIndex).result; + + v.axiWriteMaster.wstrb := resize(x"FFFF", 128); + + -- Descriptor data, 64-bits + else + v.axiWriteMaster.wdata(63 downto 32) := x"00000001"; + v.axiWriteMaster.wdata(31 downto 16) := (others => '0'); + v.axiWriteMaster.wdata(15 downto 4) := dmaRdDescRet(descIndex).buffId(11 downto 0); + v.axiWriteMaster.wdata(3) := '0'; + v.axiWriteMaster.wdata(2 downto 0) := dmaRdDescRet(descIndex).result; + + v.axiWriteMaster.wstrb := resize(x"FF", 128); + + end if; v.axiWriteMaster.awvalid := '1'; v.axiWriteMaster.wvalid := '1'; @@ -716,13 +812,19 @@ begin end case; - -- Copy the lowest 64-bit word to the entire bus (refer to "section 9.3 Narrow transfers" of the AMBA spec) - for i in 15 downto 1 loop - v.axiWriteMaster.wdata((64*i)+63 downto (64*i)) := v.axiWriteMaster.wdata(63 downto 0); - end loop; + -- Copy the lowest words to the entire bus (refer to "section 9.3 Narrow transfers" of the AMBA spec) + if DESC_128_EN_C then + for i in 7 downto 1 loop + v.axiWriteMaster.wdata((128*i)+127 downto (128*i)) := v.axiWriteMaster.wdata(127 downto 0); + end loop; + else + for i in 15 downto 1 loop + v.axiWriteMaster.wdata((64*i)+63 downto (64*i)) := v.axiWriteMaster.wdata(63 downto 0); + end loop; + end if; -- Drive interrupt, avoid false firings during ack - if r.intReqCount /= 0 and r.intSwAckReq = '0' then + if (r.intReqCount /= 0 or r.forceInt = '1') and r.intSwAckReq = '0' then v.interrupt := r.intEnable; else v.interrupt := '0'; @@ -730,6 +832,7 @@ begin -- Ack request from software if r.intSwAckReq = '1' then + v.forceInt := '0'; -- DSPs are done if intSwAckEn = '1' then @@ -754,6 +857,7 @@ begin v.intReqEn := '0'; v.intReqCount := (others => '0'); v.interrupt := '0'; + v.forceInt := '0'; end if; -------------------------------------- @@ -767,23 +871,41 @@ begin end if; end loop; - -- Format request - dmaRdReq := AXI_READ_DMA_DESC_REQ_INIT_C; - dmaRdReq.valid := r.rdAddrValid; - dmaRdReq.address := r.buffBaseAddr & r.rdAddr; - dmaRdReq.dest := rdFifoDout(63 downto 56); - dmaRdReq.size(23 downto 0) := rdFifoDout(55 downto 32); - dmaRdReq.firstUser := rdFifoDout(31 downto 24); - dmaRdReq.lastUser := rdFifoDout(23 downto 16); - dmaRdReq.buffId(11 downto 0) := rdFifoDout(15 downto 4); - dmaRdReq.continue := rdFifoDout(3); - - -- Upper dest bits select channel - if CHAN_COUNT_G > 1 then - rdIndex := conv_integer(dmaRdReq.dest(7 downto 8-CHAN_SIZE_C)); - dmaRdReq.dest(7 downto 8-CHAN_SIZE_C) := (others => '0'); - else - rdIndex := 0; + dmaRdReq := AXI_READ_DMA_DESC_REQ_INIT_C; + dmaRdReq.valid := r.rdAddrValid; + + -- Format request, 128-bits + if DESC_128_EN_C then + dmaRdReq.address(63 downto 40) := r.buffBaseAddr(31 downto 8); + dmaRdReq.address(39 downto 4) := rdFifoDout(127 downto 92); + dmaRdReq.address(3 downto 0) := (others=>'0'); + dmaRdReq.buffId(27 downto 0) := rdFifoDout(91 downto 64); + dmaRdReq.size := rdFifoDout(63 downto 32); + dmaRdReq.firstUser := rdFifoDout(31 downto 24); + dmaRdReq.lastUser := rdFifoDout(23 downto 16); + dmaRdReq.dest := rdFifoDout(15 downto 8); + dmaRdReq.continue := rdFifoDout(3); + + rdIndex := conv_integer(rdFifoDout(7 downto 4)); + + -- Format request, 64-bits + else + dmaRdReq.address(63 downto 32) := r.buffBaseAddr; + dmaRdReq.address(31 downto 0) := r.rdAddr; + dmaRdReq.dest := rdFifoDout(63 downto 56); + dmaRdReq.size(23 downto 0) := rdFifoDout(55 downto 32); + dmaRdReq.firstUser := rdFifoDout(31 downto 24); + dmaRdReq.lastUser := rdFifoDout(23 downto 16); + dmaRdReq.buffId(11 downto 0) := rdFifoDout(15 downto 4); + dmaRdReq.continue := rdFifoDout(3); + + -- Upper dest bits select channel + if CHAN_COUNT_G > 1 then + rdIndex := conv_integer(dmaRdReq.dest(7 downto 8-CHAN_SIZE_C)); + dmaRdReq.dest(7 downto 8-CHAN_SIZE_C) := (others => '0'); + else + rdIndex := 0; + end if; end if; -- Pull next entry if we are not waiting for ack on given channel diff --git a/axi/dma/rtl/AxiStreamDmaV2DescEmulate.vhd b/axi/dma/rtl/AxiStreamDmaV2DescEmulate.vhd index 0733312f8c..e75f3e4c25 100644 --- a/axi/dma/rtl/AxiStreamDmaV2DescEmulate.vhd +++ b/axi/dma/rtl/AxiStreamDmaV2DescEmulate.vhd @@ -1,11 +1,9 @@ ------------------------------------------------------------------------------- -- File : AxiStreamDmaV2DescEmulate.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-02-02 --- Last update: 2018-01-09 ------------------------------------------------------------------------------- --- Description: --- Descriptor manager for AXI DMA read and write engines. +-- Description: Emulates the firmware/software descriptor manager +-- for AXI DMA read and write engines. ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the @@ -32,7 +30,6 @@ entity AxiStreamDmaV2DescEmulate is generic ( TPD_G : time := 1 ns; AXI_CACHE_G : slv(3 downto 0) := "0000"; - READ_EN_G : boolean := false; CHAN_COUNT_G : integer range 1 to 16 := 1; AXIL_BASE_ADDR_G : slv(31 downto 0) := x"00000000"; AXI_READY_EN_G : boolean := false; @@ -46,13 +43,13 @@ entity AxiStreamDmaV2DescEmulate is axiRst : in sl; -- Local AXI Lite Bus axilReadMaster : in AxiLiteReadMasterType; - axilReadSlave : out AxiLiteReadSlaveType; + axilReadSlave : out AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_OK_C; axilWriteMaster : in AxiLiteWriteMasterType; - axilWriteSlave : out AxiLiteWriteSlaveType; + axilWriteSlave : out AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C; -- Additional signals - interrupt : out sl; - online : out slv(CHAN_COUNT_G-1 downto 0); - acknowledge : out slv(CHAN_COUNT_G-1 downto 0); + interrupt : out sl := '0'; + online : out slv(CHAN_COUNT_G-1 downto 0) := (others => '0'); + acknowledge : out slv(CHAN_COUNT_G-1 downto 0) := (others => '0'); -- DMA write descriptor request, ack and return dmaWrDescReq : in AxiWriteDmaDescReqArray(CHAN_COUNT_G-1 downto 0); dmaWrDescAck : out AxiWriteDmaDescAckArray(CHAN_COUNT_G-1 downto 0); @@ -64,102 +61,116 @@ entity AxiStreamDmaV2DescEmulate is dmaRdDescRet : in AxiReadDmaDescRetArray(CHAN_COUNT_G-1 downto 0); dmaRdDescRetAck : out slv(CHAN_COUNT_G-1 downto 0); -- Config - axiRdCache : out slv(3 downto 0); - axiWrCache : out slv(3 downto 0); + axiRdCache : out slv(3 downto 0) := AXI_CACHE_G; + axiWrCache : out slv(3 downto 0) := AXI_CACHE_G; -- AXI Interface axiWriteMaster : out AxiWriteMasterType; axiWriteSlave : in AxiWriteSlaveType; - axiWriteCtrl : in AxiCtrlType := AXI_CTRL_UNUSED_C); + axiWriteCtrl : in AxiCtrlType := AXI_CTRL_UNUSED_C); end AxiStreamDmaV2DescEmulate; architecture rtl of AxiStreamDmaV2DescEmulate is type RegType is record - - -- Write descriptor interface dmaWrDescAck : AxiWriteDmaDescAckArray(CHAN_COUNT_G-1 downto 0); dmaWrDescRetAck : slv(CHAN_COUNT_G-1 downto 0); - - -- Read descriptor interface dmaRdDescReq : AxiReadDmaDescReqArray(CHAN_COUNT_G-1 downto 0); dmaRdDescRetAck : slv(CHAN_COUNT_G-1 downto 0); - + wrIndex : Slv8Array(CHAN_COUNT_G-1 downto 0); + rdIndex : Slv8Array(CHAN_COUNT_G-1 downto 0); + fillCnt : Slv8Array(CHAN_COUNT_G-1 downto 0); end record RegType; constant REG_INIT_C : RegType := ( dmaWrDescAck => (others => AXI_WRITE_DMA_DESC_ACK_INIT_C), dmaWrDescRetAck => (others => '0'), dmaRdDescReq => (others => AXI_READ_DMA_DESC_REQ_INIT_C), - dmaRdDescRetAck => (others => '0')); + dmaRdDescRetAck => (others => '0'), + wrIndex => (others => (others => '0')), + rdIndex => (others => (others => '0')), + fillCnt => (others => (others => '0'))); signal r : RegType := REG_INIT_C; signal rin : RegType; begin - axilReadSlave <= AXI_LITE_READ_SLAVE_INIT_C; - axilWriteSlave <= AXI_LITE_WRITE_SLAVE_INIT_C; - interrupt <= '0'; - online <= (others=>'0'); - acknowledge <= (others=>'0'); - axiWriteMaster <= AXI_WRITE_MASTER_INIT_C; + axilReadSlave <= AXI_LITE_READ_SLAVE_EMPTY_OK_C; + axilWriteSlave <= AXI_LITE_WRITE_SLAVE_EMPTY_OK_C; + interrupt <= '0'; + online <= (others => '0'); + acknowledge <= (others => '0'); + axiWriteMaster <= AXI_WRITE_MASTER_INIT_C; - comb : process (axiRst, r, dmaRdDescAck, dmaRdDescRet, dmaWrDescReq, dmaWrDescRet) is + comb : process (axiRst, dmaRdDescAck, dmaRdDescRet, dmaWrDescReq, + dmaWrDescRet, r) is variable v : RegType; + variable i : natural; begin + -- Latch the current value + v := r; - -------------------------------------- - -- Write Descriptor Requests - -------------------------------------- + -- Loop through the DMA lanes + for i in CHAN_COUNT_G-1 downto 0 loop - -- Clear acks - for i in 0 to CHAN_COUNT_G-1 loop + -- Reset strobes v.dmaWrDescAck(i).valid := '0'; + v.dmaWrDescRetAck(i) := '0'; + v.dmaRdDescRetAck(i) := '0'; - if dmaWrDescReq(i).valid = '1' then - v.dmaWrDescAck(i).valid := '1'; - v.dmaWrDescAck(i).address := r.dmaWrDescAck(i).Address + 8192; - v.dmaWrDescAck(i).dropEn := '0'; - v.dmaWrDescAck(i).maxSize := x"FFFFFFFF"; - v.dmaWrDescAck(i).contEn :='1'; - v.dmaWrDescAck(i).buffId := r.dmaWrDescAck(i).buffId + 1; - end if; - end loop; - - -------------------------------------- - -- Read/Write Descriptor Returns - -------------------------------------- - - for i in 0 to CHAN_COUNT_G-1 loop - v.dmaWrDescRetAck(i) := dmaWrDescRet(i).valid; - v.dmaRdDescRetAck(i) := dmaRdDescRet(i).valid; - end loop; - - -------------------------------------- - -- Read Descriptor Requests - -------------------------------------- - - -- Clear requests - for i in 0 to CHAN_COUNT_G-1 loop + -- Flow control if dmaRdDescAck(i) = '1' then v.dmaRdDescReq(i).valid := '0'; end if; - end loop; + if dmaRdDescRet(i).valid = '1' then + -- Reset the flag + v.dmaRdDescRetAck(i) := '1'; + -- Increment the read index + v.rdIndex(i) := r.rdIndex(i) + 1; + end if; + + -- Update the fill counter + v.fillCnt(i) := r.wrIndex(i) - r.rdIndex(i); + + -- Check for the REQ and not out of buffers + if (dmaWrDescReq(i).valid = '1') and (r.dmaWrDescAck(i).valid = '0') and (r.fillCnt(i) /= x"FF") then + -- Send the write descriptor + v.dmaWrDescAck(i).valid := '1'; + v.dmaWrDescAck(i).address(19 downto 12) := r.wrIndex(i); -- Write index + v.dmaWrDescAck(i).address(23 downto 20) := toSlv(i, 4); -- DMA Channel index + v.dmaWrDescAck(i).dropEn := '0'; + v.dmaWrDescAck(i).maxSize := toSlv(2**12, 32); -- 4kB buffers + v.dmaWrDescAck(i).contEn := '1'; + v.dmaWrDescAck(i).buffId(7 downto 0) := r.wrIndex(i); + -- Increment the write index + v.wrIndex(i) := r.wrIndex(i) + 1; + end if; - for i in 0 to CHAN_COUNT_G-1 loop - if v.dmaRdDescReq(i).valid = '0' and READ_EN_G then - v.dmaRdDescReq(i) := AXI_READ_DMA_DESC_REQ_INIT_C; - v.dmaRdDescReq(i).valid := '1'; - v.dmaRdDescReq(i).address := r.dmaRdDescReq(i).address + 8192; - v.dmaRdDescReq(i).dest := (others=>'0'); - v.dmaRdDescReq(i).size(23 downto 0) := x"001000"; - v.dmaRdDescReq(i).firstUser := (others=>'0'); - v.dmaRdDescReq(i).lastUser := (others=>'0'); - v.dmaRdDescReq(i).buffId(11 downto 0) := r.dmaRdDescReq(i).buffId(11 downto 0) + 1; - v.dmaRdDescReq(i).continue := '0'; + -- Check for the return descriptor + if (dmaWrDescRet(i).valid = '1') and (r.dmaRdDescReq(i).valid = '0') then + -- Respond with ACK + v.dmaWrDescRetAck(i) := '1'; + -- Send the read request + v.dmaRdDescReq(i).valid := '1'; + v.dmaRdDescReq(i).address(19 downto 12) := dmaWrDescRet(i).buffId(7 downto 0); -- Write index + v.dmaRdDescReq(i).address(23 downto 20) := toSlv(i, 4); -- DMA Channel index + v.dmaRdDescReq(i).buffId := dmaWrDescRet(i).buffId; + v.dmaRdDescReq(i).firstUser := dmaWrDescRet(i).firstUser; + v.dmaRdDescReq(i).lastUser := dmaWrDescRet(i).lastUser; + v.dmaRdDescReq(i).size := dmaWrDescRet(i).size; + v.dmaRdDescReq(i).continue := dmaWrDescRet(i).continue; + v.dmaRdDescReq(i).id := dmaWrDescRet(i).id; + v.dmaRdDescReq(i).dest := dmaWrDescRet(i).dest; end if; + end loop; + -- Outputs + dmaWrDescAck <= r.dmaWrDescAck; + dmaWrDescRetAck <= r.dmaWrDescRetAck; + dmaRdDescReq <= r.dmaRdDescReq; + dmaRdDescRetAck <= r.dmaRdDescRetAck; + -- Reset if (axiRst = '1') then v := REG_INIT_C; @@ -168,13 +179,6 @@ begin -- Register the variable for next clock cycle rin <= v; - dmaWrDescAck <= r.dmaWrDescAck; - dmaWrDescRetAck <= r.dmaWrDescRetAck; - dmaRdDescReq <= r.dmaRdDescReq; - dmaRdDescRetAck <= r.dmaRdDescRetAck; - axiRdCache <= AXI_CACHE_G; - axiWrCache <= AXI_CACHE_G; - end process comb; seq : process (axiClk) is @@ -185,4 +189,3 @@ begin end process seq; end rtl; - diff --git a/axi/dma/rtl/AxiStreamDmaV2Read.vhd b/axi/dma/rtl/AxiStreamDmaV2Read.vhd index e58323cf5c..2e550640c2 100644 --- a/axi/dma/rtl/AxiStreamDmaV2Read.vhd +++ b/axi/dma/rtl/AxiStreamDmaV2Read.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamDmaV2Read.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-02-02 --- Last update: 2018-03-09 ------------------------------------------------------------------------------- -- Description: -- Block to transfer a single AXI Stream frame from memory using an AXI @@ -60,7 +58,7 @@ end AxiStreamDmaV2Read; architecture rtl of AxiStreamDmaV2Read is constant DATA_BYTES_C : positive := AXIS_CONFIG_G.TDATA_BYTES_C; - constant ADDR_LSB_C : natural := bitSize(DATA_BYTES_C-1); + constant ADDR_LSB_C : natural := ite((DATA_BYTES_C=1),0,bitSize(DATA_BYTES_C-1)); constant PEND_LSB_C : natural := bitSize(PEND_THRESH_G-1); type ReqStateType is ( @@ -169,7 +167,7 @@ begin v.sMaster.tUser := (others => '0'); v.sMaster.tStrb := (others => '1'); if (AXIS_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - v.sMaster.tKeep := toSlv(AXIS_CONFIG_G.TDATA_BYTES_C, 16); + v.sMaster.tKeep := toSlv(AXIS_CONFIG_G.TDATA_BYTES_C, AXI_STREAM_MAX_TKEEP_WIDTH_C); else v.sMaster.tKeep := (others => '1'); end if; @@ -218,12 +216,15 @@ begin v.dmaRdDescRet.buffId := dmaRdDescReq.buffId; v.dmaRdDescRet.result := (others => '0'); -- Force address alignment - v.dmaRdDescReq.address(ADDR_LSB_C-1 downto 0) := (others => '0'); + if (DATA_BYTES_C > 1) then + v.dmaRdDescReq.address(ADDR_LSB_C-1 downto 0) := (others => '0'); + end if; -- Reset the counters v.reqCnt := (others => '0'); v.ackCnt := (others => '0'); -- Reset flags v.pending := false; + v.axiLen.valid := "00"; -- Check for DMA request if dmaRdDescReq.valid = '1' then v.dmaRdDescAck := '1'; @@ -325,11 +326,11 @@ begin -- Terminate the frame v.sMaster.tLast := not r.dmaRdDescReq.continue; if (AXIS_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - v.sMaster.tKeep := "00000000000" & r.size(4 downto 0); + v.sMaster.tKeep := resize(r.size(bitSize(AXI_STREAM_MAX_TKEEP_WIDTH_C)-1 downto 0), AXI_STREAM_MAX_TKEEP_WIDTH_C); else - v.sMaster.tKeep := genTKeep(conv_integer(r.size(4 downto 0))); + v.sMaster.tKeep := genTKeep(conv_integer(r.size(bitSize(AXI_STREAM_MAX_TKEEP_WIDTH_C)-1 downto 0))); end if; - v.sMaster.tStrb := genTKeep(conv_integer(r.size(4 downto 0))); + v.sMaster.tStrb := genTKeep(conv_integer(r.size(bitSize(AXI_STREAM_MAX_TKEEP_WIDTH_C)-1 downto 0))); -- Set last user field axiStreamSetUserField (AXIS_CONFIG_G, v.sMaster, r.dmaRdDescReq.lastUser(AXIS_CONFIG_G.TUSER_BITS_C-1 downto 0)); -- Set the flags diff --git a/axi/dma/rtl/AxiStreamDmaV2Write.vhd b/axi/dma/rtl/AxiStreamDmaV2Write.vhd index 5a082ad025..a32b2c99fb 100644 --- a/axi/dma/rtl/AxiStreamDmaV2Write.vhd +++ b/axi/dma/rtl/AxiStreamDmaV2Write.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamDmaV2Write.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-02-02 --- Last update: 2017-02-02 ------------------------------------------------------------------------------- -- Description: -- Block to transfer a single AXI Stream frame into memory using an AXI @@ -187,9 +185,9 @@ begin -- Count number of bytes in return data if (AXIS_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - bytes := conv_integer(intAxisMaster.tKeep(4 downto 0));-- Assumes max AXIS.TDATA width of 128-bits + bytes := conv_integer(intAxisMaster.tKeep(bitSize(AXI_STREAM_MAX_TKEEP_WIDTH_C)-1 downto 0)); else - bytes := getTKeep(intAxisMaster.tKeep(DATA_BYTES_C-1 downto 0)); + bytes := getTKeep(intAxisMaster.tKeep(DATA_BYTES_C-1 downto 0),AXIS_CONFIG_G); end if; -- State machine @@ -214,8 +212,10 @@ begin -- Current destination matches incoming frame if r.dmaWrTrack.dest = intAxisMaster.tDest and r.dmaWrTrack.inUse = '1' then if r.dmaWrTrack.dropEn = '1' then + -- Next state v.state := DUMP_S; else + -- Next state v.state := ADDR_S; end if; @@ -228,13 +228,17 @@ begin -- Is entry valid or do we need a new buffer if trackData.inUse = '1' then if trackData.dropEn = '1' then + -- Next state v.state := DUMP_S; else + -- Next state v.state := ADDR_S; end if; else - v.state := REQ_S; + -- Request a new descriptor v.dmaWrDescReq.valid := '1'; + -- Next state + v.state := REQ_S; end if; end if; end if; @@ -254,8 +258,10 @@ begin -- Descriptor return calls for dumping frame? if dmaWrDescAck.dropEn = '1' then + -- Next state v.state := DUMP_S; else + -- Next state v.state := ADDR_S; end if; end if; @@ -317,13 +323,16 @@ begin v.wMaster.wdata((DATA_BYTES_C*8)-1 downto 0) := intAxisMaster.tData((DATA_BYTES_C*8)-1 downto 0); -- Set byte write strobes if (AXIS_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - v.wMaster.wstrb(15 downto 0) := genTKeep(bytes); + v.wMaster.wstrb(AXI_STREAM_MAX_TKEEP_WIDTH_C-1 downto 0) := genTKeep(bytes); else - v.wMaster.wstrb(DATA_BYTES_C-1 downto 0) := intAxisMaster.tKeep(DATA_BYTES_C-1 downto 0); + v.wMaster.wstrb(DATA_BYTES_C-1 downto 0) := intAxisMaster.tKeep(DATA_BYTES_C-1 downto 0); end if; -- Address and size increment v.dmaWrTrack.address := r.dmaWrTrack.address + DATA_BYTES_C; - v.dmaWrTrack.address(ADDR_LSB_C-1 downto 0) := (others => '0'); + -- Force address alignment + if (DATA_BYTES_C > 1) then + v.dmaWrTrack.address(ADDR_LSB_C-1 downto 0) := (others => '0'); + end if; -- Increment the byte counter v.dmaWrTrack.size := r.dmaWrTrack.size + bytes; v.dmaWrTrack.maxSize := r.dmaWrTrack.maxSize - bytes; diff --git a/axi/dma/rtl/AxiStreamDmaWrite.vhd b/axi/dma/rtl/AxiStreamDmaWrite.vhd index 7234af7e83..7dc11aefb6 100644 --- a/axi/dma/rtl/AxiStreamDmaWrite.vhd +++ b/axi/dma/rtl/AxiStreamDmaWrite.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamDmaWrite.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-25 --- Last update: 2016-12-02 ------------------------------------------------------------------------------- -- Description: -- Block to transfer a single AXI Stream frame into memory using an AXI @@ -71,7 +69,7 @@ architecture rtl of AxiStreamDmaWrite is constant DATA_BYTES_C : integer := LOC_AXIS_CONFIG_C.TDATA_BYTES_C; constant ADDR_LSB_C : integer := bitSize(DATA_BYTES_C-1); constant AWLEN_C : slv(7 downto 0) := getAxiLen(AXI_CONFIG_G, 4096); - constant FIFO_ADDR_WIDTH_C : natural := (AXI_CONFIG_G.LEN_BITS_C+1); + constant FIFO_ADDR_WIDTH_C : natural := ite((AXI_CONFIG_G.LEN_BITS_C<3),4,(AXI_CONFIG_G.LEN_BITS_C+1)); type StateType is ( IDLE_S, @@ -261,7 +259,7 @@ begin end if; -- Count number of bytes in return data - bytes := getTKeep(intAxisMaster.tKeep(DATA_BYTES_C-1 downto 0)); + bytes := getTKeep(intAxisMaster.tKeep(DATA_BYTES_C-1 downto 0),LOC_AXIS_CONFIG_C); -- Check the AXI stream data cache if (lastDet = '1') or (cache.pause = '1') then @@ -321,10 +319,12 @@ begin v.wMaster.awlen := resize(r.dmaReq.maxSize(ADDR_LSB_C+AXI_CONFIG_G.LEN_BITS_C-1 downto ADDR_LSB_C)-1, 8); end if; end if; + -- Update the Protection control + v.wMaster.awprot := r.dmaReq.prot; -- Latch AXI awlen value v.awlen := v.wMaster.awlen(AXI_CONFIG_G.LEN_BITS_C-1 downto 0); -- Update the threshold - v.threshold := '0' & v.awlen; + v.threshold := resize(v.awlen, FIFO_ADDR_WIDTH_C); v.threshold := v.threshold + 1; -- DMA request has dropped. Abort. This is needed to disable engine while it -- is still waiting for an inbound frame. @@ -355,7 +355,7 @@ begin -- Latch AXI awlen value v.awlen := v.wMaster.awlen(AXI_CONFIG_G.LEN_BITS_C-1 downto 0); -- Update the threshold - v.threshold := '0' & v.awlen; + v.threshold := resize(v.awlen, FIFO_ADDR_WIDTH_C); v.threshold := v.threshold + 1; -- DMA request has dropped. Abort. This is needed to disable engine while it -- is still waiting for an inbound frame. diff --git a/axi/dma/tb/dma_read_tb.vhd b/axi/dma/tb/dma_read_tb.vhd index feeaa4100e..3f04218d32 100755 --- a/axi/dma/tb/dma_read_tb.vhd +++ b/axi/dma/tb/dma_read_tb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : dma_read_tb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-02 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for DMA read ------------------------------------------------------------------------------- @@ -220,7 +218,7 @@ begin v.failed(2) := '1'; end if; -- Increment the byte counter - v.byteCnt := r.byteCnt + getTKeep(axisMaster.tKeep); + v.byteCnt := r.byteCnt + getTKeep(axisMaster.tKeep,AXIS_CONFIG_C); -- Check for EOF if (axisMaster.tLast = '1') then -- Check the firstUser @@ -265,7 +263,7 @@ begin ---------------------------------------------------------------------- end case; - -- Combinatoral outputs + -- Combinatorial outputs axisSlave <= v.axisSlave; -- Reset diff --git a/axi/dma/tb/dma_tb.vhd b/axi/dma/tb/dma_tb.vhd index b965ab31b0..1577c0ef27 100644 --- a/axi/dma/tb/dma_tb.vhd +++ b/axi/dma/tb/dma_tb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : dma_tb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-02 --- Last update: 2016-09-06 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for DMA engine ------------------------------------------------------------------------------- diff --git a/axi/simlink/sim/RogueStreamSim.vhd b/axi/simlink/sim/RogueStreamSim.vhd index 2b2be53aa2..6f14f0cfe9 100755 --- a/axi/simlink/sim/RogueStreamSim.vhd +++ b/axi/simlink/sim/RogueStreamSim.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RogueStreamSim.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-12-05 --- Last update: 2017-02-02 ------------------------------------------------------------------------------- -- Description: Rogue Stream Simulation Module ------------------------------------------------------------------------------- diff --git a/axi/simlink/sim/RogueStreamSimWrap.vhd b/axi/simlink/sim/RogueStreamSimWrap.vhd index b7f7e16b36..02d5d2723f 100755 --- a/axi/simlink/sim/RogueStreamSimWrap.vhd +++ b/axi/simlink/sim/RogueStreamSimWrap.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RogueStreamSim.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-12-05 --- Last update: 2017-02-02 ------------------------------------------------------------------------------- -- Description: Wrapper for Rogue Stream Simulation Module ------------------------------------------------------------------------------- @@ -129,9 +127,9 @@ begin obMaster.tDest <= toSlv(DEST_ID_G, 8); obMaster.tId <= (others => '0'); - obMaster.tKeep(15 downto 8) <= (others => '0'); - obMaster.tData(127 downto 64) <= (others => '0'); - obMaster.tUser(127 downto 64) <= (others => '0'); + obMaster.tKeep(AXI_STREAM_MAX_TKEEP_WIDTH_C-1 downto 8) <= (others => '0'); + obMaster.tData(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 64) <= (others => '0'); + obMaster.tUser(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 64) <= (others => '0'); ------------------------------------ -- Outbound diff --git a/base/fifo/rtl/Fifo.vhd b/base/fifo/rtl/Fifo.vhd index cfcf99cf84..7cb00de5f9 100644 --- a/base/fifo/rtl/Fifo.vhd +++ b/base/fifo/rtl/Fifo.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Fifo.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-07-14 --- Last update: 2014-05-05 ------------------------------------------------------------------------------- -- Description: FIFO Wrapper ------------------------------------------------------------------------------- diff --git a/base/fifo/rtl/FifoAsync.vhd b/base/fifo/rtl/FifoAsync.vhd index 0be06e402e..3fe7e18ea3 100644 --- a/base/fifo/rtl/FifoAsync.vhd +++ b/base/fifo/rtl/FifoAsync.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : FifoAsync.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-07-10 --- Last update: 2016-06-30 ------------------------------------------------------------------------------- -- Description: ASYNC FIFO module ------------------------------------------------------------------------------- diff --git a/base/fifo/rtl/FifoAsyncBuiltIn.vhd b/base/fifo/rtl/FifoAsyncBuiltIn.vhd index b60f491a9e..8cb9977c4d 100644 --- a/base/fifo/rtl/FifoAsyncBuiltIn.vhd +++ b/base/fifo/rtl/FifoAsyncBuiltIn.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : FifoAsyncBuiltIn.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-07-28 --- Last update: 2014-07-14 ------------------------------------------------------------------------------- -- Description: Wrapper for Xilinx's built-in ASYNC FIFO module ------------------------------------------------------------------------------- diff --git a/base/fifo/rtl/FifoCascade.vhd b/base/fifo/rtl/FifoCascade.vhd index 391556201b..3616899bbc 100644 --- a/base/fifo/rtl/FifoCascade.vhd +++ b/base/fifo/rtl/FifoCascade.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : FifoCascade.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-10 --- Last update: 2014-09-23 ------------------------------------------------------------------------------- -- Description: Wrapper for cascading FWFT FIFOs together ------------------------------------------------------------------------------- diff --git a/base/fifo/rtl/FifoMux.vhd b/base/fifo/rtl/FifoMux.vhd index 6bd1d15754..511be8ac0f 100644 --- a/base/fifo/rtl/FifoMux.vhd +++ b/base/fifo/rtl/FifoMux.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : FifoMux.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-07-24 --- Last update: 2015-01-14 ------------------------------------------------------------------------------- -- Description: Resizing FIFO module ------------------------------------------------------------------------------- diff --git a/base/fifo/rtl/FifoOutputPipeline.vhd b/base/fifo/rtl/FifoOutputPipeline.vhd index 3f43b3e3c9..35b583fad0 100644 --- a/base/fifo/rtl/FifoOutputPipeline.vhd +++ b/base/fifo/rtl/FifoOutputPipeline.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : FifoOutputPipeline.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-05 --- Last update: 2016-09-06 ------------------------------------------------------------------------------- -- Description: This module is used to sync a FWFT FIFO bus -- either as a pass through or with pipeline register stages. diff --git a/base/fifo/rtl/FifoSync.vhd b/base/fifo/rtl/FifoSync.vhd index 48b512452c..3dbefeea16 100644 --- a/base/fifo/rtl/FifoSync.vhd +++ b/base/fifo/rtl/FifoSync.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : FifoSync.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-07-10 --- Last update: 2016-10-27 ------------------------------------------------------------------------------- -- Description: SYNC FIFO module ------------------------------------------------------------------------------- diff --git a/base/fifo/rtl/FifoSyncBuiltIn.vhd b/base/fifo/rtl/FifoSyncBuiltIn.vhd index c19624bbe3..a19e8cac73 100644 --- a/base/fifo/rtl/FifoSyncBuiltIn.vhd +++ b/base/fifo/rtl/FifoSyncBuiltIn.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : FifoAsyncBuiltIn.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-07-28 --- Last update: 2014-07-14 ------------------------------------------------------------------------------- -- Description: Wrapper for Xilinx's built-in SYNC FIFO module ------------------------------------------------------------------------------- diff --git a/base/fifo/tb/FifoFwftTb.vhd b/base/fifo/tb/FifoFwftTb.vhd index 8caca1726e..e2e7fc1104 100644 --- a/base/fifo/tb/FifoFwftTb.vhd +++ b/base/fifo/tb/FifoFwftTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : FifoFwftTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-05 --- Last update: 2014-05-14 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the FifoFwft module ------------------------------------------------------------------------------- diff --git a/base/fifo/tb/FifoFwftTbSubModule.vhd b/base/fifo/tb/FifoFwftTbSubModule.vhd index aa5c980059..b1215a7447 100644 --- a/base/fifo/tb/FifoFwftTbSubModule.vhd +++ b/base/fifo/tb/FifoFwftTbSubModule.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : FifoTbSubModule.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-05 --- Last update: 2014-05-05 ------------------------------------------------------------------------------- -- Description: Simulation sub module for testing the FifoFwft modules ------------------------------------------------------------------------------- diff --git a/base/general/rtl/Arbiter.vhd b/base/general/rtl/Arbiter.vhd index b55fc31164..bd3db34060 100644 --- a/base/general/rtl/Arbiter.vhd +++ b/base/general/rtl/Arbiter.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Arbiter.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-04-30 --- Last update: 2013-09-25 ------------------------------------------------------------------------------- -- Description: Example Arbiter Module ------------------------------------------------------------------------------- diff --git a/base/general/rtl/ArbiterPkg.vhd b/base/general/rtl/ArbiterPkg.vhd index 34eac040b2..3364715a3d 100644 --- a/base/general/rtl/ArbiterPkg.vhd +++ b/base/general/rtl/ArbiterPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : ArbiterPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-05-01 --- Last update: 2017-02-23 ------------------------------------------------------------------------------- -- Description: Arbiter Package File ------------------------------------------------------------------------------- diff --git a/base/general/rtl/AsyncGearbox.vhd b/base/general/rtl/AsyncGearbox.vhd new file mode 100644 index 0000000000..6e34fa7f54 --- /dev/null +++ b/base/general/rtl/AsyncGearbox.vhd @@ -0,0 +1,192 @@ +------------------------------------------------------------------------------- +-- Title : Asynchronous Gearbox +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: A generic gearbox with asynchronous input and output clocks +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.StdRtlPkg.all; + +entity AsyncGearbox is + + generic ( + TPD_G : time := 1 ns; + SLAVE_WIDTH_G : positive; + MASTER_WIDTH_G : positive; + -- Pipelining generics + INPUT_PIPE_STAGES_G : natural := 0; + OUTPUT_PIPE_STAGES_G : natural := 0; + -- Async FIFO generics + FIFO_BRAM_EN_G : boolean := false; + FIFO_ADDR_WIDTH_G : positive := 4); + port ( + slaveClk : in sl; + slaveRst : in sl; + + -- input side data and flow control + slaveData : in slv(SLAVE_WIDTH_G-1 downto 0); + slaveValid : in sl := '1'; + slaveReady : out sl; + + -- sequencing and slip + slip : in sl := '0'; + + masterClk : in sl; + masterRst : in sl; + + -- output side data and flow control + masterData : out slv(MASTER_WIDTH_G-1 downto 0); + masterValid : out sl; + masterReady : in sl := '1'); + +end entity AsyncGearbox; + +architecture mapping of AsyncGearbox is + + constant SLAVE_FASTER_C : boolean := SLAVE_WIDTH_G <= MASTER_WIDTH_G; + + signal fastClk : sl; + signal fastRst : sl; + + signal gearboxDataIn : slv(SLAVE_WIDTH_G-1 downto 0); + signal gearboxValidIn : sl; + signal gearboxReadyIn : sl; + signal gearboxDataOut : slv(MASTER_WIDTH_G-1 downto 0); + signal gearboxValidOut : sl; + signal gearboxReadyOut : sl; + signal gearboxSlip : sl; + signal almostFull : sl; + signal writeEnable : sl; + +begin + + fastClk <= slaveClk when SLAVE_FASTER_C else masterClk; + fastRst <= slaveRst when SLAVE_FASTER_C else masterRst; + + U_SynchronizerOneShot_1 : entity work.SynchronizerOneShot + generic map ( + TPD_G => TPD_G) + port map ( + clk => fastClk, -- [in] + rst => fastRst, -- [in] + dataIn => slip, -- [in] + dataOut => gearboxSlip); -- [out] + + SLAVE_FIFO_GEN : if (not SLAVE_FASTER_C) generate + U_FifoAsync_1 : entity work.FifoAsync + generic map ( + TPD_G => TPD_G, + FWFT_EN_G => true, + DATA_WIDTH_G => SLAVE_WIDTH_G, + BRAM_EN_G => FIFO_BRAM_EN_G, + PIPE_STAGES_G => INPUT_PIPE_STAGES_G, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G + ) + port map ( + rst => slaveRst, -- [in] + wr_clk => slaveClk, -- [in] + wr_en => writeEnable, -- [in] + din => slaveData, -- [in] + almost_full => almostFull, -- [out] + rd_clk => fastClk, -- [in] + rd_en => gearboxReadyIn, -- [in] + dout => gearboxDataIn, -- [out] + valid => gearboxValidIn); -- [out] + slaveReady <= not(almostFull); + writeEnable <= slaveValid and not(almostFull); + end generate SLAVE_FIFO_GEN; + + NO_SLAVE_FIFO_GEN : if (SLAVE_FASTER_C) generate + U_Input : entity work.FifoOutputPipeline + generic map ( + TPD_G => TPD_G, + DATA_WIDTH_G => SLAVE_WIDTH_G, + PIPE_STAGES_G => INPUT_PIPE_STAGES_G) + port map ( + -- Clock and Reset + clk => slaveClk, + rst => slaveRst, + -- Slave Port + sData => slaveData, + sValid => slaveValid, + sRdEn => slaveReady, + -- Master Port + mData => gearboxDataIn, + mValid => gearboxValidIn, + mRdEn => gearboxReadyIn); + end generate NO_SLAVE_FIFO_GEN; + + U_Gearbox_1 : entity work.Gearbox + generic map ( + TPD_G => TPD_G, + SLAVE_WIDTH_G => SLAVE_WIDTH_G, + MASTER_WIDTH_G => MASTER_WIDTH_G) + port map ( + clk => fastClk, -- [in] + rst => fastRst, -- [in] + slaveData => gearboxDataIn, -- [in] + slaveValid => gearboxValidIn, -- [in] + slaveReady => gearboxReadyIn, -- [out] + masterData => gearboxDataOut, -- [out] + masterValid => gearboxValidOut, -- [out] + masterReady => gearboxReadyOut, -- [in] + slip => gearboxSlip); -- [in] + + MASTER_FIFO_GEN : if (SLAVE_FASTER_C) generate + U_FifoAsync_1 : entity work.FifoAsync + generic map ( + TPD_G => TPD_G, + FWFT_EN_G => true, + DATA_WIDTH_G => MASTER_WIDTH_G, + BRAM_EN_G => FIFO_BRAM_EN_G, + PIPE_STAGES_G => OUTPUT_PIPE_STAGES_G, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => fastRst, -- [in] + wr_clk => fastClk, -- [in] + wr_en => writeEnable, -- [in] + din => gearboxDataOut, -- [in] + almost_full => almostFull, -- [out] + rd_clk => masterClk, -- [in] + rd_en => masterReady, -- [in] + dout => masterData, -- [out] + valid => masterValid); -- [out] + gearboxReadyOut <= not(almostFull); + writeEnable <= gearboxValidOut and not(almostFull); + end generate MASTER_FIFO_GEN; + + NO_MASTER_FIFO_GEN : if (not SLAVE_FASTER_C) generate + U_Output : entity work.FifoOutputPipeline + generic map ( + TPD_G => TPD_G, + DATA_WIDTH_G => MASTER_WIDTH_G, + PIPE_STAGES_G => OUTPUT_PIPE_STAGES_G) + port map ( + -- Clock and Reset + clk => masterClk, + rst => masterRst, + -- Slave Port + sData => gearboxDataOut, + sValid => gearboxValidOut, + sRdEn => gearboxReadyOut, + -- Master Port + mData => masterData, + mValid => masterValid, + mRdEn => masterReady); + end generate NO_MASTER_FIFO_GEN; + +end mapping; diff --git a/base/general/rtl/CRC32Rtl.vhd b/base/general/rtl/CRC32Rtl.vhd index 89bdd23649..90991080ee 100644 --- a/base/general/rtl/CRC32Rtl.vhd +++ b/base/general/rtl/CRC32Rtl.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : CRC32Rtl.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-05-01 --- Last update: 2018-03-15 ------------------------------------------------------------------------------- -- Description: -- VHDL source file for CRC32 calculation to replace macro of Virtex5 in Virtex6 and Spartan6. diff --git a/base/general/rtl/ClockDivider.vhd b/base/general/rtl/ClockDivider.vhd index 2e77c8620c..94b15489f2 100644 --- a/base/general/rtl/ClockDivider.vhd +++ b/base/general/rtl/ClockDivider.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : ClockDivider.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-06-01 --- Last update: 2016-09-22 ------------------------------------------------------------------------------- -- Description: A clock divider with programmable duty cycle and phase delay. ------------------------------------------------------------------------------- diff --git a/base/general/rtl/Code10b12bPkg.vhd b/base/general/rtl/Code10b12bPkg.vhd index 9c306f3fc6..2457bdb4d7 100644 --- a/base/general/rtl/Code10b12bPkg.vhd +++ b/base/general/rtl/Code10b12bPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Code10b12bPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-05 --- Last update: 2016-10-26 ------------------------------------------------------------------------------- -- Description: 10B12B Package File ------------------------------------------------------------------------------- diff --git a/base/general/rtl/Code12b14bPkg.vhd b/base/general/rtl/Code12b14bPkg.vhd index 635abd2f10..d55b7374df 100644 --- a/base/general/rtl/Code12b14bPkg.vhd +++ b/base/general/rtl/Code12b14bPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Code12b14bPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-05 --- Last update: 2017-05-01 ------------------------------------------------------------------------------- -- Description: 12B14B Package File ------------------------------------------------------------------------------- diff --git a/base/general/rtl/Code8b10bPkg.vhd b/base/general/rtl/Code8b10bPkg.vhd index dc73a6a09a..9cbf230681 100644 --- a/base/general/rtl/Code8b10bPkg.vhd +++ b/base/general/rtl/Code8b10bPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Code8b10bPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-12 --- Last update: 2016-10-12 ------------------------------------------------------------------------------- -- Description: 8B10B Package File ------------------------------------------------------------------------------- diff --git a/base/general/rtl/Crc32.vhd b/base/general/rtl/Crc32.vhd index 1d194b3f9e..d9cb5bf375 100644 --- a/base/general/rtl/Crc32.vhd +++ b/base/general/rtl/Crc32.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Crc32.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-05-01 --- Last update: 2018-03-01 ------------------------------------------------------------------------------- -- Description: -- This is an implementation of a generic N-byte input CRC32 calculation. diff --git a/base/general/rtl/Crc32Parallel.vhd b/base/general/rtl/Crc32Parallel.vhd index 6ef4e73d47..048a0ad571 100644 --- a/base/general/rtl/Crc32Parallel.vhd +++ b/base/general/rtl/Crc32Parallel.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Crc32.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-05-01 --- Last update: 2018-03-01 ------------------------------------------------------------------------------- -- Description: -- This is an implementation of an 1-to-8-byte input CRC32 calculation. diff --git a/base/general/rtl/CrcPkg.vhd b/base/general/rtl/CrcPkg.vhd index 2027e98f37..91210a17b0 100644 --- a/base/general/rtl/CrcPkg.vhd +++ b/base/general/rtl/CrcPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : CrcPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-21 --- Last update: 2014-04-21 ------------------------------------------------------------------------------- -- Description: This package defines a few functions that are useful for -- computing CRC values. diff --git a/base/general/rtl/DS2411Core.vhd b/base/general/rtl/DS2411Core.vhd index 4f9bc646c2..03c6161955 100644 --- a/base/general/rtl/DS2411Core.vhd +++ b/base/general/rtl/DS2411Core.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DS2411Core.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2007-12-19 --- Last update: 2015-01-14 ------------------------------------------------------------------------------- -- Description: Controller for DS2411 64-bit serial ID PROM ------------------------------------------------------------------------------- diff --git a/base/general/rtl/Debouncer.vhd b/base/general/rtl/Debouncer.vhd index 8705cf5147..5e265bdee6 100644 --- a/base/general/rtl/Debouncer.vhd +++ b/base/general/rtl/Debouncer.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Debouncer.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-04-30 --- Last update: 2013-08-02 ------------------------------------------------------------------------------- -- Description: Debouncer for pushbutton switches ------------------------------------------------------------------------------- @@ -41,9 +39,10 @@ end entity Debouncer; architecture rtl of Debouncer is - constant CLK_PERIOD_C : real := 1.0/CLK_FREQ_G; - constant CNT_MAX_C : natural := getTimeRatio(DEBOUNCE_PERIOD_G, CLK_PERIOD_C) - 1; - constant POLARITY_EQ_C : boolean := ite(INPUT_POLARITY_G = OUTPUT_POLARITY_G, true, false); + constant CLK_PERIOD_C : real := 1.0/CLK_FREQ_G; + constant CNT_MAX_C : natural := getTimeRatio(DEBOUNCE_PERIOD_G, CLK_PERIOD_C) - 1; + constant POLARITY_EQ_C : boolean := ite(INPUT_POLARITY_G = OUTPUT_POLARITY_G, true, false); + constant SYNC_INIT_C : slv(1 downto 0) := (others => not INPUT_POLARITY_G); type RegType is record filter : integer range 0 to CNT_MAX_C; @@ -53,7 +52,7 @@ architecture rtl of Debouncer is constant REG_RESET_C : RegType := (filter => 0, - iSyncedDly => '0', + iSyncedDly => not INPUT_POLARITY_G, o => not OUTPUT_POLARITY_G); signal r : RegType := REG_RESET_C; @@ -69,7 +68,7 @@ begin RST_POLARITY_G => RST_POLARITY_G, RST_ASYNC_G => RST_ASYNC_G, STAGES_G => 2, - INIT_G => "00") + INIT_G => SYNC_INIT_C) port map ( clk => clk, rst => rst, diff --git a/base/general/rtl/Decoder10b12b.vhd b/base/general/rtl/Decoder10b12b.vhd index aeb26d63fd..25f6ad8842 100644 --- a/base/general/rtl/Decoder10b12b.vhd +++ b/base/general/rtl/Decoder10b12b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Decoder10b12b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-07 --- Last update: 2017-05-01 ------------------------------------------------------------------------------- -- Description: 10B12B Decoder Module ------------------------------------------------------------------------------- diff --git a/base/general/rtl/Decoder12b14b.vhd b/base/general/rtl/Decoder12b14b.vhd index a3a2437e68..1b9116aecd 100644 --- a/base/general/rtl/Decoder12b14b.vhd +++ b/base/general/rtl/Decoder12b14b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Decoder12b14b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-07 --- Last update: 2017-05-01 ------------------------------------------------------------------------------- -- Description: 12B14B Decoder Module ------------------------------------------------------------------------------- @@ -67,7 +65,7 @@ architecture rtl of Decoder12b14b is begin - comb : process (dataIn, dispIn, r, rst) is + comb : process (dataIn, dispIn, r, rst, validIn) is variable v : RegType; variable dispInTmp : slv(1 downto 0); begin diff --git a/base/general/rtl/Decoder8b10b.vhd b/base/general/rtl/Decoder8b10b.vhd index 8e04e66775..4368b25034 100644 --- a/base/general/rtl/Decoder8b10b.vhd +++ b/base/general/rtl/Decoder8b10b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Decoder8b10b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-11-15 --- Last update: 2017-05-01 ------------------------------------------------------------------------------- -- Description: 8B10B Decoder Module ------------------------------------------------------------------------------- diff --git a/base/general/rtl/Encoder10b12b.vhd b/base/general/rtl/Encoder10b12b.vhd index a6f9e50030..dba553b1fd 100644 --- a/base/general/rtl/Encoder10b12b.vhd +++ b/base/general/rtl/Encoder10b12b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Encode12b14b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-07 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: 10B12B Encoder Module ------------------------------------------------------------------------------- diff --git a/base/general/rtl/Encoder12b14b.vhd b/base/general/rtl/Encoder12b14b.vhd index 167e07f277..b7c407f6ea 100644 --- a/base/general/rtl/Encoder12b14b.vhd +++ b/base/general/rtl/Encoder12b14b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Encode12b14b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-07 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: 12B14B Encoder Module ------------------------------------------------------------------------------- diff --git a/base/general/rtl/Encoder8b10b.vhd b/base/general/rtl/Encoder8b10b.vhd index 09054014cb..1c4b959fc2 100644 --- a/base/general/rtl/Encoder8b10b.vhd +++ b/base/general/rtl/Encoder8b10b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Encoder8b10b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-12 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: 8B10B Encoder Module ------------------------------------------------------------------------------- diff --git a/base/general/rtl/Gearbox.vhd b/base/general/rtl/Gearbox.vhd new file mode 100644 index 0000000000..a65cac8efb --- /dev/null +++ b/base/general/rtl/Gearbox.vhd @@ -0,0 +1,162 @@ +------------------------------------------------------------------------------- +-- Title : Gearbox +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: A generic gearbox +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.StdRtlPkg.all; + +entity Gearbox is + + generic ( + TPD_G : time := 1 ns; + SLAVE_WIDTH_G : positive; + MASTER_WIDTH_G : positive); + + port ( + clk : in sl; + rst : in sl; + + -- input side data and flow control + slaveData : in slv(SLAVE_WIDTH_G-1 downto 0); + slaveValid : in sl := '1'; + slaveReady : out sl; + + -- sequencing and slip + startOfSeq : in sl := '0'; + slip : in sl := '0'; + + -- output side data and flow control + masterData : out slv(MASTER_WIDTH_G-1 downto 0); + masterValid : out sl; + masterReady : in sl := '1'); + +end entity Gearbox; + +architecture rtl of Gearbox is + + constant MAX_C : integer := maximum(MASTER_WIDTH_G, SLAVE_WIDTH_G); + constant MIN_C : integer := minimum(MASTER_WIDTH_G, SLAVE_WIDTH_G); + + -- Don't need the +1 if slip is not used. + constant SHIFT_WIDTH_C : integer := wordCount(MAX_C, MIN_C) * MIN_C + 1; + + type RegType is record + masterValid : sl; + shiftReg : slv(SHIFT_WIDTH_C-1 downto 0); + writeIndex : integer range 0 to SHIFT_WIDTH_C-1; + slaveReady : sl; + slip : sl; + end record; + + constant REG_INIT_C : RegType := ( + masterValid => '0', + shiftReg => (others => '0'), + writeIndex => 0, + slaveReady => '0', + slip => '0'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + +begin + + comb : process (slaveData, r, masterReady, rst, slip, startOfSeq, slaveValid) is + variable v : RegType; + begin + v := r; + + -- Flow control defaults + v.slaveReady := '0'; + + if (masterReady = '1') then + v.masterValid := '0'; + end if; + + -- Slip input by incrementing the writeIndex + v.slip := slip; + if (slip = '1' and r.slip = '0') then + v.writeIndex := r.writeIndex - 1; + end if; + + + -- Only do anything if ready for data output + if (v.masterValid = '0') then + + -- If current write index (assigned last cycle) is greater than output width, + -- then we have to shift down before assinging an new input + if (v.writeIndex >= MASTER_WIDTH_G) then + v.shiftReg := slvZero(MASTER_WIDTH_G) & r.shiftReg(SHIFT_WIDTH_C-1 downto MASTER_WIDTH_G); + v.writeIndex := v.writeIndex - MASTER_WIDTH_G; + + -- If write index still greater than output width after shift, + -- then we have a valid word to output + if (v.writeIndex >= MASTER_WIDTH_G) then + v.masterValid := '1'; + end if; + end if; + end if; + + -- Accept new data if ready to output and shift above did not create an output valid + if (slaveValid = '1' and v.masterValid = '0') then + + -- Reset the sequence if requested + if (startOfSeq = '1') then + v.writeIndex := 0; + v.masterValid := '0'; + end if; + + -- Accept the input word + v.slaveReady := '1'; + + -- Assign incomming data at proper location in shift reg + v.shiftReg(v.writeIndex+SLAVE_WIDTH_G-1 downto v.writeIndex) := slaveData; + + -- Increment writeIndex + v.writeIndex := v.writeIndex + SLAVE_WIDTH_G; + + -- Assert masterValid + if (v.writeIndex >= MASTER_WIDTH_G) then + v.masterValid := '1'; + end if; + + end if; + + slaveReady <= v.slaveReady; + + if (rst = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + + masterValid <= r.masterValid; + masterData <= r.shiftReg(MASTER_WIDTH_G-1 downto 0); + + + end process comb; + + sync : process (clk) is + begin + if (rising_edge(clk)) then + r <= rin after TPD_G; + end if; + end process sync; + + +end architecture rtl; diff --git a/base/general/rtl/Heartbeat.vhd b/base/general/rtl/Heartbeat.vhd index 07ad91df79..ff4330c46c 100644 --- a/base/general/rtl/Heartbeat.vhd +++ b/base/general/rtl/Heartbeat.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Heartbeat.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-04-30 --- Last update: 2014-10-28 ------------------------------------------------------------------------------- -- Description: Heartbeat LED output ------------------------------------------------------------------------------- diff --git a/base/general/rtl/PrbsPkg.vhd b/base/general/rtl/PrbsPkg.vhd index de8fe323b1..b92892256f 100644 --- a/base/general/rtl/PrbsPkg.vhd +++ b/base/general/rtl/PrbsPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : PrbsPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-12-10 --- Last update: 2014-01-22 ------------------------------------------------------------------------------- -- Description: PseudoRandom Binary Sequence (PRBS) Package ------------------------------------------------------------------------------- diff --git a/base/general/rtl/PwrUpRst.vhd b/base/general/rtl/PwrUpRst.vhd index d08d40ce66..0fd36ec2e0 100644 --- a/base/general/rtl/PwrUpRst.vhd +++ b/base/general/rtl/PwrUpRst.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : PwrUpRst.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-07-30 --- Last update: 2013-12-05 ------------------------------------------------------------------------------- -- Description: Synchronizes a reset signal and holds it for a parametrized -- number of cycles. diff --git a/base/general/rtl/RegisterVector.vhd b/base/general/rtl/RegisterVector.vhd index 7c24776830..ebeb0a2f1a 100644 --- a/base/general/rtl/RegisterVector.vhd +++ b/base/general/rtl/RegisterVector.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RegisterVector.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-04-15 --- Last update: 2017-06-05 ------------------------------------------------------------------------------- -- Description: 1 c-c register delay ------------------------------------------------------------------------------- diff --git a/base/general/rtl/RstPipeline.vhd b/base/general/rtl/RstPipeline.vhd index e6bb4e1b63..d73721aa5e 100644 --- a/base/general/rtl/RstPipeline.vhd +++ b/base/general/rtl/RstPipeline.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RstPipeline.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-08-03 --- Last update: 2017-08-12 ------------------------------------------------------------------------------- -- Description: Reset pipeline register stages ------------------------------------------------------------------------------- diff --git a/base/general/rtl/RstPipelineVector.vhd b/base/general/rtl/RstPipelineVector.vhd index c68c4a334d..8d286b7d26 100644 --- a/base/general/rtl/RstPipelineVector.vhd +++ b/base/general/rtl/RstPipelineVector.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RstPipelineVector.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2018-05-03 --- Last update: 2018-05-03 ------------------------------------------------------------------------------- -- Description: Wrapper for multiple RstPipeline modules ------------------------------------------------------------------------------- diff --git a/base/general/rtl/SlvDelay.vhd b/base/general/rtl/SlvDelay.vhd index c6c0f7658f..eeac0722b4 100644 --- a/base/general/rtl/SlvDelay.vhd +++ b/base/general/rtl/SlvDelay.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SlvDelay.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-14 --- Last update: 2016-06-03 ------------------------------------------------------------------------------- -- Description: Shift Register Delay module for std_logic_vectors ------------------------------------------------------------------------------- diff --git a/base/general/rtl/StdRtlPkg.vhd b/base/general/rtl/StdRtlPkg.vhd index 67e253558f..897b58642c 100644 --- a/base/general/rtl/StdRtlPkg.vhd +++ b/base/general/rtl/StdRtlPkg.vhd @@ -1,7 +1,6 @@ ------------------------------------------------------------------------------- -- File : StdRtlPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-05-01 ------------------------------------------------------------------------------- -- Description: Standard RTL Package File ------------------------------------------------------------------------------ @@ -790,7 +789,7 @@ package body StdRtlPkg is inp := resize(vector, BYTES_C*8); for i in BYTES_C-1 downto 0 loop - ret(7+(8*i) downto 8*i) := inp(7+(8*(7-i)) downto (8*(7-i))); + ret(7+(8*i) downto 8*i) := inp(7+(8*(BYTES_C-1-i)) downto (8*(BYTES_C-1-i))); end loop; return ret; end function; diff --git a/base/general/rtl/TextUtilPkg.vhd b/base/general/rtl/TextUtilPkg.vhd index 9f4307be50..acc303d0bb 100644 --- a/base/general/rtl/TextUtilPkg.vhd +++ b/base/general/rtl/TextUtilPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TextUtilPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-05-01 --- Last update: 2017-02-23 ------------------------------------------------------------------------------- -- Description: Provides functions for handling text. ------------------------------------------------------------------------------ diff --git a/base/general/rtl/WatchDogRst.vhd b/base/general/rtl/WatchDogRst.vhd index dac5a84cc7..82cc68f5af 100644 --- a/base/general/rtl/WatchDogRst.vhd +++ b/base/general/rtl/WatchDogRst.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : WatchDogRst.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-06-17 --- Last update: 2018-05-21 ------------------------------------------------------------------------------- -- Description: Watch Dog Reset module ------------------------------------------------------------------------------- diff --git a/base/general/tb/ClkRst.vhd b/base/general/tb/ClkRst.vhd index 2c2eb7787b..5cc5b525fd 100644 --- a/base/general/tb/ClkRst.vhd +++ b/base/general/tb/ClkRst.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : ClkRst.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-09-18 --- Last update: 2013-03-27 ------------------------------------------------------------------------------- -- Description: Provides a clocks and reset signal to UUT in simulation. -- Assumes active high reset. diff --git a/base/general/tb/Code10b12bTb.vhd b/base/general/tb/Code10b12bTb.vhd index 07da9b4b48..c651ebafbf 100644 --- a/base/general/tb/Code10b12bTb.vhd +++ b/base/general/tb/Code10b12bTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Encoder10b12bTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-11 --- Last update: 2016-10-26 ------------------------------------------------------------------------------- -- Description: Testbench for design "Encoder10b12b" ------------------------------------------------------------------------------- diff --git a/base/general/tb/Code12b14bTb.vhd b/base/general/tb/Code12b14bTb.vhd index de3def47c7..c19a785b0e 100644 --- a/base/general/tb/Code12b14bTb.vhd +++ b/base/general/tb/Code12b14bTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Encoder12b14bTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-11 --- Last update: 2017-04-25 ------------------------------------------------------------------------------- -- Description: Testbench for design "Encoder12b14b" ------------------------------------------------------------------------------- diff --git a/base/general/tb/Encoder12b14bTb.vhd b/base/general/tb/Encoder12b14bTb.vhd index fe95fab8e1..2f89f498ae 100644 --- a/base/general/tb/Encoder12b14bTb.vhd +++ b/base/general/tb/Encoder12b14bTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Encoder12b14bTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-11 --- Last update: 2016-10-11 ------------------------------------------------------------------------------- -- Description: Testbench for design "Encoder12b14b" ------------------------------------------------------------------------------- diff --git a/base/general/tb/GearboxTb.vhd b/base/general/tb/GearboxTb.vhd new file mode 100644 index 0000000000..aa50a020b3 --- /dev/null +++ b/base/general/tb/GearboxTb.vhd @@ -0,0 +1,194 @@ +------------------------------------------------------------------------------- +-- Title : Testbench for design "Gearbox" +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +-- Platform : +-- Standard : VHDL'93/02 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- This file is part of SURF. It is subject to +-- the license terms in the LICENSE.txt file found in the top-level directory +-- of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of SURF, including this file, may be +-- copied, modified, propagated, or distributed except according to the terms +-- contained in the LICENSE.txt file. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +use work.StdRtlPkg.all; +---------------------------------------------------------------------------------------------------- + +entity GearboxTb is + +end entity GearboxTb; + +---------------------------------------------------------------------------------------------------- + +architecture sim of GearboxTb is + + -- component generics + constant TPD_G : time := 1 ns; + constant INPUT_WIDTH_G : natural := 10; + constant OUTPUT_WIDTH_G : natural := 8; + + -- component ports + signal clk32 : sl := '0'; -- [in] + signal rst32 : sl := '0'; -- [in] + + signal clk66 : sl := '0'; + signal rst66 : sl := '0'; + + signal input : slv(INPUT_WIDTH_G-1 downto 0) := (others => '0'); + + + signal slaveData_0 : slv(INPUT_WIDTH_G-1 downto 0) := (others => '0'); -- [in] + signal slaveValid_0 : sl := '0'; -- [in] + signal slaveReady_0 : sl := '0'; -- [out] + signal masterData_0 : slv(OUTPUT_WIDTH_G-1 downto 0) := (others => '0'); -- [out] + signal masterValid_0 : sl := '0'; -- [out] + signal masterReady_0 : sl := '0'; -- [in] + signal slip_0 : sl := '0'; + signal startOfSeq_0 : sl := '0'; + +-- signal slaveData_1 : slv(OUTPUT_WIDTH_G-1 downto 0) := X"A5"; -- [in] +-- signal slaveValid_1 : sl := '0'; -- [in] +-- signal slaveReady_1 : sl; -- [out] + signal masterData_1 : slv(INPUT_WIDTH_G-1 downto 0) := (others => '0'); -- [out] + signal masterValid_1 : sl := '0'; -- [out] + signal masterReady_1 : sl := '1'; -- [in] + signal slip_1 : sl := '0'; + signal startOfSeq_1 : sl := '0'; + -- + +begin + + U_FifoAsync_1 : entity work.FifoAsync + generic map ( + TPD_G => TPD_G, + FWFT_EN_G => true, + BRAM_EN_G => true, + DATA_WIDTH_G => INPUT_WIDTH_G, + PIPE_STAGES_G => 0) + port map ( + rst => rst66, -- [in] + wr_clk => clk66, -- [in] + wr_en => '1', -- [in] + din => input, + rd_clk => clk32, -- [in] + rd_en => slaveReady_0, -- [in] + dout => slaveData_0, -- [out] + valid => slaveValid_0); -- [out] + + + U_Gearbox_0 : entity work.Gearbox + generic map ( + TPD_G => TPD_G, + INPUT_WIDTH_G => INPUT_WIDTH_G, + OUTPUT_WIDTH_G => OUTPUT_WIDTH_G) + port map ( + clk => clk32, -- [in] + rst => rst32, -- [in] + slaveData => slaveData_0, -- [in] + slaveValid => slaveValid_0, -- [in] + slaveReady => slaveReady_0, -- [out] + masterData => masterData_0, -- [out] + masterValid => masterValid_0, -- [out] + masterReady => masterReady_0); -- [in] + + -- component instantiation + U_Gearbox_1 : entity work.Gearbox + generic map ( + TPD_G => TPD_G, + INPUT_WIDTH_G => OUTPUT_WIDTH_G, + OUTPUT_WIDTH_G => INPUT_WIDTH_G) + port map ( + clk => clk32, -- [in] + rst => rst32, -- [in] + slaveData => masterData_0, -- [in] + slaveValid => masterValid_0, -- [in] + slaveReady => masterReady_0, -- [out] + masterData => masterData_1, -- [out] + masterValid => masterValid_1, -- [out] + masterReady => masterReady_1, -- [in] + slip => slip_1, + startOfSeq => startOfSeq_1); + + + + U_ClkRst_1 : entity work.ClkRst + generic map ( + CLK_PERIOD_G => 30 ns, + CLK_DELAY_G => 1 ns, + RST_START_DELAY_G => 0 ns, + RST_HOLD_TIME_G => 5 us, + SYNC_RESET_G => true) + port map ( + clkP => clk32, + rst => rst32); + + U_ClkRst_2 : entity work.ClkRst + generic map ( + CLK_PERIOD_G => 80 ns, + CLK_DELAY_G => 1 ns, + RST_START_DELAY_G => 0 ns, + RST_HOLD_TIME_G => 5 us, + SYNC_RESET_G => true) + port map ( + clkP => clk66, + rst => rst66); + + tb : process is + variable count : integer := 0; + begin + wait until rst66 = '1'; + wait until rst66 = '0'; + wait for 1 us; + wait until clk66 = '1'; + wait until clk66 = '1'; +-- slaveValid_0 <= '1' after TPD_G; + +-- while (count < 498) loop +-- wait until clk = '1'; +-- count := count + 1; +-- end loop; +-- count := 0; + +-- wait until clk = '1'; +-- startOfSeq <= '1'; + +-- wait until clk = '1'; +-- startOfSeq <= '0'; +-- for i in 0 to 10 loop +-- while (count < 100) loop +-- wait until clk = '1'; +-- count := count + 1; +-- end loop; +-- count := 0; + +-- wait until clk = '1'; +-- slip_1 <= '1'; + +-- wait until clk = '1'; +-- slip_1 <= '0'; +-- end loop; + + + while (count < 10000) loop + wait until clk66 = '1'; + count := count + 1; + end loop; + count := 0; + + + + end process; + + +end architecture sim; + +---------------------------------------------------------------------------------------------------- diff --git a/base/general/tb/HeartbeatTb.vhd b/base/general/tb/HeartbeatTb.vhd index 0ff9f31f21..a0201d0c6f 100644 --- a/base/general/tb/HeartbeatTb.vhd +++ b/base/general/tb/HeartbeatTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : HeartbeatTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-09-26 --- Last update: 2013-10-02 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for the Heartbeat module ------------------------------------------------------------------------------- diff --git a/base/general/tb/glbl.vhd b/base/general/tb/glbl.vhd index c6df396d0d..a87744fba6 100644 --- a/base/general/tb/glbl.vhd +++ b/base/general/tb/glbl.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : glbl.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-11 --- Last update: 2016-10-11 ------------------------------------------------------------------------------- -- Description: GLBL module for mixed Verilog/VHDL simulation support ------------------------------------------------------------------------------ diff --git a/base/ram/rtl/DualPortRam.vhd b/base/ram/inferred/DualPortRam.vhd similarity index 99% rename from base/ram/rtl/DualPortRam.vhd rename to base/ram/inferred/DualPortRam.vhd index 11fffca86b..be0860fbbb 100644 --- a/base/ram/rtl/DualPortRam.vhd +++ b/base/ram/inferred/DualPortRam.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DualPortRam.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-12-18 --- Last update: 2016-05-09 ------------------------------------------------------------------------------- -- Description: This module infers either Block RAM or distributed RAM ------------------------------------------------------------------------------- diff --git a/base/ram/rtl/OctalPortRam.vhd b/base/ram/inferred/OctalPortRam.vhd similarity index 99% rename from base/ram/rtl/OctalPortRam.vhd rename to base/ram/inferred/OctalPortRam.vhd index 60f1f5ba60..4babad2238 100644 --- a/base/ram/rtl/OctalPortRam.vhd +++ b/base/ram/inferred/OctalPortRam.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : OctalPortRam.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-04-12 --- Last update: 2016-04-19 ------------------------------------------------------------------------------- -- Description: This module infers a Quad Port RAM as distributed RAM ------------------------------------------------------------------------------- diff --git a/base/ram/rtl/QuadPortRam.vhd b/base/ram/inferred/QuadPortRam.vhd similarity index 99% rename from base/ram/rtl/QuadPortRam.vhd rename to base/ram/inferred/QuadPortRam.vhd index 369e6cc4cc..460827f190 100644 --- a/base/ram/rtl/QuadPortRam.vhd +++ b/base/ram/inferred/QuadPortRam.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : QuadPortRam.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-12-18 --- Last update: 2016-04-19 ------------------------------------------------------------------------------- -- Description: This module infers a Quad Port RAM as distributed RAM ------------------------------------------------------------------------------- diff --git a/base/ram/rtl/SimpleDualPortRam.vhd b/base/ram/inferred/SimpleDualPortRam.vhd similarity index 94% rename from base/ram/rtl/SimpleDualPortRam.vhd rename to base/ram/inferred/SimpleDualPortRam.vhd index 277c267295..39fdfb0880 100644 --- a/base/ram/rtl/SimpleDualPortRam.vhd +++ b/base/ram/inferred/SimpleDualPortRam.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SimpleDualPortRam.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-07-11 --- Last update: 2016-05-09 ------------------------------------------------------------------------------- -- Description: This will infer this module as either Block RAM or distributed RAM ------------------------------------------------------------------------------- @@ -32,7 +30,7 @@ entity SimpleDualPortRam is ALTERA_RAM_G : string := "M9K"; BYTE_WR_EN_G : boolean := false; DATA_WIDTH_G : integer range 1 to (2**24) := 16; - BYTE_WIDTH_G : integer := 8; -- If BRAM, should be multiple or 8 or 9 + BYTE_WIDTH_G : integer := 8; -- If BRAM, should be multiple or 8 or 9 ADDR_WIDTH_G : integer range 1 to (2**24) := 4; INIT_G : slv := "0"); port ( @@ -46,16 +44,17 @@ entity SimpleDualPortRam is -- Port B clkb : in sl := '0'; enb : in sl := '1'; + regceb : in sl := '1'; rstb : in sl := not(RST_POLARITY_G); addrb : in slv(ADDR_WIDTH_G-1 downto 0) := (others => '0'); doutb : out slv(DATA_WIDTH_G-1 downto 0)); end SimpleDualPortRam; architecture rtl of SimpleDualPortRam is - + -- Set byte width to word width if byte writes not enabled -- Otherwise block ram parity bits wont be utilized - constant BYTE_WIDTH_C : natural := ite(BYTE_WR_EN_G, BYTE_WIDTH_G, DATA_WIDTH_G); + constant BYTE_WIDTH_C : natural := ite(BYTE_WR_EN_G, BYTE_WIDTH_G, DATA_WIDTH_G); constant NUM_BYTES_C : natural := wordCount(DATA_WIDTH_G, BYTE_WIDTH_C); constant FULL_DATA_WIDTH_C : natural := NUM_BYTES_C*BYTE_WIDTH_C; @@ -142,7 +141,9 @@ begin process (clkb) begin if (rising_edge(clkb)) then - doutb <= doutBInt(DATA_WIDTH_G-1 downto 0) after TPD_G; + if regceb = '1' then + doutb <= doutBInt(DATA_WIDTH_G-1 downto 0) after TPD_G; + end if; end if; end process; end generate REG; diff --git a/base/ram/rtl/TrueDualPortRam.vhd b/base/ram/inferred/TrueDualPortRam.vhd similarity index 99% rename from base/ram/rtl/TrueDualPortRam.vhd rename to base/ram/inferred/TrueDualPortRam.vhd index 1eb18dfc89..c8d16524ff 100644 --- a/base/ram/rtl/TrueDualPortRam.vhd +++ b/base/ram/inferred/TrueDualPortRam.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TrueDualPortRam.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-07-11 --- Last update: 2016-05-09 ------------------------------------------------------------------------------- -- Description: This will infer this module as Block RAM only -- diff --git a/base/ram/ruckus.tcl b/base/ram/ruckus.tcl index 6fa215e9f8..4f5234a371 100644 --- a/base/ram/ruckus.tcl +++ b/base/ram/ruckus.tcl @@ -2,4 +2,5 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Load Source Code -loadSource -dir "$::DIR_PATH/rtl/" +loadSource -dir "$::DIR_PATH/inferred" +loadSource -dir "$::DIR_PATH/xilinx" diff --git a/base/ram/xilinx/SimpleDualPortRamAlteraMfDummy.vhd b/base/ram/xilinx/SimpleDualPortRamAlteraMfDummy.vhd new file mode 100644 index 0000000000..0375fd9b9b --- /dev/null +++ b/base/ram/xilinx/SimpleDualPortRamAlteraMfDummy.vhd @@ -0,0 +1,54 @@ +------------------------------------------------------------------------------- +-- File : SimpleDualPortRamXpm.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Wrapper for XPM Simple Dual Port RAM +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.StdRtlPkg.all; + +entity SimpleDualPortRamAlteraMf is + generic ( + TPD_G : time := 1 ns; + COMMON_CLK_G : boolean := false; + RST_POLARITY_G : sl := '1'; -- '1' for active high rst, '0' for active low + MEMORY_TYPE_G : string := "block"; + READ_LATENCY_G : natural range 0 to 2 := 1; + DATA_WIDTH_G : integer range 1 to (2**24) := 16; + BYTE_WR_EN_G : boolean := false; + BYTE_WIDTH_G : integer range 8 to 9 := 8; -- If BRAM, should be multiple or 8 or 9 + ADDR_WIDTH_G : integer range 1 to (2**24) := 4); + port ( + -- Port A + clka : in sl := '0'; + ena : in sl := '1'; + wea : in slv(ite(BYTE_WR_EN_G, wordCount(DATA_WIDTH_G, BYTE_WIDTH_G), 1)-1 downto 0) := (others => '0'); + addra : in slv(ADDR_WIDTH_G-1 downto 0) := (others => '0'); + dina : in slv(DATA_WIDTH_G-1 downto 0) := (others => '0'); + -- Port B + clkb : in sl := '0'; + enb : in sl := '1'; + regceb : in sl := '1'; + rstb : in sl := not(RST_POLARITY_G); + addrb : in slv(ADDR_WIDTH_G-1 downto 0) := (others => '0'); + doutb : out slv(DATA_WIDTH_G-1 downto 0) := (others => '0')); +end SimpleDualPortRamAlteraMf; + +architecture rtl of SimpleDualPortRamAlteraMf is + +begin + +end rtl; diff --git a/base/ram/xilinx/SimpleDualPortRamXpm.vhd b/base/ram/xilinx/SimpleDualPortRamXpm.vhd new file mode 100644 index 0000000000..92d89423be --- /dev/null +++ b/base/ram/xilinx/SimpleDualPortRamXpm.vhd @@ -0,0 +1,101 @@ +------------------------------------------------------------------------------- +-- File : SimpleDualPortRamXpm.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Wrapper for XPM Simple Dual Port RAM +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.StdRtlPkg.all; + +library xpm; +use xpm.vcomponents.all; + +entity SimpleDualPortRamXpm is + generic ( + TPD_G : time := 1 ns; + COMMON_CLK_G : boolean := false; + RST_POLARITY_G : sl := '1'; -- '1' for active high rst, '0' for active low + MEMORY_TYPE_G : string := "block"; + READ_LATENCY_G : natural range 0 to 2 := 1; + DATA_WIDTH_G : integer range 1 to (2**24) := 16; + BYTE_WR_EN_G : boolean := false; + BYTE_WIDTH_G : integer range 8 to 9 := 8; -- If BRAM, should be multiple or 8 or 9 + ADDR_WIDTH_G : integer range 1 to (2**24) := 4); + port ( + -- Port A + clka : in sl := '0'; + ena : in sl := '1'; + wea : in slv(ite(BYTE_WR_EN_G, wordCount(DATA_WIDTH_G, BYTE_WIDTH_G), 1)-1 downto 0) := (others => '0'); + addra : in slv(ADDR_WIDTH_G-1 downto 0) := (others => '0'); + dina : in slv(DATA_WIDTH_G-1 downto 0) := (others => '0'); + -- Port B + clkb : in sl := '0'; + enb : in sl := '1'; + regceb : in sl := '1'; + rstb : in sl := not(RST_POLARITY_G); + addrb : in slv(ADDR_WIDTH_G-1 downto 0) := (others => '0'); + doutb : out slv(DATA_WIDTH_G-1 downto 0)); +end SimpleDualPortRamXpm; + +architecture rtl of SimpleDualPortRamXpm is + + signal resetB : sl; + +begin + + U_RAM : xpm_memory_sdpram + generic map ( + ADDR_WIDTH_A => ADDR_WIDTH_G, + ADDR_WIDTH_B => ADDR_WIDTH_G, + AUTO_SLEEP_TIME => 0, -- 0 - Disable auto-sleep feature + BYTE_WRITE_WIDTH_A => ite(BYTE_WR_EN_G, BYTE_WIDTH_G, DATA_WIDTH_G), + CLOCKING_MODE => ite(COMMON_CLK_G, "common_clock", "independent_clock"), + ECC_MODE => "no_ecc", -- Default value = no_ecc + MEMORY_OPTIMIZATION => "true", -- Default value = true + MEMORY_PRIMITIVE => MEMORY_TYPE_G, + MEMORY_SIZE => (DATA_WIDTH_G*(2**ADDR_WIDTH_G)), + MESSAGE_CONTROL => 0, -- Default value = 0 + READ_DATA_WIDTH_B => DATA_WIDTH_G, + READ_LATENCY_B => READ_LATENCY_G, + USE_EMBEDDED_CONSTRAINT => 0, -- Default value = 0 + USE_MEM_INIT => 1, -- Default value = 1 + WAKEUP_TIME => "disable_sleep", -- "disable_sleep" to disable dynamic power saving option + WRITE_DATA_WIDTH_A => DATA_WIDTH_G, + WRITE_MODE_B => ite(READ_LATENCY_G = 0, "read_first", "no_change")) -- Default value = no_change + port map ( + -- Write Interface + ena => ena, + clka => clka, + addra => addra, + dina => dina, + wea => wea, + -- Read Interface + enb => enb, + clkb => clkb, + addrb => addrb, + doutb => doutb, + regceb => regceb, + -- Misc.Interface + rstb => resetB, + dbiterrb => open, + sbiterrb => open, + injectdbiterra => '0', + injectsbiterra => '0', + sleep => '0'); + + resetB <= rstb when(RST_POLARITY_G = '1') else not(rstb); + +end rtl; diff --git a/base/sync/rtl/RstSync.vhd b/base/sync/rtl/RstSync.vhd index f97171e4c8..58cc1ae133 100644 --- a/base/sync/rtl/RstSync.vhd +++ b/base/sync/rtl/RstSync.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RstSync.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-05-01 --- Last update: 2017-02-23 ------------------------------------------------------------------------------- -- Description: Synchronizes the trailing edge of an asynchronous reset to a -- given clock. diff --git a/base/sync/rtl/SyncClockFreq.vhd b/base/sync/rtl/SyncClockFreq.vhd index 2705c6ea7b..a249961314 100644 --- a/base/sync/rtl/SyncClockFreq.vhd +++ b/base/sync/rtl/SyncClockFreq.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SyncClockFreq.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-17 --- Last update: 2017-11-08 ------------------------------------------------------------------------------- -- Description: This module measures the frequency of an input clock -- with respect to a stable reference clock. diff --git a/base/sync/rtl/SyncStatusVector.vhd b/base/sync/rtl/SyncStatusVector.vhd index dab6852222..655ef7946c 100644 --- a/base/sync/rtl/SyncStatusVector.vhd +++ b/base/sync/rtl/SyncStatusVector.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SyncStatusVector.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-11 --- Last update: 2014-06-02 ------------------------------------------------------------------------------- -- Description: General Purpose Status Vector and Status Counter module ------------------------------------------------------------------------------- diff --git a/base/sync/rtl/SyncTrigPeriod.vhd b/base/sync/rtl/SyncTrigPeriod.vhd new file mode 100644 index 0000000000..c178919d59 --- /dev/null +++ b/base/sync/rtl/SyncTrigPeriod.vhd @@ -0,0 +1,145 @@ +------------------------------------------------------------------------------- +-- File : SyncTrigPeriod.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: This module measures the trigger period between triggers +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +use work.StdRtlPkg.all; + +entity SyncTrigPeriod is + generic ( + TPD_G : time := 1 ns; -- Simulation FF output delay + COMMON_CLK_G : boolean := false; -- true if trigClk & locClk are the same clock + IN_POLARITY_G : sl := '1'; -- 0 for active LOW, 1 for active HIGH + CNT_WIDTH_G : positive := 32); -- Counters' width + port ( + -- Trigger Input (trigClk domain) + trigClk : in sl; + trigRst : in sl; + trigIn : in sl; + -- Trigger Period Output (locClk domain) + locClk : in sl; + locRst : in sl; + resetStat : in sl; + period : out slv(CNT_WIDTH_G-1 downto 0); -- units of clock cycles + periodMax : out slv(CNT_WIDTH_G-1 downto 0); -- units of clock cycles + periodMin : out slv(CNT_WIDTH_G-1 downto 0)); -- units of clock cycles +end SyncTrigPeriod; + +architecture rtl of SyncTrigPeriod is + + constant MAX_CNT_C : slv(CNT_WIDTH_G-1 downto 0) := (others => '1'); + + type RegType is record + armed : sl; + cnt : slv(CNT_WIDTH_G-1 downto 0); + period : slv(CNT_WIDTH_G-1 downto 0); + periodMax : slv(CNT_WIDTH_G-1 downto 0); + periodMin : slv(CNT_WIDTH_G-1 downto 0); + end record; + + constant REG_INIT_C : RegType := ( + armed => '0', + cnt => (others => '0'), + period => (others => '0'), + periodMax => (others => '0'), + periodMin => (others => '1')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal trig : sl := '0'; + +begin + + U_OneShot : entity work.SynchronizerOneShot + generic map ( + TPD_G => TPD_G, + BYPASS_SYNC_G => COMMON_CLK_G, + IN_POLARITY_G => IN_POLARITY_G, + OUT_POLARITY_G => '1') + port map ( + clk => locClk, + dataIn => trigIn, + dataOut => trig); + + + comb : process (locRst, r, resetStat, trig) is + variable v : RegType; + begin + -- Latch the current value + v := r; + + -- Increment the counter + if (r.cnt /= MAX_CNT_C) then + v.cnt := r.cnt + 1; + end if; + + -- Check for a trigger + if (trig = '1') then + + -- Check for first trigger strobe after reset + if (r.armed = '0') then + + -- Set the flag + v.armed := '1'; + + else + + -- Save the current period value + v.period := v.cnt; + + -- Check for max value + if (v.cnt > r.periodMax) then + v.periodMax := v.cnt; + end if; + + -- Check for min value + if (v.cnt < r.periodMin) then + v.periodMin := v.cnt; + end if; + + -- Reset the counter + v.cnt := (others => '0'); + + end if; + + end if; + + -- Outputs + period <= r.period; + periodMax <= r.periodMax; + periodMin <= r.periodMin; + + -- Reset + if (locRst = '1') or (resetStat = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (locClk) is + begin + if rising_edge(locClk) then + r <= rin after TPD_G; + end if; + end process seq; + +end rtl; diff --git a/base/sync/rtl/SyncTrigRate.vhd b/base/sync/rtl/SyncTrigRate.vhd index 2a8961147b..92c7ba9bcb 100644 --- a/base/sync/rtl/SyncTrigRate.vhd +++ b/base/sync/rtl/SyncTrigRate.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SyncTrigRate.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-16 --- Last update: 2017-01-26 ------------------------------------------------------------------------------- -- Description: This module measures the trigger rate of a trigger ------------------------------------------------------------------------------- diff --git a/base/sync/rtl/SyncTrigRateVector.vhd b/base/sync/rtl/SyncTrigRateVector.vhd index ba020dcd2b..0b570a5f59 100644 --- a/base/sync/rtl/SyncTrigRateVector.vhd +++ b/base/sync/rtl/SyncTrigRateVector.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SyncTrigRateVector.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-16 --- Last update: 2016-05-20 ------------------------------------------------------------------------------- -- Description: Wrapper for multiple SyncTrigRate modules ------------------------------------------------------------------------------- diff --git a/base/sync/rtl/Synchronizer.vhd b/base/sync/rtl/Synchronizer.vhd index 24eaafbe43..349ab352a3 100644 --- a/base/sync/rtl/Synchronizer.vhd +++ b/base/sync/rtl/Synchronizer.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Synchronizer.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-05-13 --- Last update: 2016-09-13 ------------------------------------------------------------------------------- -- Description: A simple multi Flip FLop synchronization module. -- Sets attributes to keep synthesis for mucking with FF chain. diff --git a/base/sync/rtl/SynchronizerEdge.vhd b/base/sync/rtl/SynchronizerEdge.vhd index 5ac585ff72..92434d7420 100644 --- a/base/sync/rtl/SynchronizerEdge.vhd +++ b/base/sync/rtl/SynchronizerEdge.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SynchronizerEdge.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-05-13 --- Last update: 2016-09-22 ------------------------------------------------------------------------------- -- Description: A simple multi Flip FLop synchronization module. ------------------------------------------------------------------------------- diff --git a/base/sync/rtl/SynchronizerFifo.vhd b/base/sync/rtl/SynchronizerFifo.vhd index f6466f8040..2e07bf1ea8 100644 --- a/base/sync/rtl/SynchronizerFifo.vhd +++ b/base/sync/rtl/SynchronizerFifo.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SynchronizerFifo.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-07-10 --- Last update: 2016-03-09 ------------------------------------------------------------------------------- -- Description: Synchronizing FIFO wrapper ------------------------------------------------------------------------------- diff --git a/base/sync/rtl/SynchronizerOneShot.vhd b/base/sync/rtl/SynchronizerOneShot.vhd index 17a0c3b79a..0b6e194743 100644 --- a/base/sync/rtl/SynchronizerOneShot.vhd +++ b/base/sync/rtl/SynchronizerOneShot.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SynchronizerOneShot.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-02-06 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: One-Shot Pulser that has to cross clock domains ------------------------------------------------------------------------------- diff --git a/base/sync/rtl/SynchronizerOneShotCnt.vhd b/base/sync/rtl/SynchronizerOneShotCnt.vhd index e51d4d540f..3b504ec90e 100644 --- a/base/sync/rtl/SynchronizerOneShotCnt.vhd +++ b/base/sync/rtl/SynchronizerOneShotCnt.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SynchronizerOneShotCnt.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-11 --- Last update: 2014-04-14 ------------------------------------------------------------------------------- -- Description: Wrapper for SynchronizerOneShot with counter output ------------------------------------------------------------------------------- diff --git a/base/sync/rtl/SynchronizerOneShotCntVector.vhd b/base/sync/rtl/SynchronizerOneShotCntVector.vhd index 313c587a65..b46537f0e1 100644 --- a/base/sync/rtl/SynchronizerOneShotCntVector.vhd +++ b/base/sync/rtl/SynchronizerOneShotCntVector.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SynchronizerOneShotCntVector.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-11 --- Last update: 2014-05-27 ------------------------------------------------------------------------------- -- Description: Wrapper for multiple SynchronizerOneShotCnt modules ------------------------------------------------------------------------------- diff --git a/base/sync/rtl/SynchronizerOneShotVector.vhd b/base/sync/rtl/SynchronizerOneShotVector.vhd index 24c66f4a28..43c6fd70e3 100644 --- a/base/sync/rtl/SynchronizerOneShotVector.vhd +++ b/base/sync/rtl/SynchronizerOneShotVector.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SynchronizerOneShotVector.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-11 --- Last update: 2016-11-04 ------------------------------------------------------------------------------- -- Description: Wrapper for multiple SynchronizerOneShot modules ------------------------------------------------------------------------------- diff --git a/base/sync/rtl/SynchronizerVector.vhd b/base/sync/rtl/SynchronizerVector.vhd index 5656bce40e..ae6c7c2a2e 100644 --- a/base/sync/rtl/SynchronizerVector.vhd +++ b/base/sync/rtl/SynchronizerVector.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SynchronizerVector.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-07-10 --- Last update: 2016-09-13 ------------------------------------------------------------------------------- -- Description: Wrapper for multiple SynchronizerVector modules ------------------------------------------------------------------------------- diff --git a/base/sync/tb/SynchronizerFifoTb.vhd b/base/sync/tb/SynchronizerFifoTb.vhd index 957cff48a8..c504cc824c 100644 --- a/base/sync/tb/SynchronizerFifoTb.vhd +++ b/base/sync/tb/SynchronizerFifoTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SynchronizerFifoTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-07-17 --- Last update: 2013-09-19 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for the SynchronizerFifo module ------------------------------------------------------------------------------- diff --git a/base/sync/tb/SynchronizerOneShotTb.vhd b/base/sync/tb/SynchronizerOneShotTb.vhd index a1839daca5..e2371bbb1a 100644 --- a/base/sync/tb/SynchronizerOneShotTb.vhd +++ b/base/sync/tb/SynchronizerOneShotTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SynchronizerOneShotTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-09-22 --- Last update: 2016-09-22 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for the SynchronizerOneShot module ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad5780/rtl/AxiAd5780Core.vhd b/devices/AnalogDevices/ad5780/rtl/AxiAd5780Core.vhd index 12925df063..a582932fc7 100644 --- a/devices/AnalogDevices/ad5780/rtl/AxiAd5780Core.vhd +++ b/devices/AnalogDevices/ad5780/rtl/AxiAd5780Core.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAd5780Core.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-18 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AXI-Lite interface to AD5780 DAC IC ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad5780/rtl/AxiAd5780Pkg.vhd b/devices/AnalogDevices/ad5780/rtl/AxiAd5780Pkg.vhd index 05e9eb053c..6086c46d7f 100644 --- a/devices/AnalogDevices/ad5780/rtl/AxiAd5780Pkg.vhd +++ b/devices/AnalogDevices/ad5780/rtl/AxiAd5780Pkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAd5780Pkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-18 --- Last update: 2017-05-02 ------------------------------------------------------------------------------- -- Description: AD5780 Package File ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad5780/rtl/AxiAd5780Reg.vhd b/devices/AnalogDevices/ad5780/rtl/AxiAd5780Reg.vhd index ea138fd356..76d556fda7 100644 --- a/devices/AnalogDevices/ad5780/rtl/AxiAd5780Reg.vhd +++ b/devices/AnalogDevices/ad5780/rtl/AxiAd5780Reg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAd5780Reg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-18 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AXI-Lite interface to AD5780 DAC IC ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad5780/rtl/AxiAd5780Ser.vhd b/devices/AnalogDevices/ad5780/rtl/AxiAd5780Ser.vhd index 40d55434ff..efdba27744 100644 --- a/devices/AnalogDevices/ad5780/rtl/AxiAd5780Ser.vhd +++ b/devices/AnalogDevices/ad5780/rtl/AxiAd5780Ser.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAd5780Ser.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-18 --- Last update: 2014-04-25 ------------------------------------------------------------------------------- -- Description: AD5780 DAC Module's serializer ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad9249/rtl/Ad9249ConfigNoPullup.vhd b/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ConfigNoPullup.vhd similarity index 88% rename from devices/AnalogDevices/ad9249/rtl/Ad9249ConfigNoPullup.vhd rename to devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ConfigNoPullup.vhd index d38e84fac6..6fad52f444 100644 --- a/devices/AnalogDevices/ad9249/rtl/Ad9249ConfigNoPullup.vhd +++ b/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ConfigNoPullup.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Ad9249ConfigNoPullup.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-09-23 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AD9249 Configuration/Status Module (no pullup version) ------------------------------------------------------------------------------- @@ -26,11 +24,11 @@ use work.AxiLitePkg.all; entity Ad9249ConfigNoPullup is generic ( - TPD_G : time := 1 ns; - DEN_POLARITY_G : sl := '1'; - CLK_PERIOD_G : real := 8.0e-9; - CLK_EN_PERIOD_G : real := 16.0e-9; - NUM_CHIPS_G : positive := 1); + TPD_G : time := 1 ns; + DEN_POLARITY_G : sl := '1'; + CLK_PERIOD_G : real := 8.0e-9; + CLK_EN_PERIOD_G : real := 16.0e-9; + NUM_CHIPS_G : positive := 1); port ( axilClk : in sl; @@ -252,16 +250,16 @@ begin begin if rising_edge(axilClk) then if axilRst = '1' then - adcAck <= '0' after TPD_G; - adcSDir <= '0' after TPD_G; - locSDout <= '0' after TPD_G; - adcSClk <= '0' after TPD_G; - adcCsb <= (others => '1') after TPD_G; - nextClk <= '1' after TPD_G; - shiftCnt <= (others => '0') after TPD_G; - shiftCntEn <= '0' after TPD_G; - intShift <= (others => '0') after TPD_G; - curState <= ST_IDLE after TPD_G; + adcAck <= '0' after TPD_G; + adcSDir <= '0' after TPD_G; + locSDout <= '0' after TPD_G; + adcSClk <= '0' after TPD_G; + adcCsb <= (others => '1') after TPD_G; + nextClk <= '1' after TPD_G; + shiftCnt <= (others => '0') after TPD_G; + shiftCntEn <= '0' after TPD_G; + intShift <= (others => '0') after TPD_G; + curState <= ST_IDLE after TPD_G; elsif axilClkEn = '1' then -- Next state @@ -270,23 +268,23 @@ begin -- Shift count is not enabled if shiftCntEn = '0' then - adcSClk <= '0' after TPD_G; - locSDout <= '0' after TPD_G; - adcSDir <= '0' after TPD_G; + adcSClk <= '0' after TPD_G; + locSDout <= '0' after TPD_G; + adcSDir <= '0' after TPD_G; adcCsb <= (others => '1') after TPD_G; - nextClk <= '1' after TPD_G; + nextClk <= '1' after TPD_G; -- Wait for shift request if shiftEn = '1' then - shiftCntEn <= '1' after TPD_G; + shiftCntEn <= '1' after TPD_G; shiftCnt <= (others => '0') after TPD_G; - intShift(23) <= adcRdReq after TPD_G; - intShift(22 downto 21) <= "00" after TPD_G; - intShift(20 downto 8) <= adcAddr after TPD_G; - intShift(7 downto 0) <= adcWrData after TPD_G; + intShift(23) <= adcRdReq after TPD_G; + intShift(22 downto 21) <= "00" after TPD_G; + intShift(20 downto 8) <= adcAddr after TPD_G; + intShift(7 downto 0) <= adcWrData after TPD_G; end if; else - shiftCnt <= shiftCnt + 1 after TPD_G; + shiftCnt <= shiftCnt + 1 after TPD_G; -- Clock 0, setup output if shiftCnt(7 downto 0) = 0 then @@ -305,8 +303,8 @@ begin else intShift <= intShift(22 downto 0) & adcSDin after TPD_G; locSDout <= '0' after TPD_G; - adcCsb <= (others => '1') after TPD_G; - nextClk <= '0' after TPD_G; + adcCsb <= (others => '1') after TPD_G; + nextClk <= '0' after TPD_G; end if; -- Clock 3, clock output diff --git a/devices/AnalogDevices/ad9249/rtl/Ad9249Deserializer.vhd b/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd similarity index 94% rename from devices/AnalogDevices/ad9249/rtl/Ad9249Deserializer.vhd rename to devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd index 4851d25f98..e75b10b3b9 100644 --- a/devices/AnalogDevices/ad9249/rtl/Ad9249Deserializer.vhd +++ b/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Ad9249Deserializer.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-02-22 --- Last update: 2016-06-10 ------------------------------------------------------------------------------- -- Description: 14 bit DDR deserializer using 7 series IDELAYE2 and ISERDESE2. ------------------------------------------------------------------------------- @@ -23,10 +21,10 @@ library UNISIM; use UNISIM.vcomponents.all; entity Ad9249Deserializer is - + generic ( - TPD_G : time := 1 ns; - IODELAY_GROUP_G : string; + TPD_G : time := 1 ns; + IODELAY_GROUP_G : string; IDELAYCTRL_FREQ_G : real := 200.0); port ( clkIo : in sl; @@ -35,10 +33,10 @@ entity Ad9249Deserializer is rst : in sl; slip : in sl; - sysClk : in sl; + sysClk : in sl; curDelay : out slv(4 downto 0); - setDelay : in slv(4 downto 0); - setValid : in sl; + setDelay : in slv(4 downto 0); + setValid : in sl; iData : in sl; oData : out slv(13 downto 0)); @@ -51,7 +49,7 @@ architecture rtl of Ad9249Deserializer is signal shift1 : sl; signal shift2 : sl; - attribute IODELAY_GROUP : string; + attribute IODELAY_GROUP : string; attribute IODELAY_GROUP of U_DELAY : label is IODELAY_GROUP_G; begin @@ -103,7 +101,7 @@ begin SHIFTOUT1 => shift1, -- Cascade connection to Slave ISERDES SHIFTOUT2 => shift2, -- Cascade connection to Slave ISERDES BITSLIP => slip, -- 1-bit Invoke Bitslip. This can be used with any - -- DATA_WIDTH, cascaded or not. + -- DATA_WIDTH, cascaded or not. CE1 => '1', -- 1-bit Clock enable input CE2 => '1', -- 1-bit Clock enable input CLK => clkIo, -- Fast Source Synchronous SERDES clock from BUFIO @@ -148,7 +146,7 @@ begin SHIFTIN1 => shift1, -- Cascade connections from Master ISERDES SHIFTIN2 => shift2, -- Cascade connections from Master ISERDES BITSLIP => slip, -- 1-bit Invoke Bitslip. This can be used with any - -- DATA_WIDTH, cascaded or not. + -- DATA_WIDTH, cascaded or not. CE1 => '1', -- 1-bit Clock enable input CE2 => '1', -- 1-bit Clock enable input CLK => clkIo, -- Fast source synchronous serdes clock diff --git a/devices/AnalogDevices/ad9249/rtl/Ad9249ReadoutGroup.vhd b/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Readout7S.vhd old mode 100755 new mode 100644 similarity index 99% rename from devices/AnalogDevices/ad9249/rtl/Ad9249ReadoutGroup.vhd rename to devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Readout7S.vhd index 2c524f9139..fe237471ba --- a/devices/AnalogDevices/ad9249/rtl/Ad9249ReadoutGroup.vhd +++ b/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Readout7S.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Ad9249ReadoutGroup.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-05-26 --- Last update: 2017-08-09 ------------------------------------------------------------------------------- -- Description: -- ADC Readout Controller @@ -31,7 +29,7 @@ use work.AxiLitePkg.all; use work.AxiStreamPkg.all; use work.Ad9249Pkg.all; -entity Ad9249ReadoutGroup is +entity Ad9249ReadoutGroup7S is generic ( TPD_G : time := 1 ns; NUM_CHANNELS_G : natural range 1 to 8 := 8; @@ -60,10 +58,10 @@ entity Ad9249ReadoutGroup is adcStreamClk : in sl; adcStreams : out AxiStreamMasterArray(NUM_CHANNELS_G-1 downto 0) := (others => axiStreamMasterInit((false, 2, 8, 0, TKEEP_NORMAL_C, 0, TUSER_NORMAL_C)))); -end Ad9249ReadoutGroup; +end Ad9249ReadoutGroup7S; -- Define architecture -architecture rtl of Ad9249ReadoutGroup is +architecture rtl of Ad9249ReadoutGroup7S is ------------------------------------------------------------------------------------------------- -- AXIL Registers diff --git a/xilinx/UltraScale+/general/ruckus.tcl b/devices/AnalogDevices/ad9249/7Series/ruckus.tcl similarity index 72% rename from xilinx/UltraScale+/general/ruckus.tcl rename to devices/AnalogDevices/ad9249/7Series/ruckus.tcl index 6fa215e9f8..f988a4f0c1 100644 --- a/xilinx/UltraScale+/general/ruckus.tcl +++ b/devices/AnalogDevices/ad9249/7Series/ruckus.tcl @@ -2,4 +2,4 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Load Source Code -loadSource -dir "$::DIR_PATH/rtl/" +loadSource -dir "$::DIR_PATH/rtl" diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd new file mode 100644 index 0000000000..c4fa2f2038 --- /dev/null +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd @@ -0,0 +1,441 @@ +------------------------------------------------------------------------------- +-- File : Ad9249ReadoutClk.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- ADC Readout Controller +-- Receives ADC Data from an AD9592 chip. +-- Designed specifically for Xilinx 7 series FPGAs +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +use work.StdRtlPkg.all; +use work.AxiLitePkg.all; +use work.AxiStreamPkg.all; +use work.Ad9249Pkg.all; + +entity Ad9249Deserializer is + generic ( + TPD_G : time := 1 ns; + IODELAY_GROUP_G : string := "DEFAULT_GROUP"; + IDELAY_CASCADE_G : boolean := false; + IDELAYCTRL_FREQ_G : real := 300.0; + DEFAULT_DELAY_G : slv(8 downto 0) := (others => '0'); + ADC_INVERT_CH_G : sl := '0'; + BIT_REV_G : sl := '0'); + port ( + -- Reset for adc deserializer + adcClkRst : in sl; + -- Serial Data from ADC + dClk : in sl; -- Data clock + dClkDiv4 : in sl; + dClkDiv7 : in sl; + sDataP : in sl; -- Frame clock + sDataN : in sl; + -- Signal to control data gearboxes + loadDelay : in sl; + delay : in slv(8 downto 0) := "000000000"; + delayValueOut : out slv(8 downto 0); + bitSlip : in slv(3 downto 0) := "0000"; + gearboxOffset : in slv(2 downto 0) := "000"; + adcData : out slv(13 downto 0) + ); +end Ad9249Deserializer; + +-- Define architecture +architecture rtl of Ad9249Deserializer is + + attribute keep : string; + ------------------------------------------------------------------------------------------------- + -- ADC Readout Clocked Registers + ------------------------------------------------------------------------------------------------- + + constant CASCADE_C : string := ite(IDELAY_CASCADE_G, "MASTER", "NONE"); + + type AdcClkDiv4RegType is record + masterData : slv(7 downto 0); + masterData_1 : slv(7 downto 0); + longDataCounter : slv(2 downto 0); + longData : slv(55 downto 0); + longData_1 : slv(55 downto 0); + DWByte : sl; + masterDataDW : slv(15 downto 0); + masterDataDW_1 : slv(15 downto 0); + bitSlip : slv(3 downto 0); + masterDataDWBS : slv(15 downto 0); + longDataStable : sl; + end record; + + constant ADC_CLK_DV4_REG_INIT_C : AdcClkDiv4RegType := ( + masterData => (others => '0'), + masterData_1 => (others => '0'), + longDataCounter => (others => '0'), + longData => (others => '0'), + longData_1 => (others => '0'), + DWByte => '0', + masterDataDW => (others => '0'), + masterDataDW_1 => (others => '0'), + bitSlip => (others => '0'), + masterDataDWBS => (others => '0'), + longDataStable => '0' + ); + + type AdcClkDiv7RegType is record + gearboxCounter : slv(2 downto 0); + gearboxSeq : slv(2 downto 0); + masterAdcData : slv(13 downto 0); + adcDataGearboxIn : slv(15 downto 0); + adcDataGearboxIn_1 : slv(15 downto 0); + end record; + + constant ADC_CLK_DV7_REG_INIT_C : AdcClkDiv7RegType := ( + gearboxCounter => (others => '0'), + gearboxSeq => (others => '0'), + masterAdcData => (others => '0'), + adcDataGearboxIn => (others => '0'), + adcDataGearboxIn_1 => (others => '0') + ); + + signal adcDV4R : AdcClkDiv4RegType := ADC_CLK_DV4_REG_INIT_C; + signal adcDv4Rin : AdcClkDiv4RegType; + + signal adcDV7R : AdcClkDiv7RegType := ADC_CLK_DV7_REG_INIT_C; + signal adcDv7Rin : AdcClkDiv7RegType; + + + -- Local signals + signal sDataPadP : sl; + signal sDataPadN : sl; + signal sData_i : sl; + signal sData_d : sl; + + -- idelay signals + signal masterCntValue1 : slv(8 downto 0); + signal masterCntValue2 : slv(8 downto 0); + signal cascOut : sl; + signal cascRet : sl; + -- iserdes signal + signal masterData : slv(7 downto 0); + + attribute keep of adcDV4R : signal is "true"; + attribute keep of adcDV7R : signal is "true"; + attribute keep of sData_i : signal is "true"; + +begin + + adcData <= bitReverse(adcDv7R.masterAdcData(13 downto 7)) & bitReverse(adcDv7R.masterAdcData(6 downto 0)) when BIT_REV_G = '1' + else adcDv7R.masterAdcData; + + + ------------------------------------------------------------------------------------------------- + -- Create Clocks + ------------------------------------------------------------------------------------------------- + + -- input sData buffer + -- + U_IBUFDS_sData : IBUFDS_DIFF_OUT + generic map ( + DQS_BIAS => "FALSE" -- (FALSE, TRUE) + ) + port map ( + O => sDataPadP, -- 1-bit output: Buffer output + OB => sDataPadN, + I => sDataP, -- 1-bit input: Diff_p buffer input (connect directly to top-level port) + IB => sDataN -- 1-bit input: Diff_n buffer input (connect directly to top-level port) + ); + -- Optionally invert the pad input + sData_i <= sDataPadP when ADC_INVERT_CH_G = '0' else sDataPadN; + ---------------------------------------------------------------------------- + -- idelay3 + ---------------------------------------------------------------------------- + U_IDELAYE3_0 : IDELAYE3 + generic map ( + CASCADE => CASCADE_C, -- Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE) + DELAY_FORMAT => "COUNT", -- Units of the DELAY_VALUE (COUNT, TIME) + DELAY_SRC => "IDATAIN", -- Delay input (DATAIN, IDATAIN) + DELAY_TYPE => "VAR_LOAD", -- Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD) + DELAY_VALUE => conv_integer(DEFAULT_DELAY_G), -- Input delay value setting + IS_CLK_INVERTED => '0', -- Optional inversion for CLK + IS_RST_INVERTED => '0', -- Optional inversion for RST + REFCLK_FREQUENCY => IDELAYCTRL_FREQ_G, -- IDELAYCTRL clock input frequency in MHz (200.0-2667.0) + SIM_DEVICE => "ULTRASCALE", -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, + -- ULTRASCALE_PLUS_ES2) + UPDATE_MODE => "ASYNC" -- Determines when updates to the delay will take effect (ASYNC, MANUAL, + -- SYNC) + ) + port map ( + CASC_IN => '0', -- 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT + CASC_OUT => cascOut, -- 1-bit output: Cascade delay output to ODELAY input cascade + CASC_RETURN => cascRet, -- 1-bit input: Cascade delay returning from slave ODELAY DATAOUT + CNTVALUEOUT => masterCntValue1, -- 9-bit output: Counter value output + DATAOUT => sData_d, -- 1-bit output: Delayed data output + CE => '0', -- 1-bit input: Active high enable increment/decrement input + CLK => dClkDiv4, -- 1-bit input: Clock input + CNTVALUEIN => delay, -- 9-bit input: Counter value input + DATAIN => '1', -- 1-bit input: Data input from the logic + EN_VTC => '0', -- 1-bit input: Keep delay constant over VT + IDATAIN => sData_i, -- 1-bit input: Data input from the IOBUF + INC => '0', -- 1-bit input: Increment / Decrement tap delay input + LOAD => loadDelay, -- 1-bit input: Load DELAY_VALUE input + RST => '0' -- 1-bit input: Asynchronous Reset to the DELAY_VALUE + ); + + G_IdelayCascade: if IDELAY_CASCADE_G = true generate + signal masterCntValue : slv(9 downto 0); + begin + + U_ODELAYE3_0 : ODELAYE3 + generic map ( + CASCADE => "SLAVE_END", -- Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE) + DELAY_FORMAT => "COUNT", -- Units of the DELAY_VALUE (COUNT, TIME) + DELAY_TYPE => "VAR_LOAD", -- Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD) + DELAY_VALUE => conv_integer(DEFAULT_DELAY_G), -- Input delay value setting + IS_CLK_INVERTED => '0', -- Optional inversion for CLK + IS_RST_INVERTED => '0', -- Optional inversion for RST + REFCLK_FREQUENCY => IDELAYCTRL_FREQ_G, -- IDELAYCTRL clock input frequency in MHz (200.0-2400.0) + UPDATE_MODE => "ASYNC") -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC) + port map ( + CASC_IN => cascOut, -- 1-bit input: Cascade delay input from slave IDELAY CASCADE_OUT + CASC_OUT => open, -- 1-bit output: Cascade delay output to IDELAY input cascade + CASC_RETURN => '0', -- 1-bit input: Cascade delay returning from slave IDELAY DATAOUT + ODATAIN => '0', -- 1-bit input: Data input + DATAOUT => cascRet, -- 1-bit output: Delayed data from ODATAIN input port + CLK => dClkDiv4, -- 1-bit input: Clock input + EN_VTC => '0', -- 1-bit input: Keep delay constant over VT + INC => '0', -- 1-bit input: Increment / Decrement tap delay input + CE => '0', -- 1-bit input: Active high enable increment/decrement input + LOAD => loadDelay, -- 1-bit input: Load DELAY_VALUE input + RST => '0', -- 1-bit input: Asynchronous Reset to the DELAY_VALUE + CNTVALUEIN => delay, -- 9-bit input: Counter value input + CNTVALUEOUT => masterCntValue2); -- 9-bit output: Counter value output + + masterCntValue <= resize(masterCntValue1, 10, '0') + masterCntValue2; + delayValueOut <= masterCntValue(9 downto 1); + + end generate; + G_IdelayNoCascade: if IDELAY_CASCADE_G = false generate + delayValueOut <= masterCntValue1; + masterCntValue2 <= (others=>'0'); + cascRet <= '0'; + end generate; + + ---------------------------------------------------------------------------- + -- iserdes3 + ---------------------------------------------------------------------------- + U_ISERDESE3_master : ISERDESE3 + generic map ( + DATA_WIDTH => 8, -- Parallel data width (4,8) + FIFO_ENABLE => "FALSE", -- Enables the use of the FIFO + FIFO_SYNC_MODE => "FALSE", -- Enables the use of internal 2-stage synchronizers on the FIFO + IS_CLK_B_INVERTED => '1', -- Optional inversion for CLK_B + IS_CLK_INVERTED => '0', -- Optional inversion for CLK + IS_RST_INVERTED => '0', -- Optional inversion for RST + SIM_DEVICE => "ULTRASCALE" -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, + ) + port map ( + FIFO_EMPTY => open, -- 1-bit output: FIFO empty flag + INTERNAL_DIVCLK => open, -- 1-bit output: Internally divided down clock used when FIFO is + Q => masterData, -- bit registered output + CLK => dClk, -- 1-bit input: High-speed clock + CLKDIV => dClkDiv4, -- 1-bit input: Divided Clock + CLK_B => dClk, -- 1-bit input: Inversion of High-speed clock CLK + D => sData_d, -- 1-bit input: Serial Data Input + FIFO_RD_CLK => '1', -- 1-bit input: FIFO read clock + FIFO_RD_EN => '1', -- 1-bit input: Enables reading the FIFO when asserted + RST => adcClkRst -- 1-bit input: Asynchronous Reset + ); + + ----------------------------------------------------------------------------- + -- 8 to 16, 56 gearbox and bitSlip control logic + -- Part or all 56 bits can be used for idelay3 adjustment + ----------------------------------------------------------------------------- + adc8to56GearboxComb : process (adcDv4R, masterData, bitSlip) is + variable v : AdcClkDiv4RegType; + begin + + v := adcDv4R; + + -- update register with signal values + v.masterData := masterData; + v.bitSlip := bitSlip; + + -- creates pipeline + v.masterData_1 := adcDv4R.masterData; + v.longData_1 := adcDv4R.longData; + + -- data checks on this logic. + -- 56 bit assembly logic + case (adcDv4R.longDataCounter) is + when "000" => + v.longData(7 downto 0) := adcDv4R.masterData_1; + v.longDataCounter := adcDv4R.longDataCounter + 1; + when "001" => + v.longData(15 downto 8) := adcDv4R.masterData_1; + v.longDataCounter := adcDv4R.longDataCounter + 1; + when "010" => + v.longData(23 downto 16) := adcDv4R.masterData_1; + v.longDataCounter := adcDv4R.longDataCounter + 1; + when "011" => + v.longData(31 downto 24) := adcDv4R.masterData_1; + v.longDataCounter := adcDv4R.longDataCounter + 1; + when "100" => + v.longData(39 downto 32) := adcDv4R.masterData_1; + v.longDataCounter := adcDv4R.longDataCounter + 1; + when "101" => + v.longData(47 downto 40) := adcDv4R.masterData_1; + v.longDataCounter := adcDv4R.longDataCounter + 1; + when "110" => + v.longData(55 downto 48) := adcDv4R.masterData_1; + v.longDataCounter := (others => '0'); + when others => + v.longData := (others => '0'); + v.longDataCounter := (others => '0'); + end case; + + if adcDv4R.longDataCounter = "000" then + if adcDv4r.longData = adcDv4r.longData_1 then + v.longDataStable := '1'; + else + v.longDataStable := '0'; + end if; + end if; + + --16 bit data assembly logic + if adcDv4R.DWByte = '1' then + v.masterDataDW(7 downto 0) := adcDv4R.masterData_1; + v.masterDataDW(15 downto 8) := adcDv4R.masterData; + v.masterDataDW_1 := adcDv4R.masterDataDW; + end if; + + v.DWByte := not adcDv4R.DWByte; + + --bit slip logic + case (adcDv4R.bitSlip) is + when "0000" => + v.masterDataDWBS := adcDv4R.masterDataDW(15 downto 0); + when "0001" => + v.masterDataDWBS := adcDv4R.masterDataDW(14 downto 0) & adcDv4R.masterDataDW_1(15); + when "0010" => + v.masterDataDWBS := adcDv4R.masterDataDW(13 downto 0) & adcDv4R.masterDataDW_1(15 downto 14); + when "0011" => + v.masterDataDWBS := adcDv4R.masterDataDW(12 downto 0) & adcDv4R.masterDataDW_1(15 downto 13); + when "0100" => + v.masterDataDWBS := adcDv4R.masterDataDW(11 downto 0) & adcDv4R.masterDataDW_1(15 downto 12); + when "0101" => + v.masterDataDWBS := adcDv4R.masterDataDW(10 downto 0) & adcDv4R.masterDataDW_1(15 downto 11); + when "0110" => + v.masterDataDWBS := adcDv4R.masterDataDW(9 downto 0) & adcDv4R.masterDataDW_1(15 downto 10); + when "0111" => + v.masterDataDWBS := adcDv4R.masterDataDW(8 downto 0) & adcDv4R.masterDataDW_1(15 downto 9); + when "1000" => + v.masterDataDWBS := adcDv4R.masterDataDW(7 downto 0) & adcDv4R.masterDataDW_1(15 downto 8); + when "1001" => + v.masterDataDWBS := adcDv4R.masterDataDW(6 downto 0) & adcDv4R.masterDataDW_1(15 downto 7); + when "1010" => + v.masterDataDWBS := adcDv4R.masterDataDW(5 downto 0) & adcDv4R.masterDataDW_1(15 downto 6); + when "1011" => + v.masterDataDWBS := adcDv4R.masterDataDW(4 downto 0) & adcDv4R.masterDataDW_1(15 downto 5); + when "1100" => + v.masterDataDWBS := adcDv4R.masterDataDW(3 downto 0) & adcDv4R.masterDataDW_1(15 downto 4); + when "1101" => + v.masterDataDWBS := adcDv4R.masterDataDW(2 downto 0) & adcDv4R.masterDataDW_1(15 downto 3); + when "1110" => + v.masterDataDWBS := adcDv4R.masterDataDW(1 downto 0) & adcDv4R.masterDataDW_1(15 downto 2); + when "1111" => + v.masterDataDWBS := adcDv4R.masterDataDW(0) & adcDv4R.masterDataDW_1(15 downto 1); + when others => + v.masterDataDWBS := (others => '0'); + end case; + + adcDv4Rin <= v; + + --outputs + + end process; + + adclongSeq : process (adcClkRst, dClkDiv4, adcDv4Rin) is + begin + if (adcClkRst = '1') then + adcDv4R <= ADC_CLK_DV4_REG_INIT_C; + elsif (rising_edge(dClkDiv4)) then + -- latch deserializer data + adcDv4R <= adcDv4Rin after TPD_G; + end if; + end process; + + + adc8To7GearboxComb : process (adcDv4R, adcDv7R, gearboxOffset) is + variable v : AdcClkDiv7RegType; + begin + + v := adcDv7R; + + v.gearboxSeq := adcDv7R.gearboxCounter + gearboxOffset; + v.adcDataGearboxIn := adcDv4R.masterDataDWBS; + + -- creates pipeline + v.adcDataGearboxIn_1 := adcDv7R.adcDataGearboxIn; + + case (adcDv7R.gearboxSeq) is + when "000" => + v.masterAdcData := adcDv7R.adcDataGearboxIn(13 downto 0); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when "001" => + v.masterAdcData := adcDv7R.adcDataGearboxIn(11 downto 0) & adcDv7R.adcDataGearboxIn_1(15 downto 14); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when "010" => + v.masterAdcData := adcDv7R.adcDataGearboxIn(9 downto 0) & adcDv7R.adcDataGearboxIn_1(15 downto 12); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when "011" => + v.masterAdcData := adcDv7R.adcDataGearboxIn(7 downto 0) & adcDv7R.adcDataGearboxIn_1(15 downto 10); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when "100" => + v.masterAdcData := adcDv7R.adcDataGearboxIn(5 downto 0) & adcDv7R.adcDataGearboxIn_1(15 downto 8); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when "101" => + v.masterAdcData := adcDv7R.adcDataGearboxIn(3 downto 0) & adcDv7R.adcDataGearboxIn_1(15 downto 6); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when "110" => + v.masterAdcData := adcDv7R.adcDataGearboxIn(1 downto 0) & adcDv7R.adcDataGearboxIn_1(15 downto 4); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when "111" => + v.masterAdcData := adcDv7R.adcDataGearboxIn_1(15 downto 2); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when others => + v.masterAdcData := (others => '0'); + v.gearboxCounter := (others => '0'); + end case; + + adcDv7Rin <= v; + + --outputs + + end process; + + + adc8To7GearboxSeq : process (adcClkRst, dClkDiv7, adcDv7Rin) is + begin + if (adcClkRst = '1') then + adcDv7R <= ADC_CLK_DV7_REG_INIT_C; + elsif (rising_edge(dClkDiv7)) then + -- latch deserializer data + adcDv7R <= adcDv7Rin after TPD_G; + end if; + end process; +end rtl; + diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutClkUS.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutClkUS.vhd new file mode 100644 index 0000000000..c417ae0c89 --- /dev/null +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutClkUS.vhd @@ -0,0 +1,652 @@ +------------------------------------------------------------------------------- +-- File : Ad9249ReadoutClkUS.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- ADC Readout Controller +-- Receives ADC Data from an AD9592 chip. +-- Designed specifically for Xilinx 7 series FPGAs +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use ieee.std_logic_arith.all; +use ieee.numeric_std.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +use work.StdRtlPkg.all; +use work.AxiLitePkg.all; +use work.AxiStreamPkg.all; +use work.Ad9249Pkg.all; + +entity Ad9249ReadoutClkUS is + generic ( + TPD_G : time := 1 ns; + NUM_CHANNELS_G : natural range 1 to 8 := 8; + IODELAY_GROUP_G : string := "DEFAULT_GROUP"; + IDELAYCTRL_FREQ_G : real := 350.0; + DELAY_VALUE_G : natural := 1250; + DEFAULT_DELAY_G : slv(4 downto 0) := (others => '0'); + ADC_INVERT_CH_G : slv(7 downto 0) := "00000000"); + port ( + -- Master system clock, 125Mhz + axilClk : in sl; + axilRst : in sl; + -- Reset for adc deserializer + adcClkRst : in sl; + -- Signals to/from idelayCtrl + idelayCtrlRdy : in sl; + cmt_locked : out sl; -- MMCM/PLL locked if used + -- Serial Data from ADC + dClkP : in sl; -- Data clock + dClkN : in sl; + dClkPOut : out sl; + dClkNOut : out sl; + dClkDiv4Out : out sl; + dClkDiv7Out : out sl; + fClkP : in sl; -- Frame clock + fClkN : in sl; + -- Signal to control data gearboxes + loadDelay : in sl; + delay : in slv(8 downto 0) := "000000000"; + masterDelayValueOut : out slv(8 downto 0); + slaveDelayValueOut : out slv(8 downto 0); + bitSlip : in slv(3 downto 0) := "0000"; + gearboxOffset : in slv(2 downto 0) := "000"; + pixData : out slv(13 downto 0) + ); +end Ad9249ReadoutClkUS; + +-- Define architecture +architecture rtl of Ad9249ReadoutClkUS is + ------------------------------------------------------------------------------------------------- + -- ADC Readout Clocked Registers + ------------------------------------------------------------------------------------------------- + + type StateType is (IDLE_S, WAIT_IDELAY_CTRL_RDY_S, LOAD_VALUE_S, WAIT_LOAD_S, LOAD_PULSE_S, WAIT_READ_S, READ_VALUE_S); + + type AdcClkRegType is record + state : StateType; + waitStateCnt : slv(3 downto 0); + -- idelay signals + masterCntValueIn : slv(8 downto 0); + slaveCntValueIn : slv(8 downto 0); + masterCntValue : slv(8 downto 0); + slaveCntValue : slv(8 downto 0); + masterCE : sl; + slaveCE : sl; + masterEn_Vtc : sl; + slaveEn_Vtc : sl; + masterLoad : sl; + slaveLoad : sl; + end record; + + constant ADC_CLK_REG_INIT_C : AdcClkRegType := ( + state => IDLE_S, + waitStateCnt => (others => '0'), + masterCntValueIn => (others => '0'), + slaveCntValueIn => (others => '0'), + masterCntValue => (others => '0'), + slaveCntValue => (others => '0'), + masterCE => '1', + slaveCE => '1', + masterEn_Vtc => '0', + slaveEn_Vtc => '0', + masterLoad => '0', + slaveLoad => '0' + ); + + type AdcClkDiv4RegType is record + masterData : slv(7 downto 0); + masterData_1 : slv(7 downto 0); + slaveData : slv(7 downto 0); + slaveData_1 : slv(7 downto 0); + longDataCounter : slv(2 downto 0); + longData : slv(55 downto 0); + longData_1 : slv(55 downto 0); + longDataD : slv(55 downto 0); + DWByte : sl; + masterDataDW : slv(15 downto 0); + masterDataDW_1 : slv(15 downto 0); + bitSlip : slv(3 downto 0); + masterDataDWBS : slv(15 downto 0); + longDataStable : sl; + end record; + + constant ADC_CLK_DV4_REG_INIT_C : AdcClkDiv4RegType := ( + masterData => (others => '0'), + masterData_1 => (others => '0'), + slaveData => (others => '0'), + slaveData_1 => (others => '0'), + longDataCounter => (others => '0'), + longData => (others => '0'), + longData_1 => (others => '0'), + longDataD => (others => '0'), + DWByte => '0', + masterDataDW => (others => '0'), + masterDataDW_1 => (others => '0'), + bitSlip => (others => '0'), + masterDataDWBS => (others => '0'), + longDataStable => '0' + ); + + type AdcClkDiv7RegType is record + gearboxCounter : slv(2 downto 0); + gearboxSeq : slv(2 downto 0); + masterPixData : slv(13 downto 0); + slavePixData : slv(13 downto 0); + dataAligned : sl; + pixDataGearboxIn : slv(15 downto 0); + pixDataGearboxIn_1 : slv(15 downto 0); + end record; + + constant ADC_CLK_DV7_REG_INIT_C : AdcClkDiv7RegType := ( + gearboxCounter => (others => '0'), + gearboxSeq => (others => '0'), + masterPixData => (others => '0'), + slavePixData => (others => '0'), + dataAligned => '0', + pixDataGearboxIn => (others => '0'), + pixDataGearboxIn_1 => (others => '0') + ); + + + + signal adcR : AdcClkRegType := ADC_CLK_REG_INIT_C; + signal adcRin : AdcClkRegType; + + signal adcDV4R : AdcClkDiv4RegType := ADC_CLK_DV4_REG_INIT_C; + signal adcDv4Rin : AdcClkDiv4RegType; + + signal adcDV7R : AdcClkDiv7RegType := ADC_CLK_DV7_REG_INIT_C; + signal adcDv7Rin : AdcClkDiv7RegType; + + + -- Local signals + signal fClkP_i : sl; + signal fClkN_i : sl; + signal fClkP_d : sl; + signal fClkN_d : sl; + signal dClk : sl; + signal dClkP_i : sl; + signal dClkN_i : sl; + signal dClkDiv7 : sl; + signal dClkDiv4 : sl; + -- idelay signals + signal idelayRdy_n : sl; + signal masterCntValue : slv(8 downto 0); + signal slaveCntValue : slv(8 downto 0); + -- iserdes signal + signal masterData : slv(7 downto 0); + signal slaveData : slv(7 downto 0); + +begin + + cmt_locked <= '1'; + idelayRdy_n <= not idelayCtrlRdy; + dClkPOut <= dClkP_i; + dClkNOut <= dClkN_i; + dClk <= dClkP_i; + dClkDiv4Out <= dClkDiv4; + dClkDiv7Out <= dClkDiv7; + + ------------------------------------------------------------------------------------------------- + -- Create Clocks + ------------------------------------------------------------------------------------------------- + + -- input fclk buffer + -- the fclock in this module has the function of a reference data + -- + U_IBUFDS_DIFF_OUT_fclk : IBUFDS_DIFF_OUT + generic map ( + DQS_BIAS => "FALSE" -- (FALSE, TRUE) + ) + port map ( + O => fClkP_i, -- 1-bit output: Buffer diff_p output + OB => fClkN_i, -- 1-bit output: Buffer diff_n output + I => fClkP, -- 1-bit input: Diff_p buffer input (connect directly to top-level port) + IB => fClkN -- 1-bit input: Diff_n buffer input (connect directly to top-level port) + ); + + U_IBUFDS_dclk : IBUFDS_DIFF_OUT + generic map ( + DQS_BIAS => "FALSE" -- (FALSE, TRUE) + ) + port map ( + O => dclkP_i, -- 1-bit output: Buffer output + OB => dClkN_i, -- 1-bit output: Buffer diff_n output + I => dclkP, -- 1-bit input: Diff_p buffer input (connect directly to top-level port) + IB => dclkN -- 1-bit input: Diff_n buffer input (connect directly to top-level port) + ); + + U_BUFGCE_DIV_dclk2 : BUFGCE_DIV + generic map ( + BUFGCE_DIVIDE => 7, -- 1-8 + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_CE_INVERTED => '0', -- Optional inversadion for CE + IS_CLR_INVERTED => '0', -- Optional inversion for CLR + IS_I_INVERTED => '0' -- Optional inversion for I + ) + port map ( + O => dClkDiv7, -- 1-bit output: Buffer + CE => '1', -- 1-bit input: Buffer enable + CLR => '0', -- 1-bit input: Asynchronous clear + I => dClk -- 1-bit input: Buffer + ); + + U_BUFGCE_DIV_dclk8 : BUFGCE_DIV + generic map ( + BUFGCE_DIVIDE => 4, -- 1-8 + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_CE_INVERTED => '0', -- Optional inversion for CE + IS_CLR_INVERTED => '0', -- Optional inversion for CLR + IS_I_INVERTED => '0' -- Optional inversion for I + ) + port map ( + O => dClkDiv4, -- 1-bit output: Buffer + CE => '1', -- 1-bit input: Buffer enable + CLR => '0', -- 1-bit input: Asynchronous clear + I => dClk -- 1-bit input: Buffer + ); + + ---------------------------------------------------------------------------- + -- idelay3 + ---------------------------------------------------------------------------- + U_IDELAYE3_0 : IDELAYE3 + generic map ( + CASCADE => "NONE", -- Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE) + DELAY_FORMAT => "TIME", -- Units of the DELAY_VALUE (COUNT, TIME) + DELAY_SRC => "IDATAIN", -- Delay input (DATAIN, IDATAIN) + DELAY_TYPE => "VAR_LOAD", -- Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD) + DELAY_VALUE => DELAY_VALUE_G, -- Input delay value setting + IS_CLK_INVERTED => '0', -- Optional inversion for CLK + IS_RST_INVERTED => '0', -- Optional inversion for RST + REFCLK_FREQUENCY => IDELAYCTRL_FREQ_G, -- IDELAYCTRL clock input frequency in MHz (200.0-2667.0) + SIM_DEVICE => "ULTRASCALE", -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, + -- ULTRASCALE_PLUS_ES2) + UPDATE_MODE => "ASYNC" -- Determines when updates to the delay will take effect (ASYNC, MANUAL, + -- SYNC) + ) + port map ( + CASC_OUT => open, -- 1-bit output: Cascade delay output to ODELAY input cascade + CNTVALUEOUT => masterCntValue, -- 9-bit output: Counter value output + DATAOUT => fClkP_d, -- 1-bit output: Delayed data output + CASC_IN => '1', -- 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT + CASC_RETURN => '1', -- 1-bit input: Cascade delay returning from slave ODELAY DATAOUT + CE => adcR.masterCE, -- 1-bit input: Active high enable increment/decrement input + CLK => dClk, -- 1-bit input: Clock input + CNTVALUEIN => adcR.masterCntValueIn, -- 9-bit input: Counter value input + DATAIN => '1', -- 1-bit input: Data input from the logic + EN_VTC => adcR.masterEn_Vtc, -- 1-bit input: Keep delay constant over VT + IDATAIN => fclkP_i, -- 1-bit input: Data input from the IOBUF + INC => '0', -- 1-bit input: Increment / Decrement tap delay input + LOAD => adcR.masterLoad, -- 1-bit input: Load DELAY_VALUE input + RST => axilRst -- 1-bit input: Asynchronous Reset to the DELAY_VALUE + ); + + U_IDELAYE3_1 : IDELAYE3 + generic map ( + CASCADE => "NONE", + DELAY_FORMAT => "TIME", + DELAY_SRC => "IDATAIN", + DELAY_TYPE => "VAR_LOAD", + DELAY_VALUE => DELAY_VALUE_G, + IS_CLK_INVERTED => '0', + IS_RST_INVERTED => '0', + REFCLK_FREQUENCY => IDELAYCTRL_FREQ_G, + SIM_DEVICE => "ULTRASCALE", + UPDATE_MODE => "ASYNC" + ) + port map ( + CASC_OUT => open, + CNTVALUEOUT => slaveCntValue, + DATAOUT => fClkN_d, + CASC_IN => '1', + CASC_RETURN => '1', + CE => adcR.slaveCE, + CLK => dClk, + CNTVALUEIN => adcR.slaveCntValueIn, + DATAIN => '1', + EN_VTC => adcR.slaveEn_Vtc, + IDATAIN => fclkN_i, + INC => '0', + LOAD => adcR.slaveLoad, + RST => axilRst + ); + + ---------------------------------------------------------------------------- + -- iserdes3 + ---------------------------------------------------------------------------- + U_ISERDESE3_master : ISERDESE3 + generic map ( + DATA_WIDTH => 8, -- Parallel data width (4,8) + FIFO_ENABLE => "FALSE", -- Enables the use of the FIFO + FIFO_SYNC_MODE => "FALSE", -- Enables the use of internal 2-stage synchronizers on the FIFO + IS_CLK_B_INVERTED => '0', -- Optional inversion for CLK_B + IS_CLK_INVERTED => '0', -- Optional inversion for CLK + IS_RST_INVERTED => '0', -- Optional inversion for RST + SIM_DEVICE => "ULTRASCALE" -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, + -- ULTRASCALE_PLUS_ES2) + ) + port map ( + FIFO_EMPTY => open, -- 1-bit output: FIFO empty flag + INTERNAL_DIVCLK => open, -- 1-bit output: Internally divided down clock used when FIFO is + -- disabled (do not connect) + + Q => masterData, -- bit registered output + CLK => dClkP_i, -- 1-bit input: High-speed clock + CLKDIV => dClkDiv4, -- 1-bit input: Divided Clock + CLK_B => dClkN_i, -- 1-bit input: Inversion of High-speed clock CLK + D => fclkP_d, -- 1-bit input: Serial Data Input + FIFO_RD_CLK => '1', -- 1-bit input: FIFO read clock + FIFO_RD_EN => '1', -- 1-bit input: Enables reading the FIFO when asserted + RST => axilRst -- 1-bit input: Asynchronous Reset + ); + + U_ISERDESE3_slave : ISERDESE3 + generic map ( + DATA_WIDTH => 8, + FIFO_ENABLE => "FALSE", + FIFO_SYNC_MODE => "FALSE", + IS_CLK_B_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_RST_INVERTED => '0', + SIM_DEVICE => "ULTRASCALE" + ) + port map ( + FIFO_EMPTY => open, + INTERNAL_DIVCLK => open, + Q => slaveData, + CLK => dClkP_i, + CLKDIV => dClkDiv4, + CLK_B => dClkN_i, + D => fclkN_d, + FIFO_RD_CLK => '1', + FIFO_RD_EN => '1', + RST => axilRst + ); + + ----------------------------------------------------------------------------- + -- custom logic + ----------------------------------------------------------------------------- + adcComb : process (adcR, loadDelay, masterCntValue, slaveCntValue) is + variable v : AdcClkRegType; + begin + v := adcR; + + case (adcR.state) is + when WAIT_IDELAY_CTRL_RDY_S => + if idelayCtrlRdy = '1' then + v.state := LOAD_VALUE_S; + else + v.state := IDLE_S; -- can't program the delay if control is + -- not ready yet. + end if; + when LOAD_VALUE_S => + v.slaveEn_Vtc := '0'; + v.masterEn_Vtc := '0'; -- needed to readback the tapdelay value + v.slaveLoad := '0'; + v.masterLoad := '0'; + v.waitStateCnt := (others => '0'); + v.state := WAIT_LOAD_S; + when WAIT_LOAD_S => + v.waitStateCnt := adcR.waitStateCnt + '1'; + if adcR.waitStateCnt = X"1" then + v.state := LOAD_PULSE_S; + end if; + when LOAD_PULSE_S => + v.slaveLoad := '1'; + v.masterLoad := '1'; + v.waitStateCnt := (others => '0'); + v.state := WAIT_READ_S; + when WAIT_READ_S => + v.slaveLoad := '0'; + v.masterLoad := '0'; + v.waitStateCnt := adcR.waitStateCnt + '1'; + if adcR.waitStateCnt = X"9" then + v.state := READ_VALUE_S; + end if; + when READ_VALUE_S => + v.slaveCntValue := slaveCntValue; + v.masterCntValue := masterCntValue; + v.state := IDLE_S; + when IDLE_S => + v.slaveLoad := '0'; + v.masterLoad := '0'; + v.slaveCE := '0'; + v.masterCE := '0'; + v.slaveEn_Vtc := idelayRdy_n; -- check if the value should be '1' + -- or idelayRdy_n + v.masterEn_Vtc := idelayRdy_n; + v.slaveCntValueIn := delay; -- save new delay value + v.masterCntValueIn := delay; -- save new delay value + if loadDelay = '1' then + v.state := WAIT_IDELAY_CTRL_RDY_S; --loopthrough load delay routine + end if; + when others => + v.state := IDLE_S; + end case; + + adcRin <= v; + + --outputs + masterDelayValueOut <= adcR.masterCntValue; + slaveDelayValueOut <= adcR.slaveCntValue; + + end process adcComb; + + + adcSeq : process (dClkDiv4, axilRst) is + begin + if (axilRst = '1') then + adcR <= ADC_CLK_REG_INIT_C after TPD_G; + elsif (rising_edge(dClkDiv4)) then + adcR <= adcRin after TPD_G; + end if; + end process adcSeq; + + + ----------------------------------------------------------------------------- + -- 8 to 16, 56 gearbox and bitSlip control logic + -- Part or all 56 bits can be used for idelay3 adjustment + ----------------------------------------------------------------------------- + adc8to56GearboxComb : process (adcDv4R, masterData, slaveData, bitSlip) is + variable v : AdcClkDiv4RegType; + begin + + v := adcDv4R; + + -- update register with signal values + v.masterData := masterData; + v.slaveData := slaveData; + v.bitSlip := bitSlip; + + -- creates pipeline + v.masterData_1 := adcDv4R.masterData; + v.slaveData_1 := adcDv4R.slaveData; + v.longData_1 := adcDv4R.longData; + + -- data checks on this logic. + -- 56 bit assembly logic + case (adcDv4R.longDataCounter) is + when "000" => + v.longData(7 downto 0) := adcDv4R.masterData_1; + v.longDataCounter := adcDv4R.longDataCounter + 1; + when "001" => + v.longData(15 downto 8) := adcDv4R.masterData_1; + v.longDataCounter := adcDv4R.longDataCounter + 1; + when "010" => + v.longData(23 downto 16) := adcDv4R.masterData_1; + v.longDataCounter := adcDv4R.longDataCounter + 1; + when "011" => + v.longData(31 downto 24) := adcDv4R.masterData_1; + v.longDataCounter := adcDv4R.longDataCounter + 1; + when "100" => + v.longData(39 downto 32) := adcDv4R.masterData_1; + v.longDataCounter := adcDv4R.longDataCounter + 1; + when "101" => + v.longData(47 downto 40) := adcDv4R.masterData_1; + v.longDataCounter := adcDv4R.longDataCounter + 1; + when "110" => + v.longData(55 downto 48) := adcDv4R.masterData_1; + v.longDataCounter := (others => '0'); + when others => + v.longData := (others => '0'); + v.longDataCounter := (others => '0'); + end case; + + if adcDv4R.longDataCounter = "000" then + if adcDv4r.longData = adcDv4r.longData_1 then + v.longDataStable := '1'; + else + v.longDataStable := '0'; + end if; + end if; + + --16 bit data assembly logic + if adcDv4R.DWByte = '1' then + v.masterDataDW(7 downto 0) := adcDv4R.masterData_1; + v.masterDataDW(15 downto 8) := adcDv4R.masterData; + v.masterDataDW_1 := adcDv4R.masterDataDW; + end if; + + v.DWByte := not adcDv4R.DWByte; + + --bit slip logic + case (adcDv4R.bitSlip) is + when "0000" => + v.masterDataDWBS := adcDv4R.masterDataDW(15 downto 0); + when "0001" => + v.masterDataDWBS := adcDv4R.masterDataDW(14 downto 0) & adcDv4R.masterDataDW_1(15); + when "0010" => + v.masterDataDWBS := adcDv4R.masterDataDW(13 downto 0) & adcDv4R.masterDataDW_1(15 downto 14); + when "0011" => + v.masterDataDWBS := adcDv4R.masterDataDW(12 downto 0) & adcDv4R.masterDataDW_1(15 downto 13); + when "0100" => + v.masterDataDWBS := adcDv4R.masterDataDW(11 downto 0) & adcDv4R.masterDataDW_1(15 downto 12); + when "0101" => + v.masterDataDWBS := adcDv4R.masterDataDW(10 downto 0) & adcDv4R.masterDataDW_1(15 downto 11); + when "0110" => + v.masterDataDWBS := adcDv4R.masterDataDW(9 downto 0) & adcDv4R.masterDataDW_1(15 downto 10); + when "0111" => + v.masterDataDWBS := adcDv4R.masterDataDW(8 downto 0) & adcDv4R.masterDataDW_1(15 downto 9); + when "1000" => + v.masterDataDWBS := adcDv4R.masterDataDW(7 downto 0) & adcDv4R.masterDataDW_1(15 downto 8); + when "1001" => + v.masterDataDWBS := adcDv4R.masterDataDW(6 downto 0) & adcDv4R.masterDataDW_1(15 downto 7); + when "1010" => + v.masterDataDWBS := adcDv4R.masterDataDW(5 downto 0) & adcDv4R.masterDataDW_1(15 downto 6); + when "1011" => + v.masterDataDWBS := adcDv4R.masterDataDW(4 downto 0) & adcDv4R.masterDataDW_1(15 downto 5); + when "1100" => + v.masterDataDWBS := adcDv4R.masterDataDW(3 downto 0) & adcDv4R.masterDataDW_1(15 downto 4); + when "1101" => + v.masterDataDWBS := adcDv4R.masterDataDW(2 downto 0) & adcDv4R.masterDataDW_1(15 downto 3); + when "1110" => + v.masterDataDWBS := adcDv4R.masterDataDW(1 downto 0) & adcDv4R.masterDataDW_1(15 downto 2); + when "1111" => + v.masterDataDWBS := adcDv4R.masterDataDW(0) & adcDv4R.masterDataDW_1(15 downto 1); + when others => + v.masterDataDWBS := (others => '0'); + end case; + + adcDv4Rin <= v; + + --outputs + + end process; + + adclongSeq : process (axilRst, dClkDiv4, adcDv4Rin) is + begin + if (axilRst = '1') then + adcDv4R <= ADC_CLK_DV4_REG_INIT_C; + elsif (rising_edge(dClkDiv4)) then + -- latch deserializer data + adcDv4R <= adcDv4Rin after TPD_G; + end if; + end process; + + + adc8To7GearboxComb : process (adcDv4R, adcDv7R, gearboxOffset) is + variable v : AdcClkDiv7RegType; + begin + + v := adcDv7R; + + v.gearboxSeq := adcDv7R.gearboxCounter + gearboxOffset; + v.pixDataGearboxIn := adcDv4R.masterDataDWBS; + + -- creates pipeline + v.pixDataGearboxIn_1 := adcDv7R.pixDataGearboxIn; + + -- flag that indicates data, or frame signal matches the expected pattern + if adcDv7R.masterPixData = "11111110000000" then + v.dataAligned := '1'; + else + v.dataAligned := '0'; + end if; + + case (adcDv7R.gearboxSeq) is + when "000" => + v.masterPixData := adcDv7R.pixDataGearboxIn(15 downto 2); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when "001" => + v.masterPixData := adcDv7R.pixDataGearboxIn(13 downto 0); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when "010" => + v.masterPixData := adcDv7R.pixDataGearboxIn(11 downto 0) & adcDv7R.pixDataGearboxIn_1(15 downto 14); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when "011" => + v.masterPixData := adcDv7R.pixDataGearboxIn(9 downto 0) & adcDv7R.pixDataGearboxIn_1(15 downto 12); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when "100" => + v.masterPixData := adcDv7R.pixDataGearboxIn(7 downto 0) & adcDv7R.pixDataGearboxIn_1(15 downto 10); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when "101" => + v.masterPixData := adcDv7R.pixDataGearboxIn(5 downto 0) & adcDv7R.pixDataGearboxIn_1(15 downto 8); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when "110" => + v.masterPixData := adcDv7R.pixDataGearboxIn(3 downto 0) & adcDv7R.pixDataGearboxIn_1(15 downto 6); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when "111" => + v.masterPixData := adcDv7R.pixDataGearboxIn(1 downto 0) & adcDv7R.pixDataGearboxIn_1(15 downto 4); + v.gearboxCounter := adcDv7R.gearboxCounter + 1; + when others => + v.masterPixData := (others => '0'); + v.gearboxCounter := (others => '0'); + end case; + + adcDv7Rin <= v; + + --outputs + PixData <= adcDv7R.masterPixData; + + end process; + + + adc8To7GearboxSeq : process (axilRst, dClkDiv7, adcDv7Rin) is + begin + if (axilRst = '1') then + adcDv7R <= ADC_CLK_DV7_REG_INIT_C; + elsif (rising_edge(dClkDiv7)) then + -- latch deserializer data + adcDv7R <= adcDv7Rin after TPD_G; + end if; + end process; + + +end rtl; + diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd new file mode 100644 index 0000000000..4587bbf094 --- /dev/null +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd @@ -0,0 +1,613 @@ +------------------------------------------------------------------------------- +-- File : Ad9249ReadoutGroup.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- ADC Readout Controller +-- Receives ADC Data from an AD9592 chip. +-- Designed specifically for Xilinx Ultrascale series FPGAs +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +use work.StdRtlPkg.all; +use work.AxiLitePkg.all; +use work.AxiStreamPkg.all; +use work.Ad9249Pkg.all; + +entity Ad9249ReadoutGroup is + generic ( + TPD_G : time := 1 ns; + NUM_CHANNELS_G : natural range 1 to 8 := 8; + IODELAY_GROUP_G : string := "DEFAULT_GROUP"; + D_DELAY_CASCADE_G : boolean := false; + F_DELAY_CASCADE_G : boolean := false; + IDELAYCTRL_FREQ_G : real := 200.0; + DELAY_VALUE_G : natural := 1250; + DEFAULT_DELAY_G : slv(8 downto 0) := (others => '0'); + ADC_INVERT_CH_G : slv(7 downto 0) := "00000000"; + USE_MMCME_G : boolean := false; + SIM_SPEEDUP_G : boolean := false); + port ( + -- Master system clock, 125Mhz + axilClk : in sl; + axilRst : in sl; + + -- Axi Interface + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType; + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType; + + -- Reset for adc deserializer + adcClkRst : in sl; + + -- Serial Data from ADC + adcSerial : in Ad9249SerialGroupType; + + -- Deserialized ADC Data + adcStreamClk : in sl; + adcStreams : out AxiStreamMasterArray(NUM_CHANNELS_G-1 downto 0) := + (others => axiStreamMasterInit((false, 2, 8, 0, TKEEP_NORMAL_C, 0, TUSER_NORMAL_C)))); +end Ad9249ReadoutGroup; + +-- Define architecture +architecture rtl of Ad9249ReadoutGroup is + + attribute keep : string; + + constant FRAME_PATTERN_C : slv(13 downto 0) := "00000001111111"; + + ------------------------------------------------------------------------------------------------- + -- AXIL Registers + ------------------------------------------------------------------------------------------------- + type AxilRegType is record + axilWriteSlave : AxiLiteWriteSlaveType; + axilReadSlave : AxiLiteReadSlaveType; + delay : slv(8 downto 0); + dataDelaySet : slv(NUM_CHANNELS_G-1 downto 0); + frameDelaySet : sl; + freezeDebug : sl; + readoutDebug0 : slv16Array(NUM_CHANNELS_G-1 downto 0); + readoutDebug1 : slv16Array(NUM_CHANNELS_G-1 downto 0); + lockedCountRst : sl; + end record; + + constant AXIL_REG_INIT_C : AxilRegType := ( + axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, + axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, + delay => DEFAULT_DELAY_G, + dataDelaySet => (others => '1'), + frameDelaySet => '1', + freezeDebug => '0', + readoutDebug0 => (others => (others => '0')), + readoutDebug1 => (others => (others => '0')), + lockedCountRst => '0'); + + signal lockedSync : sl; + signal lockedFallCount : slv(15 downto 0); + + signal axilR : AxilRegType := AXIL_REG_INIT_C; + signal axilRin : AxilRegType; + + ------------------------------------------------------------------------------------------------- + -- ADC Readout Clocked Registers + ------------------------------------------------------------------------------------------------- + type AdcRegType is record + slip : slv(3 downto 0); + count : slv(5 downto 0); + gearBoxOffset : slv(2 downto 0); + --loadDelay : sl; + --delayValue : slv(8 downto 0); + locked : sl; + fifoWrData : Slv16Array(NUM_CHANNELS_G-1 downto 0); + end record; + + constant ADC_REG_INIT_C : AdcRegType := ( + slip => (others => '0'), + count => (others => '0'), + gearBoxOffset => (others => '0'), + --loadDelay => '0', + --delayValue => (others => '0'), + locked => '0', + fifoWrData => (others => (others => '0'))); + + signal adcR : AdcRegType := ADC_REG_INIT_C; + signal adcRin : AdcRegType; + + + -- Local Signals + signal tmpAdcClk : sl; + signal adcBitClkIoIn : sl; + signal adcBitClkIo : sl; + signal adcBitClkR : sl; + signal adcBitClkRD4 : sl; + signal adcBitRst : sl; + signal adcBitIoRst : sl; + + signal adcFramePad : sl; + signal adcFrame : slv(13 downto 0); + signal adcFrameSync : slv(13 downto 0); + signal adcDataPadOut : slv(NUM_CHANNELS_G-1 downto 0); + signal adcDataPad : slv(NUM_CHANNELS_G-1 downto 0); + signal adcData : Slv14Array(NUM_CHANNELS_G-1 downto 0); + + signal curDelayFrame : slv(8 downto 0); + signal curDelayData : slv9Array(NUM_CHANNELS_G-1 downto 0); + + signal fifoDataValid : sl; + signal fifoDataOut : slv(NUM_CHANNELS_G*16-1 downto 0); + signal fifoDataIn : slv(NUM_CHANNELS_G*16-1 downto 0); + signal fifoDataTmp : slv16Array(NUM_CHANNELS_G-1 downto 0); + + signal debugDataValid : sl; + signal debugDataOut : slv(NUM_CHANNELS_G*16-1 downto 0); + signal debugDataTmp : slv16Array(NUM_CHANNELS_G-1 downto 0); + + signal frameDelay : slv(8 downto 0); + signal frameDelaySet : sl; + + attribute keep of adcBitClkRD4 : signal is "true"; + attribute keep of adcBitClkR : signal is "true"; + attribute keep of adcFrame : signal is "true"; + attribute keep of adcBitClkIo : signal is "true"; + +begin + ------------------------------------------------------------------------------------------------- + -- Synchronize adcR.locked across to axil clock domain and count falling edges on it + ------------------------------------------------------------------------------------------------- + + SynchronizerOneShotCnt_1 : entity work.SynchronizerOneShotCnt + generic map ( + TPD_G => TPD_G, + IN_POLARITY_G => '0', + OUT_POLARITY_G => '0', + CNT_RST_EDGE_G => true, + CNT_WIDTH_G => 16) + port map ( + dataIn => adcR.locked, + rollOverEn => '0', + cntRst => axilR.lockedCountRst, + dataOut => open, + cntOut => lockedFallCount, + wrClk => adcBitClkR, + wrRst => '0', + rdClk => axilClk, + rdRst => axilRst); + + Synchronizer_1 : entity work.Synchronizer + generic map ( + TPD_G => TPD_G, + STAGES_G => 2) + port map ( + clk => axilClk, + rst => axilRst, + dataIn => adcR.locked, + dataOut => lockedSync); + + SynchronizerVec_1 : entity work.SynchronizerVector + generic map ( + TPD_G => TPD_G, + STAGES_G => 2, + WIDTH_G => 14) + port map ( + clk => axilClk, + rst => axilRst, + dataIn => adcFrame, + dataOut => adcFrameSync); + + ------------------------------------------------------------------------------------------------- + -- AXIL Interface + ------------------------------------------------------------------------------------------------- + axilComb : process (adcFrameSync, axilR, axilReadMaster, axilRst, axilWriteMaster, curDelayData, + curDelayFrame, debugDataTmp, debugDataValid, lockedFallCount, lockedSync, adcClkRst) is + variable v : AxilRegType; + variable axilEp : AxiLiteEndpointType; + begin + v := axilR; + + v.dataDelaySet := (others => '0'); + v.frameDelaySet := '0'; + v.axilReadSlave.rdata := (others => '0'); + v.lockedCountRst := '0'; + + -- Store last two samples read from ADC + if (debugDataValid = '1' and axilR.freezeDebug = '0') then + v.readoutDebug0 := debugDataTmp; + v.readoutDebug1 := axilR.readoutDebug0; + end if; + + axiSlaveWaitTxn(axilEp, axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave); + + -- Up to 8 delay registers + -- Write delay values to IDELAY primatives + -- All writes go to same r.delay register, + -- dataDelaySet(i) or frameDelaySet enables the primative write + for i in 0 to NUM_CHANNELS_G-1 loop + axiSlaveRegister(axilEp, X"00"+toSlv((i*4), 8), 0, v.delay); + axiSlaveRegister(axilEp, X"00"+toSlv((i*4), 8), 9, v.dataDelaySet(i), '1'); + end loop; + axiSlaveRegister(axilEp, X"20", 0, v.delay); + axiSlaveRegister(axilEp, X"20", 9, v.frameDelaySet, '1'); + + -- Override read from r.delay and use curDealy output from delay primative instead + for i in 0 to NUM_CHANNELS_G-1 loop + axiSlaveRegisterR(axilEp, X"00"+toSlv((i*4), 8), 0, curDelayData(i)); + end loop; + axiSlaveRegisterR(axilEp, X"20", 0, curDelayFrame); + + + -- Debug output to see how many times the shift has needed a relock + axiSlaveRegisterR(axilEp, X"30", 0, lockedFallCount); + axiSlaveRegisterR(axilEp, X"30", 16, lockedSync); + axiSlaveRegisterR(axilEp, X"34", 0, adcFrameSync); + axiSlaveRegister(axilEp, X"38", 0, v.lockedCountRst); + + -- Debug registers. Output the last 2 words received + for i in 0 to NUM_CHANNELS_G-1 loop + axiSlaveRegisterR(axilEp, X"80"+toSlv((i*4), 8), 0, axilR.readoutDebug0(i)); + axiSlaveRegisterR(axilEp, X"80"+toSlv((i*4), 8), 16, axilR.readoutDebug1(i)); + end loop; + + axiSlaveRegister(axilEp, X"A0", 0, v.freezeDebug); + + axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C); + + if adcClkRst = '1' then + v.lockedCountRst := '1'; + end if; + + if (axilRst = '1') then + v := AXIL_REG_INIT_C; + end if; + + axilRin <= v; + axilWriteSlave <= axilR.axilWriteSlave; + axilReadSlave <= axilR.axilReadSlave; + + end process; + + axilSeq : process (axilClk) is + begin + if (rising_edge(axilClk)) then + axilR <= axilRin after TPD_G; + end if; + end process axilSeq; + + + + ------------------------------------------------------------------------------------------------- + -- Create Clocks + ------------------------------------------------------------------------------------------------- + AdcClk_I_Ibufds : IBUFDS + generic map ( + DQS_BIAS => "FALSE" -- (FALSE, TRUE) + ) + port map ( + I => adcSerial.dClkP, + IB => adcSerial.dClkN, + O => adcBitClkIoIn); + + G_MMCM : if USE_MMCME_G = true generate + ------------------------------------------ + -- Generate clocks from 156.25 MHz PGP -- + ------------------------------------------ + -- clkIn : 350.00 MHz PGP + -- clkOut(0) : 350.00 MHz adcBitClkIo clock + U_iserdesClockGen : entity work.ClockManagerUltraScale + generic map( + TPD_G => 1 ns, + TYPE_G => "MMCM", -- or "PLL" + INPUT_BUFG_G => true, + FB_BUFG_G => true, + RST_IN_POLARITY_G => '1', -- '0' for active low + NUM_CLOCKS_G => 1, + -- MMCM attributes + BANDWIDTH_G => "OPTIMIZED", + CLKIN_PERIOD_G => 2.85, -- Input period in ns ); + DIVCLK_DIVIDE_G => 10, + CLKFBOUT_MULT_F_G => 20.0, + CLKFBOUT_MULT_G => 5, + CLKOUT0_DIVIDE_F_G => 1.0, + CLKOUT0_DIVIDE_G => 2, + CLKOUT0_PHASE_G => 0.0, + CLKOUT0_DUTY_CYCLE_G => 0.5, + CLKOUT0_RST_HOLD_G => 3, + CLKOUT0_RST_POLARITY_G => '1') + port map( + clkIn => adcBitClkIoIn, + rstIn => adcClkRst, + clkOut(0) => tmpAdcClk, + rstOut(0) => adcBitIoRst, + locked => open + ); + + U_bitClkBufG : BUFG + port map ( + O => adcBitClkIo, + I => tmpAdcClk); + + end generate G_MMCM; + + G_NO_MMCM : if USE_MMCME_G = false generate + + tmpAdcClk <= adcBitClkIoIn; + + U_bitClkBufG : BUFG + port map ( + O => adcBitClkIo, + I => tmpAdcClk); + + U_PwrUpRst : entity work.PwrUpRst + generic map ( + TPD_G => TPD_G, + SIM_SPEEDUP_G => SIM_SPEEDUP_G, + DURATION_G => 511, + IN_POLARITY_G => '1', + OUT_POLARITY_G => '1') + port map ( + clk => adcBitClkIo, + arst => adcClkRst, + rstOut => adcBitIoRst); + + end generate G_NO_MMCM; + + + + -- Regional clock + U_AdcBitClkR : BUFGCE_DIV + generic map ( + BUFGCE_DIVIDE => 7, -- 1-8 + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_CE_INVERTED => '0', -- Optional inversion for CE + IS_CLR_INVERTED => '0', -- Optional inversion for CLR + IS_I_INVERTED => '0' -- Optional inversion for I + ) + port map ( + I => adcBitClkIo, + O => adcBitClkR, + CE => '1', + CLR => '0'); + + -- Regional clock + U_AdcBitClkRD4 : BUFGCE_DIV + generic map ( + BUFGCE_DIVIDE => 4, -- 1-8 + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_CE_INVERTED => '0', -- Optional inversion for CE + IS_CLR_INVERTED => '0', -- Optional inversion for CLR + IS_I_INVERTED => '0' -- Optional inversion for I + ) + port map ( + I => adcBitClkIo, + O => adcBitClkRD4, + CE => '1', + CLR => '0'); + + -- Regional clock reset + ADC_BITCLK_RST_SYNC : entity work.RstSync + generic map ( + TPD_G => TPD_G, + RELEASE_DELAY_G => 5) + port map ( + clk => adcBitClkR, + asyncRst => adcBitIoRst, + syncRst => adcBitRst); + + ------------------------------------------------------------------------------------------------- + -- Deserializers + ------------------------------------------------------------------------------------------------- + U_FRAME_DESERIALIZER : entity work.Ad9249Deserializer + generic map ( + TPD_G => TPD_G, + IODELAY_GROUP_G => "DEFAULT_GROUP", + IDELAY_CASCADE_G => F_DELAY_CASCADE_G, + IDELAYCTRL_FREQ_G => 350.0, + DEFAULT_DELAY_G => (others => '0'), + ADC_INVERT_CH_G => '1', + BIT_REV_G => '0') + port map ( + adcClkRst => adcBitRst, + dClk => adcBitClkIo, -- Data clock + dClkDiv4 => adcBitClkRD4, + dClkDiv7 => adcBitClkR, + sDataP => adcSerial.fClkP, -- Frame clock + sDataN => adcSerial.fClkN, + loadDelay => frameDelaySet, + delay => frameDelay, + delayValueOut => curDelayFrame, + bitSlip => adcR.slip, + gearboxOffset => adcR.gearboxOffset, + adcData => adcFrame + ); + + U_FrmDlyFifo : entity work.SynchronizerFifo + generic map ( + TPD_G => TPD_G, + BRAM_EN_G => false, + DATA_WIDTH_G => 9, + ADDR_WIDTH_G => 4, + INIT_G => "0") + port map ( + rst => axilRst, + wr_clk => axilClk, + wr_en => axilR.frameDelaySet, + din => axilR.delay, + rd_clk => adcBitClkRD4, + rd_en => '1', + valid => frameDelaySet, + dout => frameDelay); + + -------------------------------- + -- Data Input, 8 channels + -------------------------------- + GenData : for i in NUM_CHANNELS_G-1 downto 0 generate + signal dataDelaySet : slv(NUM_CHANNELS_G-1 downto 0); + signal dataDelay : slv9Array(NUM_CHANNELS_G-1 downto 0); + begin + + U_DATA_DESERIALIZER : entity work.Ad9249Deserializer + generic map ( + TPD_G => TPD_G, + IODELAY_GROUP_G => "DEFAULT_GROUP", + IDELAY_CASCADE_G => D_DELAY_CASCADE_G, + IDELAYCTRL_FREQ_G => 350.0, + DEFAULT_DELAY_G => (others => '0'), + ADC_INVERT_CH_G => ADC_INVERT_CH_G(i), + BIT_REV_G => '1') + port map ( + adcClkRst => adcBitRst, + dClk => adcBitClkIo, -- Data clock + dClkDiv4 => adcBitClkRD4, + dClkDiv7 => adcBitClkR, + sDataP => adcSerial.chP(i), -- Frame clock + sDataN => adcSerial.chN(i), + loadDelay => dataDelaySet(i), + delay => dataDelay(i), + delayValueOut => curDelayData(i), + bitSlip => adcR.slip, + gearboxOffset => adcR.gearboxOffset, + adcData => adcData(i) + ); + + + U_DataDlyFifo : entity work.SynchronizerFifo + generic map ( + TPD_G => TPD_G, + BRAM_EN_G => false, + DATA_WIDTH_G => 9, + ADDR_WIDTH_G => 4, + INIT_G => "0") + port map ( + rst => axilRst, + wr_clk => axilClk, + wr_en => axilR.dataDelaySet(i), + din => axilR.delay, + rd_clk => adcBitClkRD4, + rd_en => '1', + valid => dataDelaySet(i), + dout => dataDelay(i)); + + end generate; + + ------------------------------------------------------------------------------------------------- + -- ADC Bit Clocked Logic + ------------------------------------------------------------------------------------------------- + adcComb : process (adcData, adcFrame, adcR) is + variable v : AdcRegType; + begin + v := adcR; + + ---------------------------------------------------------------------------------------------- + -- Slip bits until correct alignment seen + ---------------------------------------------------------------------------------------------- + if (adcR.count = 0) then + if (adcFrame = FRAME_PATTERN_C) then + v.locked := '1'; + else + v.locked := '0'; + v.slip := adcR.slip + 1; + v.count := adcR.count + 1; + -- increments the gearbox + if adcR.slip = 0 then + v.gearBoxOffset := adcR.gearBoxOffset + 1; + end if; + end if; + end if; + + if (adcR.count /= 0) then + v.count := adcR.count + 1; + end if; + + + + ---------------------------------------------------------------------------------------------- + -- Look for Frame rising edges and write data to fifos + ---------------------------------------------------------------------------------------------- + for i in NUM_CHANNELS_G-1 downto 0 loop + if (adcR.locked = '1' and adcFrame = FRAME_PATTERN_C) then + -- Locked, output adc data + v.fifoWrData(i) := "00" & adcData(i); + else + -- Not locked + v.fifoWrData(i) := (others => '1'); --"10" & "00000000000000"; + end if; + end loop; + + adcRin <= v; + + end process adcComb; + + adcSeq : process (adcBitClkR, adcBitRst) is + begin + if (adcBitRst = '1') then + adcR <= ADC_REG_INIT_C after TPD_G; + elsif (rising_edge(adcBitClkR)) then + adcR <= adcRin after TPD_G; + end if; + end process adcSeq; + + -- Flatten fifoWrData onto fifoDataIn for FIFO + -- Regroup fifoDataOut by channel into fifoDataTmp + -- Format fifoDataTmp into AxiStream channels + glue : for i in NUM_CHANNELS_G-1 downto 0 generate + fifoDataIn(i*16+15 downto i*16) <= adcR.fifoWrData(i); + fifoDataTmp(i) <= fifoDataOut(i*16+15 downto i*16); + debugDataTmp(i) <= debugDataOut(i*16+15 downto i*16); + adcStreams(i).tdata(15 downto 0) <= fifoDataTmp(i); + adcStreams(i).tDest <= toSlv(i, 8); + adcStreams(i).tValid <= fifoDataValid; + end generate; + + -- Single fifo to synchronize adc data to the Stream clock + U_DataFifo : entity work.SynchronizerFifo + generic map ( + TPD_G => TPD_G, + BRAM_EN_G => false, + DATA_WIDTH_G => NUM_CHANNELS_G*16, + ADDR_WIDTH_G => 4, + INIT_G => "0") + port map ( + rst => adcBitRst, + wr_clk => adcBitClkR, + wr_en => '1', --Always write data + din => fifoDataIn, + rd_clk => adcStreamClk, + rd_en => fifoDataValid, + valid => fifoDataValid, + dout => fifoDataOut); + + U_DataFifoDebug : entity work.SynchronizerFifo + generic map ( + TPD_G => TPD_G, + BRAM_EN_G => false, + DATA_WIDTH_G => NUM_CHANNELS_G*16, + ADDR_WIDTH_G => 4, + INIT_G => "0") + port map ( + rst => adcBitRst, + wr_clk => adcBitClkR, + wr_en => '1', --Always write data + din => fifoDataIn, + rd_clk => axilClk, + rd_en => debugDataValid, + valid => debugDataValid, + dout => debugDataOut); + + +end rtl; + diff --git a/devices/AnalogDevices/ad9249/UltraScale/ruckus.tcl b/devices/AnalogDevices/ad9249/UltraScale/ruckus.tcl new file mode 100644 index 0000000000..f988a4f0c1 --- /dev/null +++ b/devices/AnalogDevices/ad9249/UltraScale/ruckus.tcl @@ -0,0 +1,5 @@ +# Load RUCKUS library +source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl + +# Load Source Code +loadSource -dir "$::DIR_PATH/rtl" diff --git a/devices/AnalogDevices/ad9249/rtl/Ad9249Config.vhd b/devices/AnalogDevices/ad9249/core/Ad9249Config.vhd similarity index 92% rename from devices/AnalogDevices/ad9249/rtl/Ad9249Config.vhd rename to devices/AnalogDevices/ad9249/core/Ad9249Config.vhd index 509441c6c2..671705aff1 100644 --- a/devices/AnalogDevices/ad9249/rtl/Ad9249Config.vhd +++ b/devices/AnalogDevices/ad9249/core/Ad9249Config.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Ad9249Config.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-09-23 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AD9249 Configuration/Status Module ------------------------------------------------------------------------------- @@ -29,10 +27,10 @@ use work.AxiLitePkg.all; entity Ad9249Config is generic ( - TPD_G : time := 1 ns; - NUM_CHIPS_G : positive := 1; - SCLK_PERIOD_G : real := 1.0e-6; - AXIL_CLK_PERIOD_G : real := 8.0e-9); + TPD_G : time := 1 ns; + NUM_CHIPS_G : positive := 1; + SCLK_PERIOD_G : real := 1.0e-6; + AXIL_CLK_PERIOD_G : real := 8.0e-9); port ( axilClk : in sl; axilRst : in sl; @@ -117,8 +115,8 @@ begin -- Any other address is forwarded to the chip via SPI if (axilEp.axiStatus.writeEnable = '1' and axilWriteMaster.awaddr(PWDN_ADDR_BIT_C) = '0') then - v.wrData(23) := '0'; -- Write bit - v.wrData(22 downto 21) := "00"; -- Number of bytes (1) + v.wrData(23) := '0'; -- Write bit + v.wrData(22 downto 21) := "00"; -- Number of bytes (1) v.wrData(20 downto 17) := "0000"; -- Unused address bits v.wrData(16 downto 8) := axilWriteMaster.awaddr(10 downto 2); -- Address v.wrData(7 downto 0) := axilWriteMaster.wdata(7 downto 0); -- Data @@ -130,7 +128,7 @@ begin if (axilEp.axiStatus.readEnable = '1' and axilReadMaster.araddr(PWDN_ADDR_BIT_C) = '0') then v.wrData(23) := '1'; -- read bit v.wrData(22 downto 21) := "00"; -- Number of bytes (1) - v.wrData(20 downto 17) := "0000"; -- Unused address bits + v.wrData(20 downto 17) := "0000"; -- Unused address bits v.wrData(16 downto 8) := axilReadMaster.araddr(10 downto 2); -- Address v.wrData(7 downto 0) := (others => '1'); -- Make bus float to Z so slave can -- drive during data segment @@ -139,7 +137,7 @@ begin v.state := WAIT_CYCLE_S; end if; - axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C, v.wrEn); + axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C, v.wrEn); when WAIT_CYCLE_S => -- Wait 1 cycle for rdEn to drop @@ -159,7 +157,7 @@ begin axilEp.axiReadSlave.rdata := (others => '0'); axilEp.axiReadSlave.rdata(7 downto 0) := rdData(7 downto 0); axiSlaveReadResponse(axilEp.axiReadSlave); - v.axilReadSlave := axilEp.axiReadSlave; + v.axilReadSlave := axilEp.axiReadSlave; end if; end if; @@ -221,7 +219,7 @@ begin adcSclk <= coreSclk; -- Allow input when doing a read and in the data segment of the shift operation - sdioDir <= '1' when shiftCount >= 16 and r.wrData(23)='1' else '0'; + sdioDir <= '1' when shiftCount >= 16 and r.wrData(23) = '1' else '0'; SDIO_IOBUFT : IOBUF port map ( I => coreSDout, diff --git a/devices/AnalogDevices/ad9249/rtl/Ad9249Pkg.vhd b/devices/AnalogDevices/ad9249/core/Ad9249Pkg.vhd similarity index 97% rename from devices/AnalogDevices/ad9249/rtl/Ad9249Pkg.vhd rename to devices/AnalogDevices/ad9249/core/Ad9249Pkg.vhd index a39885cb65..5044b6eac7 100644 --- a/devices/AnalogDevices/ad9249/rtl/Ad9249Pkg.vhd +++ b/devices/AnalogDevices/ad9249/core/Ad9249Pkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Ad9249Pkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-05-26 --- Last update: 2016-06-06 ------------------------------------------------------------------------------- -- Description: AD9249 Package File ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad9249/rtl/StreamPatternTester.vhd b/devices/AnalogDevices/ad9249/core/StreamPatternTester.vhd similarity index 98% rename from devices/AnalogDevices/ad9249/rtl/StreamPatternTester.vhd rename to devices/AnalogDevices/ad9249/core/StreamPatternTester.vhd index 1c71792f8a..ffe5c9a265 100644 --- a/devices/AnalogDevices/ad9249/rtl/StreamPatternTester.vhd +++ b/devices/AnalogDevices/ad9249/core/StreamPatternTester.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : StreamPatternTester.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 05/27/2016 --- Last update: 05/27/2016 ------------------------------------------------------------------------------- -- Description: Test which compares the data stream to selected pattern -- Designed for the automated delay alignment of the fast LVDS lines @@ -29,7 +27,7 @@ use work.AxiStreamPkg.all; entity StreamPatternTester is generic ( TPD_G : time := 1 ns; - NUM_CHANNELS_G : integer range 1 to 31 := 8 + NUM_CHANNELS_G : integer range 1 to 128 := 8 ); port ( -- Master system clock diff --git a/devices/AnalogDevices/ad9249/ruckus.tcl b/devices/AnalogDevices/ad9249/ruckus.tcl index 56ee54a49a..34bf4dc676 100644 --- a/devices/AnalogDevices/ad9249/ruckus.tcl +++ b/devices/AnalogDevices/ad9249/ruckus.tcl @@ -2,5 +2,22 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Load Source Code -loadSource -dir "$::DIR_PATH/rtl/" -loadSource -sim_only -dir "$::DIR_PATH/sim/" +loadSource -dir "$::DIR_PATH/core" +loadSource -sim_only -dir "$::DIR_PATH/tb" + +# Get the family type +set family [getFpgaFamily] + +if { ${family} eq {artix7} || + ${family} eq {kintex7} || + ${family} eq {virtex7} || + ${family} eq {zynq} } { + loadRuckusTcl "$::DIR_PATH/7Series" +} + +if { ${family} eq {kintexu} || + ${family} eq {kintexuplus} || + ${family} eq {virtexuplus} || + ${family} eq {zynquplus} } { + loadRuckusTcl "$::DIR_PATH/UltraScale" +} \ No newline at end of file diff --git a/devices/AnalogDevices/ad9249/sim/Ad9249.vhd b/devices/AnalogDevices/ad9249/tb/Ad9249.vhd similarity index 98% rename from devices/AnalogDevices/ad9249/sim/Ad9249.vhd rename to devices/AnalogDevices/ad9249/tb/Ad9249.vhd index f612d3939b..a77d603f81 100644 --- a/devices/AnalogDevices/ad9249/sim/Ad9249.vhd +++ b/devices/AnalogDevices/ad9249/tb/Ad9249.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Ad9249.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-11-14 --- Last update: 2016-12-06 ------------------------------------------------------------------------------- -- Description: AD9249 Module ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad9249/sim/Ad9249Group.vhd b/devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd similarity index 99% rename from devices/AnalogDevices/ad9249/sim/Ad9249Group.vhd rename to devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd index c64e32fb4c..c97cabb575 100644 --- a/devices/AnalogDevices/ad9249/sim/Ad9249Group.vhd +++ b/devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Ad9249Group.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-11-14 --- Last update: 2016-12-06 ------------------------------------------------------------------------------- -- Description: AD9249 Group Module ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad9249/sim/Ad9249Serializer.vhd b/devices/AnalogDevices/ad9249/tb/Ad9249Serializer.vhd similarity index 98% rename from devices/AnalogDevices/ad9249/sim/Ad9249Serializer.vhd rename to devices/AnalogDevices/ad9249/tb/Ad9249Serializer.vhd index 9d70148b85..8421b12be3 100644 --- a/devices/AnalogDevices/ad9249/sim/Ad9249Serializer.vhd +++ b/devices/AnalogDevices/ad9249/tb/Ad9249Serializer.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Ad9249Serializer.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-02-22 --- Last update: 2016-11-30 ------------------------------------------------------------------------------- -- Description: 14 bit DDR deserializer using 7 series IDELAYE2 and ISERDESE2. ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad9467/rtl/AxiAd9467Core.vhd b/devices/AnalogDevices/ad9467/rtl/AxiAd9467Core.vhd index 785b3612bf..18167fbd65 100644 --- a/devices/AnalogDevices/ad9467/rtl/AxiAd9467Core.vhd +++ b/devices/AnalogDevices/ad9467/rtl/AxiAd9467Core.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAd9467Core.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-09-23 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AXI-Lite interface to AD9467 ADC IC ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad9467/rtl/AxiAd9467Deser.vhd b/devices/AnalogDevices/ad9467/rtl/AxiAd9467Deser.vhd index f21ad7d261..b7b60edfe1 100644 --- a/devices/AnalogDevices/ad9467/rtl/AxiAd9467Deser.vhd +++ b/devices/AnalogDevices/ad9467/rtl/AxiAd9467Deser.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAd9467Deser.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-09-23 --- Last update: 2014-09-24 ------------------------------------------------------------------------------- -- Description: Wrapper for AxiAd9467DeserBit modules ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad9467/rtl/AxiAd9467DeserBit.vhd b/devices/AnalogDevices/ad9467/rtl/AxiAd9467DeserBit.vhd index 625ddbf38b..e41424ae84 100644 --- a/devices/AnalogDevices/ad9467/rtl/AxiAd9467DeserBit.vhd +++ b/devices/AnalogDevices/ad9467/rtl/AxiAd9467DeserBit.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAd9467DeserBit.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-09-23 --- Last update: 2014-09-24 ------------------------------------------------------------------------------- -- Description: AD9467 Deserializer Bit Module ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad9467/rtl/AxiAd9467Mon.vhd b/devices/AnalogDevices/ad9467/rtl/AxiAd9467Mon.vhd index c49689cbfe..de7bd8f369 100644 --- a/devices/AnalogDevices/ad9467/rtl/AxiAd9467Mon.vhd +++ b/devices/AnalogDevices/ad9467/rtl/AxiAd9467Mon.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAd9467Mon.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-09-23 --- Last update: 2014-09-24 ------------------------------------------------------------------------------- -- Description: AD9467 Monitor Module ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad9467/rtl/AxiAd9467Pkg.vhd b/devices/AnalogDevices/ad9467/rtl/AxiAd9467Pkg.vhd index 6deb6162bc..da3ac630c9 100644 --- a/devices/AnalogDevices/ad9467/rtl/AxiAd9467Pkg.vhd +++ b/devices/AnalogDevices/ad9467/rtl/AxiAd9467Pkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAd9467Pkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-09-23 --- Last update: 2014-09-24 -------------------------------------------------------------------------------------------------------------------------------------------------------------- -- Description: AD9467 Package File ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad9467/rtl/AxiAd9467Pll.vhd b/devices/AnalogDevices/ad9467/rtl/AxiAd9467Pll.vhd index 6f1058cf12..066e1ef3ee 100644 --- a/devices/AnalogDevices/ad9467/rtl/AxiAd9467Pll.vhd +++ b/devices/AnalogDevices/ad9467/rtl/AxiAd9467Pll.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAd9467Core.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-09-23 --- Last update: 2014-09-24 ------------------------------------------------------------------------------- -- Description: AD9467 PLL Module ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad9467/rtl/AxiAd9467Reg.vhd b/devices/AnalogDevices/ad9467/rtl/AxiAd9467Reg.vhd index 9512b9bad4..b902f50597 100644 --- a/devices/AnalogDevices/ad9467/rtl/AxiAd9467Reg.vhd +++ b/devices/AnalogDevices/ad9467/rtl/AxiAd9467Reg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAd9467Reg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-09-23 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AD9467 AXI-Lite Register Access Module ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/ad9467/rtl/AxiAd9467Spi.vhd b/devices/AnalogDevices/ad9467/rtl/AxiAd9467Spi.vhd index 750e928f7b..e8980cc917 100644 --- a/devices/AnalogDevices/ad9467/rtl/AxiAd9467Spi.vhd +++ b/devices/AnalogDevices/ad9467/rtl/AxiAd9467Spi.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAd9467Spi.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-05-23 --- Last update: 2014-09-24 ------------------------------------------------------------------------------- -- Description: AD9467 SPI Interface Module ------------------------------------------------------------------------------- diff --git a/devices/AnalogDevices/general/rtl/AdiConfigSlave.vhd b/devices/AnalogDevices/general/rtl/AdiConfigSlave.vhd index ef1647af59..8cffe43aa7 100644 --- a/devices/AnalogDevices/general/rtl/AdiConfigSlave.vhd +++ b/devices/AnalogDevices/general/rtl/AdiConfigSlave.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AdiConfigSlave.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-01-14 --- Last update: 2016-11-14 ------------------------------------------------------------------------------- -- Description: An implementation of the common SPI configuration interface -- use by many AnalogDevices chips. diff --git a/devices/Linear/lct2270/rtl/AxiLtc2270Core.vhd b/devices/Linear/lct2270/rtl/AxiLtc2270Core.vhd index 7b1c92e6c5..07fedbfb5a 100644 --- a/devices/Linear/lct2270/rtl/AxiLtc2270Core.vhd +++ b/devices/Linear/lct2270/rtl/AxiLtc2270Core.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLtc2270Core.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-21 --- Last update: 2018-03-07 ------------------------------------------------------------------------------- -- Description: AXI-Lite interface to LTC2270 ADC IC ------------------------------------------------------------------------------- diff --git a/devices/Linear/lct2270/rtl/AxiLtc2270Deser.vhd b/devices/Linear/lct2270/rtl/AxiLtc2270Deser.vhd index 3b681e978e..63f0062232 100644 --- a/devices/Linear/lct2270/rtl/AxiLtc2270Deser.vhd +++ b/devices/Linear/lct2270/rtl/AxiLtc2270Deser.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLtc2270Deser.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-21 --- Last update: 2015-01-20 ------------------------------------------------------------------------------- -- Description: ADC DDR Deserializer ------------------------------------------------------------------------------- diff --git a/devices/Linear/lct2270/rtl/AxiLtc2270DeserBit.vhd b/devices/Linear/lct2270/rtl/AxiLtc2270DeserBit.vhd index 88fbcd9fdd..f80551ff2f 100644 --- a/devices/Linear/lct2270/rtl/AxiLtc2270DeserBit.vhd +++ b/devices/Linear/lct2270/rtl/AxiLtc2270DeserBit.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLtc2270DeserBit.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-21 --- Last update: 2014-04-21 ------------------------------------------------------------------------------- -- Description: ADC DDR Deserializer ------------------------------------------------------------------------------- diff --git a/devices/Linear/lct2270/rtl/AxiLtc2270Pkg.vhd b/devices/Linear/lct2270/rtl/AxiLtc2270Pkg.vhd index 835fe63986..7063ec4b41 100644 --- a/devices/Linear/lct2270/rtl/AxiLtc2270Pkg.vhd +++ b/devices/Linear/lct2270/rtl/AxiLtc2270Pkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLtc2270Pkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-21 --- Last update: 2017-05-02 ------------------------------------------------------------------------------- -- Description: AxiLtc2270 Package File ------------------------------------------------------------------------------- diff --git a/devices/Linear/lct2270/rtl/AxiLtc2270Reg.vhd b/devices/Linear/lct2270/rtl/AxiLtc2270Reg.vhd index e4c284bdbf..adbd069497 100644 --- a/devices/Linear/lct2270/rtl/AxiLtc2270Reg.vhd +++ b/devices/Linear/lct2270/rtl/AxiLtc2270Reg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLtc2270Reg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-21 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AXI-Lite Register Access Module ------------------------------------------------------------------------------- diff --git a/devices/Microchip/sy56040/rtl/AxiSy56040Core.vhd b/devices/Microchip/sy56040/rtl/AxiSy56040Core.vhd index ddea889011..923b96fcc9 100644 --- a/devices/Microchip/sy56040/rtl/AxiSy56040Core.vhd +++ b/devices/Microchip/sy56040/rtl/AxiSy56040Core.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiSy56040Core.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-06-12 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AXI-Lite interface to Clock Crossbar ------------------------------------------------------------------------------- diff --git a/devices/Microchip/sy56040/rtl/AxiSy56040Pkg.vhd b/devices/Microchip/sy56040/rtl/AxiSy56040Pkg.vhd index ef185f42eb..f09b549aa9 100644 --- a/devices/Microchip/sy56040/rtl/AxiSy56040Pkg.vhd +++ b/devices/Microchip/sy56040/rtl/AxiSy56040Pkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiSy56040Pkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-06-12 --- Last update: 2015-06-12 ------------------------------------------------------------------------------- -- Description: AxiSy56040 Package File ------------------------------------------------------------------------------- diff --git a/devices/Microchip/sy56040/rtl/AxiSy56040Reg.vhd b/devices/Microchip/sy56040/rtl/AxiSy56040Reg.vhd index 61d90a3dcf..67c3038b95 100644 --- a/devices/Microchip/sy56040/rtl/AxiSy56040Reg.vhd +++ b/devices/Microchip/sy56040/rtl/AxiSy56040Reg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiSy56040Reg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-06-12 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: This controller is designed around the Micrel SY56040AR. ------------------------------------------------------------------------------- diff --git a/devices/Micron/mt28ew/rtl/AxiMicronMt28ewCore.vhd b/devices/Micron/mt28ew/rtl/AxiMicronMt28ewCore.vhd index e9cf7bfc37..dcbbca9f28 100644 --- a/devices/Micron/mt28ew/rtl/AxiMicronMt28ewCore.vhd +++ b/devices/Micron/mt28ew/rtl/AxiMicronMt28ewCore.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiMicronMt28ewCore.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2018-04-10 --- Last update: 2018-06-22 ------------------------------------------------------------------------------- -- Description: AXI-Lite interface to Micron MT28EW FLASH IC ------------------------------------------------------------------------------- diff --git a/devices/Micron/mt28ew/rtl/AxiMicronMt28ewPkg.vhd b/devices/Micron/mt28ew/rtl/AxiMicronMt28ewPkg.vhd index 5411ca4cc1..601b7f2703 100644 --- a/devices/Micron/mt28ew/rtl/AxiMicronMt28ewPkg.vhd +++ b/devices/Micron/mt28ew/rtl/AxiMicronMt28ewPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiMicronMt28ewPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2018-04-10 --- Last update: 2018-04-10 ------------------------------------------------------------------------------- -- Description: AxiMicronMt28ew Package File ------------------------------------------------------------------------------- diff --git a/devices/Micron/mt28ew/rtl/AxiMicronMt28ewReg.vhd b/devices/Micron/mt28ew/rtl/AxiMicronMt28ewReg.vhd index 9675ea3bb6..f4a351a5e4 100644 --- a/devices/Micron/mt28ew/rtl/AxiMicronMt28ewReg.vhd +++ b/devices/Micron/mt28ew/rtl/AxiMicronMt28ewReg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiMicronMt28ewReg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2018-04-10 --- Last update: 2018-06-22 ------------------------------------------------------------------------------- -- Description: This controller is designed around the Micron MT28EW FLASH IC. ------------------------------------------------------------------------------- diff --git a/devices/Micron/n25q/rtl/AxiMicronN25QCore.vhd b/devices/Micron/n25q/rtl/AxiMicronN25QCore.vhd index 1f1a517c5d..9dbd68aed8 100644 --- a/devices/Micron/n25q/rtl/AxiMicronN25QCore.vhd +++ b/devices/Micron/n25q/rtl/AxiMicronN25QCore.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiMicronN25QCore.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-03 --- Last update: 2018-06-22 ------------------------------------------------------------------------------- -- Description: AXI-Lite interface to N25Q FLASH Memory IC ------------------------------------------------------------------------------- diff --git a/devices/Micron/n25q/rtl/AxiMicronN25QReg.vhd b/devices/Micron/n25q/rtl/AxiMicronN25QReg.vhd index c632cd2b6c..24e3d4996c 100644 --- a/devices/Micron/n25q/rtl/AxiMicronN25QReg.vhd +++ b/devices/Micron/n25q/rtl/AxiMicronN25QReg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiMicronN25QReg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-25 --- Last update: 2018-06-22 ------------------------------------------------------------------------------- -- Description: MicronN25Q AXI-Lite Register Access ------------------------------------------------------------------------------- diff --git a/devices/Micron/p30/rtl/AxiMicronP30Core.vhd b/devices/Micron/p30/rtl/AxiMicronP30Core.vhd index 672d256cbf..0bac7d061d 100644 --- a/devices/Micron/p30/rtl/AxiMicronP30Core.vhd +++ b/devices/Micron/p30/rtl/AxiMicronP30Core.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiMicronP30Core.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-06-23 --- Last update: 2018-06-22 ------------------------------------------------------------------------------- -- Description: AXI-Lite interface to FLASH Memory ------------------------------------------------------------------------------- diff --git a/devices/Micron/p30/rtl/AxiMicronP30Pkg.vhd b/devices/Micron/p30/rtl/AxiMicronP30Pkg.vhd index 52ce14bb0c..0f504deffd 100644 --- a/devices/Micron/p30/rtl/AxiMicronP30Pkg.vhd +++ b/devices/Micron/p30/rtl/AxiMicronP30Pkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiMicronP30Pkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-06-23 --- Last update: 2017-03-24 ------------------------------------------------------------------------------- -- Description: AxiMicronP30 Package File ------------------------------------------------------------------------------- diff --git a/devices/Micron/p30/rtl/AxiMicronP30Reg.vhd b/devices/Micron/p30/rtl/AxiMicronP30Reg.vhd index 8e7ba427f6..8fc64bf301 100644 --- a/devices/Micron/p30/rtl/AxiMicronP30Reg.vhd +++ b/devices/Micron/p30/rtl/AxiMicronP30Reg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiMicronP30Reg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-10-21 --- Last update: 2018-06-22 ------------------------------------------------------------------------------- -- Description: This controller is designed around the Micron PC28F FLASH IC. ------------------------------------------------------------------------------- diff --git a/devices/Silabs/ruckus.tcl b/devices/Silabs/ruckus.tcl new file mode 100644 index 0000000000..e2f32e97d4 --- /dev/null +++ b/devices/Silabs/ruckus.tcl @@ -0,0 +1,5 @@ +# Load RUCKUS environment and library +source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl + +# Load ruckus files +loadRuckusTcl "$::DIR_PATH/si5345" diff --git a/devices/Silabs/si5345/rtl/Si5345.vhd b/devices/Silabs/si5345/rtl/Si5345.vhd new file mode 100644 index 0000000000..66052e5099 --- /dev/null +++ b/devices/Silabs/si5345/rtl/Si5345.vhd @@ -0,0 +1,267 @@ +------------------------------------------------------------------------------- +-- File : Si5345.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: SPI Master Wrapper that includes a state machine for SPI paging +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.StdRtlPkg.all; +use work.AxiLitePkg.all; + +entity Si5345 is + generic ( + TPD_G : time := 1 ns; + CLK_PERIOD_G : real := (1.0/156.25E+6); + SPI_SCLK_PERIOD_G : real := (1.0/10.0E+6)); + port ( + -- Clock and Reset + axiClk : in sl; + axiRst : in sl; + -- AXI-Lite Interface + axiReadMaster : in AxiLiteReadMasterType; + axiReadSlave : out AxiLiteReadSlaveType; + axiWriteMaster : in AxiLiteWriteMasterType; + axiWriteSlave : out AxiLiteWriteSlaveType; + -- SPI Interface + coreRst : out sl; + coreSclk : out sl; + coreSDin : in sl; + coreSDout : out sl; + coreCsb : out sl); +end entity Si5345; + +architecture rtl of Si5345 is + + constant DLY_C : natural := 4*integer(SPI_SCLK_PERIOD_G/CLK_PERIOD_G); -- >= 2 SCLK delay between SPI cycles + + type StateType is ( + IDLE_S, + INIT_S, + REQ_S, + ACK_S, + DONE_S); + + type RegType is record + axiRd : sl; + wrEn : sl; + wrData : slv(15 downto 0); + data : slv(7 downto 0); + addr : slv(7 downto 0); + page : slv(7 downto 0); + timer : natural range 0 to DLY_C; + cnt : natural range 0 to 4; + wrArray : Slv16Array(3 downto 0); + axiReadSlave : AxiLiteReadSlaveType; + axiWriteSlave : AxiLiteWriteSlaveType; + state : StateType; + end record RegType; + + constant REG_INIT_C : RegType := ( + axiRd => '0', + wrEn => '0', + wrData => (others => '0'), + data => (others => '0'), + addr => (others => '0'), + page => (others => '0'), + timer => 0, + cnt => 0, + wrArray => (others => (others => '0')), + axiWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, + axiReadSlave => AXI_LITE_READ_SLAVE_INIT_C, + state => IDLE_S); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal freeRunClk : sl; + signal rdEn : sl; + signal rdData : slv(15 downto 0); + + -- attribute dont_touch : string; + -- attribute dont_touch of r : signal is "TRUE"; + -- attribute dont_touch of freeRunClk : signal is "TRUE"; + -- attribute dont_touch of rdEn : signal is "TRUE"; + -- attribute dont_touch of rdData : signal is "TRUE"; + +begin + + comb : process (axiReadMaster, axiRst, axiWriteMaster, r, rdData, rdEn) is + variable v : RegType; + variable axiStatus : AxiLiteStatusType; + begin + -- Latch the current value + v := r; + + -- Flow Control + if (rdEn = '0') then + v.wrEn := '0'; + end if; + + -- Increment the timer + if (r.timer /= DLY_C) then + v.timer := r.timer + 1; + end if; + + -- Get the AXI-Lite status + axiSlaveWaitTxn(axiWriteMaster, axiReadMaster, v.axiWriteSlave, v.axiReadSlave, axiStatus); + + -- State Machine + case r.state is + ---------------------------------------------------------------------- + when IDLE_S => + -- Reset the timer + v.timer := 0; + -- Check if write transaction + if (axiStatus.writeEnable = '1') then + -- Set the flag + v.axiRd := '0'; + -- Save the data/address + v.data := axiWriteMaster.wdata(7 downto 0); + v.addr := axiWriteMaster.awaddr(9 downto 2); + v.page := x"0" & axiWriteMaster.awaddr(13 downto 10); + -- Send the write response + axiSlaveWriteResponse(v.axiWriteSlave); + -- Next State + v.state := INIT_S; + -- Check if read transaction + elsif (axiStatus.readEnable = '1') then + -- Set the flag + v.axiRd := '1'; + -- Save the address + v.addr := axiReadMaster.araddr(9 downto 2); + v.page := x"0" & axiReadMaster.araddr(13 downto 10); + -- Next State + v.state := INIT_S; + end if; + ---------------------------------------------------------------------- + when INIT_S => + ----------------------------------------------------------------- + -- Refer to Si5345, Si5344, Si5342 Rev. D Family Reference Manual + -- In Section 9.2 SPI Interface + ----------------------------------------------------------------- + -- Set the address to page location + v.wrArray(0) := x"00" & x"01"; + -- Write the page location + v.wrArray(1) := x"40" & r.page; + -- Set the address location within the page + v.wrArray(2) := x"00" & r.addr; + -- Check if write transaction + if (r.axiRd = '0') then + -- Write Data + v.wrArray(3) := x"40" & r.data; + else + -- Read Data + v.wrArray(3) := x"80" & x"FF"; + end if; + -- Next State + v.state := REQ_S; + ---------------------------------------------------------------------- + when REQ_S => + -- Check for min. chip select gap + if (r.timer = DLY_C) then + -- Start the transaction + v.wrEn := '1'; + v.wrData := r.wrArray(r.cnt); + --- Next state + v.state := ACK_S; + end if; + ---------------------------------------------------------------------- + when ACK_S => + -- Wait for the transaction to complete + if (rdEn = '1') and (r.wrEn = '0') then + -- Reset the timer + v.timer := 0; + -- Increment the counter + v.cnt := r.cnt + 1; + -- Check for last transaction + if (r.cnt = 3) then + -- Reset the counter + v.cnt := 0; + -- Check if read transaction type + if (r.axiRd = '1') then + -- Latch the read byte + v.axiReadSlave.rdata(7 downto 0) := rdData(7 downto 0); + -- Send the response + axiSlaveReadResponse(v.axiReadSlave); + end if; + --- Next state + v.state := DONE_S; + else + --- Next state + v.state := REQ_S; + end if; + end if; + ---------------------------------------------------------------------- + when DONE_S => + -- Check for min. chip select gap + if (r.timer = DLY_C) then + --- Next state + v.state := IDLE_S; + end if; + ---------------------------------------------------------------------- + end case; + + -- Outputs + axiWriteSlave <= r.axiWriteSlave; + axiReadSlave <= r.axiReadSlave; + coreRst <= axiRst; + if (r.state = IDLE_S) then + freeRunClk <= '0'; + else + freeRunClk <= '1'; + end if; + + -- Reset + if (axiRst = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (axiClk) is + begin + if (rising_edge(axiClk)) then + r <= rin after TPD_G; + end if; + end process seq; + + U_SpiMaster : entity work.SpiMaster + generic map ( + TPD_G => TPD_G, + NUM_CHIPS_G => 1, + DATA_SIZE_G => 16, + CPHA_G => '0', + CPOL_G => '0', + CLK_PERIOD_G => CLK_PERIOD_G, + SPI_SCLK_PERIOD_G => SPI_SCLK_PERIOD_G) + port map ( + clk => axiClk, + sRst => axiRst, + chipSel => "0", + freeRunClk => freeRunClk, + wrEn => r.wrEn, + wrData => r.wrData, + rdEn => rdEn, + rdData => rdData, + spiCsL(0) => coreCsb, + spiSclk => coreSclk, + spiSdi => coreSDout, + spiSdo => coreSDin); + +end architecture rtl; diff --git a/devices/Silabs/si5345/ruckus.tcl b/devices/Silabs/si5345/ruckus.tcl new file mode 100644 index 0000000000..f988a4f0c1 --- /dev/null +++ b/devices/Silabs/si5345/ruckus.tcl @@ -0,0 +1,5 @@ +# Load RUCKUS library +source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl + +# Load Source Code +loadSource -dir "$::DIR_PATH/rtl" diff --git a/devices/Ti/adc32rf45/rtl/adc32rf45.vhd b/devices/Ti/adc32rf45/rtl/adc32rf45.vhd index 2f85ca9831..dc2a094e61 100644 --- a/devices/Ti/adc32rf45/rtl/adc32rf45.vhd +++ b/devices/Ti/adc32rf45/rtl/adc32rf45.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : adc32rf45.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-05-26 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: SPI Master Wrapper that includes a state machine for SPI paging ------------------------------------------------------------------------------- @@ -25,9 +23,9 @@ use work.AxiLitePkg.all; entity adc32rf45 is generic ( - TPD_G : time := 1 ns; - CLK_PERIOD_G : real := (1.0/156.25E+6); - SPI_SCLK_PERIOD_G : real := (1.0/10.0E+6)); + TPD_G : time := 1 ns; + CLK_PERIOD_G : real := (1.0/156.25E+6); + SPI_SCLK_PERIOD_G : real := (1.0/10.0E+6)); port ( -- Clock and Reset axiClk : in sl; @@ -118,26 +116,53 @@ begin case r.state is ---------------------------------------------------------------------- when IDLE_S => - -- Check if write transaction - if (axiStatus.writeEnable = '1') then - -- Set the flag - v.axiRd := '0'; - -- Save the data/address - v.data := axiWriteMaster.wdata(7 downto 0); - v.addr := axiWriteMaster.awaddr(13 downto 2); - v.xferType := axiWriteMaster.awaddr(17 downto 14); - -- Next State - v.state := INIT_S; - -- Check if read transaction - elsif (axiStatus.readEnable = '1') then - -- Set the flag - v.axiRd := '1'; - -- Save the data/address - v.data := x"FF"; - v.addr := axiReadMaster.araddr(13 downto 2); - v.xferType := axiReadMaster.araddr(17 downto 14); - -- Next State - v.state := INIT_S; + -- Check for basic access + if (axiReadMaster.araddr(18) = '0') then + -- Check if write transaction + if (axiStatus.writeEnable = '1') then + -- Set the flag + v.axiRd := '0'; + -- Save the data/address + v.data := axiWriteMaster.wdata(7 downto 0); + v.addr := axiWriteMaster.awaddr(13 downto 2); + v.xferType := axiWriteMaster.awaddr(17 downto 14); + -- Next State + v.state := INIT_S; + -- Check if read transaction + elsif (axiStatus.readEnable = '1') then + -- Set the flag + v.axiRd := '1'; + -- Save the data/address + v.data := x"FF"; + v.addr := axiReadMaster.araddr(13 downto 2); + v.xferType := axiReadMaster.araddr(17 downto 14); + -- Next State + v.state := INIT_S; + end if; + else -- Check advance user access + -- Check if write transaction + if (axiStatus.writeEnable = '1') then + -- Set the flag + v.axiRd := '0'; + -- Save the data/address + v.size := 1; + v.wrArray(0) := ('0' & axiWriteMaster.awaddr(17 downto 2) & axiWriteMaster.wdata(7 downto 0)); + -- Reset the counter + v.cnt := 0; + -- Next State + v.state := REQ_S; + -- Check if read transaction + elsif (axiStatus.readEnable = '1') then + -- Set the flag + v.axiRd := '1'; + -- Save the data/address + v.size := 1; + v.wrArray(0) := ('1' & axiReadMaster.araddr(17 downto 2) & x"FF"); + -- Reset the counter + v.cnt := 0; + -- Next State + v.state := REQ_S; + end if; end if; ---------------------------------------------------------------------- when INIT_S => diff --git a/devices/Ti/ads42lb69/rtl/AxiAds42lb69Core.vhd b/devices/Ti/ads42lb69/rtl/AxiAds42lb69Core.vhd index 6869472c59..f11a796592 100644 --- a/devices/Ti/ads42lb69/rtl/AxiAds42lb69Core.vhd +++ b/devices/Ti/ads42lb69/rtl/AxiAds42lb69Core.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAds42lb69Core.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-20 --- Last update: 2018-04-10 ------------------------------------------------------------------------------- -- Description: AXI-Lite interface to ADS42LB69 ADC IC ------------------------------------------------------------------------------- diff --git a/devices/Ti/ads42lb69/rtl/AxiAds42lb69Deser.vhd b/devices/Ti/ads42lb69/rtl/AxiAds42lb69Deser.vhd index 36ae8585b7..9dc99ae3b1 100644 --- a/devices/Ti/ads42lb69/rtl/AxiAds42lb69Deser.vhd +++ b/devices/Ti/ads42lb69/rtl/AxiAds42lb69Deser.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAds42lb69Deser.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-20 --- Last update: 2015-05-19 ------------------------------------------------------------------------------- -- Description: ADC DDR Deserializer ------------------------------------------------------------------------------- diff --git a/devices/Ti/ads42lb69/rtl/AxiAds42lb69DeserBit.vhd b/devices/Ti/ads42lb69/rtl/AxiAds42lb69DeserBit.vhd index e4ccf1bf56..c772f065fe 100644 --- a/devices/Ti/ads42lb69/rtl/AxiAds42lb69DeserBit.vhd +++ b/devices/Ti/ads42lb69/rtl/AxiAds42lb69DeserBit.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAds42lb69DeserBit.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-20 --- Last update: 2015-03-23 ------------------------------------------------------------------------------- -- Description: ADC DDR Deserializer ------------------------------------------------------------------------------- diff --git a/devices/Ti/ads42lb69/rtl/AxiAds42lb69Pkg.vhd b/devices/Ti/ads42lb69/rtl/AxiAds42lb69Pkg.vhd index e6c0048032..2ca040ae2f 100644 --- a/devices/Ti/ads42lb69/rtl/AxiAds42lb69Pkg.vhd +++ b/devices/Ti/ads42lb69/rtl/AxiAds42lb69Pkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAds42lb69Pkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-20 --- Last update: 2015-03-23 ------------------------------------------------------------------------------- -- Description: AxiAds42lb69 Package File ------------------------------------------------------------------------------- diff --git a/devices/Ti/ads42lb69/rtl/AxiAds42lb69Pll.vhd b/devices/Ti/ads42lb69/rtl/AxiAds42lb69Pll.vhd index 2ec5efd7b2..41096a95ef 100644 --- a/devices/Ti/ads42lb69/rtl/AxiAds42lb69Pll.vhd +++ b/devices/Ti/ads42lb69/rtl/AxiAds42lb69Pll.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAds42lb69Pll.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-20 --- Last update: 2016-09-20 ------------------------------------------------------------------------------- -- Description: PLL Module ------------------------------------------------------------------------------- diff --git a/devices/Ti/ads42lb69/rtl/AxiAds42lb69Reg.vhd b/devices/Ti/ads42lb69/rtl/AxiAds42lb69Reg.vhd index 303a7ee9b7..bf3baef307 100644 --- a/devices/Ti/ads42lb69/rtl/AxiAds42lb69Reg.vhd +++ b/devices/Ti/ads42lb69/rtl/AxiAds42lb69Reg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiAds42lb69Reg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-20 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AXI-Lite Register Access ------------------------------------------------------------------------------- diff --git a/devices/Ti/ads54j60/rtl/ads54j60.vhd b/devices/Ti/ads54j60/rtl/ads54j60.vhd index 402c4e768a..10f03292dd 100644 --- a/devices/Ti/ads54j60/rtl/ads54j60.vhd +++ b/devices/Ti/ads54j60/rtl/ads54j60.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : ads54j60.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-10-09 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: SPI Master Wrapper that includes a state machine for SPI paging ------------------------------------------------------------------------------- diff --git a/devices/Ti/dac7654/rtl/AxiDac7654Core.vhd b/devices/Ti/dac7654/rtl/AxiDac7654Core.vhd index 244b50f2f8..dc0daa963d 100644 --- a/devices/Ti/dac7654/rtl/AxiDac7654Core.vhd +++ b/devices/Ti/dac7654/rtl/AxiDac7654Core.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiDac7654Core.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-09-23 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AXI-Lite interface to DAC7654 DAC IC ------------------------------------------------------------------------------- diff --git a/devices/Ti/dac7654/rtl/AxiDac7654Pkg.vhd b/devices/Ti/dac7654/rtl/AxiDac7654Pkg.vhd index 51b0377e39..fc4fa9e4a7 100644 --- a/devices/Ti/dac7654/rtl/AxiDac7654Pkg.vhd +++ b/devices/Ti/dac7654/rtl/AxiDac7654Pkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiDac7654Pkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-20 --- Last update: 2015-03-23 ------------------------------------------------------------------------------- -- Description: AxiDac7654 Package File ------------------------------------------------------------------------------- diff --git a/devices/Ti/dac7654/rtl/AxiDac7654Reg.vhd b/devices/Ti/dac7654/rtl/AxiDac7654Reg.vhd index c1c916e84d..e44abef0b6 100644 --- a/devices/Ti/dac7654/rtl/AxiDac7654Reg.vhd +++ b/devices/Ti/dac7654/rtl/AxiDac7654Reg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiDac7654Reg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-09-24 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AXI-Lite Register Access Module ------------------------------------------------------------------------------- diff --git a/devices/Ti/dac7654/rtl/AxiDac7654Spi.vhd b/devices/Ti/dac7654/rtl/AxiDac7654Spi.vhd index c4cad0c3f0..f092d16aad 100644 --- a/devices/Ti/dac7654/rtl/AxiDac7654Spi.vhd +++ b/devices/Ti/dac7654/rtl/AxiDac7654Spi.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiDac7654Spi.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-05-22 --- Last update: 2016-09-20 ------------------------------------------------------------------------------- -- Description: SPI Interface Module ------------------------------------------------------------------------------- diff --git a/devices/Xilinx/xcf128/rtl/AxiXcf128Core.vhd b/devices/Xilinx/xcf128/rtl/AxiXcf128Core.vhd index 84c1d4b118..6521a199ce 100644 --- a/devices/Xilinx/xcf128/rtl/AxiXcf128Core.vhd +++ b/devices/Xilinx/xcf128/rtl/AxiXcf128Core.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiXcf128Core.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-24 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AXI-Lite interface to XCF128 FLASH IC ------------------------------------------------------------------------------- diff --git a/devices/Xilinx/xcf128/rtl/AxiXcf128Pkg.vhd b/devices/Xilinx/xcf128/rtl/AxiXcf128Pkg.vhd index 35c15f70e2..b68d8501bc 100644 --- a/devices/Xilinx/xcf128/rtl/AxiXcf128Pkg.vhd +++ b/devices/Xilinx/xcf128/rtl/AxiXcf128Pkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiXcf128Pkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-18 --- Last update: 2015-01-13 ------------------------------------------------------------------------------- -- Description: AxiXcf128 Package File ------------------------------------------------------------------------------- diff --git a/devices/Xilinx/xcf128/rtl/AxiXcf128Reg.vhd b/devices/Xilinx/xcf128/rtl/AxiXcf128Reg.vhd index f8a76c208f..908b9b7ad2 100644 --- a/devices/Xilinx/xcf128/rtl/AxiXcf128Reg.vhd +++ b/devices/Xilinx/xcf128/rtl/AxiXcf128Reg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiXcf128Reg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-18 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AXI-Lite Register Access ------------------------------------------------------------------------------- diff --git a/devices/ruckus.tcl b/devices/ruckus.tcl index 31da9571f5..cad45d19f4 100644 --- a/devices/ruckus.tcl +++ b/devices/ruckus.tcl @@ -6,6 +6,7 @@ loadRuckusTcl "$::DIR_PATH/AnalogDevices" loadRuckusTcl "$::DIR_PATH/Linear" loadRuckusTcl "$::DIR_PATH/Microchip" loadRuckusTcl "$::DIR_PATH/Micron" +loadRuckusTcl "$::DIR_PATH/Silabs" loadRuckusTcl "$::DIR_PATH/Ti" loadRuckusTcl "$::DIR_PATH/transceivers" loadRuckusTcl "$::DIR_PATH/Xilinx" diff --git a/devices/transceivers/rtl/Sff8472.vhd b/devices/transceivers/rtl/Sff8472.vhd index f3d5828905..71a7e05e15 100644 --- a/devices/transceivers/rtl/Sff8472.vhd +++ b/devices/transceivers/rtl/Sff8472.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Sff8472.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2018-05-07 --- Last update: 2018-05-07 ------------------------------------------------------------------------------- -- Description: Optical Module SFF-8472 Wrapper (I2C for SFP, QSFP, etc) ------------------------------------------------------------------------------- diff --git a/dsp/core/DspPkg.vhd b/dsp/core/DspPkg.vhd index fa610ce0f1..36e9171257 100644 --- a/dsp/core/DspPkg.vhd +++ b/dsp/core/DspPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-24 --- Last update: 2017-09-21 ------------------------------------------------------------------------------- -- Description: DSP Package File ------------------------------------------------------------------------------- diff --git a/dsp/fixed/DspAddSub.vhd b/dsp/fixed/DspAddSub.vhd index 3261856490..fe3c2a0e8a 100644 --- a/dsp/fixed/DspAddSub.vhd +++ b/dsp/fixed/DspAddSub.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspAddSub.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-12 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: Generalized DSP inferred DSP inferred add/sub -- Equation: p = a +/- b diff --git a/dsp/fixed/DspComparator.vhd b/dsp/fixed/DspComparator.vhd index f2debebe59..48c8a2526f 100644 --- a/dsp/fixed/DspComparator.vhd +++ b/dsp/fixed/DspComparator.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspComparator.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-07 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: Generalized DSP inferred comparator ------------------------------------------------------------------------------- diff --git a/dsp/fixed/DspPreSubMult.vhd b/dsp/fixed/DspPreSubMult.vhd index 1f42097254..91369cc7b1 100644 --- a/dsp/fixed/DspPreSubMult.vhd +++ b/dsp/fixed/DspPreSubMult.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspPreSubMult.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-08 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: Generalized DSP inferred multiplier with pre-adder -- configured as subtractor (based on UG901) diff --git a/dsp/fixed/DspSquareDiffMult.vhd b/dsp/fixed/DspSquareDiffMult.vhd index d23cba481e..46d5d5f9cd 100644 --- a/dsp/fixed/DspSquareDiffMult.vhd +++ b/dsp/fixed/DspSquareDiffMult.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspSquareDiffMult.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-08 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: Generalized DSP inferred Squarer with pre-adder -- configured as subtractor (based on UG901) diff --git a/dsp/float/DspFp32Accum.vhd b/dsp/float/DspFp32Accum.vhd index b67e5c0bb8..39794bd24d 100644 --- a/dsp/float/DspFp32Accum.vhd +++ b/dsp/float/DspFp32Accum.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspFp32Accum.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-12 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: 32-bit Floating Point DSP inferred accumulator -- Equation: p = sum(+/-a[i]) diff --git a/dsp/float/DspFp32AddSub.vhd b/dsp/float/DspFp32AddSub.vhd index 9a57b18630..8327101263 100644 --- a/dsp/float/DspFp32AddSub.vhd +++ b/dsp/float/DspFp32AddSub.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspFp32AddSub.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-30 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: 32-bit Floating Point DSP inferred add/sub -- Equation: p = a +/- b diff --git a/dsp/float/DspFp32Max.vhd b/dsp/float/DspFp32Max.vhd index 2ab3118cc4..5164ed457d 100644 --- a/dsp/float/DspFp32Max.vhd +++ b/dsp/float/DspFp32Max.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspFp32Max.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-18 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: 32-bit Floating Point DSP inferred maximum module -- Equation: p = max(a[i]) diff --git a/dsp/float/DspFp32Min.vhd b/dsp/float/DspFp32Min.vhd index cae12d8039..19371be078 100644 --- a/dsp/float/DspFp32Min.vhd +++ b/dsp/float/DspFp32Min.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspFp32Min.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-18 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: 32-bit Floating Point DSP inferred minimum module -- Equation: p = min(a[i]) diff --git a/dsp/float/DspFp32Mult.vhd b/dsp/float/DspFp32Mult.vhd index 665364d98e..fe1ff3e2a0 100644 --- a/dsp/float/DspFp32Mult.vhd +++ b/dsp/float/DspFp32Mult.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspFp32Mult.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-12 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: 32-bit Floating Point DSP inferred multiplier -- Equation: p = a x b diff --git a/dsp/float/DspFp32PreMultAccum.vhd b/dsp/float/DspFp32PreMultAccum.vhd index 346980aff3..8a59103abf 100644 --- a/dsp/float/DspFp32PreMultAccum.vhd +++ b/dsp/float/DspFp32PreMultAccum.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspFp32PreMultAccum.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-12 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: 32-bit Floating Point DSP inferred accumulator with pre-multiplier -- Equation: p = sum(+/-(a x b)[i]) diff --git a/dsp/float/DspFp32Rectifier.vhd b/dsp/float/DspFp32Rectifier.vhd index 661a92ebea..8a3b0e86c8 100644 --- a/dsp/float/DspFp32Rectifier.vhd +++ b/dsp/float/DspFp32Rectifier.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspFp32Rectifier.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-18 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: 32-bit Floating Point DSP inferred rectifier module -- Equation: p = a when( a > 0) else 0 diff --git a/dsp/logic/DspXor.vhd b/dsp/logic/DspXor.vhd index 64466ccd57..3405292ba0 100644 --- a/dsp/logic/DspXor.vhd +++ b/dsp/logic/DspXor.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspXor.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-19 --- Last update: 2017-09-25 ------------------------------------------------------------------------------- -- Description: Generalized DSP inferred XOR, which can be used to help with -- performance when implementing FEC and CRC algorithms diff --git a/dsp/tb/DspAddSubTb.vhd b/dsp/tb/DspAddSubTb.vhd index 583b7c5911..0b5134cca5 100644 --- a/dsp/tb/DspAddSubTb.vhd +++ b/dsp/tb/DspAddSubTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspAddSubTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-07 --- Last update: 2017-09-13 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for the DspAddSub module ------------------------------------------------------------------------------- diff --git a/dsp/tb/DspComparatorTb.vhd b/dsp/tb/DspComparatorTb.vhd index 33bada0ad8..3aa2402eb5 100644 --- a/dsp/tb/DspComparatorTb.vhd +++ b/dsp/tb/DspComparatorTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspComparatorTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-07 --- Last update: 2017-09-07 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for the DspComparator module ------------------------------------------------------------------------------- diff --git a/dsp/tb/DspFp32AddSubTb.vhd b/dsp/tb/DspFp32AddSubTb.vhd index 3855d5d2be..18e587e5b1 100644 --- a/dsp/tb/DspFp32AddSubTb.vhd +++ b/dsp/tb/DspFp32AddSubTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspFp32AddSubTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-07 --- Last update: 2017-09-30 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for the DspAddSub module ------------------------------------------------------------------------------- diff --git a/dsp/tb/DspFp32PreMultAccumTb.vhd b/dsp/tb/DspFp32PreMultAccumTb.vhd index 9c070934e3..acadfe25a0 100644 --- a/dsp/tb/DspFp32PreMultAccumTb.vhd +++ b/dsp/tb/DspFp32PreMultAccumTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DspFp32PreMultAccumTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-30 --- Last update: 2017-09-30 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for the DspFp32PreMultAccum module ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthCrc32Parallel.vhd b/ethernet/EthMacCore/rtl/EthCrc32Parallel.vhd index eec935e25d..fb0acd816d 100644 --- a/ethernet/EthMacCore/rtl/EthCrc32Parallel.vhd +++ b/ethernet/EthMacCore/rtl/EthCrc32Parallel.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthCrc32Parallel.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-05-01 --- Last update: 2017-09-26 ------------------------------------------------------------------------------- -- Description: Ethernet CRC32 Ethernet/AAL5 Module -- Polynomial: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1 diff --git a/ethernet/EthMacCore/rtl/EthCrc32Pkg.vhd b/ethernet/EthMacCore/rtl/EthCrc32Pkg.vhd index 9c8403017e..25b40d0399 100644 --- a/ethernet/EthMacCore/rtl/EthCrc32Pkg.vhd +++ b/ethernet/EthMacCore/rtl/EthCrc32Pkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthCrc32Pkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-09-25 --- Last update: 2017-09-25 ------------------------------------------------------------------------------- -- Description: Ethernet CRC32 Ethernet/AAL5 Package File -- Polynomial: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1 diff --git a/ethernet/EthMacCore/rtl/EthMacFlowCtrl.vhd b/ethernet/EthMacCore/rtl/EthMacFlowCtrl.vhd index 385e5430d7..64df6dbe83 100644 --- a/ethernet/EthMacCore/rtl/EthMacFlowCtrl.vhd +++ b/ethernet/EthMacCore/rtl/EthMacFlowCtrl.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacFlowCtrl.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-09-21 --- Last update: 2016-10-20 ------------------------------------------------------------------------------- -- Description: ETH MAC Flow Control Module ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacPkg.vhd b/ethernet/EthMacCore/rtl/EthMacPkg.vhd index 2fd325c6f6..1c2d3d1bf8 100644 --- a/ethernet/EthMacCore/rtl/EthMacPkg.vhd +++ b/ethernet/EthMacCore/rtl/EthMacPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-21 --- Last update: 2016-10-20 ------------------------------------------------------------------------------- -- Description: Ethernet MAC Package File ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacRx.vhd b/ethernet/EthMacCore/rtl/EthMacRx.vhd index e1e8358dde..28c4205e14 100644 --- a/ethernet/EthMacCore/rtl/EthMacRx.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacRx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-22 --- Last update: 2016-10-20 ------------------------------------------------------------------------------- -- Description: Ethernet MAC RX Wrapper ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacRxBypass.vhd b/ethernet/EthMacCore/rtl/EthMacRxBypass.vhd index 586c496a24..182efdcb7e 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxBypass.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxBypass.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacRxBypass.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-01-04 --- Last update: 2016-09-14 ------------------------------------------------------------------------------- -- Description: RX bypass frame extractor. ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacRxCsum.vhd b/ethernet/EthMacCore/rtl/EthMacRxCsum.vhd index 94645c7477..d21b2a3817 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxCsum.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxCsum.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacRxCsum.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-09-08 --- Last update: 2018-01-31 ------------------------------------------------------------------------------- -- Description: RX Checksum Hardware Offloading Engine -- https://docs.google.com/spreadsheets/d/1_1M1keasfq8RLmRYHkO0IlRhMq5YZTgJ7OGrWvkib8I/edit?usp=sharing @@ -292,8 +290,8 @@ begin -- Move the data v.mAxisMaster := sAxisMaster; -- Fill in the TCP/UDP checksum - v.tKeep := sAxisMaster.tKeep; - v.tData := sAxisMaster.tData; + v.tKeep := sAxisMaster.tKeep(15 downto 0); + v.tData := sAxisMaster.tData(127 downto 0); -- Check if NON-VLAN if (VLAN_G = false) then -- Fill in the IPv4 header checksum @@ -311,7 +309,7 @@ begin v.protLen(0)(7 downto 0) := sAxisMaster.tData(63 downto 56); end if; -- Track the number of bytes (include IPv4 header offset from previous state) - v.byteCnt := getTKeep(sAxisMaster.tKeep) + 18; + v.byteCnt := getTKeep(sAxisMaster.tKeep,EMAC_AXIS_CONFIG_C) + 18; else -- Fill in the IPv4 header checksum v.ipv4Hdr(14) := sAxisMaster.tData(7 downto 0); -- Source IP Address @@ -332,7 +330,7 @@ begin v.protLen(0)(7 downto 0) := sAxisMaster.tData(95 downto 88); end if; -- Track the number of bytes (include IPv4 header offset from previous state) - v.byteCnt := getTKeep(sAxisMaster.tKeep) + 14; + v.byteCnt := getTKeep(sAxisMaster.tKeep,EMAC_AXIS_CONFIG_C) + 14; end if; -- Check for EOF if (sAxisMaster.tLast = '1') then @@ -350,8 +348,8 @@ begin -- Move the data v.mAxisMaster := sAxisMaster; -- Fill in the TCP/UDP checksum - v.tData := sAxisMaster.tData; - v.tKeep := sAxisMaster.tKeep; + v.tData := sAxisMaster.tData(127 downto 0); + v.tKeep := sAxisMaster.tKeep(15 downto 0); -- Check for TCP data with inbound checksum if (r.ipv4Det(0) = '1') and (r.tcpDet(0) = '1') and (r.tcpFlag = '0') then -- Set the flag @@ -374,7 +372,7 @@ begin end if; end if; -- Track the number of bytes - v.byteCnt := r.byteCnt + getTKeep(sAxisMaster.tKeep); + v.byteCnt := r.byteCnt + getTKeep(sAxisMaster.tKeep,EMAC_AXIS_CONFIG_C); -- Check for EOF if (sAxisMaster.tLast = '1') or (v.byteCnt > MAX_FRAME_SIZE_C) then -- Check for overflow condition diff --git a/ethernet/EthMacCore/rtl/EthMacRxFifo.vhd b/ethernet/EthMacCore/rtl/EthMacRxFifo.vhd index d8c170467a..786e52a36a 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxFifo.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxFifo.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacRxFifo.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-09-21 --- Last update: 2016-10-21 ------------------------------------------------------------------------------- -- Description: Outbound FIFO buffers ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacRxFilter.vhd b/ethernet/EthMacCore/rtl/EthMacRxFilter.vhd index 8ee862b47c..cae3de02dc 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxFilter.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxFilter.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacRxFilter.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-21 --- Last update: 2016-09-14 ------------------------------------------------------------------------------- -- Description: Ethernet MAC's RX frame filter ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacRxImport.vhd b/ethernet/EthMacCore/rtl/EthMacRxImport.vhd index f1a297768e..16bf6136b0 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxImport.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxImport.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacRxImport.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-09-09 --- Last update: 2016-09-14 ------------------------------------------------------------------------------- -- Description: Mapping for 1GbE/10GbE/40GbE ETH MAC RX path ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacRxImportGmii.vhd b/ethernet/EthMacCore/rtl/EthMacRxImportGmii.vhd index 1429ebef1f..065de94f03 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxImportGmii.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxImportGmii.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacRxImportGmii.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-02-04 --- Last update: 2016-09-14 ------------------------------------------------------------------------------- -- Description: 1GbE Import MAC core with GMII interface ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacRxImportXgmii.vhd b/ethernet/EthMacCore/rtl/EthMacRxImportXgmii.vhd index 75efd6a9bd..8be2c93ab0 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxImportXgmii.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxImportXgmii.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacRxImportXgmii.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2008-02-11 --- Last update: 2016-09-14 ------------------------------------------------------------------------------- -- Description: 10GbE Import MAC core with GMII interface ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacRxImportXlgmii.vhd b/ethernet/EthMacCore/rtl/EthMacRxImportXlgmii.vhd index 69956b88c9..dc77d858a2 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxImportXlgmii.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxImportXlgmii.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacRxImportXlgmii.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-09-13 --- Last update: 2016-09-14 ------------------------------------------------------------------------------- -- Description: 40GbE Import MAC core with XLGMII interface ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacRxPause.vhd b/ethernet/EthMacCore/rtl/EthMacRxPause.vhd index a7c4faf4da..046dc17a48 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxPause.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxPause.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacRxPause.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-21 --- Last update: 2016-10-20 ------------------------------------------------------------------------------- -- Description: -- Generic pause frame receiver for Ethernet MACs. Pause frames are dropped diff --git a/ethernet/EthMacCore/rtl/EthMacRxShift.vhd b/ethernet/EthMacCore/rtl/EthMacRxShift.vhd index 00d03c6609..3543f2b49d 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxShift.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxShift.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacRxShift.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-09-08 --- Last update: 2016-09-14 ------------------------------------------------------------------------------- -- Description: Ethernet MAC's RX byte Shifting Module ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacTop.vhd b/ethernet/EthMacCore/rtl/EthMacTop.vhd index 604bcf3618..0f5fb951df 100644 --- a/ethernet/EthMacCore/rtl/EthMacTop.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTop.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacTop.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-22 --- Last update: 2016-10-20 ------------------------------------------------------------------------------- -- Description: Top-level for 1GbE/10GbE/40GbE ETH MAC Module ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacTx.vhd b/ethernet/EthMacCore/rtl/EthMacTx.vhd index f403325449..76303b098b 100644 --- a/ethernet/EthMacCore/rtl/EthMacTx.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacTx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-22 --- Last update: 2016-10-20 ------------------------------------------------------------------------------- -- Description: Ethernet MAC TX Wrapper ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacTxBypass.vhd b/ethernet/EthMacCore/rtl/EthMacTxBypass.vhd index 4629888c6b..4905188e9b 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxBypass.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxBypass.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacTxBypass.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-01-04 --- Last update: 2016-09-14 ------------------------------------------------------------------------------- -- Description: -- Mux stage to allow high priority bypass traffic to override primary path diff --git a/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd b/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd index aa8cd01512..e2b6220752 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacTxCsum.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-09-08 --- Last update: 2018-01-31 ------------------------------------------------------------------------------- -- Description: TX Checksum Hardware Offloading Engine -- https://docs.google.com/spreadsheets/d/1_1M1keasfq8RLmRYHkO0IlRhMq5YZTgJ7OGrWvkib8I/edit?usp=sharing @@ -352,8 +350,8 @@ begin -- Move data v.sMaster := rxMaster; -- Fill in the TCP/UDP checksum - v.tKeep := rxMaster.tKeep; - v.tData := rxMaster.tData; + v.tKeep := rxMaster.tKeep(15 downto 0); + v.tData := rxMaster.tData(127 downto 0); -- Check if NON-VLAN if (VLAN_G = false) then -- Fill in the IPv4 header checksum @@ -365,8 +363,8 @@ begin v.tData := rxMaster.tData(127 downto 80) & x"00000000" & rxMaster.tData(47 downto 0); end if; -- Track the number of bytes - v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep) - 2; - v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep) - 2; + v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep,EMAC_AXIS_CONFIG_C) - 2; + v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep,EMAC_AXIS_CONFIG_C) - 2; else -- Fill in the IPv4 header checksum v.ipv4Hdr(14) := rxMaster.tData(7 downto 0); -- Source IP Address @@ -381,8 +379,8 @@ begin v.tData := rxMaster.tData(127 downto 112) & x"00000000" & rxMaster.tData(79 downto 0); end if; -- Track the number of bytes - v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep) - 6; - v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep) - 6; + v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep,EMAC_AXIS_CONFIG_C) - 6; + v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep,EMAC_AXIS_CONFIG_C) - 6; end if; -- Check for EOF if (rxMaster.tLast = '1') then @@ -406,8 +404,8 @@ begin -- Move data v.sMaster := rxMaster; -- Fill in the TCP/UDP checksum - v.tData := rxMaster.tData; - v.tKeep := rxMaster.tKeep; + v.tData := rxMaster.tData(127 downto 0); + v.tKeep := rxMaster.tKeep(15 downto 0); -- Check for TCP data with inbound checksum if (r.ipv4Det(0) = '1') and (r.tcpDet(0) = '1') and (r.tcpFlag = '0') then -- Set the flag @@ -422,8 +420,8 @@ begin end if; end if; -- Track the number of bytes - v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep); - v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep); + v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep,EMAC_AXIS_CONFIG_C); + v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep,EMAC_AXIS_CONFIG_C); -- Check for EOF if (rxMaster.tLast = '1') or (v.ipv4Len(0) > MAX_FRAME_SIZE_C) then -- Save the EOFE value diff --git a/ethernet/EthMacCore/rtl/EthMacTxExport.vhd b/ethernet/EthMacCore/rtl/EthMacTxExport.vhd index f4bf026bc4..ff4f5939f8 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxExport.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxExport.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacTxExport.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-09-08 --- Last update: 2017-05-10 ------------------------------------------------------------------------------- -- Description: Mapping for 1GbE/10GbE/40GbE ETH MAC TX path ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacTxExportGmii.vhd b/ethernet/EthMacCore/rtl/EthMacTxExportGmii.vhd index 52dffb5654..55393582ef 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxExportGmii.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxExportGmii.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacTxExportGmii.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-02-04 --- Last update: 2017-10-19 ------------------------------------------------------------------------------- -- Description: 1GbE Export MAC core with GMII interface ------------------------------------------------------------------------------- @@ -76,7 +74,7 @@ architecture rtl of EthMacTxExportGmii is gmiiTxEr : sl; gmiiTxd : slv(7 downto 0); txCount : slv(7 downto 0); - txData_d : slv(7 downto 0); + txData : slv(7 downto 0); txCountEn : sl; txUnderRun : sl; txLinkNotReady : sl; @@ -92,7 +90,7 @@ architecture rtl of EthMacTxExportGmii is gmiiTxEr => '0', gmiiTxd => (others => '0'), txCount => (others => '0'), - txData_d => (others => '0'), + txData => (others => '0'), txCountEn => '0', txUnderRun => '0', txLinkNotReady => '0', @@ -121,32 +119,22 @@ architecture rtl of EthMacTxExportGmii is begin - DATA_MUX : entity work.AxiStreamFifoV2 + U_Resize : entity work.AxiStreamResize generic map ( -- General Configurations TPD_G => TPD_G, - INT_PIPE_STAGES_G => 0, - PIPE_STAGES_G => 1, - SLAVE_READY_EN_G => true, - VALID_THOLD_G => 1, - -- FIFO configurations - BRAM_EN_G => false, - USE_BUILT_IN_G => false, - GEN_SYNC_FIFO_G => true, - CASCADE_SIZE_G => 1, - FIFO_ADDR_WIDTH_G => 4, + READY_EN_G => true, -- AXI Stream Port Configurations SLAVE_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C, -- 128-bit AXI stream interface - MASTER_AXI_CONFIG_G => AXI_CONFIG_C) -- 8-bit AXI stream interface + MASTER_AXI_CONFIG_G => AXI_CONFIG_C) -- 8-bit AXI stream interface port map ( + -- Clock and reset + axisClk => ethClk, + axisRst => ethRst, -- Slave Port - sAxisClk => ethClk, - sAxisRst => ethRst, sAxisMaster => macObMaster, -- 128-bit AXI stream interface sAxisSlave => macObSlave, -- Master Port - mAxisClk => ethClk, - mAxisRst => ethRst, mAxisMaster => macMaster, -- 8-bit AXI stream interface mAxisSlave => macSlave); @@ -167,10 +155,11 @@ begin case r.state is ---------------------------------------------------------------------- when IDLE_S => + -- Reset the flags v.crcReset := '1'; - v.TxCount := x"00"; - v.txData_d := x"07"; - v.gmiiTxd := x"07"; + v.txCount := x"00"; + v.txData := x"55"; -- Preset to PREAMBLE CHAR + v.gmiiTxd := x"00"; v.gmiiTxEn := '0'; v.gmiiTxEr := '0'; -- Wait for start flag @@ -180,38 +169,36 @@ begin v.state := TX_PREAMBLE_S; -- Phy is not ready dump data else - v.state := DUMP_S; v.txLinkNotReady := '1'; + v.state := DUMP_S; end if; end if; ---------------------------------------------------------------------- when TX_PREAMBLE_S => + v.crcReset := '0'; v.gmiiTxEn := '1'; - if (r.TxCount = x"07") then - v.CrcReset := '0'; - v.txData_d := x"D5"; - v.gmiiTxd := r.txData_d; - v.TxCount := x"00"; - v.state := TX_DATA_S; + v.gmiiTxd := r.txData; + if (r.txCount = x"06") then + v.txCount := x"00"; + v.txData := x"D5"; -- Set to SFD char + v.state := TX_DATA_S; else - v.TxCount := r.TxCount +1; - v.txData_d := x"55"; - v.gmiiTxd := r.txData_d; - v.state := TX_PREAMBLE_S; + v.txCount := r.txCount +1; + v.txData := x"55"; -- Set to PREAMBLE char end if; ---------------------------------------------------------------------- when TX_DATA_S => v.macSlave.tReady := '1'; v.crcDataValid := '1'; v.crcIn := macMaster.tdata(7 downto 0); - v.txData_d := macMaster.tdata(7 downto 0); - v.gmiiTxd := r.txData_d; - if (r.TxCount < x"3C") then -- Minimum frame of 64 includes 4byte FCS - v.TxCount := r.TxCount + 1; + v.txData := macMaster.tdata(7 downto 0); + v.gmiiTxd := r.txData; + if (r.txCount < x"3C") then -- Minimum frame of 60B (= 84B - 8B Preamble - 4B CRC - 12B intergap) + v.txCount := r.txCount + 1; end if; if (macMaster.tValid = '1') then if (macMaster.tlast = '1') then - if (v.TxCount = x"3C") then + if (v.txCount = x"3C") then v.state := TX_CRC_S; else v.state := PAD_S; @@ -226,16 +213,16 @@ begin when PAD_S => v.crcDataValid := '1'; v.crcIn := x"00"; - v.txData_d := x"00"; - v.gmiiTxd := r.txData_d; - if (r.TxCount < x"3C") then - v.TxCount := v.TxCount + 1; + v.txData := x"00"; + v.gmiiTxd := r.txData; + if (r.txCount < x"3C") then + v.txCount := v.txCount + 1; else v.state := TX_CRC_S; end if; ---------------------------------------------------------------------- when TX_CRC_S => - v.gmiiTxd := r.txData_d; + v.gmiiTxd := r.txData; v.state := TX_CRC0_S; ---------------------------------------------------------------------- when TX_CRC0_S => @@ -253,27 +240,29 @@ begin when TX_CRC3_S => v.txCountEn := '1'; v.gmiitxd := crcOut(7 downto 0); - v.TxCount := x"00"; + v.txCount := x"00"; v.state := INTERGAP_S; ---------------------------------------------------------------------- when DUMP_S => v.gmiiTxEn := '0'; + v.gmiiTxd := x"00"; v.macSlave.tReady := '1'; - v.TxCount := x"00"; + v.txCount := x"00"; if ((macMaster.tValid = '1') and (macMaster.tlast = '1')) then v.state := INTERGAP_S; end if; ---------------------------------------------------------------------- when INTERGAP_S => v.gmiiTxEn := '0'; - v.TxCount := r.TxCount +1; - if r.TxCount = x"0A" then -- 12 Octels - IDLE state - v.TxCount := x"00"; + v.gmiiTxd := x"00"; + v.txCount := r.txCount +1; + if r.txCount = x"0A" then -- 12 Octels (11 in INTERGAP_S + 1 in IDLE_S) + v.txCount := x"00"; v.state := IDLE_S; end if; ---------------------------------------------------------------------- end case; - + -- Combinatorial outputs before the reset macSlave <= v.macSlave; crcDataValid <= v.crcDataValid; diff --git a/ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd b/ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd index 4f39899e82..b88ad12c0e 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd @@ -2,8 +2,6 @@ -- File : EthMacTxExportXgmii.vhd -- Author : Ryan Herbst -- Company : SLAC National Accelerator Laboratory --- Created : 2008-02-11 --- Last update: 2016-10-06 ------------------------------------------------------------------------------- -- Description: 10GbE Export MAC core with GMII interface ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacTxExportXlgmii.vhd b/ethernet/EthMacCore/rtl/EthMacTxExportXlgmii.vhd index 5d3d430c8f..6db74d2cab 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxExportXlgmii.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxExportXlgmii.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacTxExportXlgmii.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-09-13 --- Last update: 2017-05-10 ------------------------------------------------------------------------------- -- Description: 40GbE Export MAC core with XLGMII interface ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacTxFifo.vhd b/ethernet/EthMacCore/rtl/EthMacTxFifo.vhd index 1a7696c426..8ad4942bac 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxFifo.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxFifo.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacTxFifo.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-09-21 --- Last update: 2016-10-20 ------------------------------------------------------------------------------- -- Description: Inbound FIFO buffers ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/rtl/EthMacTxPause.vhd b/ethernet/EthMacCore/rtl/EthMacTxPause.vhd index 8a70767a19..feda7bfca8 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxPause.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxPause.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacTxPause.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-22 --- Last update: 2016-10-20 ------------------------------------------------------------------------------- -- Description: -- Generic pause frame generator for Ethernet MACs. This module as acts as @@ -220,12 +218,12 @@ begin v.mAxisMaster.tData(127 downto 16) := (others => '0'); -- 14 bytes elsif (r.txCount = 2) then -- Zero Padding - v.mAxisMaster.tData := (others => '0'); - v.mAxisMaster.tKeep := x"FFFF"; -- 16 bytes + v.mAxisMaster.tData(127 downto 0) := (others => '0'); + v.mAxisMaster.tKeep(15 downto 0) := x"FFFF"; -- 16 bytes else -- Zero Padding - v.mAxisMaster.tData := (others => '0'); - v.mAxisMaster.tKeep := x"0FFF"; -- 12 bytes (Fixed frame size = 46 bytes) + v.mAxisMaster.tData(127 downto 0) := (others => '0'); + v.mAxisMaster.tKeep(15 downto 0) := x"0FFF"; -- 12 bytes (Fixed frame size = 46 bytes) -- Set EOF v.mAxisMaster.tLast := '1'; -- Latch the Pause time diff --git a/ethernet/EthMacCore/rtl/EthMacTxShift.vhd b/ethernet/EthMacCore/rtl/EthMacTxShift.vhd index 34c185cfd0..f4a19108f3 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxShift.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxShift.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacTxShift.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-09-08 --- Last update: 2016-09-14 ------------------------------------------------------------------------------- -- Description: Ethernet MAC's TX byte Shifting Module ------------------------------------------------------------------------------- diff --git a/ethernet/EthMacCore/tb/EthMacTb.vhd b/ethernet/EthMacCore/tb/EthMacTb.vhd index 7684605701..a3a0ae0fc6 100644 --- a/ethernet/EthMacCore/tb/EthMacTb.vhd +++ b/ethernet/EthMacCore/tb/EthMacTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : EthMacTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-09-20 --- Last update: 2016-09-21 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the EthMac module ------------------------------------------------------------------------------- diff --git a/ethernet/GigEthCore/core/rtl/GigEthPkg.vhd b/ethernet/GigEthCore/core/rtl/GigEthPkg.vhd index 46117ed1e1..eccb27b964 100644 --- a/ethernet/GigEthCore/core/rtl/GigEthPkg.vhd +++ b/ethernet/GigEthCore/core/rtl/GigEthPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GigEthPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-02-07 --- Last update: 2016-02-07 ------------------------------------------------------------------------------- -- Description: 1GbE Package Files ------------------------------------------------------------------------------- diff --git a/ethernet/GigEthCore/core/rtl/GigEthReg.vhd b/ethernet/GigEthCore/core/rtl/GigEthReg.vhd index ee2e45f2f3..e8c6c697c2 100644 --- a/ethernet/GigEthCore/core/rtl/GigEthReg.vhd +++ b/ethernet/GigEthCore/core/rtl/GigEthReg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GigEthReg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-02-20 --- Last update: 2018-01-22 ------------------------------------------------------------------------------- -- Description: AXI-Lite 1GbE Register Interface ------------------------------------------------------------------------------- diff --git a/ethernet/GigEthCore/gth7/images/.gitattributes b/ethernet/GigEthCore/gth7/images/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/GigEthCore/gth7/images/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd b/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd index 554c366d32..cbc3246b18 100644 --- a/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd +++ b/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GigEthGth7.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-02-07 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: 1000BASE-X Ethernet for Gth7 ------------------------------------------------------------------------------- @@ -26,11 +24,13 @@ use work.GigEthPkg.all; entity GigEthGth7 is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -125,9 +125,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "GMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "GMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, @@ -188,7 +190,7 @@ begin gt0_qplloutclk_in => '0', -- QPLL not used gt0_qplloutrefclk_in => '0', -- QPLL not used -- Configuration and Status - an_restart_config => '0', + an_restart_config => '0', an_adv_config_vector => GIG_ETH_AN_ADV_CONFIG_INIT_C, an_interrupt => open, configuration_vector => config.coreConfig, @@ -203,8 +205,8 @@ begin -------------------------------- U_GigEthReg : entity work.GigEthReg generic map ( - TPD_G => TPD_G, - EN_AXI_REG_G => EN_AXI_REG_G) + TPD_G => TPD_G, + EN_AXI_REG_G => EN_AXI_REG_G) port map ( -- Local Configurations localMac => localMac, diff --git a/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd b/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd index 79cb79ec8a..17ca5657e7 100644 --- a/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd +++ b/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GigEthGth7Wrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-30 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gth7 Wrapper for 1000BASE-X Ethernet -- Note: This module supports up to a MGT QUAD of 1GigE interfaces @@ -32,6 +30,8 @@ entity GigEthGth7Wrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk CLKIN_PERIOD_G : real := 8.0; @@ -73,7 +73,7 @@ entity GigEthGth7Wrapper is gtTxP : out slv(NUM_LANE_G-1 downto 0); gtTxN : out slv(NUM_LANE_G-1 downto 0); gtRxP : in slv(NUM_LANE_G-1 downto 0); - gtRxN : in slv(NUM_LANE_G-1 downto 0)); + gtRxN : in slv(NUM_LANE_G-1 downto 0)); end GigEthGth7Wrapper; architecture mapping of GigEthGth7Wrapper is @@ -102,7 +102,7 @@ begin IB => gtClkN, CEB => '0', ODIV2 => open, - O => gtClk); + O => gtClk); BUFG_Inst : BUFG port map ( @@ -120,7 +120,7 @@ begin port map ( arst => extRst, clk => refClk, - rstOut => refRst); + rstOut => refRst); ---------------- -- Clock Manager @@ -146,21 +146,23 @@ begin clkOut(0) => sysClk125, clkOut(1) => sysClk62, rstOut(0) => sysRst125, - rstOut(1) => sysRst62); + rstOut(1) => sysRst62); -------------- -- GigE Module -------------- GEN_LANE : for i in 0 to NUM_LANE_G-1 generate - + U_GigEthGth7 : entity work.GigEthGth7 generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G(i)) + AXIS_CONFIG_G => AXIS_CONFIG_G(i)) port map ( -- Local Configurations localMac => localMac(i), @@ -189,7 +191,7 @@ begin gtTxP => gtTxP(i), gtTxN => gtTxN(i), gtRxP => gtRxP(i), - gtRxN => gtRxN(i)); + gtRxN => gtRxN(i)); end generate GEN_LANE; diff --git a/ethernet/GigEthCore/gthUltraScale+/images/.gitattributes b/ethernet/GigEthCore/gthUltraScale+/images/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/GigEthCore/gthUltraScale+/images/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd b/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd index be63eaab66..eaab47f1c9 100644 --- a/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd +++ b/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GigEthGthUltraScale.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-02-07 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: 1000BASE-X Ethernet for Gth7 ------------------------------------------------------------------------------- @@ -26,11 +24,13 @@ use work.GigEthPkg.all; entity GigEthGthUltraScale is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -125,9 +125,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "GMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "GMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, @@ -184,7 +186,7 @@ begin rxp => gtRxP, rxn => gtRxN, -- Configuration and Status - an_restart_config => '0', + an_restart_config => '0', an_adv_config_vector => GIG_ETH_AN_ADV_CONFIG_INIT_C, an_interrupt => open, configuration_vector => config.coreConfig, @@ -199,8 +201,8 @@ begin -------------------------------- U_GigEthReg : entity work.GigEthReg generic map ( - TPD_G => TPD_G, - EN_AXI_REG_G => EN_AXI_REG_G) + TPD_G => TPD_G, + EN_AXI_REG_G => EN_AXI_REG_G) port map ( -- Local Configurations localMac => localMac, diff --git a/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd b/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd index e18e36ac37..0fc98a2f3c 100644 --- a/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd +++ b/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GigEthGthUltraScaleWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-30 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gth7 Wrapper for 1000BASE-X Ethernet -- Note: This module supports up to a MGT QUAD of 1GigE interfaces @@ -32,6 +30,8 @@ entity GigEthGthUltraScaleWrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk CLKIN_PERIOD_G : real := 8.0; @@ -73,7 +73,7 @@ entity GigEthGthUltraScaleWrapper is gtTxP : out slv(NUM_LANE_G-1 downto 0); gtTxN : out slv(NUM_LANE_G-1 downto 0); gtRxP : in slv(NUM_LANE_G-1 downto 0); - gtRxN : in slv(NUM_LANE_G-1 downto 0)); + gtRxN : in slv(NUM_LANE_G-1 downto 0)); end GigEthGthUltraScaleWrapper; architecture mapping of GigEthGthUltraScaleWrapper is @@ -105,7 +105,7 @@ begin IB => gtClkN, CEB => '0', ODIV2 => gtClk, - O => open); + O => open); BUFG_GT_Inst : BUFG_GT port map ( @@ -128,7 +128,7 @@ begin port map ( arst => extRst, clk => refClk, - rstOut => refRst); + rstOut => refRst); ---------------- -- Clock Manager @@ -154,21 +154,23 @@ begin clkOut(0) => sysClk125, clkOut(1) => sysClk62, rstOut(0) => sysRst125, - rstOut(1) => sysRst62); + rstOut(1) => sysRst62); -------------- -- GigE Module -------------- GEN_LANE : for i in 0 to NUM_LANE_G-1 generate - + U_GigEthGthUltraScale : entity work.GigEthGthUltraScale generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G(i)) + AXIS_CONFIG_G => AXIS_CONFIG_G(i)) port map ( -- Local Configurations localMac => localMac(i), @@ -197,7 +199,7 @@ begin gtTxP => gtTxP(i), gtTxN => gtTxN(i), gtRxP => gtRxP(i), - gtRxN => gtRxN(i)); + gtRxN => gtRxN(i)); end generate GEN_LANE; diff --git a/ethernet/GigEthCore/gthUltraScale/images/.gitattributes b/ethernet/GigEthCore/gthUltraScale/images/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/GigEthCore/gthUltraScale/images/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd index 00c2f33ab9..a5811f05f9 100644 --- a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd +++ b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GigEthGthUltraScale.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-02-07 --- Last update: 2018-07-24 ------------------------------------------------------------------------------- -- Description: 1000BASE-X Ethernet for Gth7 ------------------------------------------------------------------------------- @@ -26,11 +24,13 @@ use work.GigEthPkg.all; entity GigEthGthUltraScale is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -176,9 +176,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "GMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "GMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, diff --git a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd index edb6922fa2..98fbb8d0f6 100644 --- a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd +++ b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GigEthGthUltraScaleWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-30 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gth7 Wrapper for 1000BASE-X Ethernet -- Note: This module supports up to a MGT QUAD of 1GigE interfaces @@ -32,6 +30,8 @@ entity GigEthGthUltraScaleWrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk CLKIN_PERIOD_G : real := 8.0; @@ -73,7 +73,7 @@ entity GigEthGthUltraScaleWrapper is gtTxP : out slv(NUM_LANE_G-1 downto 0); gtTxN : out slv(NUM_LANE_G-1 downto 0); gtRxP : in slv(NUM_LANE_G-1 downto 0); - gtRxN : in slv(NUM_LANE_G-1 downto 0)); + gtRxN : in slv(NUM_LANE_G-1 downto 0)); end GigEthGthUltraScaleWrapper; architecture mapping of GigEthGthUltraScaleWrapper is @@ -105,7 +105,7 @@ begin IB => gtClkN, CEB => '0', ODIV2 => gtClk, - O => open); + O => open); BUFG_GT_Inst : BUFG_GT port map ( @@ -128,7 +128,7 @@ begin port map ( arst => extRst, clk => refClk, - rstOut => refRst); + rstOut => refRst); ---------------- -- Clock Manager @@ -154,21 +154,23 @@ begin clkOut(0) => sysClk125, clkOut(1) => sysClk62, rstOut(0) => sysRst125, - rstOut(1) => sysRst62); + rstOut(1) => sysRst62); -------------- -- GigE Module -------------- GEN_LANE : for i in 0 to NUM_LANE_G-1 generate - + U_GigEthGthUltraScale : entity work.GigEthGthUltraScale generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G(i)) + AXIS_CONFIG_G => AXIS_CONFIG_G(i)) port map ( -- Local Configurations localMac => localMac(i), @@ -197,7 +199,7 @@ begin gtTxP => gtTxP(i), gtTxN => gtTxN(i), gtRxP => gtRxP(i), - gtRxN => gtRxN(i)); + gtRxN => gtRxN(i)); end generate GEN_LANE; diff --git a/ethernet/GigEthCore/gtp7/ip/.gitattributes b/ethernet/GigEthCore/gtp7/ip/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/GigEthCore/gtp7/ip/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd index 34fdac6d1e..bf25e8077b 100644 --- a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd +++ b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GigEthGtp7.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-02-07 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: 1000BASE-X Ethernet for Gtp7 ------------------------------------------------------------------------------- @@ -26,11 +24,13 @@ use work.GigEthPkg.all; entity GigEthGtp7 is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -131,9 +131,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "GMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "GMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, @@ -199,7 +201,7 @@ begin gt0_pll1outclk_in => qPllOutClk(1), gt0_pll1outrefclk_in => qPllOutRefClk(1), -- Configuration and Status - an_restart_config => '0', + an_restart_config => '0', an_adv_config_vector => GIG_ETH_AN_ADV_CONFIG_INIT_C, an_interrupt => open, configuration_vector => config.coreConfig, @@ -215,8 +217,8 @@ begin -------------------------------- U_GigEthReg : entity work.GigEthReg generic map ( - TPD_G => TPD_G, - EN_AXI_REG_G => EN_AXI_REG_G) + TPD_G => TPD_G, + EN_AXI_REG_G => EN_AXI_REG_G) port map ( -- Local Configurations localMac => localMac, diff --git a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd index 0651bdc9ed..348d79503d 100644 --- a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd +++ b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GigEthGtp7Wrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-30 --- Last update: 2018-04-05 ------------------------------------------------------------------------------- -- Description: Gtp7 Wrapper for 1000BASE-X Ethernet -- Note: This module supports up to a MGT QUAD of 1GigE interfaces @@ -32,6 +30,8 @@ entity GigEthGtp7Wrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk CLKIN_PERIOD_G : real := 8.0; @@ -170,14 +170,16 @@ begin PLL1_FBDIV_45_IN_G => 5, PLL1_REFCLK_DIV_IN_G => 1) port map ( - qPllRefClk => (others => sysClk125), - qPllOutClk => qPllOutClk, - qPllOutRefClk => qPllOutRefClk, - qPllLock => qPllLock, - qPllLockDetClk => (others => sysClk125), - qPllRefClkLost => qPllRefClkLost, - qPllPowerDown => "10", -- power down PLL1 (unused PLL) - qPllReset => qpllReset); + qPllRefClk(0) => sysClk125, + qPllRefClk(1) => sysClk125, + qPllOutClk => qPllOutClk, + qPllOutRefClk => qPllOutRefClk, + qPllLock => qPllLock, + qPllLockDetClk(0) => sysClk125, + qPllLockDetClk(1) => sysClk125, + qPllRefClkLost => qPllRefClkLost, + qPllPowerDown => "10", -- power down PLL1 (unused PLL) + qPllReset => qpllReset); -- Once the QPLL is locked, prevent the -- IP cores from accidentally reseting each other @@ -192,11 +194,13 @@ begin U_GigEthGtp7 : entity work.GigEthGtp7 generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G(i)) + AXIS_CONFIG_G => AXIS_CONFIG_G(i)) port map ( -- Local Configurations localMac => localMac(i), diff --git a/ethernet/GigEthCore/gtx7/images/.gitattributes b/ethernet/GigEthCore/gtx7/images/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/GigEthCore/gtx7/images/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd index fddd2c5f73..fc564a0549 100644 --- a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd +++ b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GigEthGtx7.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-02-07 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: 1000BASE-X Ethernet for Gtx7 ------------------------------------------------------------------------------- @@ -26,11 +24,13 @@ use work.GigEthPkg.all; entity GigEthGtx7 is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -125,9 +125,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "GMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "GMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, @@ -188,7 +190,7 @@ begin gt0_qplloutclk_in => '0', -- QPLL not used gt0_qplloutrefclk_in => '0', -- QPLL not used -- Configuration and Status - an_restart_config => '0', + an_restart_config => '0', an_adv_config_vector => GIG_ETH_AN_ADV_CONFIG_INIT_C, an_interrupt => open, configuration_vector => config.coreConfig, @@ -203,8 +205,8 @@ begin -------------------------------- U_GigEthReg : entity work.GigEthReg generic map ( - TPD_G => TPD_G, - EN_AXI_REG_G => EN_AXI_REG_G) + TPD_G => TPD_G, + EN_AXI_REG_G => EN_AXI_REG_G) port map ( -- Local Configurations localMac => localMac, diff --git a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd index 7e540a01bb..a9502d3865 100644 --- a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd +++ b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GigEthGtx7Wrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-30 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gtx7 Wrapper for 1000BASE-X Ethernet -- Note: This module supports up to a MGT QUAD of 1GigE interfaces @@ -32,6 +30,8 @@ entity GigEthGtx7Wrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk CLKIN_PERIOD_G : real := 8.0; @@ -73,7 +73,7 @@ entity GigEthGtx7Wrapper is gtTxP : out slv(NUM_LANE_G-1 downto 0); gtTxN : out slv(NUM_LANE_G-1 downto 0); gtRxP : in slv(NUM_LANE_G-1 downto 0); - gtRxN : in slv(NUM_LANE_G-1 downto 0)); + gtRxN : in slv(NUM_LANE_G-1 downto 0)); end GigEthGtx7Wrapper; architecture mapping of GigEthGtx7Wrapper is @@ -102,7 +102,7 @@ begin IB => gtClkN, CEB => '0', ODIV2 => open, - O => gtClk); + O => gtClk); BUFG_Inst : BUFG port map ( @@ -120,7 +120,7 @@ begin port map ( arst => extRst, clk => refClk, - rstOut => refRst); + rstOut => refRst); ---------------- -- Clock Manager @@ -146,21 +146,23 @@ begin clkOut(0) => sysClk125, clkOut(1) => sysClk62, rstOut(0) => sysRst125, - rstOut(1) => sysRst62); + rstOut(1) => sysRst62); -------------- -- GigE Module -------------- GEN_LANE : for i in 0 to NUM_LANE_G-1 generate - + U_GigEthGtx7 : entity work.GigEthGtx7 generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G(i)) + AXIS_CONFIG_G => AXIS_CONFIG_G(i)) port map ( -- Local Configurations localMac => localMac(i), @@ -189,7 +191,7 @@ begin gtTxP => gtTxP(i), gtTxN => gtTxN(i), gtRxP => gtRxP(i), - gtRxN => gtRxN(i)); + gtRxN => gtRxN(i)); end generate GEN_LANE; diff --git a/ethernet/GigEthCore/gtyUltraScale+/images/.gitattributes b/ethernet/GigEthCore/gtyUltraScale+/images/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/GigEthCore/gtyUltraScale+/images/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/GigEthCore/gtyUltraScale+/images/GigEthGtyUltraScaleCore.dcp b/ethernet/GigEthCore/gtyUltraScale+/images/GigEthGtyUltraScaleCore.dcp index e3184af53d..16644c75f4 100644 --- a/ethernet/GigEthCore/gtyUltraScale+/images/GigEthGtyUltraScaleCore.dcp +++ b/ethernet/GigEthCore/gtyUltraScale+/images/GigEthGtyUltraScaleCore.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a3362c80996ad9f03c6b0e181e002c8b7dea00d00ba05ad65fa5820e1a63878e -size 514351 +oid sha256:0d813d4ef86eecc7368ed037acd59527a4af7ada8b82f6819b02ab89a7c46df0 +size 514356 diff --git a/ethernet/GigEthCore/gtyUltraScale+/images/README.md b/ethernet/GigEthCore/gtyUltraScale+/images/README.md index b71bb8e28f..3fc8101999 100644 --- a/ethernet/GigEthCore/gtyUltraScale+/images/README.md +++ b/ethernet/GigEthCore/gtyUltraScale+/images/README.md @@ -1 +1,18 @@ -Refer to https://github.com/slaclab/surf-dcp-targets/tree/master/firmware/dcp/GigEthGtyUltraScale+/ for original source code \ No newline at end of file +Refer to https://github.com/slaclab/surf-dcp-targets/tree/master/firmware/dcp/GigEthGtyUltraScale+/ for original source code + +# Remove the IO Lock Constraints +set_property is_loc_fixed false [get_ports [list rxp]] +set_property is_loc_fixed false [get_ports [list rxn]] +set_property is_loc_fixed false [get_ports [list txp]] +set_property is_loc_fixed false [get_ports [list txn]] + +# Removed the IO location Constraints +set_property package_pin "" [get_ports [list rxp]] +set_property package_pin "" [get_ports [list rxn]] +set_property package_pin "" [get_ports [list txp]] +set_property package_pin "" [get_ports [list txn]] + +# Removed the Placement Constraints +set_property is_bel_fixed false [get_cells -hierarchical *GTYE4_CHANNEL_PRIM_INST*] +set_property is_loc_fixed false [get_cells -hierarchical *GTYE4_CHANNEL_PRIM_INST*] +unplace_cell [get_cells -hierarchical *GTYE4_CHANNEL_PRIM_INST*] diff --git a/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScale.vhd b/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScale.vhd index ec2657e36c..9b10f2c3f3 100644 --- a/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScale.vhd +++ b/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScale.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GigEthGtyUltraScale.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2018-04-05 --- Last update: 2018-04-05 ------------------------------------------------------------------------------- -- Description: 1000BASE-X Ethernet for Gty ------------------------------------------------------------------------------- @@ -26,11 +24,13 @@ use work.GigEthPkg.all; entity GigEthGtyUltraScale is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -125,9 +125,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "GMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "GMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, @@ -184,7 +186,7 @@ begin rxp => gtRxP, rxn => gtRxN, -- Configuration and Status - an_restart_config => '0', + an_restart_config => '0', an_adv_config_vector => GIG_ETH_AN_ADV_CONFIG_INIT_C, an_interrupt => open, configuration_vector => config.coreConfig, @@ -199,8 +201,8 @@ begin -------------------------------- U_GigEthReg : entity work.GigEthReg generic map ( - TPD_G => TPD_G, - EN_AXI_REG_G => EN_AXI_REG_G) + TPD_G => TPD_G, + EN_AXI_REG_G => EN_AXI_REG_G) port map ( -- Local Configurations localMac => localMac, diff --git a/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd b/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd index 977c430839..2b051ae62b 100644 --- a/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd +++ b/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GigEthGtyUltraScaleWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2018-04-05 --- Last update: 2018-04-05 ------------------------------------------------------------------------------- -- Description: Gty Wrapper for 1000BASE-X Ethernet -- Note: This module supports up to a MGT QUAD of 1GigE interfaces @@ -32,6 +30,8 @@ entity GigEthGtyUltraScaleWrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk CLKIN_PERIOD_G : real := 8.0; @@ -164,11 +164,13 @@ begin U_GigEthGtyUltraScale : entity work.GigEthGtyUltraScale generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G(i)) + AXIS_CONFIG_G => AXIS_CONFIG_G(i)) port map ( -- Local Configurations localMac => localMac(i), diff --git a/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd b/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd index 59c5ff91f9..9929001154 100644 --- a/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd +++ b/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GigEthLvdsUltraScale.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-02-07 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: SGMII Ethernet over LVDS ------------------------------------------------------------------------------- @@ -26,11 +24,13 @@ use work.GigEthPkg.all; entity GigEthLvdsUltraScale is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -71,28 +71,28 @@ end GigEthLvdsUltraScale; architecture mapping of GigEthLvdsUltraScale is - signal config : GigEthConfigType; - signal status : GigEthStatusType; + signal config : GigEthConfigType; + signal status : GigEthStatusType; signal mAxiReadMaster : AxiLiteReadMasterType; signal mAxiReadSlave : AxiLiteReadSlaveType; signal mAxiWriteMaster : AxiLiteWriteMasterType; signal mAxiWriteSlave : AxiLiteWriteSlaveType; - signal gmiiTxClk : sl; - signal gmiiTxd : slv(7 downto 0); - signal gmiiTxEn : sl; - signal gmiiTxEr : sl; + signal gmiiTxClk : sl; + signal gmiiTxd : slv(7 downto 0); + signal gmiiTxEn : sl; + signal gmiiTxEr : sl; - signal gmiiRxClk : sl; - signal gmiiRxd : slv(7 downto 0); - signal gmiiRxDv : sl; - signal gmiiRxEr : sl; + signal gmiiRxClk : sl; + signal gmiiRxd : slv(7 downto 0); + signal gmiiRxDv : sl; + signal gmiiRxEr : sl; - signal areset : sl; - signal coreRst : sl; + signal areset : sl; + signal coreRst : sl; - signal delayCtrlRdy : sl; + signal delayCtrlRdy : sl; begin @@ -134,9 +134,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "GMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "GMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, @@ -170,34 +172,34 @@ begin U_GigEthLvdsUltraScaleCore : entity work.SaltUltraScaleCore port map ( -- Clocks and Resets - clk125m => sysClk125, - clk312 => sysClk312, - clk625 => sysClk625, - idelay_rdy_in => delayCtrlRdy, - mmcm_locked => mmcmLocked, - sgmii_clk_r => open, - sgmii_clk_f => open, - sgmii_clk_en => open, - speed_is_10_100 => speed_is_10_100, - speed_is_100 => speed_is_100, - reset => coreRst, + clk125m => sysClk125, + clk312 => sysClk312, + clk625 => sysClk625, + idelay_rdy_in => delayCtrlRdy, + mmcm_locked => mmcmLocked, + sgmii_clk_r => open, + sgmii_clk_f => open, + sgmii_clk_en => open, + speed_is_10_100 => speed_is_10_100, + speed_is_100 => speed_is_100, + reset => coreRst, -- PHY Interface - gmii_txd => gmiiTxd, - gmii_tx_en => gmiiTxEn, - gmii_tx_er => gmiiTxEr, - gmii_rxd => gmiiRxd, - gmii_rx_dv => gmiiRxDv, - gmii_rx_er => gmiiRxEr, - gmii_isolate => open, + gmii_txd => gmiiTxd, + gmii_tx_en => gmiiTxEn, + gmii_tx_er => gmiiTxEr, + gmii_rxd => gmiiRxd, + gmii_rx_dv => gmiiRxDv, + gmii_rx_er => gmiiRxEr, + gmii_isolate => open, -- MGT Ports - txp => sgmiiTxP, - txn => sgmiiTxN, - rxp => sgmiiRxP, - rxn => sgmiiRxN, + txp => sgmiiTxP, + txn => sgmiiTxN, + rxp => sgmiiRxP, + rxn => sgmiiRxN, -- Configuration and Status - configuration_vector => config.coreConfig, - status_vector => status.coreStatus, - signal_detect => sigDet); + configuration_vector => config.coreConfig, + status_vector => status.coreStatus, + signal_detect => sigDet); status.phyReady <= status.coreStatus(0); phyReady <= status.phyReady; @@ -207,8 +209,8 @@ begin -------------------------------- U_GigEthReg : entity work.GigEthReg generic map ( - TPD_G => TPD_G, - EN_AXI_REG_G => EN_AXI_REG_G) + TPD_G => TPD_G, + EN_AXI_REG_G => EN_AXI_REG_G) port map ( -- Local Configurations localMac => localMac, diff --git a/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScaleWrapper.vhd b/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScaleWrapper.vhd index 787eaf84cb..bacd46d1d6 100644 --- a/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScaleWrapper.vhd +++ b/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScaleWrapper.vhd @@ -27,18 +27,20 @@ use unisim.vcomponents.all; entity GigEthLvdsUltraScaleWrapper is generic ( - TPD_G : time := 1 ns; - NUM_LANE_G : natural range 1 to 4 := 1; + TPD_G : time := 1 ns; + NUM_LANE_G : natural range 1 to 4 := 1; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- Clocking Configurations - USE_REFCLK_G : boolean := false; -- FALSE: sgmiiClkP/N, TRUE: sgmiiRefClk - CLKIN_PERIOD_G : real := 1.6; - DIVCLK_DIVIDE_G : positive := 2; - CLKFBOUT_MULT_F_G : real := 2.0; + USE_REFCLK_G : boolean := false; -- FALSE: sgmiiClkP/N, TRUE: sgmiiRefClk + CLKIN_PERIOD_G : real := 1.6; + DIVCLK_DIVIDE_G : positive := 2; + CLKFBOUT_MULT_F_G : real := 2.0; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigArray(3 downto 0) := (others => AXI_STREAM_CONFIG_INIT_C) - ); + AXIS_CONFIG_G : AxiStreamConfigArray(3 downto 0) := (others => AXI_STREAM_CONFIG_INIT_C) + ); port ( -- Local Configurations localMac : in Slv48Array(NUM_LANE_G-1 downto 0) := (others => MAC_ADDR_INIT_C); @@ -74,7 +76,7 @@ entity GigEthLvdsUltraScaleWrapper is sgmiiTxN : out slv(NUM_LANE_G-1 downto 0); sgmiiRxP : in slv(NUM_LANE_G-1 downto 0); sgmiiRxN : in slv(NUM_LANE_G-1 downto 0) - ); + ); end GigEthLvdsUltraScaleWrapper; architecture mapping of GigEthLvdsUltraScaleWrapper is @@ -82,26 +84,26 @@ architecture mapping of GigEthLvdsUltraScaleWrapper is -- reset is asserted for 2*RST_DURATION_C constant RST_DURATION_C : natural range 0 to ((2**30)-1) := 156250000; - constant NUM_CLOCKS_C : natural := 3; + constant NUM_CLOCKS_C : natural := 3; - signal sgmiiClk : sl; - signal refClk : sl; - signal refRst : sl := '1'; - signal sysClk12NB : sl; - signal sysClk125 : sl; - signal sysRst125 : sl; - signal sysClk312 : sl; - signal sysRst312 : sl; - signal sysClk625 : sl; - signal sysRst625 : sl; - signal sysClkNB : slv(6 downto 0); - signal sysClkB : slv(6 downto 0); - signal sysRst : slv(6 downto 0); - signal locked : sl; - signal clkFb : sl; - signal extRstSync : sl; - signal refCE : sl := '0'; - signal refRstCnt : natural range 0 to RST_DURATION_C := RST_DURATION_C; + signal sgmiiClk : sl; + signal refClk : sl; + signal refRst : sl := '1'; + signal sysClk12NB : sl; + signal sysClk125 : sl; + signal sysRst125 : sl; + signal sysClk312 : sl; + signal sysRst312 : sl; + signal sysClk625 : sl; + signal sysRst625 : sl; + signal sysClkNB : slv(6 downto 0); + signal sysClkB : slv(6 downto 0); + signal sysRst : slv(6 downto 0); + signal locked : sl; + signal clkFb : sl; + signal extRstSync : sl; + signal refCE : sl := '0'; + signal refRstCnt : natural range 0 to RST_DURATION_C := RST_DURATION_C; begin @@ -113,14 +115,14 @@ begin ----------------------------- IBUFGDS_SGMII : IBUFGDS generic map ( - DIFF_TERM => FALSE, - IBUF_LOW_PWR => FALSE - ) + DIFF_TERM => false, + IBUF_LOW_PWR => false + ) port map ( - I => sgmiiClkP, - IB => sgmiiClkN, - O => sgmiiClk - ); + I => sgmiiClkP, + IB => sgmiiClkN, + O => sgmiiClk + ); refClk <= sgmiiClk when(USE_REFCLK_G = false) else sgmiiRefClk; @@ -133,15 +135,15 @@ begin ----------------- U_RstSync : entity work.RstSync generic map ( - TPD_G => TPD_G, - IN_POLARITY_G => '1', - OUT_POLARITY_G => '1' - ) + TPD_G => TPD_G, + IN_POLARITY_G => '1', + OUT_POLARITY_G => '1' + ) port map ( - clk => refClk, - asyncRst => extRst, - syncRst => extRstSync - ); + clk => refClk, + asyncRst => extRst, + syncRst => extRstSync + ); -- don't reset refCE in order to reduce possible -- timing problems. This leads to uncertainty of @@ -149,21 +151,21 @@ begin -- an issue. process (refClk) begin - if ( rising_edge(refClk) ) then + if (rising_edge(refClk)) then refCE <= not refCE; end if; end process; process (refClk) begin - if ( rising_edge(refClk) ) then - if ( extRstSync = '1' ) then + if (rising_edge(refClk)) then + if (extRstSync = '1') then refRst <= '1' after TPD_G; - refRstCnt <= 0 after TPD_G; + refRstCnt <= 0 after TPD_G; else - if ( refCE = '1' ) then - if ( refRstCnt = RST_DURATION_C ) then - refRst <= '0' after TPD_G; + if (refCE = '1') then + if (refRstCnt = RST_DURATION_C) then + refRst <= '0' after TPD_G; else refRstCnt <= refRstCnt + 1 after TPD_G; end if; @@ -195,50 +197,50 @@ begin -- the BUFG in the feedback chain. U_MMCM : MMCME3_BASE generic map( - CLKOUT0_DIVIDE_F => 5.0, - CLKOUT1_DIVIDE => 2, - CLKOUT2_DIVIDE => 1, - CLKOUT3_DIVIDE => 50, - CLKOUT4_DIVIDE => 50, - CLKOUT4_CASCADE => "TRUE", - CLKOUT6_DIVIDE => 10, - CLKFBOUT_MULT_F => CLKFBOUT_MULT_F_G, - DIVCLK_DIVIDE => DIVCLK_DIVIDE_G, - CLKIN1_PERIOD => CLKIN_PERIOD_G - ) + CLKOUT0_DIVIDE_F => 5.0, + CLKOUT1_DIVIDE => 2, + CLKOUT2_DIVIDE => 1, + CLKOUT3_DIVIDE => 50, + CLKOUT4_DIVIDE => 50, + CLKOUT4_CASCADE => "TRUE", + CLKOUT6_DIVIDE => 10, + CLKFBOUT_MULT_F => CLKFBOUT_MULT_F_G, + DIVCLK_DIVIDE => DIVCLK_DIVIDE_G, + CLKIN1_PERIOD => CLKIN_PERIOD_G + ) port map ( - CLKIN1 => refClk, - RST => refRst, - CLKFBIN => clkFb, - CLKFBOUT => clkFb, - CLKOUT0 => sysClkNB(0), - CLKOUT1 => sysClkNB(1), - CLKOUT2 => sysClkNB(2), - CLKOUT3 => sysClkNB(3), - CLKOUT4 => sysClkNB(4), - CLKOUT5 => sysClkNB(5), - CLKOUT6 => sysClkNB(6), - LOCKED => locked, - PWRDWN => '0' - ); + CLKIN1 => refClk, + RST => refRst, + CLKFBIN => clkFb, + CLKFBOUT => clkFb, + CLKOUT0 => sysClkNB(0), + CLKOUT1 => sysClkNB(1), + CLKOUT2 => sysClkNB(2), + CLKOUT3 => sysClkNB(3), + CLKOUT4 => sysClkNB(4), + CLKOUT5 => sysClkNB(5), + CLKOUT6 => sysClkNB(6), + LOCKED => locked, + PWRDWN => '0' + ); GEN_BUFG : for i in 0 to NUM_CLOCKS_C - 1 generate U_BUFG_125 : BUFG port map ( - I => sysClkNB(i), - O => sysClkB(i) - ); + I => sysClkNB(i), + O => sysClkB(i) + ); - U_RESET : entity work.RstSync + U_RESET : entity work.RstSync generic map ( - TPD_G => TPD_G, - IN_POLARITY_G => '0' - ) + TPD_G => TPD_G, + IN_POLARITY_G => '0' + ) port map ( - clk => sysClkB(i), - asyncRst => locked, - syncRst => sysRst(i) - ); + clk => sysClkB(i), + asyncRst => locked, + syncRst => sysRst(i) + ); end generate; sysClk125 <= sysClkB(0); @@ -280,28 +282,30 @@ begin sel12p50 => speed_is_10_100(i), sel1p250 => speed_is_10, O => ethClk - ); + ); -- Generate reset synchronous to the currently selected clock - U_RESET : entity work.RstSync + U_RESET : entity work.RstSync generic map ( - TPD_G => TPD_G, - IN_POLARITY_G => '0' - ) + TPD_G => TPD_G, + IN_POLARITY_G => '0' + ) port map ( - clk => ethClk, - asyncRst => locked, - syncRst => ethRst - ); + clk => ethClk, + asyncRst => locked, + syncRst => ethRst + ); U_GigEthLvdsUltraScale : entity work.GigEthLvdsUltraScale generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G(i) - ) + AXIS_CONFIG_G => AXIS_CONFIG_G(i) + ) port map ( -- Local Configurations localMac => localMac(i), @@ -337,7 +341,7 @@ begin sgmiiTxN => sgmiiTxN(i), sgmiiRxP => sgmiiRxP(i), sgmiiRxN => sgmiiRxN(i) - ); + ); end generate GEN_LANE; diff --git a/ethernet/IpV4Engine/rtl/ArpEngine.vhd b/ethernet/IpV4Engine/rtl/ArpEngine.vhd index 41fc2b45d7..91451dec25 100644 --- a/ethernet/IpV4Engine/rtl/ArpEngine.vhd +++ b/ethernet/IpV4Engine/rtl/ArpEngine.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : ArpEngine.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-12 --- Last update: 2016-09-16 ------------------------------------------------------------------------------- -- Description: ARP Engine ------------------------------------------------------------------------------- @@ -206,7 +204,7 @@ begin v.ibArpSlave.tReady := '1'; -- Word[0] if r.cnt = 0 then - v.tData(0) := ibArpMaster.tData; + v.tData(0) := ibArpMaster.tData(127 downto 0); if (ssiGetUserSof(EMAC_AXIS_CONFIG_C, ibArpMaster) = '1') then -- Increment the counter v.cnt := r.cnt + 1; @@ -216,7 +214,7 @@ begin end if; -- Word[1] elsif r.cnt = 1 then - v.tData(1) := ibArpMaster.tData; + v.tData(1) := ibArpMaster.tData(127 downto 0); if (ibArpMaster.tLast = '0') then -- Increment the counter v.cnt := r.cnt + 1; @@ -226,7 +224,7 @@ begin end if; -- Word[2] elsif r.cnt = 2 then - v.tData(2) := ibArpMaster.tData; + v.tData(2) := ibArpMaster.tData(127 downto 0); if (ibArpMaster.tLast = '0') then -- Increment the counter v.cnt := r.cnt + 1; @@ -370,8 +368,8 @@ begin -- Check if ready to move data if v.txArpMaster.tValid = '0' then -- Move data - v.txArpMaster.tValid := '1'; - v.txArpMaster.tData := r.tData(r.cnt); + v.txArpMaster.tValid := '1'; + v.txArpMaster.tData(127 downto 0) := r.tData(r.cnt); -- Increment the counter v.cnt := r.cnt + 1; if r.cnt = 0 then @@ -381,9 +379,9 @@ begin v.txArpMaster.tLast := '1'; -- Set the tKeep if (VLAN_G = false) then - v.txArpMaster.tKeep := x"03FF"; + v.txArpMaster.tKeep(15 downto 0) := x"03FF"; else - v.txArpMaster.tKeep := x"3FFF"; + v.txArpMaster.tKeep(15 downto 0) := x"3FFF"; end if; -- Next state v.state := IDLE_S; diff --git a/ethernet/IpV4Engine/rtl/IcmpEngine.vhd b/ethernet/IpV4Engine/rtl/IcmpEngine.vhd index 150d92c55d..83913f1294 100644 --- a/ethernet/IpV4Engine/rtl/IcmpEngine.vhd +++ b/ethernet/IpV4Engine/rtl/IcmpEngine.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : IcmpEngine.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-08-16 --- Last update: 2016-09-16 ------------------------------------------------------------------------------- -- Description: ICMP Engine (A.K.A. "ping" protocol) ------------------------------------------------------------------------------- @@ -148,8 +146,8 @@ begin -- outbound packet. --------------------------------------------------------- -- Send the IPv4 base header - v.obIcmpMaster.tValid := '1'; - v.obIcmpMaster.tData := r.tData; + v.obIcmpMaster.tValid := '1'; + v.obIcmpMaster.tData(127 downto 0) := r.tData; ssiSetUserSof(EMAC_AXIS_CONFIG_C, v.obIcmpMaster, '1'); -- Next state v.state := TX_HDR_S; diff --git a/ethernet/IpV4Engine/rtl/IpV4Engine.vhd b/ethernet/IpV4Engine/rtl/IpV4Engine.vhd index ce9a0abea9..29908f2d2c 100644 --- a/ethernet/IpV4Engine/rtl/IpV4Engine.vhd +++ b/ethernet/IpV4Engine/rtl/IpV4Engine.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : IpV4Engine.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-12 --- Last update: 2018-01-18 ------------------------------------------------------------------------------- -- Description: IPv4 Top-level Module for IPv4/ARP/ICMP ------------------------------------------------------------------------------- diff --git a/ethernet/IpV4Engine/rtl/IpV4EngineDeMux.vhd b/ethernet/IpV4Engine/rtl/IpV4EngineDeMux.vhd index f0e58e80b6..470262fb3d 100644 --- a/ethernet/IpV4Engine/rtl/IpV4EngineDeMux.vhd +++ b/ethernet/IpV4Engine/rtl/IpV4EngineDeMux.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : IpV4EngineDeMux.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-12 --- Last update: 2016-09-16 ------------------------------------------------------------------------------- -- Description: IPv4 AXIS DEMUX module ------------------------------------------------------------------------------- diff --git a/ethernet/IpV4Engine/rtl/IpV4EngineRx.vhd b/ethernet/IpV4Engine/rtl/IpV4EngineRx.vhd index 8aa69d2bd2..09fd8e138a 100644 --- a/ethernet/IpV4Engine/rtl/IpV4EngineRx.vhd +++ b/ethernet/IpV4Engine/rtl/IpV4EngineRx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : IpV4EngineRx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-12 --- Last update: 2016-09-16 ------------------------------------------------------------------------------- -- Description: IPv4 RX Engine Module -- Note: IPv4 checksum checked in EthMac core @@ -259,9 +257,9 @@ begin -- Accept the data v.rxSlave.tReady := '1'; -- Move the data - v.txMaster.tValid := '1'; - v.txMaster.tData := r.tData; - v.txMaster.tKeep := r.tKeep; + v.txMaster.tValid := '1'; + v.txMaster.tData(127 downto 0) := r.tData; + v.txMaster.tKeep(15 downto 0) := r.tKeep; -- Track the leftovers v.tData(15 downto 0) := rxMaster.tData(127 downto 112); v.tKeep(1 downto 0) := rxMaster.tKeep(15 downto 14); @@ -338,10 +336,10 @@ begin -- Check for data if (v.txMaster.tValid = '0') then -- Move the data - v.txMaster.tValid := '1'; - v.txMaster.tData := r.tData; - v.txMaster.tKeep := r.tKeep; - v.txMaster.tLast := '1'; + v.txMaster.tValid := '1'; + v.txMaster.tData(127 downto 0) := r.tData; + v.txMaster.tKeep(15 downto 0) := r.tKeep; + v.txMaster.tLast := '1'; ssiSetUserEofe(EMAC_AXIS_CONFIG_C, v.txMaster, r.eofe); -- Next state v.state := IDLE_S; diff --git a/ethernet/IpV4Engine/rtl/IpV4EngineTx.vhd b/ethernet/IpV4Engine/rtl/IpV4EngineTx.vhd index 35ee051e5a..6bf4c7f064 100644 --- a/ethernet/IpV4Engine/rtl/IpV4EngineTx.vhd +++ b/ethernet/IpV4Engine/rtl/IpV4EngineTx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : IpV4EngineTx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-12 --- Last update: 2016-09-16 ------------------------------------------------------------------------------- -- Description: IPv4 TX Engine Module -- Note: IPv4 checksum checked in EthMac core @@ -378,10 +376,10 @@ begin -- Check for data if (v.txMaster.tValid = '0') then -- Move the data - v.txMaster.tValid := '1'; - v.txMaster.tData := r.tData; - v.txMaster.tKeep := r.tKeep; - v.txMaster.tLast := '1'; + v.txMaster.tValid := '1'; + v.txMaster.tData(127 downto 0) := r.tData; + v.txMaster.tKeep(15 downto 0) := r.tKeep; + v.txMaster.tLast := '1'; ssiSetUserEofe(EMAC_AXIS_CONFIG_C, v.txMaster, r.eofe); -- Next state v.state := IDLE_S; diff --git a/ethernet/IpV4Engine/tb/IpV4EngineCoreTb.vhd b/ethernet/IpV4Engine/tb/IpV4EngineCoreTb.vhd index 82e8695ef2..0f1dc84523 100644 --- a/ethernet/IpV4Engine/tb/IpV4EngineCoreTb.vhd +++ b/ethernet/IpV4Engine/tb/IpV4EngineCoreTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : IpV4EngineCoreTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-17 --- Last update: 2015-08-18 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the IpV4EngineCore ------------------------------------------------------------------------------- @@ -283,7 +281,7 @@ begin end if; end loop; -- Check for errors - if (v.tKeep /= ibProtocolMaster.tKeep) then + if (v.tKeep(15 downto 0) /= ibProtocolMaster.tKeep(15 downto 0)) then v.failed(4) := '1'; end if; -- Check the counter @@ -298,7 +296,7 @@ begin v.failed(5) := '1'; end if; -- Check for full word transfer and full size - if (ibProtocolMaster.tKeep = x"FFFF") and (r.rxWordCnt = 255) then + if (ibProtocolMaster.tKeep(15 downto 0) = x"FFFF") and (r.rxWordCnt = 255) then -- Next state v.state := DONE_S; end if; diff --git a/ethernet/IpV4Engine/tb/IpV4EngineLoopback.vhd b/ethernet/IpV4Engine/tb/IpV4EngineLoopback.vhd index f4be8138b6..f43025b953 100644 --- a/ethernet/IpV4Engine/tb/IpV4EngineLoopback.vhd +++ b/ethernet/IpV4Engine/tb/IpV4EngineLoopback.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : IpV4EngineLoopback.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-17 --- Last update: 2015-08-25 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the IpV4Engine in Loopback ------------------------------------------------------------------------------- diff --git a/ethernet/IpV4Engine/tb/IpV4EngineTb.vhd b/ethernet/IpV4Engine/tb/IpV4EngineTb.vhd index c4d24d1fa5..92846820dc 100644 --- a/ethernet/IpV4Engine/tb/IpV4EngineTb.vhd +++ b/ethernet/IpV4Engine/tb/IpV4EngineTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : IpV4EngineTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-17 --- Last update: 2015-08-25 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the IpV4Engine module ------------------------------------------------------------------------------- diff --git a/ethernet/RawEthFramer/rtl/RawEthFramer.vhd b/ethernet/RawEthFramer/rtl/RawEthFramer.vhd index 92a7fba5f4..5823dedf29 100644 --- a/ethernet/RawEthFramer/rtl/RawEthFramer.vhd +++ b/ethernet/RawEthFramer/rtl/RawEthFramer.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RawEthFramer.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-05-23 --- Last update: 2016-05-26 ------------------------------------------------------------------------------- -- Description: Top-level Raw L2 Ethernet Framer ------------------------------------------------------------------------------- diff --git a/ethernet/RawEthFramer/rtl/RawEthFramerPkg.vhd b/ethernet/RawEthFramer/rtl/RawEthFramerPkg.vhd index 932dd8a58a..e10a2830c4 100644 --- a/ethernet/RawEthFramer/rtl/RawEthFramerPkg.vhd +++ b/ethernet/RawEthFramer/rtl/RawEthFramerPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RawEthFramerPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-05-25 --- Last update: 2016-05-26 ------------------------------------------------------------------------------- -- Description: Raw L2 Ethernet Framer Package File ------------------------------------------------------------------------------- diff --git a/ethernet/RawEthFramer/rtl/RawEthFramerRx.vhd b/ethernet/RawEthFramer/rtl/RawEthFramerRx.vhd index 76d6e3936b..9b8013f629 100644 --- a/ethernet/RawEthFramer/rtl/RawEthFramerRx.vhd +++ b/ethernet/RawEthFramer/rtl/RawEthFramerRx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RawEthFramerRx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-05-23 --- Last update: 2016-05-26 ------------------------------------------------------------------------------- -- Description: Raw L2 Ethernet Framer's RX Engine ------------------------------------------------------------------------------- @@ -103,7 +101,7 @@ begin v.ibAppMaster.tValid := '0'; v.ibAppMaster.tLast := '0'; v.ibAppMaster.tUser := (others => '0'); - v.ibAppMaster.tKeep := x"00FF"; + v.ibAppMaster.tKeep := resize(x"00FF",AXI_STREAM_MAX_TKEEP_WIDTH_C); end if; -- State Machine diff --git a/ethernet/RawEthFramer/rtl/RawEthFramerTx.vhd b/ethernet/RawEthFramer/rtl/RawEthFramerTx.vhd index 69fbeac24c..2490db49a9 100644 --- a/ethernet/RawEthFramer/rtl/RawEthFramerTx.vhd +++ b/ethernet/RawEthFramer/rtl/RawEthFramerTx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RawEthFramerTx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-05-23 --- Last update: 2016-05-26 ------------------------------------------------------------------------------- -- Description: Raw L2 Ethernet Framer's TX Engine ------------------------------------------------------------------------------- @@ -128,7 +126,7 @@ begin v.ibMacMaster.tValid := '0'; v.ibMacMaster.tLast := '0'; v.ibMacMaster.tUser := (others => '0'); - v.ibMacMaster.tKeep := x"00FF"; + v.ibMacMaster.tKeep := resize(x"00FF",AXI_STREAM_MAX_TKEEP_WIDTH_C); end if; -- Update variables @@ -174,7 +172,7 @@ begin end if; end loop; -- Update the min. ETH Byte counter - v.minByteCnt := 16 + getTKeep(tKeep); -- include header offset + v.minByteCnt := 16 + getTKeep(tKeep,RAW_ETH_CONFIG_INIT_C); -- include header offset -- Check for tLast if obAppMaster.tLast = '1' then -- Set EOF @@ -225,7 +223,7 @@ begin end if; end loop; -- Update the min. ETH Byte counter - v.minByteCnt := r.minByteCnt + getTKeep(tKeep); + v.minByteCnt := r.minByteCnt + getTKeep(tKeep,RAW_ETH_CONFIG_INIT_C); -- Check for tLast if obAppMaster.tLast = '1' then -- Set EOF diff --git a/ethernet/RawEthFramer/rtl/RawEthFramerWrapper.vhd b/ethernet/RawEthFramer/rtl/RawEthFramerWrapper.vhd index 84c3615421..8d9175946d 100644 --- a/ethernet/RawEthFramer/rtl/RawEthFramerWrapper.vhd +++ b/ethernet/RawEthFramer/rtl/RawEthFramerWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RawEthFramerWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-05-23 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Wrapper for RawEthFramer Module ------------------------------------------------------------------------------- diff --git a/ethernet/RawEthFramer/tb/RawEthFramerTb.vhd b/ethernet/RawEthFramer/tb/RawEthFramerTb.vhd index d0a1e5d7fa..329d80604a 100644 --- a/ethernet/RawEthFramer/tb/RawEthFramerTb.vhd +++ b/ethernet/RawEthFramer/tb/RawEthFramerTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RawEthFramerTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-05-24 --- Last update: 2016-05-26 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the RawEthFramer module ------------------------------------------------------------------------------- diff --git a/ethernet/TenGigEthCore/core/rtl/TenGigEthPkg.vhd b/ethernet/TenGigEthCore/core/rtl/TenGigEthPkg.vhd index 69940594bb..194a40c959 100644 --- a/ethernet/TenGigEthCore/core/rtl/TenGigEthPkg.vhd +++ b/ethernet/TenGigEthCore/core/rtl/TenGigEthPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-02-12 --- Last update: 2015-04-07 ------------------------------------------------------------------------------- -- Description: 10GbE Package Files ------------------------------------------------------------------------------- diff --git a/ethernet/TenGigEthCore/core/rtl/TenGigEthReg.vhd b/ethernet/TenGigEthCore/core/rtl/TenGigEthReg.vhd index b74af0d175..69727091c3 100644 --- a/ethernet/TenGigEthCore/core/rtl/TenGigEthReg.vhd +++ b/ethernet/TenGigEthCore/core/rtl/TenGigEthReg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthReg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-02-20 --- Last update: 2018-01-22 ------------------------------------------------------------------------------- -- Description: AXI-Lite 10GbE Register Interface ------------------------------------------------------------------------------- diff --git a/ethernet/TenGigEthCore/core/rtl/TenGigEthRst.vhd b/ethernet/TenGigEthCore/core/rtl/TenGigEthRst.vhd index b75a05d6aa..ccbb4da9bc 100644 --- a/ethernet/TenGigEthCore/core/rtl/TenGigEthRst.vhd +++ b/ethernet/TenGigEthCore/core/rtl/TenGigEthRst.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthRst.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-30 --- Last update: 2015-10-20 ------------------------------------------------------------------------------- -- Description: 10GbE Reset Module ------------------------------------------------------------------------------- diff --git a/ethernet/TenGigEthCore/gth7/ip/.gitattributes b/ethernet/TenGigEthCore/gth7/ip/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/TenGigEthCore/gth7/ip/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd index f180bc27f5..a649063e33 100644 --- a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd +++ b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGth7.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-02-12 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: 10GBASE-R Ethernet for Gth7 ------------------------------------------------------------------------------- @@ -26,11 +24,13 @@ use work.EthMacPkg.all; entity TenGigEthGth7 is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -66,7 +66,7 @@ entity TenGigEthGth7 is gtTxP : out sl; gtTxN : out sl; gtRxP : in sl; - gtRxN : in sl); + gtRxN : in sl); end TenGigEthGth7; architecture mapping of TenGigEthGth7 is @@ -104,7 +104,7 @@ architecture mapping of TenGigEthGth7 is signal macRxAxisCtrl : AxiStreamCtrlType; signal macTxAxisMaster : AxiStreamMasterType; signal macTxAxisSlave : AxiStreamSlaveType; - + begin phyReady <= status.phyReady; @@ -131,7 +131,7 @@ begin mAxiReadMaster => mAxiReadMaster, mAxiReadSlave => mAxiReadSlave, mAxiWriteMaster => mAxiWriteMaster, - mAxiWriteSlave => mAxiWriteSlave); + mAxiWriteSlave => mAxiWriteSlave); txDisable <= status.txDisable; @@ -148,16 +148,18 @@ begin -- Output dataOut(0) => status.sigDet, dataOut(1) => status.txFault, - dataOut(2) => status.txUsrRdy); + dataOut(2) => status.txUsrRdy); -------------------- -- Ethernet MAC core -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "XGMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "XGMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, @@ -176,7 +178,7 @@ begin xgmiiRxd => phyRxd, xgmiiRxc => phyRxc, xgmiiTxd => phyTxd, - xgmiiTxc => phyTxc); + xgmiiTxc => phyTxc); ----------------- -- 10GBASE-R core @@ -259,7 +261,7 @@ begin rstCntDone => status.rstCntDone, -- Quad PLL Ports qplllock => status.qplllock, - qpllRst => qpllRst); + qpllRst => qpllRst); ------------------------------- -- Configuration Vector Mapping @@ -280,8 +282,8 @@ begin -------------------------------- U_TenGigEthReg : entity work.TenGigEthReg generic map ( - TPD_G => TPD_G, - EN_AXI_REG_G => EN_AXI_REG_G) + TPD_G => TPD_G, + EN_AXI_REG_G => EN_AXI_REG_G) port map ( -- Local Configurations localMac => localMac, @@ -295,6 +297,6 @@ begin axiWriteSlave => mAxiWriteSlave, -- Configuration and Status Interface config => config, - status => status); + status => status); end mapping; diff --git a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Clk.vhd b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Clk.vhd index f1fdbe3c0c..da95f8f4c4 100644 --- a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Clk.vhd +++ b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Clk.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGth7Clk.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-30 --- Last update: 2016-05-19 ------------------------------------------------------------------------------- -- Description: 10GBASE-R Ethernet's Clock Module ------------------------------------------------------------------------------- diff --git a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd index 4fb11f5817..e109b51d62 100644 --- a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd +++ b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGth7Wrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-30 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gth7 Wrapper for 10GBASE-R Ethernet -- Note: This module supports up to a MGT QUAD of 10GigE interfaces @@ -29,6 +27,8 @@ entity TenGigEthGth7Wrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- QUAD PLL Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk REFCLK_DIV2_G : boolean := false; -- FALSE: gtClkP/N = 156.25 MHz, TRUE: gtClkP/N = 312.5 MHz @@ -71,7 +71,7 @@ entity TenGigEthGth7Wrapper is gtTxP : out slv(NUM_LANE_G-1 downto 0); gtTxN : out slv(NUM_LANE_G-1 downto 0); gtRxP : in slv(NUM_LANE_G-1 downto 0); - gtRxN : in slv(NUM_LANE_G-1 downto 0)); + gtRxN : in slv(NUM_LANE_G-1 downto 0)); end TenGigEthGth7Wrapper; architecture mapping of TenGigEthGth7Wrapper is @@ -99,7 +99,7 @@ begin TPD_G => TPD_G, USE_GTREFCLK_G => USE_GTREFCLK_G, REFCLK_DIV2_G => REFCLK_DIV2_G, - QPLL_REFCLK_SEL_G => QPLL_REFCLK_SEL_G) + QPLL_REFCLK_SEL_G => QPLL_REFCLK_SEL_G) port map ( -- Clocks and Resets extRst => extRst, @@ -113,7 +113,7 @@ begin qplllock => qplllock, qplloutclk => qplloutclk, qplloutrefclk => qplloutrefclk, - qpllRst => qpllReset); + qpllRst => qpllReset); qpllReset <= uOr(qpllRst) and not(qPllLock); @@ -122,14 +122,16 @@ begin ---------------- GEN_LANE : for i in 0 to NUM_LANE_G-1 generate - + TenGigEthGth7_Inst : entity work.TenGigEthGth7 generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G(i)) + AXIS_CONFIG_G => AXIS_CONFIG_G(i)) port map ( -- Local Configurations localMac => localMac(i), @@ -164,7 +166,7 @@ begin gtTxP => gtTxP(i), gtTxN => gtTxN(i), gtRxP => gtRxP(i), - gtRxN => gtRxN(i)); + gtRxN => gtRxN(i)); end generate GEN_LANE; diff --git a/ethernet/TenGigEthCore/gthUltraScale+/ip/.gitattributes b/ethernet/TenGigEthCore/gthUltraScale+/ip/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/TenGigEthCore/gthUltraScale+/ip/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd index 8b13951f32..686bfd4f5e 100644 --- a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGthUltraScale.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-08 --- Last update: 2018-04-06 ------------------------------------------------------------------------------- -- Description: 10GBASE-R Ethernet for GTH Ultra Scale ------------------------------------------------------------------------------- @@ -26,11 +24,13 @@ use work.EthMacPkg.all; entity TenGigEthGthUltraScale is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -234,9 +234,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "XGMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "XGMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, diff --git a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd index 2598b84fff..f22e54e204 100644 --- a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGthUltraScaleClk.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2018-04-06 --- Last update: 2018-04-06 ------------------------------------------------------------------------------- -- Description: 10GBASE-R Ethernet's Clock Module ------------------------------------------------------------------------------- diff --git a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd index 978ce7b7d2..8e5f34c42e 100644 --- a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGthUltraScaleRst.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2018-04-06 --- Last update: 2018-04-09 ------------------------------------------------------------------------------- -- Description: 10GBASE-R Ethernet Reset Module ------------------------------------------------------------------------------- diff --git a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd index 4b7230f658..d9065360a9 100644 --- a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGthUltraScaleWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-08 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: GTH Ultra Scale Wrapper for 10GBASE-R Ethernet -- Note: This module supports up to a MGT QUAD of 10GigE interfaces @@ -27,8 +25,10 @@ use work.TenGigEthPkg.all; entity TenGigEthGthUltraScaleWrapper is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- QUAD PLL Configurations QPLL_REFCLK_SEL_G : slv(2 downto 0) := "001"; -- AXI-Lite Configurations @@ -74,7 +74,7 @@ entity TenGigEthGthUltraScaleWrapper is gtTxP : out slv(NUM_LANE_G-1 downto 0); gtTxN : out slv(NUM_LANE_G-1 downto 0); gtRxP : in slv(NUM_LANE_G-1 downto 0); - gtRxN : in slv(NUM_LANE_G-1 downto 0)); + gtRxN : in slv(NUM_LANE_G-1 downto 0)); end TenGigEthGthUltraScaleWrapper; architecture mapping of TenGigEthGthUltraScaleWrapper is @@ -83,7 +83,7 @@ architecture mapping of TenGigEthGthUltraScaleWrapper is signal qplloutclk : slv(1 downto 0); signal qplloutrefclk : slv(1 downto 0); - signal qpllRst : Slv2Array(3 downto 0) := (others=>"00"); + signal qpllRst : Slv2Array(3 downto 0) := (others => "00"); signal qpllReset : slv(1 downto 0); signal coreClock : sl; @@ -104,7 +104,7 @@ begin port map ( arst => extRst, clk => coreClock, - rstOut => coreReset); + rstOut => coreReset); ---------------------- -- Common Clock Module @@ -112,7 +112,7 @@ begin TenGigEthGthUltraScaleClk_Inst : entity work.TenGigEthGthUltraScaleClk generic map ( TPD_G => TPD_G, - QPLL_REFCLK_SEL_G => QPLL_REFCLK_SEL_G) + QPLL_REFCLK_SEL_G => QPLL_REFCLK_SEL_G) port map ( -- MGT Clock Port (156.25 MHz) gtRefClk => gtRefClk, @@ -125,7 +125,7 @@ begin qplllock => qplllock, qplloutclk => qplloutclk, qplloutrefclk => qplloutrefclk, - qpllRst => qpllReset); + qpllRst => qpllReset); qpllReset(0) <= (qpllRst(0)(0) or qpllRst(1)(0) or qpllRst(2)(0) or qpllRst(3)(0)) and not(qPllLock(0)); qpllReset(1) <= (qpllRst(0)(1) or qpllRst(1)(1) or qpllRst(2)(1) or qpllRst(3)(1)) and not(qPllLock(1)); @@ -135,14 +135,16 @@ begin ---------------- GEN_LANE : for i in 0 to NUM_LANE_G-1 generate - + TenGigEthGthUltraScale_Inst : entity work.TenGigEthGthUltraScale generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G(i)) + AXIS_CONFIG_G => AXIS_CONFIG_G(i)) port map ( -- Local Configurations localMac => localMac(i), @@ -176,12 +178,12 @@ begin qplllock => qplllock, qplloutclk => qplloutclk, qplloutrefclk => qplloutrefclk, - qpllRst => qpllRst(i), + qpllRst => qpllRst(i), -- MGT Ports gtTxP => gtTxP(i), gtTxN => gtTxN(i), gtRxP => gtRxP(i), - gtRxN => gtRxN(i)); + gtRxN => gtRxN(i)); end generate GEN_LANE; diff --git a/ethernet/TenGigEthCore/gthUltraScale/ip/.gitattributes b/ethernet/TenGigEthCore/gthUltraScale/ip/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/TenGigEthCore/gthUltraScale/ip/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd index e1f2aaa9b2..01d698c9c0 100644 --- a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGthUltraScale.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-08 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: 10GBASE-R Ethernet for GTH Ultra Scale ------------------------------------------------------------------------------- @@ -26,11 +24,13 @@ use work.EthMacPkg.all; entity TenGigEthGthUltraScale is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -247,9 +247,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "XGMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "XGMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, @@ -400,8 +402,8 @@ begin -------------------------------- U_TenGigEthReg : entity work.TenGigEthReg generic map ( - TPD_G => TPD_G, - EN_AXI_REG_G => EN_AXI_REG_G) + TPD_G => TPD_G, + EN_AXI_REG_G => EN_AXI_REG_G) port map ( -- Local Configurations localMac => localMac, diff --git a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd index 4dfc22f22e..0cd0122581 100644 --- a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGthUltraScaleClk.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-08 --- Last update: 2016-04-19 ------------------------------------------------------------------------------- -- Description: 10GBASE-R Ethernet's Clock Module ------------------------------------------------------------------------------- diff --git a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd index 22ee5ff2ad..ee0b711cef 100644 --- a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGthUltraScaleRst.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-05-04 --- Last update: 2015-12-03 ------------------------------------------------------------------------------- -- Description: 10GBASE-R Ethernet Reset Module ------------------------------------------------------------------------------- diff --git a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd index 9e7dfe5b84..bc809997b1 100644 --- a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGthUltraScaleWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-08 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: GTH Ultra Scale Wrapper for 10GBASE-R Ethernet -- Note: This module supports up to a MGT QUAD of 10GigE interfaces @@ -27,8 +25,10 @@ use work.TenGigEthPkg.all; entity TenGigEthGthUltraScaleWrapper is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- QUAD PLL Configurations QPLL_REFCLK_SEL_G : slv(2 downto 0) := "001"; -- AXI-Lite Configurations @@ -78,7 +78,7 @@ entity TenGigEthGthUltraScaleWrapper is gtTxP : out slv(NUM_LANE_G-1 downto 0); gtTxN : out slv(NUM_LANE_G-1 downto 0); gtRxP : in slv(NUM_LANE_G-1 downto 0); - gtRxN : in slv(NUM_LANE_G-1 downto 0)); + gtRxN : in slv(NUM_LANE_G-1 downto 0)); end TenGigEthGthUltraScaleWrapper; architecture mapping of TenGigEthGthUltraScaleWrapper is @@ -108,7 +108,7 @@ begin port map ( arst => extRst, clk => coreClock, - rstOut => coreReset); + rstOut => coreReset); ---------------------- -- Common Clock Module @@ -116,7 +116,7 @@ begin TenGigEthGthUltraScaleClk_Inst : entity work.TenGigEthGthUltraScaleClk generic map ( TPD_G => TPD_G, - QPLL_REFCLK_SEL_G => QPLL_REFCLK_SEL_G) + QPLL_REFCLK_SEL_G => QPLL_REFCLK_SEL_G) port map ( -- MGT Clock Port (156.25 MHz) gtRefClk => gtRefClk, @@ -129,7 +129,7 @@ begin qplllock => qplllock, qplloutclk => qplloutclk, qplloutrefclk => qplloutrefclk, - qpllRst => qpllReset); + qpllRst => qpllReset); qpllReset <= uOr(qpllRst) and not(qPllLock); @@ -138,14 +138,16 @@ begin ---------------- GEN_LANE : for i in 0 to NUM_LANE_G-1 generate - + TenGigEthGthUltraScale_Inst : entity work.TenGigEthGthUltraScale generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G(i)) + AXIS_CONFIG_G => AXIS_CONFIG_G(i)) port map ( -- Local Configurations localMac => localMac(i), @@ -187,7 +189,7 @@ begin gtTxP => gtTxP(i), gtTxN => gtTxN(i), gtRxP => gtRxP(i), - gtRxN => gtRxN(i)); + gtRxN => gtRxN(i)); end generate GEN_LANE; diff --git a/ethernet/TenGigEthCore/gtx7/ip/.gitattributes b/ethernet/TenGigEthCore/gtx7/ip/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/TenGigEthCore/gtx7/ip/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd index 59cf3df828..f101c0a203 100644 --- a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd +++ b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGtx7.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-02-12 --- Last update: 2018-07-30 ------------------------------------------------------------------------------- -- Description: 10GBASE-R Ethernet for Gtx7 ------------------------------------------------------------------------------- @@ -26,11 +24,13 @@ use work.EthMacPkg.all; entity TenGigEthGtx7 is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -233,9 +233,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "XGMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "XGMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, diff --git a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Clk.vhd b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Clk.vhd index 988cfe46a9..e89c99eb72 100644 --- a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Clk.vhd +++ b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Clk.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGtx7Clk.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-30 --- Last update: 2016-05-19 ------------------------------------------------------------------------------- -- Description: 10GBASE-R Ethernet's Clock Module ------------------------------------------------------------------------------- diff --git a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd index 1056a02287..e2604739d9 100644 --- a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd +++ b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGtx7Wrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-30 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gtx7 Wrapper for 10GBASE-R Ethernet -- Note: This module supports up to a MGT QUAD of 10GigE interfaces @@ -29,6 +27,8 @@ entity TenGigEthGtx7Wrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- QUAD PLL Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk REFCLK_DIV2_G : boolean := false; -- FALSE: gtClkP/N = 156.25 MHz, TRUE: gtClkP/N = 312.5 MHz @@ -68,7 +68,7 @@ entity TenGigEthGtx7Wrapper is gtTxPostCursor : in slv(4 downto 0) := "00000"; gtTxDiffCtrl : in slv(3 downto 0) := "1110"; gtRxPolarity : in sl := '0'; - gtTxPolarity : in sl := '0'; + gtTxPolarity : in sl := '0'; -- MGT Clock Port (156.25 MHz or 312.5 MHz) gtRefClk : in sl := '0'; -- 156.25 MHz only gtClkP : in sl := '1'; @@ -78,7 +78,7 @@ entity TenGigEthGtx7Wrapper is gtTxP : out slv(NUM_LANE_G-1 downto 0); gtTxN : out slv(NUM_LANE_G-1 downto 0); gtRxP : in slv(NUM_LANE_G-1 downto 0); - gtRxN : in slv(NUM_LANE_G-1 downto 0)); + gtRxN : in slv(NUM_LANE_G-1 downto 0)); end TenGigEthGtx7Wrapper; architecture mapping of TenGigEthGtx7Wrapper is @@ -106,7 +106,7 @@ begin TPD_G => TPD_G, USE_GTREFCLK_G => USE_GTREFCLK_G, REFCLK_DIV2_G => REFCLK_DIV2_G, - QPLL_REFCLK_SEL_G => QPLL_REFCLK_SEL_G) + QPLL_REFCLK_SEL_G => QPLL_REFCLK_SEL_G) port map ( -- Clocks and Resets extRst => extRst, @@ -121,7 +121,7 @@ begin qplllock => qplllock, qplloutclk => qplloutclk, qplloutrefclk => qplloutrefclk, - qpllRst => qpllReset); + qpllRst => qpllReset); qpllReset <= uOr(qpllRst) and not(qPllLock); @@ -130,14 +130,16 @@ begin ---------------- GEN_LANE : for i in 0 to NUM_LANE_G-1 generate - + TenGigEthGtx7_Inst : entity work.TenGigEthGtx7 generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G(i)) + AXIS_CONFIG_G => AXIS_CONFIG_G(i)) port map ( -- Local Configurations localMac => localMac(i), @@ -169,7 +171,7 @@ begin gtTxPostCursor => gtTxPostCursor, gtTxDiffCtrl => gtTxDiffCtrl, gtRxPolarity => gtRxPolarity, - gtTxPolarity => gtTxPolarity, + gtTxPolarity => gtTxPolarity, -- Quad PLL Ports qplllock => qplllock, qplloutclk => qplloutclk, @@ -178,7 +180,7 @@ begin gtTxP => gtTxP(i), gtTxN => gtTxN(i), gtRxP => gtRxP(i), - gtRxN => gtRxN(i)); + gtRxN => gtRxN(i)); end generate GEN_LANE; diff --git a/ethernet/TenGigEthCore/gtyUltraScale+/ip/.gitattributes b/ethernet/TenGigEthCore/gtyUltraScale+/ip/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/TenGigEthCore/gtyUltraScale+/ip/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/TenGigEthCore/gtyUltraScale+/ip/README.txt b/ethernet/TenGigEthCore/gtyUltraScale+/ip/README.txt index 34e6a38c47..5c0a70ebe3 100644 --- a/ethernet/TenGigEthCore/gtyUltraScale+/ip/README.txt +++ b/ethernet/TenGigEthCore/gtyUltraScale+/ip/README.txt @@ -1,18 +1,18 @@ -## LLR - 06MARCHY2018 +## LLR - 06AUG2018 ## After generating each of the .DCP files from their corresponding .XCI files, ## performed the following TCL commands in the DCP to generate a modified DCP file: # Remove the IO Lock Constraints -set_property is_loc_fixed false [get_ports [list gt_txp_out]] -set_property is_loc_fixed false [get_ports [list gt_txn_out]] -set_property is_loc_fixed false [get_ports [list gt_rxp_in]] -set_property is_loc_fixed false [get_ports [list gt_rxn_in]] +set_property is_loc_fixed false [get_ports [list xaui_tx_l*_p]] +set_property is_loc_fixed false [get_ports [list xaui_tx_l*_n]] +set_property is_loc_fixed false [get_ports [list xaui_rx_l*_p]] +set_property is_loc_fixed false [get_ports [list xaui_rx_l*_n]] # Removed the IO location Constraints -set_property package_pin "" [get_ports [list gt_txp_out]] -set_property package_pin "" [get_ports [list gt_txn_out]] -set_property package_pin "" [get_ports [list gt_rxp_in]] -set_property package_pin "" [get_ports [list gt_rxn_in]] +set_property package_pin "" [get_ports [list xaui_tx_l*_p]] +set_property package_pin "" [get_ports [list xaui_tx_l*_n]] +set_property package_pin "" [get_ports [list xaui_rx_l*_p]] +set_property package_pin "" [get_ports [list xaui_rx_l*_n]] # Removed the Placement Constraints set_property is_bel_fixed false [get_cells -hierarchical *GTYE4_CHANNEL_PRIM_INST*] diff --git a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd index 71839d126d..d41b1fcb1f 100644 --- a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd +++ b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGtyUltraScale.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2018-04-06 --- Last update: 2018-04-09 ------------------------------------------------------------------------------- -- Description: 10GBASE-R Ethernet for GTH Ultra Scale ------------------------------------------------------------------------------- @@ -26,11 +24,13 @@ use work.EthMacPkg.all; entity TenGigEthGtyUltraScale is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -234,9 +234,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "XGMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "XGMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, diff --git a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleClk.vhd b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleClk.vhd index 159ca2b6de..3bad031ab4 100644 --- a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleClk.vhd +++ b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleClk.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGtyUltraScaleClk.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2018-04-06 --- Last update: 2018-04-06 ------------------------------------------------------------------------------- -- Description: 10GBASE-R Ethernet's Clock Module ------------------------------------------------------------------------------- diff --git a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleRst.vhd b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleRst.vhd index da5048b4bf..7dc6fe2a0f 100644 --- a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleRst.vhd +++ b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleRst.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGtyUltraScaleRst.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2018-04-06 --- Last update: 2018-04-09 ------------------------------------------------------------------------------- -- Description: 10GBASE-R Ethernet Reset Module ------------------------------------------------------------------------------- diff --git a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd index 0673862459..163c6bef20 100644 --- a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd +++ b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : TenGigEthGtyUltraScaleWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2018-04-06 --- Last update: 2018-04-06 ------------------------------------------------------------------------------- -- Description: GTH Ultra Scale Wrapper for 10GBASE-R Ethernet -- Note: This module supports up to a MGT QUAD of 10GigE interfaces @@ -30,6 +28,8 @@ entity TenGigEthGtyUltraScaleWrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- QUAD PLL Configurations QPLL_REFCLK_SEL_G : slv(2 downto 0) := "001"; -- AXI-Lite Configurations @@ -139,11 +139,13 @@ begin TenGigEthGtyUltraScale_Inst : entity work.TenGigEthGtyUltraScale generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G(i)) + AXIS_CONFIG_G => AXIS_CONFIG_G(i)) port map ( -- Local Configurations localMac => localMac(i), diff --git a/ethernet/UdpEngine/rtl/UdpEngine.vhd b/ethernet/UdpEngine/rtl/UdpEngine.vhd index f111990c2e..69e2670876 100644 --- a/ethernet/UdpEngine/rtl/UdpEngine.vhd +++ b/ethernet/UdpEngine/rtl/UdpEngine.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : UdpEngine.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-20 --- Last update: 2017-10-18 ------------------------------------------------------------------------------- -- Description: Top-Level UDP/DHCP Module ------------------------------------------------------------------------------- diff --git a/ethernet/UdpEngine/rtl/UdpEngineArp.vhd b/ethernet/UdpEngine/rtl/UdpEngineArp.vhd index 0db1469ce8..7a5ed7fb46 100644 --- a/ethernet/UdpEngine/rtl/UdpEngineArp.vhd +++ b/ethernet/UdpEngine/rtl/UdpEngineArp.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : UdpEngineArp.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-20 --- Last update: 2016-09-16 ------------------------------------------------------------------------------- -- Description: UDP Client's ARP Messaging Module ------------------------------------------------------------------------------- diff --git a/ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd b/ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd index a92c265314..9404f93607 100644 --- a/ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd +++ b/ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : UdpEngineDhcp.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-08-12 --- Last update: 2018-08-02 ------------------------------------------------------------------------------- -- Description: DHCP Engine ------------------------------------------------------------------------------- @@ -278,7 +276,7 @@ begin -- OP/HTYPE/HLEN/HOPS when 0 => v.txMaster.tData(31 downto 0) := CLIENT_HDR_C; - v.txMaster.tKeep := x"000F"; + v.txMaster.tKeep(15 downto 0) := x"000F"; ssiSetUserSof(DHCP_CONFIG_C, v.txMaster, '1'); -- XID when 1 => @@ -342,15 +340,15 @@ begin when 64 => v.txMaster.tData(15 downto 0) := r.siaddr(31 downto 16); -- SIADDR[31:16] when 65 => - v.txMaster.tData(7 downto 0) := x"FF"; -- Endmark - v.txMaster.tKeep := x"0001"; - v.txMaster.tLast := '1'; + v.txMaster.tData(7 downto 0) := x"FF"; -- Endmark + v.txMaster.tKeep(15 downto 0) := x"0001"; + v.txMaster.tLast := '1'; -- Start the communication timer - v.commCnt := COMM_TIMEOUT_C; + v.commCnt := COMM_TIMEOUT_C; -- Reset the counter - v.cnt := 0; + v.cnt := 0; -- Next state - v.state := IDLE_S; + v.state := IDLE_S; when others => null; end case; @@ -497,7 +495,7 @@ begin v.index := r.index + 1; end if; -- Check for last transfer - if (rxMaster.tLast = '1') and (getTKeep(tKeep) = (r.index+1)) then + if (rxMaster.tLast = '1') and (getTKeep(tKeep,DHCP_CONFIG_C) = (r.index+1)) then -- Check for no EOFE if ssiGetUserEofe(DHCP_CONFIG_C, rxMaster) = '0' then -- Next state diff --git a/ethernet/UdpEngine/rtl/UdpEngineRx.vhd b/ethernet/UdpEngine/rtl/UdpEngineRx.vhd index ec95542bee..766398b7f0 100644 --- a/ethernet/UdpEngine/rtl/UdpEngineRx.vhd +++ b/ethernet/UdpEngine/rtl/UdpEngineRx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : UdpEngineRx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-20 --- Last update: 2017-10-18 ------------------------------------------------------------------------------- -- Description: UDP RX Engine Module -- Note: UDP checksum checked in EthMac core @@ -182,7 +180,7 @@ begin -- Check for SOF with no EOF if (ssiGetUserSof(EMAC_AXIS_CONFIG_C, rxMaster) = '1') and (rxMaster.tLast = '0') then -- Latch the first header - v.tData := rxMaster.tData; + v.tData := rxMaster.tData(127 downto 0); -- Next state v.state := CHECK_PORT_S; end if; @@ -315,10 +313,10 @@ begin -- Next state v.state := LAST_S; else - v.serverMaster.tKeep := rxMaster.tKeep(11 downto 0) & x"F"; - v.serverMaster.tLast := '1'; + v.serverMaster.tKeep(15 downto 0) := rxMaster.tKeep(11 downto 0) & x"F"; + v.serverMaster.tLast := '1'; -- Next state - v.state := IDLE_S; + v.state := IDLE_S; end if; end if; end if; @@ -362,8 +360,8 @@ begin -- Next state v.state := LAST_S; else - v.clientMaster.tKeep := rxMaster.tKeep(11 downto 0) & x"F"; - v.clientMaster.tLast := '1'; + v.clientMaster.tKeep(15 downto 0) := rxMaster.tKeep(11 downto 0) & x"F"; + v.clientMaster.tLast := '1'; -- Next state v.state := IDLE_S; end if; @@ -417,39 +415,39 @@ begin -- Check if ready to move data if (v.serverMaster.tValid = '0') then -- Move the data - v.serverMaster.tValid := '1'; - v.serverMaster.tData := r.tData; - v.serverMaster.tKeep := genTKeep(conv_integer(r.byteCnt)); - v.serverMaster.tLast := '1'; + v.serverMaster.tValid := '1'; + v.serverMaster.tData(127 downto 0) := r.tData; + v.serverMaster.tKeep := genTKeep(conv_integer(r.byteCnt)); + v.serverMaster.tLast := '1'; ssiSetUserSof(EMAC_AXIS_CONFIG_C, v.serverMaster, r.sof); -- Next state - v.state := IDLE_S; + v.state := IDLE_S; end if; ---------------------------------------------------------------------- when CLIENT_S => -- Check if ready to move data if (v.clientMaster.tValid = '0') then -- Move the data - v.clientMaster.tValid := '1'; - v.clientMaster.tData := r.tData; - v.clientMaster.tKeep := genTKeep(conv_integer(r.byteCnt)); - v.clientMaster.tLast := '1'; + v.clientMaster.tValid := '1'; + v.clientMaster.tData(127 downto 0) := r.tData; + v.clientMaster.tKeep := genTKeep(conv_integer(r.byteCnt)); + v.clientMaster.tLast := '1'; ssiSetUserSof(EMAC_AXIS_CONFIG_C, v.clientMaster, r.sof); -- Next state - v.state := IDLE_S; + v.state := IDLE_S; end if; ---------------------------------------------------------------------- when DHCP_S => -- Check if ready to move data if (v.dhcpMaster.tValid = '0') then -- Move the data - v.dhcpMaster.tValid := '1'; - v.dhcpMaster.tData := r.tData; - v.dhcpMaster.tKeep := genTKeep(conv_integer(r.byteCnt)); - v.dhcpMaster.tLast := '1'; + v.dhcpMaster.tValid := '1'; + v.dhcpMaster.tData(127 downto 0) := r.tData; + v.dhcpMaster.tKeep := genTKeep(conv_integer(r.byteCnt)); + v.dhcpMaster.tLast := '1'; ssiSetUserSof(EMAC_AXIS_CONFIG_C, v.dhcpMaster, r.sof); -- Next state - v.state := IDLE_S; + v.state := IDLE_S; end if; ---------------------------------------------------------------------- when NULL_S => diff --git a/ethernet/UdpEngine/rtl/UdpEngineTx.vhd b/ethernet/UdpEngine/rtl/UdpEngineTx.vhd index e5b181d93c..8cda0fd60d 100644 --- a/ethernet/UdpEngine/rtl/UdpEngineTx.vhd +++ b/ethernet/UdpEngine/rtl/UdpEngineTx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : UdpEngineTx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-20 --- Last update: 2016-09-16 ------------------------------------------------------------------------------- -- Description: UDP TX Engine Module -- Note: UDP checksum checked in EthMac core @@ -339,13 +337,13 @@ begin -- Check if ready to move data if (v.txMaster.tValid = '0') then -- Move the data - v.txMaster.tValid := '1'; - v.txMaster.tData := r.tData; - v.txMaster.tKeep := r.tKeep; - v.txMaster.tLast := '1'; + v.txMaster.tValid := '1'; + v.txMaster.tData(127 downto 0) := r.tData; + v.txMaster.tKeep(15 downto 0) := r.tKeep; + v.txMaster.tLast := '1'; ssiSetUserEofe(EMAC_AXIS_CONFIG_C, v.txMaster, r.eofe); -- Next state - v.state := IDLE_S; + v.state := IDLE_S; end if; ---------------------------------------------------------------------- end case; diff --git a/ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd b/ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd index 0e890310f6..5f92cbe299 100644 --- a/ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd +++ b/ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : UdpEngineWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-20 --- Last update: 2017-10-18 ------------------------------------------------------------------------------- -- Description: Wrapper for UdpEngine ------------------------------------------------------------------------------- diff --git a/ethernet/UdpEngine/tb/UdpEngineCoreTb.vhd b/ethernet/UdpEngine/tb/UdpEngineCoreTb.vhd index d75a287d4f..bd75574943 100644 --- a/ethernet/UdpEngine/tb/UdpEngineCoreTb.vhd +++ b/ethernet/UdpEngine/tb/UdpEngineCoreTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : UdpEngineCoreTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-17 --- Last update: 2015-08-25 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the UdpEngineCore module ------------------------------------------------------------------------------- @@ -196,7 +194,7 @@ begin end if; end loop; -- Check for errors - if (v.tKeep /= obClientMaster.tKeep) then + if (v.tKeep /= obClientMaster.tKeep(15 downto 0)) then v.failed(3) := '1'; end if; -- Check the counter @@ -211,7 +209,7 @@ begin v.failed(4) := '1'; end if; -- Check for full word transfer and full size - if (obClientMaster.tKeep = x"FFFF") and (r.rxWordCnt = 63) then + if (obClientMaster.tKeep(15 downto 0) = x"FFFF") and (r.rxWordCnt = 63) then -- Next state v.state := DONE_S; end if; diff --git a/ethernet/UdpEngine/tb/UdpEngineTb.vhd b/ethernet/UdpEngine/tb/UdpEngineTb.vhd index d3bd9faa97..38d898c215 100644 --- a/ethernet/UdpEngine/tb/UdpEngineTb.vhd +++ b/ethernet/UdpEngine/tb/UdpEngineTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : UdpEngineTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-17 --- Last update: 2015-08-28 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the UdpEngine module ------------------------------------------------------------------------------- diff --git a/ethernet/XauiCore/core/rtl/XauiPkg.vhd b/ethernet/XauiCore/core/rtl/XauiPkg.vhd index dffd69f560..a7024a6dd3 100644 --- a/ethernet/XauiCore/core/rtl/XauiPkg.vhd +++ b/ethernet/XauiCore/core/rtl/XauiPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : XauiPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-07 --- Last update: 2015-04-07 ------------------------------------------------------------------------------- -- Description: XAUI Package Files ------------------------------------------------------------------------------- diff --git a/ethernet/XauiCore/core/rtl/XauiReg.vhd b/ethernet/XauiCore/core/rtl/XauiReg.vhd index 13ad986a22..d2ad05046e 100644 --- a/ethernet/XauiCore/core/rtl/XauiReg.vhd +++ b/ethernet/XauiCore/core/rtl/XauiReg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : XauiReg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-07 --- Last update: 2018-01-22 ------------------------------------------------------------------------------- -- Description: AXI-Lite XAUI Register Interface ------------------------------------------------------------------------------- diff --git a/ethernet/XauiCore/gth7/rtl/.gitattributes b/ethernet/XauiCore/gth7/rtl/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/XauiCore/gth7/rtl/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd b/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd index fc1f35a942..041b2d31cb 100644 --- a/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd +++ b/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : XauiGth7.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-02-12 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: 10 GigE XAUI for Gth7 ------------------------------------------------------------------------------- @@ -26,11 +24,13 @@ use work.EthMacPkg.all; entity XauiGth7 is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -58,7 +58,7 @@ entity XauiGth7 is gtTxP : out slv(3 downto 0); gtTxN : out slv(3 downto 0); gtRxP : in slv(3 downto 0); - gtRxN : in slv(3 downto 0)); + gtRxN : in slv(3 downto 0)); end XauiGth7; architecture mapping of XauiGth7 is @@ -79,7 +79,7 @@ architecture mapping of XauiGth7 is signal macRxAxisCtrl : AxiStreamCtrlType; signal macTxAxisMaster : AxiStreamMasterType; signal macTxAxisSlave : AxiStreamSlaveType; - + begin phyClk <= phyClock; @@ -91,9 +91,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "XGMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "XGMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, @@ -112,7 +114,7 @@ begin xgmiiRxd => phyRxd, xgmiiRxc => phyRxc, xgmiiTxd => phyTxd, - xgmiiTxc => phyTxc); + xgmiiTxc => phyTxc); -------------------- -- 10 GigE XAUI Core @@ -151,7 +153,7 @@ begin signal_detect => (others => '1'), debug => status.debugVector, configuration_vector => config.configVector, - status_vector => status.statusVector); + status_vector => status.statusVector); status.phyReady <= uAnd(status.debugVector); @@ -165,7 +167,7 @@ begin TPD_G => TPD_G, IN_POLARITY_G => '1', OUT_POLARITY_G => '1', - RELEASE_DELAY_G => 4) + RELEASE_DELAY_G => 4) port map ( clk => gtRefClk, asyncRst => status.areset, @@ -176,19 +178,19 @@ begin TPD_G => TPD_G, IN_POLARITY_G => '0', OUT_POLARITY_G => '1', - RELEASE_DELAY_G => 4) + RELEASE_DELAY_G => 4) port map ( clk => gtRefClk, asyncRst => status.clkLock, - syncRst => phyReset); + syncRst => phyReset); -------------------------------- -- Configuration/Status Register -------------------------------- U_XauiReg : entity work.XauiReg generic map ( - TPD_G => TPD_G, - EN_AXI_REG_G => EN_AXI_REG_G) + TPD_G => TPD_G, + EN_AXI_REG_G => EN_AXI_REG_G) port map ( -- Local Configurations localMac => localMac, @@ -203,6 +205,6 @@ begin phyClk => phyClock, phyRst => phyReset, config => config, - status => status); + status => status); end mapping; diff --git a/ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd b/ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd index 00bd74fdc3..210165eac6 100644 --- a/ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd +++ b/ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : XauiGth7Core.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-02-12 --- Last update: 2016-02-19 ------------------------------------------------------------------------------- -- Description: 10 GigE XAUI for Gth7 Core ------------------------------------------------------------------------------- diff --git a/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd b/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd index c1de0e2971..39c8b2ea59 100644 --- a/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd +++ b/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : XauiGth7Wrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-07 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gth7 Wrapper for 10 GigE XAUI ------------------------------------------------------------------------------- @@ -29,14 +27,16 @@ use unisim.vcomponents.all; entity XauiGth7Wrapper is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- QUAD PLL Configurations - USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk - REFCLK_DIV2_G : boolean := false; -- FALSE: gtClkP/N = 156.25 MHz, TRUE: gtClkP/N = 312.5 MHz + USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk + REFCLK_DIV2_G : boolean := false; -- FALSE: gtClkP/N = 156.25 MHz, TRUE: gtClkP/N = 312.5 MHz -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -67,7 +67,7 @@ entity XauiGth7Wrapper is gtTxP : out slv(3 downto 0); gtTxN : out slv(3 downto 0); gtRxP : in slv(3 downto 0); - gtRxN : in slv(3 downto 0)); + gtRxN : in slv(3 downto 0)); end XauiGth7Wrapper; architecture mapping of XauiGth7Wrapper is @@ -85,7 +85,7 @@ begin IB => gtClkN, CEB => '0', ODIV2 => refClockDiv2, - O => refClock); + O => refClock); refClk <= gtRefClk when (USE_GTREFCLK_G) else refClockDiv2 when(REFCLK_DIV2_G) else refClock; @@ -94,11 +94,13 @@ begin ---------------------- XauiGth7_Inst : entity work.XauiGth7 generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G) + AXIS_CONFIG_G => AXIS_CONFIG_G) port map ( -- Local Configurations localMac => localMac, @@ -126,6 +128,6 @@ begin gtTxP => gtTxP, gtTxN => gtTxN, gtRxP => gtRxP, - gtRxN => gtRxN); + gtRxN => gtRxN); end mapping; diff --git a/ethernet/XauiCore/gthUltraScale+/ip/.gitattributes b/ethernet/XauiCore/gthUltraScale+/ip/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/XauiCore/gthUltraScale+/ip/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd index f08be9cede..2b1c289ea6 100644 --- a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd +++ b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : XauiGthUltraScale.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-08 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: 10 GigE XAUI for GTH Ultra Scale ------------------------------------------------------------------------------- @@ -29,13 +27,15 @@ use unisim.vcomponents.all; entity XauiGthUltraScale is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive range 1 to 1024 := 8; -- XAUI Configurations - REF_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz + REF_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -102,9 +102,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "XGMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "XGMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, @@ -262,8 +264,8 @@ begin -------------------------------- U_XauiReg : entity work.XauiReg generic map ( - TPD_G => TPD_G, - EN_AXI_REG_G => EN_AXI_REG_G) + TPD_G => TPD_G, + EN_AXI_REG_G => EN_AXI_REG_G) port map ( -- Local Configurations localMac => localMac, diff --git a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd index 43f3959ddc..e44d3987ed 100644 --- a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd +++ b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : XauiGthUltraScaleWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-08 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: GTH UltraScale+ Wrapper for 10 GigE XAUI ------------------------------------------------------------------------------- @@ -29,13 +27,15 @@ use unisim.vcomponents.all; entity XauiGthUltraScaleWrapper is generic ( - TPD_G : time := 1 ns; - EN_WDT_G : boolean := false; - STABLE_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive range 1 to 1024 := 8; + EN_WDT_G : boolean := false; + STABLE_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -133,11 +133,13 @@ begin ---------------------- XauiGthUltraScale_Inst : entity work.XauiGthUltraScale generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G) + AXIS_CONFIG_G => AXIS_CONFIG_G) port map ( -- Local Configurations localMac => localMac, diff --git a/ethernet/XauiCore/gthUltraScale/ip/.gitattributes b/ethernet/XauiCore/gthUltraScale/ip/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/XauiCore/gthUltraScale/ip/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd index 7238ea9edf..089d5064cc 100644 --- a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd +++ b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : XauiGthUltraScale.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-08 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: 10 GigE XAUI for GTH Ultra Scale ------------------------------------------------------------------------------- @@ -29,11 +27,13 @@ use unisim.vcomponents.all; entity XauiGthUltraScale is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -100,9 +100,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "XGMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "XGMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, @@ -256,8 +258,8 @@ begin -------------------------------- U_XauiReg : entity work.XauiReg generic map ( - TPD_G => TPD_G, - EN_AXI_REG_G => EN_AXI_REG_G) + TPD_G => TPD_G, + EN_AXI_REG_G => EN_AXI_REG_G) port map ( -- Local Configurations localMac => localMac, diff --git a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd index d5afe1535c..cdb05eb991 100644 --- a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd +++ b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : XauiGthUltraScaleWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-08 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: GTH Ultra Scale Wrapper for 10 GigE XAUI ------------------------------------------------------------------------------- @@ -30,6 +28,8 @@ use unisim.vcomponents.all; entity XauiGthUltraScaleWrapper is generic ( TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; EN_WDT_G : boolean := false; STABLE_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz -- AXI-Lite Configurations @@ -133,11 +133,13 @@ begin ---------------------- XauiGthUltraScale_Inst : entity work.XauiGthUltraScale generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G) + AXIS_CONFIG_G => AXIS_CONFIG_G) port map ( -- Local Configurations localMac => localMac, diff --git a/ethernet/XauiCore/gtx7/rtl/.gitattributes b/ethernet/XauiCore/gtx7/rtl/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/XauiCore/gtx7/rtl/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd b/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd index 4b3a6e6633..c097175a5a 100644 --- a/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd +++ b/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : XauiGtx7.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-02-12 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: 10 GigE XAUI for Gtx7 ------------------------------------------------------------------------------- @@ -26,11 +24,13 @@ use work.EthMacPkg.all; entity XauiGtx7 is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -58,7 +58,7 @@ entity XauiGtx7 is gtTxP : out slv(3 downto 0); gtTxN : out slv(3 downto 0); gtRxP : in slv(3 downto 0); - gtRxN : in slv(3 downto 0)); + gtRxN : in slv(3 downto 0)); end XauiGtx7; architecture mapping of XauiGtx7 is @@ -79,7 +79,7 @@ architecture mapping of XauiGtx7 is signal macRxAxisCtrl : AxiStreamCtrlType; signal macTxAxisMaster : AxiStreamMasterType; signal macTxAxisSlave : AxiStreamSlaveType; - + begin phyClk <= phyClock; @@ -91,9 +91,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "XGMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "XGMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, @@ -112,7 +114,7 @@ begin xgmiiRxd => phyRxd, xgmiiRxc => phyRxc, xgmiiTxd => phyTxd, - xgmiiTxc => phyTxc); + xgmiiTxc => phyTxc); -------------------- -- 10 GigE XAUI Core @@ -151,7 +153,7 @@ begin signal_detect => (others => '1'), debug => status.debugVector, configuration_vector => config.configVector, - status_vector => status.statusVector); + status_vector => status.statusVector); status.phyReady <= uAnd(status.debugVector); @@ -165,7 +167,7 @@ begin TPD_G => TPD_G, IN_POLARITY_G => '1', OUT_POLARITY_G => '1', - RELEASE_DELAY_G => 4) + RELEASE_DELAY_G => 4) port map ( clk => gtRefClk, asyncRst => status.areset, @@ -176,19 +178,19 @@ begin TPD_G => TPD_G, IN_POLARITY_G => '0', OUT_POLARITY_G => '1', - RELEASE_DELAY_G => 4) + RELEASE_DELAY_G => 4) port map ( clk => gtRefClk, asyncRst => status.clkLock, - syncRst => phyReset); + syncRst => phyReset); -------------------------------- -- Configuration/Status Register -------------------------------- U_XauiReg : entity work.XauiReg generic map ( - TPD_G => TPD_G, - EN_AXI_REG_G => EN_AXI_REG_G) + TPD_G => TPD_G, + EN_AXI_REG_G => EN_AXI_REG_G) port map ( -- Local Configurations localMac => localMac, @@ -203,6 +205,6 @@ begin phyClk => phyClock, phyRst => phyReset, config => config, - status => status); + status => status); end mapping; diff --git a/ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd b/ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd index 1e5ebf9e47..3df772633d 100644 --- a/ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd +++ b/ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : XauiGtx7Core.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-02-12 --- Last update: 2016-02-19 ------------------------------------------------------------------------------- -- Description: 10 GigE XAUI for Gtx7 ------------------------------------------------------------------------------- diff --git a/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd b/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd index dd899b041b..276ae1d110 100644 --- a/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd +++ b/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : XauiGtx7Wrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-07 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gtx7 Wrapper for 10 GigE XAUI ------------------------------------------------------------------------------- @@ -29,14 +27,16 @@ use unisim.vcomponents.all; entity XauiGtx7Wrapper is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- QUAD PLL Configurations - USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk - REFCLK_DIV2_G : boolean := false; -- FALSE: gtClkP/N = 156.25 MHz, TRUE: gtClkP/N = 312.5 MHz + USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk + REFCLK_DIV2_G : boolean := false; -- FALSE: gtClkP/N = 156.25 MHz, TRUE: gtClkP/N = 312.5 MHz -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -67,7 +67,7 @@ entity XauiGtx7Wrapper is gtTxP : out slv(3 downto 0); gtTxN : out slv(3 downto 0); gtRxP : in slv(3 downto 0); - gtRxN : in slv(3 downto 0)); + gtRxN : in slv(3 downto 0)); end XauiGtx7Wrapper; architecture mapping of XauiGtx7Wrapper is @@ -85,7 +85,7 @@ begin IB => gtClkN, CEB => '0', ODIV2 => refClockDiv2, - O => refClock); + O => refClock); refClk <= gtRefClk when (USE_GTREFCLK_G) else refClockDiv2 when(REFCLK_DIV2_G) else refClock; @@ -94,11 +94,13 @@ begin ---------------------- XauiGtx7_Inst : entity work.XauiGtx7 generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G) + AXIS_CONFIG_G => AXIS_CONFIG_G) port map ( -- Local Configurations localMac => localMac, @@ -126,6 +128,6 @@ begin gtTxP => gtTxP, gtTxN => gtTxN, gtRxP => gtRxP, - gtRxN => gtRxN); + gtRxN => gtRxN); end mapping; diff --git a/ethernet/XauiCore/gtyUltraScale+/ip/.gitattributes b/ethernet/XauiCore/gtyUltraScale+/ip/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/ethernet/XauiCore/gtyUltraScale+/ip/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/ethernet/XauiCore/gtyUltraScale+/ip/XauiGtyUltraScale156p25MHz10GigECore.dcp b/ethernet/XauiCore/gtyUltraScale+/ip/XauiGtyUltraScale156p25MHz10GigECore.dcp index 89a9385560..5b2ccd19b6 100644 --- a/ethernet/XauiCore/gtyUltraScale+/ip/XauiGtyUltraScale156p25MHz10GigECore.dcp +++ b/ethernet/XauiCore/gtyUltraScale+/ip/XauiGtyUltraScale156p25MHz10GigECore.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:215368a08c7c80d76c84be70d5c08cead1302de83632aa8c17f16311aa94f08d -size 996655 +oid sha256:1656bad4cae0d03c87dc9fdaa50ff4a3cd7b7afd8be618e2178dc1096dff624a +size 996556 diff --git a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd index 981294dd5d..19450c91b9 100644 --- a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd +++ b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : XauiGtyUltraScale.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-08 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: 10 GigE XAUI for GTH Ultra Scale ------------------------------------------------------------------------------- @@ -29,13 +27,15 @@ use unisim.vcomponents.all; entity XauiGtyUltraScale is generic ( - TPD_G : time := 1 ns; + TPD_G : time := 1 ns; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- XAUI Configurations - REF_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz + REF_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz -- AXI-Lite Configurations - EN_AXI_REG_G : boolean := false; + EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations - AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C); port ( -- Local Configurations localMac : in slv(47 downto 0) := MAC_ADDR_INIT_C; @@ -102,9 +102,11 @@ begin -------------------- U_MAC : entity work.EthMacTop generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "XGMII", - PRIM_CONFIG_G => AXIS_CONFIG_G) + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "XGMII", + PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( -- Primary Interface primClk => dmaClk, @@ -262,8 +264,8 @@ begin -------------------------------- U_XauiReg : entity work.XauiReg generic map ( - TPD_G => TPD_G, - EN_AXI_REG_G => EN_AXI_REG_G) + TPD_G => TPD_G, + EN_AXI_REG_G => EN_AXI_REG_G) port map ( -- Local Configurations localMac => localMac, diff --git a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd index 1838d608ea..8a86d9d679 100644 --- a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd +++ b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : XauiGtyUltraScaleWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-08 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: GTH UltraScale+ Wrapper for 10 GigE XAUI ------------------------------------------------------------------------------- @@ -32,6 +30,8 @@ entity XauiGtyUltraScaleWrapper is TPD_G : time := 1 ns; EN_WDT_G : boolean := false; STABLE_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive := 8; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations @@ -133,11 +133,13 @@ begin ---------------------- XauiGtyUltraScale_Inst : entity work.XauiGtyUltraScale generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, -- AXI-Lite Configurations - EN_AXI_REG_G => EN_AXI_REG_G, + EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations - AXIS_CONFIG_G => AXIS_CONFIG_G) + AXIS_CONFIG_G => AXIS_CONFIG_G) port map ( -- Local Configurations localMac => localMac, diff --git a/protocols/batcher/rtl/AxiStreamBatcher.vhd b/protocols/batcher/rtl/AxiStreamBatcher.vhd new file mode 100644 index 0000000000..35bc7c3afe --- /dev/null +++ b/protocols/batcher/rtl/AxiStreamBatcher.vhd @@ -0,0 +1,402 @@ +------------------------------------------------------------------------------- +-- File : AxiStreamBatcher.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: The firmware batcher combines sub-frames into a larger super-frame +-- https://confluence.slac.stanford.edu/x/th1SDg +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +use work.StdRtlPkg.all; +use work.AxiStreamPkg.all; +use work.SsiPkg.all; + +entity AxiStreamBatcher is + generic ( + TPD_G : time := 1 ns; + MAX_NUMBER_SUB_FRAMES_G : positive := 32; -- Units of sub-frames + SUPER_FRAME_BYTE_THRESHOLD_G : natural := 8192; -- Units of bytes + MAX_CLK_GAP_G : natural := 256; -- Units of clock cycles + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C; + INPUT_PIPE_STAGES_G : natural := 0; + OUTPUT_PIPE_STAGES_G : natural := 1); + port ( + -- Clock and Reset + axisClk : in sl; + axisRst : in sl; + -- External Control Interface + superFrameByteThreshold : in slv(31 downto 0) := toSlv(SUPER_FRAME_BYTE_THRESHOLD_G, 32); + maxSubFrames : in slv(15 downto 0) := toSlv(MAX_NUMBER_SUB_FRAMES_G, 16); + maxClkGap : in slv(11 downto 0) := toSlv(MAX_CLK_GAP_G, 12); + idle : out sl; + -- AXIS Interfaces + sAxisMaster : in AxiStreamMasterType; + sAxisSlave : out AxiStreamSlaveType; + mAxisMaster : out AxiStreamMasterType; + mAxisSlave : in AxiStreamSlaveType); +end entity AxiStreamBatcher; + +architecture rtl of AxiStreamBatcher is + + constant AXIS_WORD_SIZE_C : positive := AXIS_CONFIG_G.TDATA_BYTES_C; -- Units of bytes + + type StateType is ( + HEADER_S, + SUB_FRAME_S, + TAIL_S, + CHUNK_TAIL_2BYTE_S, + CHUNK_TAIL_4BYTE_S, + GAP_S); + + type RegType is record + superFrameByteThreshold : slv(31 downto 0); + superByteCnt : slv(31 downto 0); + subByteCnt : slv(31 downto 0); + maxSubFrames : slv(15 downto 0); + subFrameCnt : slv(15 downto 0); + maxClkGap : slv(11 downto 0); + clkGapCnt : slv(11 downto 0); + superFrameByteThresholdDet : sl; + maxSubFramesDet : sl; + seqCnt : slv(7 downto 0); + tDest : slv(7 downto 0); + tUserFirst : slv(7 downto 0); + tUserLast : slv(7 downto 0); + lastByteCnt : slv(7 downto 0); + chunkCnt : natural range 0 to 3; + rxSlave : AxiStreamSlaveType; + txMaster : AxiStreamMasterType; + state : StateType; + end record RegType; + + constant REG_INIT_C : RegType := ( + superFrameByteThreshold => toSlv(SUPER_FRAME_BYTE_THRESHOLD_G, 32), + superByteCnt => toSlv(AXIS_WORD_SIZE_C, 32), + subByteCnt => (others => '0'), + maxSubFrames => toSlv(MAX_NUMBER_SUB_FRAMES_G, 16), + subFrameCnt => (others => '0'), + maxClkGap => toSlv(MAX_CLK_GAP_G, 12), + clkGapCnt => (others => '0'), + superFrameByteThresholdDet => '0', + maxSubFramesDet => '0', + seqCnt => (others => '0'), + tDest => (others => '0'), + tUserFirst => (others => '0'), + tUserLast => (others => '0'), + lastByteCnt => (others => '0'), + chunkCnt => 1, + rxSlave => AXI_STREAM_SLAVE_INIT_C, + txMaster => AXI_STREAM_MASTER_INIT_C, + state => HEADER_S); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal rxMaster : AxiStreamMasterType; + signal rxSlave : AxiStreamSlaveType; + signal txMaster : AxiStreamMasterType; + signal txSlave : AxiStreamSlaveType; + +begin + + assert (AXIS_WORD_SIZE_C >= 2) + report "AXIS_CONFIG_G.TDATA_BYTES_C must be >= 2" severity error; + + ----------------- + -- Input pipeline + ----------------- + U_Input : entity work.AxiStreamPipeline + generic map ( + TPD_G => TPD_G, + PIPE_STAGES_G => INPUT_PIPE_STAGES_G) + port map ( + axisClk => axisClk, + axisRst => axisRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + mAxisMaster => rxMaster, + mAxisSlave => rxSlave); + + comb : process (axisRst, maxClkGap, maxSubFrames, r, rxMaster, + superFrameByteThreshold, txSlave) is + variable v : RegType; + + procedure doTail is + begin + -- Check for end of super-frame condition + if (v.superFrameByteThresholdDet = '1') or (v.maxSubFramesDet = '1') then + -- Move the outbound data + v.txMaster.tValid := '1'; + -- Terminate the super-frame + v.txMaster.tLast := '1'; + -- Next state + v.state := HEADER_S; + -- Check if new data to move or bypassing clock gap + elsif (rxMaster.tValid = '1') or (r.maxClkGap = 0) then + -- Move the outbound data + v.txMaster.tValid := '1'; + -- Next state + v.state := SUB_FRAME_S; + else + -- Next state + v.state := GAP_S; + end if; + end procedure doTail; + + begin + -- Latch the current value + v := r; + + -- Reset the strobes + v.rxSlave.tReady := '0'; + if (txSlave.tReady = '1') then + v.txMaster.tValid := '0'; + v.txMaster.tLast := '0'; + v.txMaster.tUser := (others => '0'); + end if; + + -- Check for max. super frame + if(r.superByteCnt = r.superFrameByteThreshold) and (r.superFrameByteThreshold /= 0) then + -- Set the flag + v.superFrameByteThresholdDet := '1'; + end if; + + -- Check for max. super frame + if(r.subFrameCnt = r.maxSubFrames) then + -- Set the flag + v.maxSubFramesDet := '1'; + end if; + + -- Main state machine + case r.state is + ---------------------------------------------------------------------- + when HEADER_S => + -- Reset the flag + v.superFrameByteThresholdDet := '0'; + v.maxSubFramesDet := '0'; + -- Sample external signals + v.superFrameByteThreshold := superFrameByteThreshold; + v.maxSubFrames := maxSubFrames; + v.maxClkGap := maxClkGap; + -- Floor the superFrameByteThreshold to nearest word increment + -- This is done to remove the ">" operator + v.superFrameByteThreshold(bitSize(AXIS_WORD_SIZE_C)-1 downto 0) := (others => '0'); + -- Check for zero byte superFrameByteThreshold case + if (v.superFrameByteThreshold = 0) then + -- Prevent zero case + v.superFrameByteThreshold := toSlv(AXIS_WORD_SIZE_C, 32); + end if; + -- Check for zero maxSubFrames case + if (v.maxSubFrames = 0) then + -- Prevent zero case + v.maxSubFrames := toSlv(1, 16); + end if; + -- Check if ready to move data + if (rxMaster.tValid = '1') and (v.txMaster.tValid = '0') then + -- Send the super-frame header + v.txMaster.tValid := '1'; + v.txMaster.tData(3 downto 0) := x"1"; -- Version = 0x1 + v.txMaster.tData(7 downto 4) := toSlv(log2(AXIS_WORD_SIZE_C/2), 4); + v.txMaster.tData(15 downto 8) := r.seqCnt; + v.txMaster.tData(127 downto 16) := (others => '0'); + ssiSetUserSof(AXIS_CONFIG_G, v.txMaster, '1'); + -- Increment the sequence counter + v.seqCnt := r.seqCnt + 1; + -- Next state + v.state := SUB_FRAME_S; + end if; + -- Reset the sub-frame counter + v.subFrameCnt := (others => '0'); + -- Preset the super-frame byte counter + v.superByteCnt := toSlv(AXIS_WORD_SIZE_C, 32); + ---------------------------------------------------------------------- + when SUB_FRAME_S => + -- Check if ready to move data + if (rxMaster.tValid = '1') and (v.txMaster.tValid = '0') then + -- Accept the inbound data + v.rxSlave.tReady := '1'; + -- Move the outbound data + v.txMaster.tValid := '1'; + v.txMaster.tData := rxMaster.tData; + -- Check if first transaction + if (r.subByteCnt = 0) then + -- Sample the first transaction + v.tUserFirst(AXIS_CONFIG_G.TUSER_BITS_C-1 downto 0) := axiStreamGetUserField(AXIS_CONFIG_G, rxMaster, 0); + -- Increment the sub-frame counter + v.subFrameCnt := r.subFrameCnt + 1; + end if; + -- Check for last transaction in sub-frame + if (rxMaster.tLast = '1') then + -- Get the number of valid bytes in the last transaction of the sub-frame + v.lastByteCnt := toSlv(getTKeep(rxMaster.tKeep, AXIS_CONFIG_G), 8); + -- Increment the sub-frame byte counter + v.subByteCnt := r.subByteCnt + getTKeep(rxMaster.tKeep, AXIS_CONFIG_G); + -- Sample the meta data + v.tUserLast(AXIS_CONFIG_G.TUSER_BITS_C-1 downto 0) := axiStreamGetUserField(AXIS_CONFIG_G, rxMaster); + v.tDest(AXIS_CONFIG_G.TDEST_BITS_C-1 downto 0) := rxMaster.tDest(AXIS_CONFIG_G.TDEST_BITS_C-1 downto 0); + -- Next state + v.state := TAIL_S; + else + -- Increment the sub-frame byte counter + v.subByteCnt := r.subByteCnt + AXIS_WORD_SIZE_C; + end if; + -- Increment the super-frame byte counter + v.superByteCnt := r.superByteCnt + AXIS_WORD_SIZE_C; + end if; + ---------------------------------------------------------------------- + when TAIL_S => + -- Check if ready to move data + if (v.txMaster.tValid = '0') then + -- Set the sub-frame tail data field + v.txMaster.tData := (others => '0'); + v.txMaster.tData(31 downto 0) := r.subByteCnt; + v.txMaster.tData(39 downto 32) := r.tDest; + v.txMaster.tData(47 downto 40) := r.tUserFirst; + v.txMaster.tData(55 downto 48) := r.tUserLast; + v.txMaster.tData(63 downto 56) := r.lastByteCnt; + -- Reset the counter + v.subByteCnt := (others => '0'); + -- Check the AXIS width + if (AXIS_WORD_SIZE_C = 2) then + -- Move the outbound data + v.txMaster.tValid := '1'; + -- Next state + v.state := CHUNK_TAIL_2BYTE_S; + elsif (AXIS_WORD_SIZE_C = 4) then + -- Move the outbound data + v.txMaster.tValid := '1'; + -- Next state + v.state := CHUNK_TAIL_4BYTE_S; + else + -- Process the tail + doTail; + end if; + -- Preset chunk counter + v.chunkCnt := 1; + -- Increment the super-frame byte counter + v.superByteCnt := r.superByteCnt + AXIS_WORD_SIZE_C; + end if; + ---------------------------------------------------------------------- + when CHUNK_TAIL_2BYTE_S => + -- Check if ready to move data + if (v.txMaster.tValid = '0') then + -- Shift the data + v.txMaster.tData(63 downto 0) := x"0000" & r.txMaster.tData(63 downto 16); + -- Check the chunking counter + if r.chunkCnt = 3 then + -- Process the tail + doTail; + else + -- Move the outbound data + v.txMaster.tValid := '1'; + -- Increment the counter + v.chunkCnt := r.chunkCnt + 1; + end if; + -- Increment the super-frame byte counter + v.superByteCnt := r.superByteCnt + AXIS_WORD_SIZE_C; + end if; + ---------------------------------------------------------------------- + when CHUNK_TAIL_4BYTE_S => + -- Check if ready to move data + if (v.txMaster.tValid = '0') then + -- Shift the data + v.txMaster.tData(63 downto 0) := x"0000_0000" & r.txMaster.tData(63 downto 32); + -- Check the chunking counter + if r.chunkCnt = 1 then + -- Process the tail + doTail; + else + -- Move the outbound data + v.txMaster.tValid := '1'; + -- Increment the counter + v.chunkCnt := r.chunkCnt + 1; + end if; + -- Increment the super-frame byte counter + v.superByteCnt := r.superByteCnt + AXIS_WORD_SIZE_C; + end if; + ---------------------------------------------------------------------- + when GAP_S => + -- Check for new sub-frame + if (rxMaster.tValid = '1') then + -- Reset the counter + v.clkGapCnt := (others => '0'); + -- Next state + v.state := SUB_FRAME_S; + -- Check for the clock gap event + elsif (r.clkGapCnt = r.maxClkGap) then + -- Check if ready to move data + if (v.txMaster.tValid = '0') then + -- Reset the counter + v.clkGapCnt := (others => '0'); + -- Move the outbound data + v.txMaster.tValid := '1'; + -- Terminate the super-frame + v.txMaster.tLast := '1'; + -- Next state + v.state := HEADER_S; + end if; + else + -- Increment the counter + v.clkGapCnt := r.clkGapCnt + 1; + end if; + ---------------------------------------------------------------------- + end case; + + -- Always the same outbound AXIS stream width + v.txMaster.tKeep := genTKeep(AXIS_WORD_SIZE_C); + v.txMaster.tStrb := genTKeep(AXIS_WORD_SIZE_C); + + -- Outputs + rxSlave <= v.rxSlave; + txMaster <= r.txMaster; + if (r.state = HEADER_S) then + idle <= '1'; + else + idle <= '0'; + end if; + + -- Reset + if (axisRst = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (axisClk) is + begin + if (rising_edge(axisClk)) then + r <= rin after TPD_G; + end if; + end process seq; + + ------------------ + -- Output pipeline + ------------------ + U_Output : entity work.AxiStreamPipeline + generic map ( + TPD_G => TPD_G, + PIPE_STAGES_G => OUTPUT_PIPE_STAGES_G) + port map ( + axisClk => axisClk, + axisRst => axisRst, + sAxisMaster => txMaster, + sAxisSlave => txSlave, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave); + +end rtl; diff --git a/protocols/batcher/rtl/AxiStreamBatcherEventBuilder.vhd b/protocols/batcher/rtl/AxiStreamBatcherEventBuilder.vhd new file mode 100644 index 0000000000..926c03b41d --- /dev/null +++ b/protocols/batcher/rtl/AxiStreamBatcherEventBuilder.vhd @@ -0,0 +1,263 @@ +------------------------------------------------------------------------------- +-- File : AxiStreamBatcherEventBuilder.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Wrapper on AxiStreamBatcher for multi-AXI stream event building +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +use work.StdRtlPkg.all; +use work.AxiStreamPkg.all; +use work.SsiPkg.all; + +entity AxiStreamBatcherEventBuilder is + generic ( + TPD_G : time := 1 ns; + + -- Number of Inbound AXIS stream SLAVES + NUM_SLAVES_G : positive := 2; + + -- In INDEXED mode, the output TDEST is set based on the selected slave index + -- In ROUTED mode, TDEST is set according to the TDEST_ROUTES_G table + MODE_G : string := "INDEXED"; + + -- In ROUTED mode, an array mapping how TDEST should be assigned for each slave port + -- Each TDEST bit can be set to '0', '1' or '-' for passthrough from slave TDEST. + TDEST_ROUTES_G : Slv8Array := (0 => "--------"); + + -- In INDEXED mode, assign slave index to TDEST at this bit offset + TDEST_LOW_G : integer range 0 to 7 := 0; + + AXIS_CONFIG_G : AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C; + INPUT_PIPE_STAGES_G : natural := 0; + OUTPUT_PIPE_STAGES_G : natural := 0); + port ( + -- Clock and Reset + axisClk : in sl; + axisRst : in sl; + -- AXIS Interfaces + sAxisMasters : in AxiStreamMasterArray(NUM_SLAVES_G-1 downto 0); + sAxisSlaves : out AxiStreamSlaveArray(NUM_SLAVES_G-1 downto 0); + mAxisMaster : out AxiStreamMasterType; + mAxisSlave : in AxiStreamSlaveType); +end entity AxiStreamBatcherEventBuilder; + +architecture rtl of AxiStreamBatcherEventBuilder is + + constant DEST_SIZE_C : integer := bitSize(NUM_SLAVES_G-1); + + type StateType is ( + IDLE_S, + MOVE_S); + + type RegType is record + ready : sl; + maxSubFrames : slv(15 downto 0); + accept : slv(NUM_SLAVES_G-1 downto 0); + index : natural range 0 to NUM_SLAVES_G-1; + rxSlaves : AxiStreamSlaveArray(NUM_SLAVES_G-1 downto 0); + txMaster : AxiStreamMasterType; + state : StateType; + end record RegType; + + constant REG_INIT_C : RegType := ( + ready => '0', + maxSubFrames => toSlv(NUM_SLAVES_G, 16), + accept => (others => '0'), + index => 0, + rxSlaves => (others => AXI_STREAM_SLAVE_INIT_C), + txMaster => AXI_STREAM_MASTER_INIT_C, + state => IDLE_S); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal sAxisMastersTmp : AxiStreamMasterArray(NUM_SLAVES_G-1 downto 0); + signal rxMasters : AxiStreamMasterArray(NUM_SLAVES_G-1 downto 0); + signal rxSlaves : AxiStreamSlaveArray(NUM_SLAVES_G-1 downto 0); + signal txMaster : AxiStreamMasterType; + signal txSlave : AxiStreamSlaveType; + + signal batcherIdle : sl; + +begin + + ------------------------- + -- Override Inbound TDEST + ------------------------- + TDEST_REMAP : process (sAxisMasters) is + variable tmp : AxiStreamMasterArray(NUM_SLAVES_G-1 downto 0); + variable i : natural; + variable j : natural; + begin + tmp := sAxisMasters; + for i in NUM_SLAVES_G-1 downto 0 loop + if MODE_G = "ROUTED" then + for j in 7 downto 0 loop + if (TDEST_ROUTES_G(i)(j) = '1') then + tmp(i).tDest(j) := '1'; + elsif(TDEST_ROUTES_G(i)(j) = '0') then + tmp(i).tDest(j) := '0'; + else + tmp(i).tDest(j) := sAxisMasters(i).tDest(j); + end if; + end loop; + else + tmp(i).tDest(7 downto TDEST_LOW_G) := (others => '0'); + tmp(i).tDest(DEST_SIZE_C+TDEST_LOW_G-1 downto TDEST_LOW_G) := toSlv(i, DEST_SIZE_C); + end if; + end loop; + sAxisMastersTmp <= tmp; + end process; + + ----------------- + -- Input pipeline + ----------------- + GEN_VEC : + for i in (NUM_SLAVES_G-1) downto 0 generate + U_Input : entity work.AxiStreamPipeline + generic map ( + TPD_G => TPD_G, + PIPE_STAGES_G => INPUT_PIPE_STAGES_G) + port map ( + axisClk => axisClk, + axisRst => axisRst, + sAxisMaster => sAxisMastersTmp(i), + sAxisSlave => sAxisSlaves(i), + mAxisMaster => rxMasters(i), + mAxisSlave => rxSlaves(i)); + end generate GEN_VEC; + + comb : process (axisRst, batcherIdle, r, rxMasters, txSlave) is + variable v : RegType; + variable i : natural; + begin + -- Latch the current value + v := r; + + -- Reset the flow control strobes + for i in (NUM_SLAVES_G-1) downto 0 loop + v.rxSlaves(i).tReady := '0'; + end loop; + if (txSlave.tReady = '1') then + v.txMaster.tValid := '0'; + end if; + + -- State machine + case r.state is + ---------------------------------------------------------------------- + when IDLE_S => + -- Loop through RX channels + v.ready := '1'; + for i in (NUM_SLAVES_G-1) downto 0 loop + -- Check if no data + if (rxMasters(i).tValid = '0') then + -- Reset the flag + v.ready := '0'; + else + -- Check for NULL frame (defined as a single word transaction with EOFE asserted and byte count = 1) + if (rxMasters(i).tLast = '1') and -- TLAST asserted + (ssiGetUserEofe(AXIS_CONFIG_G, rxMasters(i)) = '1') and -- EOFE flag set + (getTKeep(rxMasters(i).tKeep(AXIS_CONFIG_G.TDATA_BYTES_C-1 downto 0), AXIS_CONFIG_G) = 1) then -- byte count = 1 + -- NULL frame detected + v.accept(i) := '0'; + else + -- Normal frame detected + v.accept(i) := '1'; + end if; + end if; + end loop; + -- Check if ready to move data + if (batcherIdle = '1') and (r.ready = '1') then + -- Reset the flag + v.ready := '0'; + -- Set the sub-frame count + v.maxSubFrames := resize(onesCount(r.accept), 16); + -- Next state + v.state := MOVE_S; + end if; + ---------------------------------------------------------------------- + when MOVE_S => + -- Check if ready to move data + if (rxMasters(r.index).tValid = '1') and (v.txMaster.tValid = '0') then + -- Move the data + v.rxSlaves(r.index).tReady := '1'; + v.txMaster := rxMasters(r.index); + -- Only forward the non-NULL frames + v.txMaster.tValid := r.accept(r.index); + -- Check for the last transfer + if (rxMasters(r.index).tLast = '1') then + -- Check for last channel + if (r.index = NUM_SLAVES_G-1) then + -- Reset the counter + v.index := 0; + -- Next state + v.state := IDLE_S; + else + -- Increment the counter + v.index := r.index + 1; + end if; + end if; + end if; + ---------------------------------------------------------------------- + end case; + + -- Outputs + rxSlaves <= v.rxSlaves; + txMaster <= r.txMaster; + + -- Reset + if (axisRst = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (axisClk) is + begin + if (rising_edge(axisClk)) then + r <= rin after TPD_G; + end if; + end process seq; + + ------------------ + -- AxiStreamBatcher + ------------------ + U_AxiStreamBatcher : entity work.AxiStreamBatcher + generic map ( + TPD_G => TPD_G, + MAX_NUMBER_SUB_FRAMES_G => NUM_SLAVES_G, + SUPER_FRAME_BYTE_THRESHOLD_G => 0, -- 0 = bypass super threshold check + MAX_CLK_GAP_G => 0, -- 0 = bypass MAX clock GAP + AXIS_CONFIG_G => AXIS_CONFIG_G, + INPUT_PIPE_STAGES_G => 1, -- Break apart the long combinatorial tReady chain + OUTPUT_PIPE_STAGES_G => OUTPUT_PIPE_STAGES_G) + port map ( + -- Clock and Reset + axisClk => axisClk, + axisRst => axisRst, + -- External Control Interface + maxSubFrames => r.maxSubFrames, + idle => batcherIdle, + -- AXIS Interfaces + sAxisMaster => txMaster, + sAxisSlave => txSlave, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave); + +end rtl; diff --git a/protocols/batcher/ruckus.tcl b/protocols/batcher/ruckus.tcl new file mode 100644 index 0000000000..f988a4f0c1 --- /dev/null +++ b/protocols/batcher/ruckus.tcl @@ -0,0 +1,5 @@ +# Load RUCKUS library +source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl + +# Load Source Code +loadSource -dir "$::DIR_PATH/rtl" diff --git a/protocols/clink/hdl/ClinkCtrl.vhd b/protocols/clink/hdl/ClinkCtrl.vhd index f3e809989c..de912b27ad 100644 --- a/protocols/clink/hdl/ClinkCtrl.vhd +++ b/protocols/clink/hdl/ClinkCtrl.vhd @@ -1,7 +1,6 @@ ------------------------------------------------------------------------------- -- File : ClinkCtrl.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-13 ------------------------------------------------------------------------------- -- Description: -- CameraLink control interface. diff --git a/protocols/clink/hdl/ClinkData.vhd b/protocols/clink/hdl/ClinkData.vhd index 98b034baa8..42bd40db03 100644 --- a/protocols/clink/hdl/ClinkData.vhd +++ b/protocols/clink/hdl/ClinkData.vhd @@ -1,7 +1,6 @@ ------------------------------------------------------------------------------- -- File : ClinkData.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-13 ------------------------------------------------------------------------------- -- Description: -- CameraLink data de-serializer. diff --git a/protocols/clink/hdl/ClinkDataClk.vhd b/protocols/clink/hdl/ClinkDataClk.vhd index c9767ca7ae..b9c2225ced 100644 --- a/protocols/clink/hdl/ClinkDataClk.vhd +++ b/protocols/clink/hdl/ClinkDataClk.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : ClinkDataClk.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-10-28 --- Last update: 2016-08-24 ------------------------------------------------------------------------------- -- Description: A wrapper over MMCM ------------------------------------------------------------------------------- diff --git a/protocols/clink/hdl/ClinkDataShift.vhd b/protocols/clink/hdl/ClinkDataShift.vhd index dc744799cc..5bfeb6690b 100644 --- a/protocols/clink/hdl/ClinkDataShift.vhd +++ b/protocols/clink/hdl/ClinkDataShift.vhd @@ -1,7 +1,6 @@ ------------------------------------------------------------------------------- -- File : ClinkDataShift.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-13 ------------------------------------------------------------------------------- -- Description: -- Block to de-serialize a block of 28 bits packed into 4 7-bit serial streams. diff --git a/protocols/clink/hdl/ClinkFraming.vhd b/protocols/clink/hdl/ClinkFraming.vhd index 884897461d..682d828e3a 100644 --- a/protocols/clink/hdl/ClinkFraming.vhd +++ b/protocols/clink/hdl/ClinkFraming.vhd @@ -1,7 +1,6 @@ ------------------------------------------------------------------------------- -- File : ClinkFraming.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-13 ------------------------------------------------------------------------------- -- Description: -- CameraLink framing module diff --git a/protocols/clink/hdl/ClinkPkg.vhd b/protocols/clink/hdl/ClinkPkg.vhd index e56a37ce5c..0e0df76676 100644 --- a/protocols/clink/hdl/ClinkPkg.vhd +++ b/protocols/clink/hdl/ClinkPkg.vhd @@ -1,7 +1,6 @@ ------------------------------------------------------------------------------- -- File : ClinkPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-13 ------------------------------------------------------------------------------- -- Description: -- CameraLink Package diff --git a/protocols/clink/hdl/ClinkTop.vhd b/protocols/clink/hdl/ClinkTop.vhd index 639d2533fd..0e3d23a182 100644 --- a/protocols/clink/hdl/ClinkTop.vhd +++ b/protocols/clink/hdl/ClinkTop.vhd @@ -1,7 +1,6 @@ ------------------------------------------------------------------------------- -- File : ClinkTop.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-13 ------------------------------------------------------------------------------- -- Description: -- CameraLink Top Level diff --git a/protocols/clink/hdl/ClinkUart.vhd b/protocols/clink/hdl/ClinkUart.vhd index b85e7c1d87..05dad207a4 100644 --- a/protocols/clink/hdl/ClinkUart.vhd +++ b/protocols/clink/hdl/ClinkUart.vhd @@ -1,7 +1,6 @@ ------------------------------------------------------------------------------- -- File : ClinkUart.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-13 ------------------------------------------------------------------------------- -- Description: -- CameraLink UART RX/TX diff --git a/protocols/clink/sim/ClinkFramerTb.vhd b/protocols/clink/sim/ClinkFramerTb.vhd index 1e331629ce..d0b727f8ac 100755 --- a/protocols/clink/sim/ClinkFramerTb.vhd +++ b/protocols/clink/sim/ClinkFramerTb.vhd @@ -1,6 +1,5 @@ ------------------------------------------------------------------------------- -- File : ClinkFramerTb.vhd --- Created : 2017-11-13 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for clink framer ------------------------------------------------------------------------------- diff --git a/protocols/glink/core/rtl/GLinkDecoder.vhd b/protocols/glink/core/rtl/GLinkDecoder.vhd index decc73af65..23d861a878 100644 --- a/protocols/glink/core/rtl/GLinkDecoder.vhd +++ b/protocols/glink/core/rtl/GLinkDecoder.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GlinkDecoder.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-03-12 --- Last update: 2015-12-07 ------------------------------------------------------------------------------- -- Description: Decoder for the Condition Inversion Master Transition coding -- used by the GLink Protocol. diff --git a/protocols/glink/core/rtl/GLinkEncoder.vhd b/protocols/glink/core/rtl/GLinkEncoder.vhd index 17e4dd97f3..e134a4c71f 100644 --- a/protocols/glink/core/rtl/GLinkEncoder.vhd +++ b/protocols/glink/core/rtl/GLinkEncoder.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GLinkEncoder.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-04-19 --- Last update: 2017-05-05 ------------------------------------------------------------------------------- -- Description: Encodes 16 bit data raw words into 20 bit GLink words. ------------------------------------------------------------------------------- diff --git a/protocols/glink/core/rtl/GLinkPkg.vhd b/protocols/glink/core/rtl/GLinkPkg.vhd index 66cb9e679e..b71153ba8d 100644 --- a/protocols/glink/core/rtl/GLinkPkg.vhd +++ b/protocols/glink/core/rtl/GLinkPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GlinkDecoder.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-03-12 --- Last update: 2014-10-24 ------------------------------------------------------------------------------- -- Description: A collection of common constants and functions intended for -- use encoding/decoding the GLink Protocol. diff --git a/protocols/glink/core/rtl/GLinkTxToRx.vhd b/protocols/glink/core/rtl/GLinkTxToRx.vhd index 28fa07e532..5da0ed7a76 100644 --- a/protocols/glink/core/rtl/GLinkTxToRx.vhd +++ b/protocols/glink/core/rtl/GLinkTxToRx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GLinkTxToRx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-20 --- Last update: 2014-05-20 ------------------------------------------------------------------------------- -- Description: Wrapper for GLinkEncoder/GLinkDecoder loopback testing ------------------------------------------------------------------------------- diff --git a/protocols/glink/gtp7/rtl/GLinkGtp7FixedLat.vhd b/protocols/glink/gtp7/rtl/GLinkGtp7FixedLat.vhd index 55371e3645..61b9114217 100644 --- a/protocols/glink/gtp7/rtl/GLinkGtp7FixedLat.vhd +++ b/protocols/glink/gtp7/rtl/GLinkGtp7FixedLat.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GLinkGtp7FixedLat.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-01-30 --- Last update: 2017-05-08 ------------------------------------------------------------------------------- -- Description: G-Link wrapper for GTP7 transceiver ------------------------------------------------------------------------------- diff --git a/protocols/glink/gtx7/rtl/GLinkGtx7Core.vhd b/protocols/glink/gtx7/rtl/GLinkGtx7Core.vhd index 28c1d715c5..410d30ca32 100644 --- a/protocols/glink/gtx7/rtl/GLinkGtx7Core.vhd +++ b/protocols/glink/gtx7/rtl/GLinkGtx7Core.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Gtx7Core.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-12-17 --- Last update: 2017-05-08 ------------------------------------------------------------------------------- -- Description: G-Link wrapper for GTX7 primitive ------------------------------------------------------------------------------- diff --git a/protocols/glink/gtx7/rtl/GLinkGtx7FixedLat.vhd b/protocols/glink/gtx7/rtl/GLinkGtx7FixedLat.vhd index 6b52157656..6fcf2c6a60 100644 --- a/protocols/glink/gtx7/rtl/GLinkGtx7FixedLat.vhd +++ b/protocols/glink/gtx7/rtl/GLinkGtx7FixedLat.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GLinkGtx7FixedLat.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-01-30 --- Last update: 2015-02-23 ------------------------------------------------------------------------------- -- Description: G-Link wrapper for GTX7 Fixed Latency transceiver ------------------------------------------------------------------------------- diff --git a/protocols/glink/gtx7/rtl/GLinkGtx7RxRst.vhd b/protocols/glink/gtx7/rtl/GLinkGtx7RxRst.vhd index 48846a74f7..5296c374e8 100644 --- a/protocols/glink/gtx7/rtl/GLinkGtx7RxRst.vhd +++ b/protocols/glink/gtx7/rtl/GLinkGtx7RxRst.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GLinkGtx7RxRst.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-12-17 --- Last update: 2014-11-10 ------------------------------------------------------------------------------- -- Description: G-Link GTX7 Reset module ------------------------------------------------------------------------------- diff --git a/protocols/glink/gtx7/tb/GLinkGtx7FixedLatTb.vhd b/protocols/glink/gtx7/tb/GLinkGtx7FixedLatTb.vhd index 3b426fc24d..a647b10336 100644 --- a/protocols/glink/gtx7/tb/GLinkGtx7FixedLatTb.vhd +++ b/protocols/glink/gtx7/tb/GLinkGtx7FixedLatTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : GLinkGtx7FixedLatTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-02-03 --- Last update: 2014-02-03 ------------------------------------------------------------------------------- -- Description: Simulation testbed for GLinkGtx7FixedLat ------------------------------------------------------------------------------- diff --git a/protocols/i2c/rtl/AxiI2cEeprom.vhd b/protocols/i2c/rtl/AxiI2cEeprom.vhd index 5671df6622..532d31228a 100644 --- a/protocols/i2c/rtl/AxiI2cEeprom.vhd +++ b/protocols/i2c/rtl/AxiI2cEeprom.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiI2cEeprom.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-07-11 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Wrapper for AxiI2cEepromCore -- diff --git a/protocols/i2c/rtl/AxiI2cEepromCore.vhd b/protocols/i2c/rtl/AxiI2cEepromCore.vhd index 36e58059a0..ee700c73b7 100644 --- a/protocols/i2c/rtl/AxiI2cEepromCore.vhd +++ b/protocols/i2c/rtl/AxiI2cEepromCore.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiI2cEepromCore.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-07-11 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AXI-Lite Read/ModifyWrite for standard EEPROM Module -- diff --git a/protocols/i2c/rtl/AxiI2cMasterCore.vhd b/protocols/i2c/rtl/AxiI2cMasterCore.vhd deleted file mode 100644 index 016e58bb67..0000000000 --- a/protocols/i2c/rtl/AxiI2cMasterCore.vhd +++ /dev/null @@ -1,114 +0,0 @@ -------------------------------------------------------------------------------- --- File : AxiI2cMasterCore.vhd --- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-22 --- Last update: 2018-03-07 -------------------------------------------------------------------------------- --- Description: AXI-Lite interface to generic I2C master controller -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.StdRtlPkg.all; -use work.AxiLitePkg.all; -use work.I2cPkg.all; -use work.AxiI2cMasterPkg.all; - -library unisim; -use unisim.vcomponents.all; - -entity AxiI2cMasterCore is - generic ( - TPD_G : time := 1 ns; - DEVICE_MAP_G : I2cAxiLiteDevArray := I2C_AXIL_DEV_ARRAY_DEFAULT_C; - AXI_CLK_FREQ_G : real := 200.0E+6; -- units of Hz - I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz - I2C_MIN_PULSE_G : real := 100.0E-9); -- units of seconds - port ( - -- DAC Ports - i2cInOut : inout AxiI2cMasterInOutType; - -- AXI-Lite Register Interface - axiReadMaster : in AxiLiteReadMasterType; - axiReadSlave : out AxiLiteReadSlaveType; - axiWriteMaster : in AxiLiteWriteMasterType; - axiWriteSlave : out AxiLiteWriteSlaveType; - -- Clocks and Resets - axiClk : in sl; - axiRst : in sl); -end AxiI2cMasterCore; - -architecture mapping of AxiI2cMasterCore is - - -- Note: PRESCALE_G = (clk_freq / (5 * i2c_freq)) - 1 - -- FILTER_G = (min_pulse_time / clk_period) + 1 - constant I2C_SCL_5xFREQ_C : real := 5.0 * I2C_SCL_FREQ_G; - constant PRESCALE_C : natural := (getTimeRatio(AXI_CLK_FREQ_G, I2C_SCL_5xFREQ_C)) - 1; - constant FILTER_C : natural := natural(AXI_CLK_FREQ_G * I2C_MIN_PULSE_G) + 1; - - signal i2cRegMasterIn : I2cRegMasterInType; - signal i2cRegMasterOut : I2cRegMasterOutType; - - signal i2ci : i2c_in_type; - signal i2co : i2c_out_type; - -begin - - IOBUF_SCL : IOBUF - port map ( - O => i2ci.scl, -- Buffer output - IO => i2cInOut.scl, -- Buffer inout port (connect directly to top-level port) - I => i2co.scl, -- Buffer input - T => i2co.scloen); -- 3-state enable input, high=input, low=output - - IOBUF_SDA : IOBUF - port map ( - O => i2ci.sda, -- Buffer output - IO => i2cInOut.sda, -- Buffer inout port (connect directly to top-level port) - I => i2co.sda, -- Buffer input - T => i2co.sdaoen); -- 3-state enable input, high=input, low=output - - I2cRegMasterAxiBridge_Inst : entity work.I2cRegMasterAxiBridge - generic map ( - TPD_G => TPD_G, - DEVICE_MAP_G => DEVICE_MAP_G, - EN_USER_REG_G => false) - port map ( - -- I2C Interface - i2cRegMasterIn => i2cRegMasterIn, - i2cRegMasterOut => i2cRegMasterOut, - -- AXI-Lite Register Interface - axiReadMaster => axiReadMaster, - axiReadSlave => axiReadSlave, - axiWriteMaster => axiWriteMaster, - axiWriteSlave => axiWriteSlave, - -- Clock and Reset - axiClk => axiClk, - axiRst => axiRst); - - I2cRegMaster_Inst : entity work.I2cRegMaster - generic map( - TPD_G => TPD_G, - OUTPUT_EN_POLARITY_G => 0, - FILTER_G => FILTER_C, - PRESCALE_G => PRESCALE_C) - port map ( - -- I2C Port Interface - i2ci => i2ci, - i2co => i2co, - -- I2C Register Interface - regIn => i2cRegMasterIn, - regOut => i2cRegMasterOut, - -- Clock and Reset - clk => axiClk, - srst => axiRst); - -end mapping; diff --git a/protocols/i2c/rtl/AxiI2cMasterPkg.vhd b/protocols/i2c/rtl/AxiI2cMasterPkg.vhd deleted file mode 100644 index b8da53f6e5..0000000000 --- a/protocols/i2c/rtl/AxiI2cMasterPkg.vhd +++ /dev/null @@ -1,35 +0,0 @@ -------------------------------------------------------------------------------- --- File : AxiI2cRegMaster.vhd --- Company : SLAC National Accelerator Laboratory --- Created : 2015-07-08 --- Last update: 2016-09-20 -------------------------------------------------------------------------------- --- Description: AXI-Lite I2C Master Package File -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.StdRtlPkg.all; - -package AxiI2cMasterPkg is - - type AxiI2cMasterInOutType is record - scl : sl; -- Two wire serial ID interface clock line (SCL) - sda : sl; -- Two wire serial ID interface data line (SDA) - end record; - type AxiI2cMasterInOutArray is array (natural range <>) of AxiI2cMasterInOutType; - type AxiI2cMasterInOutVectorArray is array (integer range<>, integer range<>)of AxiI2cMasterInOutType; - constant AXI_SFP_IN_OUT_INIT_C : AxiI2cMasterInOutType := ( - 'Z', - 'Z'); - -end package; diff --git a/protocols/i2c/rtl/AxiI2cRegMaster.vhd b/protocols/i2c/rtl/AxiI2cRegMaster.vhd index 56aaa425ff..11d50b108a 100644 --- a/protocols/i2c/rtl/AxiI2cRegMaster.vhd +++ b/protocols/i2c/rtl/AxiI2cRegMaster.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiI2cRegMaster.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-07-08 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: AXI-Lite I2C Register Master ------------------------------------------------------------------------------- @@ -27,23 +25,24 @@ use unisim.vcomponents.all; entity AxiI2cRegMaster is generic ( - TPD_G : time := 1 ns; - DEVICE_MAP_G : I2cAxiLiteDevArray := I2C_AXIL_DEV_ARRAY_DEFAULT_C; - I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz - I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds - AXI_CLK_FREQ_G : real := 156.25E+6); -- units of Hz + TPD_G : time := 1 ns; + DEVICE_MAP_G : I2cAxiLiteDevArray := I2C_AXIL_DEV_ARRAY_DEFAULT_C; + I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz + I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds + AXI_CLK_FREQ_G : real := 156.25E+6); -- units of Hz port ( - -- I2C Ports - scl : inout sl; - sda : inout sl; + -- Clocks and Resets + axiClk : in sl; + axiRst : in sl; -- AXI-Lite Register Interface axiReadMaster : in AxiLiteReadMasterType; axiReadSlave : out AxiLiteReadSlaveType; axiWriteMaster : in AxiLiteWriteMasterType; axiWriteSlave : out AxiLiteWriteSlaveType; - -- Clocks and Resets - axiClk : in sl; - axiRst : in sl); + -- I2C Ports + scl : inout sl; + sda : inout sl); + end AxiI2cRegMaster; architecture mapping of AxiI2cRegMaster is @@ -64,8 +63,8 @@ begin I2cRegMasterAxiBridge_Inst : entity work.I2cRegMasterAxiBridge generic map ( - TPD_G => TPD_G, - DEVICE_MAP_G => DEVICE_MAP_G) + TPD_G => TPD_G, + DEVICE_MAP_G => DEVICE_MAP_G) port map ( -- I2C Register Interface i2cRegMasterIn => i2cRegMasterIn, diff --git a/protocols/i2c/rtl/I2cPkg.vhd b/protocols/i2c/rtl/I2cPkg.vhd index 49d28fc880..c802ef390d 100644 --- a/protocols/i2c/rtl/I2cPkg.vhd +++ b/protocols/i2c/rtl/I2cPkg.vhd @@ -195,11 +195,11 @@ package I2cPkg is clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL -- input signals - start, - stop, - read, - write, - ack_in : std_logic; + start : in std_logic; + stop : in std_logic; + read : in std_logic; + write : in std_logic; + ack_in : in std_logic; din : in std_logic_vector(7 downto 0); filt : in std_logic_vector((filter-1)*dynfilt downto 0); diff --git a/protocols/i2c/rtl/I2cRegMaster.vhd b/protocols/i2c/rtl/I2cRegMaster.vhd index fdb029b377..2938b2c9a1 100644 --- a/protocols/i2c/rtl/I2cRegMaster.vhd +++ b/protocols/i2c/rtl/I2cRegMaster.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : I2cRegMaster.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-01-22 --- Last update: 2016-07-11 ------------------------------------------------------------------------------- -- Description: -- PRESCALE_G = (clk_freq / (5 * i2c_freq)) - 1 diff --git a/protocols/i2c/rtl/I2cRegMasterAxiBridge.vhd b/protocols/i2c/rtl/I2cRegMasterAxiBridge.vhd index 85ea3df705..aa653d0631 100644 --- a/protocols/i2c/rtl/I2cRegMasterAxiBridge.vhd +++ b/protocols/i2c/rtl/I2cRegMasterAxiBridge.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : I2cRegMasterAxiBridge.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-09-23 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Maps a number of I2C devices on an I2C bus onto an AXI Bus. ------------------------------------------------------------------------------- @@ -28,11 +26,7 @@ entity I2cRegMasterAxiBridge is generic ( TPD_G : time := 1 ns; - DEVICE_MAP_G : I2cAxiLiteDevArray := I2C_AXIL_DEV_ARRAY_DEFAULT_C; - EN_USER_REG_G : boolean := false; - NUM_WRITE_REG_G : integer range 1 to 128 := 1; - NUM_READ_REG_G : integer range 1 to 128 := 1); - + DEVICE_MAP_G : I2cAxiLiteDevArray := I2C_AXIL_DEV_ARRAY_DEFAULT_C); port ( axiClk : in sl; axiRst : in sl; @@ -42,11 +36,6 @@ entity I2cRegMasterAxiBridge is axiWriteMaster : in AxiLiteWriteMasterType; axiWriteSlave : out AxiLiteWriteSlaveType; - -- Optional User Read/Write Register Interface - readRegister : in Slv32Array(0 to NUM_READ_REG_G) := (others => x"00000000"); - writeRegisterInit : in Slv32Array(0 to NUM_WRITE_REG_G) := (others => x"00000000"); - writeRegister : out Slv32Array(0 to NUM_WRITE_REG_G); - i2cRegMasterIn : out I2cRegMasterInType; i2cRegMasterOut : in I2cRegMasterOutType); @@ -66,11 +55,7 @@ architecture rtl of I2cRegMasterAxiBridge is constant I2C_REG_AXI_ADDR_LOW_C : natural := 2; constant I2C_REG_AXI_ADDR_HIGH_C : natural := ite(I2C_REG_ADDR_SIZE_C = 0, - ite(EN_USER_REG_G = false, - 2, - --else (EN_USER_REG_G = true) - 8), -- Need minimum size of 8 if user regs enabled - -- else (I2C_REG_ADDR_SIZE_C > 0) + 2, I2C_REG_AXI_ADDR_LOW_C + I2C_REG_ADDR_SIZE_C-1); subtype I2C_REG_AXI_ADDR_RANGE_C is natural range @@ -86,21 +71,13 @@ architecture rtl of I2cRegMasterAxiBridge is subtype I2C_DEV_AXI_ADDR_RANGE_C is natural range I2C_DEV_AXI_ADDR_HIGH_C downto I2C_DEV_AXI_ADDR_LOW_C; - constant USER_AXI_ADDR_HIGH_C : natural := I2C_DEV_AXI_ADDR_HIGH_C+1; - constant USER_AXI_ADDR_LOW_C : natural := I2C_DEV_AXI_ADDR_HIGH_C+1; - - subtype USER_AXI_ADDR_RANGE_C is natural range - USER_AXI_ADDR_HIGH_C downto USER_AXI_ADDR_LOW_C; - type RegType is record - writeRegister : Slv32Array(0 to NUM_WRITE_REG_G); axiReadSlave : AxiLiteReadSlaveType; axiWriteSlave : AxiLiteWriteSlaveType; i2cRegMasterIn : I2cRegMasterInType; end record RegType; constant REG_INIT_C : RegType := ( - writeRegister => (others => x"00000000"), axiReadSlave => AXI_LITE_READ_SLAVE_INIT_C, axiWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, i2cRegMasterIn => I2C_REG_MASTER_IN_INIT_C); @@ -108,32 +85,12 @@ architecture rtl of I2cRegMasterAxiBridge is signal r : RegType := REG_INIT_C; signal rin : RegType; --- attribute keep : string; --- attribute keep of --- axiReadMaster, --- axiReadSlave, --- axiWriteMaster, --- axiWriteSlave, --- i2cRegMasterOut, --- i2cRegMasterIn : signal is "TRUE"; - --- attribute dont_touch : string; --- attribute dont_touch of --- axiReadMaster, --- axiReadSlave, --- axiWriteMaster, --- axiWriteSlave, --- i2cRegMasterOut, --- i2cRegMasterIn : signal is "TRUE"; - - begin ------------------------------------------------------------------------------------------------- -- Main Comb Process ------------------------------------------------------------------------------------------------- - comb : process (axiReadMaster, axiRst, axiWriteMaster, i2cRegMasterOut, r, readRegister, - writeRegisterInit) is + comb : process (axiReadMaster, axiRst, axiWriteMaster, i2cRegMasterOut, r) is variable v : RegType; variable devInt : integer; variable axiStatus : AxiLiteStatusType; @@ -169,8 +126,7 @@ begin if (axiStatus.writeEnable = '1') then - -- Decode address and perform write - if (axiWriteMaster.awaddr(USER_AXI_ADDR_RANGE_C) = "0" or not EN_USER_REG_G) then + -- I2C Address Space -- Decode i2c device address and send command to I2cRegMaster devInt := conv_integer(axiWriteMaster.awaddr(I2C_DEV_AXI_ADDR_RANGE_C)); @@ -179,25 +135,7 @@ begin v.i2cRegMasterIn.regOp := '1'; -- Write v.i2cRegMasterIn.regReq := '1'; - -- User Configuration Address Space - elsif (axiWriteMaster.awaddr(USER_AXI_ADDR_RANGE_C) = "1") and (EN_USER_REG_G = true) then - -- Check for valid address space range - if (axiWriteMaster.awaddr(8 downto 2) < NUM_WRITE_REG_G) and (axiWriteMaster.awaddr(9) = '1') then - -- Write the the User Register space - v.writeRegister(conv_integer(axiWriteMaster.awaddr(7 downto 2))) := axiWriteMaster.wdata; - -- Send AXI response - axiSlaveWriteResponse(v.axiWriteSlave); - else - -- Send AXI Error response - axiSlaveWriteResponse(v.axiWriteSlave, AXI_RESP_DECERR_C); - end if; - else - -- Send AXI Error response - axiSlaveWriteResponse(v.axiWriteSlave, AXI_RESP_DECERR_C); - end if; elsif (axiStatus.readEnable = '1') then - -- Decode address and perform write - if (axiReadMaster.araddr(USER_AXI_ADDR_RANGE_C) = "0" or not EN_USER_REG_G) then -- I2C Address Space -- Decode i2c device address and send command to I2cRegMaster devInt := conv_integer(axiReadMaster.araddr(I2C_DEV_AXI_ADDR_RANGE_C)); @@ -207,29 +145,6 @@ begin v.i2cRegMasterIn.regOp := '0'; -- Read v.i2cRegMasterIn.regReq := '1'; - -- User Configuration Address Space - elsif (axiReadMaster.araddr(USER_AXI_ADDR_RANGE_C) = "1") and (EN_USER_REG_G = true) then - -- Check for valid address space range - if (axiReadMaster.araddr(8 downto 2) < NUM_WRITE_REG_G) and (axiReadMaster.araddr(9) = '0') then - -- Write the the User Register space - v.axiReadSlave.rdata := r.writeRegister(conv_integer(axiReadMaster.araddr(7 downto 2))); - -- Send AXI response - axiSlaveWriteResponse(v.axiWriteSlave); - -- Check for valid address space range - elsif (axiReadMaster.araddr(8 downto 2) < NUM_READ_REG_G) and (axiReadMaster.araddr(9) = '1') then - -- Write the the User Register space - v.axiReadSlave.rdata := readRegister(conv_integer(axiReadMaster.araddr(7 downto 2))); - -- Send AXI response - axiSlaveWriteResponse(v.axiWriteSlave); - else - -- Send AXI Error response - axiSlaveWriteResponse(v.axiWriteSlave, AXI_RESP_DECERR_C); - end if; - else - -- Send AXI Error response - axiSlaveWriteResponse(v.axiWriteSlave, AXI_RESP_DECERR_C); - end if; - end if; if (i2cRegMasterOut.regAck = '1' and r.i2cRegMasterIn.regReq = '1') then @@ -252,7 +167,6 @@ begin ---------------------------------------------------------------------------------------------- if (axiRst = '1') then v := REG_INIT_C; - v.writeRegister := writeRegisterInit; end if; rin <= v; @@ -260,7 +174,6 @@ begin axiReadSlave <= r.axiReadSlave; axiWriteSlave <= r.axiWriteSlave; i2cRegMasterIn <= r.i2cRegMasterIn; - writeRegister <= r.writeRegister; end process comb; diff --git a/protocols/i2c/rtl/I2cRegMasterMux.vhd b/protocols/i2c/rtl/I2cRegMasterMux.vhd index b75122b9c1..9029cf3ebf 100644 --- a/protocols/i2c/rtl/I2cRegMasterMux.vhd +++ b/protocols/i2c/rtl/I2cRegMasterMux.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : I2cRegMasterMux.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-09-21 --- Last update: 2018-06-27 ------------------------------------------------------------------------------- -- Description: Multiplexes access to a single I2cRegMaster module -- Attached devices may also lock others out in order to execute multiple diff --git a/protocols/i2c/rtl/I2cRegSlave.vhd b/protocols/i2c/rtl/I2cRegSlave.vhd index 8815d08acf..d2147aa238 100644 --- a/protocols/i2c/rtl/I2cRegSlave.vhd +++ b/protocols/i2c/rtl/I2cRegSlave.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : I2cRegSlave.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-01-16 --- Last update: 2014-03-13 ------------------------------------------------------------------------------- -- Description: Implements an I2C slave attached to a generic RAM interface. -- Protocol is simple: Address of configurable size, followed by data of diff --git a/protocols/i2c/rtl/i2c_master_byte_ctrl.vhd b/protocols/i2c/rtl/i2c_master_byte_ctrl.vhd index dce9332dd3..5df99cdec9 100644 --- a/protocols/i2c/rtl/i2c_master_byte_ctrl.vhd +++ b/protocols/i2c/rtl/i2c_master_byte_ctrl.vhd @@ -91,13 +91,13 @@ entity i2c_master_byte_ctrl is clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL -- input signals - start, - stop, - read, - write, - ack_in : std_logic; + start : in std_logic; + stop : in std_logic; + read : in std_logic; + write : in std_logic; + ack_in : in std_logic; din : in std_logic_vector(7 downto 0); - filt : in std_logic_vector((filter-1)*dynfilt downto 0); + filt : in std_logic_vector((filter-1)*dynfilt downto 0); -- output signals cmd_ack : out std_logic; -- command done diff --git a/protocols/i2c/sim/i2cRamSlave.vhd b/protocols/i2c/sim/i2cRamSlave.vhd index 49f45f343f..ae51f59870 100644 --- a/protocols/i2c/sim/i2cRamSlave.vhd +++ b/protocols/i2c/sim/i2cRamSlave.vhd @@ -2,8 +2,6 @@ -- File : i2cRamSlave.vhd -- Author : Benjamin Reese -- Company : SLAC National Accelerator Laboratory --- Created : 2013-01-24 --- Last update: 2013-01-28 ------------------------------------------------------------------------------- -- Description: Simulation testbed for i2cRamSlave ------------------------------------------------------------------------------- diff --git a/protocols/i2c/sim/i2cRegMasterSimPkg.vhd b/protocols/i2c/sim/i2cRegMasterSimPkg.vhd index edd759d79b..890c359f79 100644 --- a/protocols/i2c/sim/i2cRegMasterSimPkg.vhd +++ b/protocols/i2c/sim/i2cRegMasterSimPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : i2cRegMasterSimPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-01-24 --- Last update: 2013-01-28 ------------------------------------------------------------------------------- -- Description: Simulation Package file for i2cRegMasterPkg ------------------------------------------------------------------------------- diff --git a/protocols/i2c/sim/i2cRegTb.vhd b/protocols/i2c/sim/i2cRegTb.vhd index 8e796a60dc..fb60716758 100644 --- a/protocols/i2c/sim/i2cRegTb.vhd +++ b/protocols/i2c/sim/i2cRegTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : i2cRegTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-01-24 --- Last update: 2013-01-28 ------------------------------------------------------------------------------- -- Description: Simulation testbed for i2cReg ------------------------------------------------------------------------------- diff --git a/protocols/jesd204b/example/Jesd204bRxGthUltra.vhd b/protocols/jesd204b/example/Jesd204bRxGthUltra.vhd deleted file mode 100644 index f8ee0456c4..0000000000 --- a/protocols/jesd204b/example/Jesd204bRxGthUltra.vhd +++ /dev/null @@ -1,357 +0,0 @@ -------------------------------------------------------------------------------- --- File : Jesd204bRxGthUltra.vhd --- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-14 --- Last update: 2018-01-08 -------------------------------------------------------------------------------- --- Description: JESD204b receiver module containing the GTH Ultrascale MGT --- Wrapper module for JESD receiver. --- GTH coregen generated core 2 GTH modules --- Note: Intended only for two serial lanes L_G=2. --- 7.4 GHz lane rate and 370MHz reference, Freerunning clk 185 MHz --- If different amount of lanes or freq is required the Core has to be regenerated --- by Xilinx Coregen. -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -library unisim; -use unisim.vcomponents.all; - -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; - -use work.StdRtlPkg.all; -use work.AxiLitePkg.all; -use work.AxiStreamPkg.all; -use work.SsiPkg.all; -use work.Jesd204bPkg.all; - -entity Jesd204bRxGthUltra is - generic ( - TPD_G : time := 1 ns; - - -- Test tx module instead of GTX - TEST_G : boolean := false; - - -- Internal SYSREF SYSREF_GEN_G= TRUE else - -- External SYSREF - SYSREF_GEN_G : boolean := false; - - -- JESD generics - ---------------------------------------------------------------------------------------------- - F_G : positive := 2; - K_G : positive := 32; - L_G : positive := 2 - ); - - port ( - -- GT Interface - ---------------------------------------------------------------------------------------------- - -- GT Clocking - stableClk : in sl; -- GT needs a stable clock to "boot up"(buffered refClkDiv2) - refClk : in sl; -- GT Reference clock directly from GT GTH diff. input buffer - -- Gt Serial IO - gtTxP : out slv(L_G-1 downto 0); -- GT Serial Transmit Positive - gtTxN : out slv(L_G-1 downto 0); -- GT Serial Transmit Negative - gtRxP : in slv(L_G-1 downto 0); -- GT Serial Receive Positive - gtRxN : in slv(L_G-1 downto 0); -- GT Serial Receive Negative - - -- User clocks and resets - ---------------------------------------------------------------------------------------------- - devClk_i : in sl; -- Device clock also rxUsrClkIn for MGT - devClk2_i : in sl; -- Device clock divided by 2 also rxUsrClk2In for MGT - devRst_i : in sl; -- - - -- AXI interface - ------------------------------------------------------------------------------------------------ - axiClk : in sl; - axiRst : in sl; - - -- AXI-Lite Register Interface - axilReadMaster : in AxiLiteReadMasterType; - axilReadSlave : out AxiLiteReadSlaveType; - axilWriteMaster : in AxiLiteWriteMasterType; - axilWriteSlave : out AxiLiteWriteSlaveType; - - -- AXI Streaming Interface - rxAxisMasterArr : out AxiStreamMasterArray(L_G-1 downto 0); - rxCtrlArr : in AxiStreamCtrlArray(L_G-1 downto 0); - - -- JESD - ------------------------------------------------------------------------------------------------ - - -- SYSREF for subclass 1 fixed latency - sysRef_i : in sl; - - -- SYSREF out when it is generated internally SYSREF_GEN_G=True - sysRef_o : out sl; - - -- Synchronization output combined from all receivers - nSync_o : out sl; - - -- Out to led - leds_o : out slv(1 downto 0); - - -- Rising edge pulses for test - pulse_o : out slv(L_G-1 downto 0); - - -- Out to led - qPllLock_o : out sl - ); -end Jesd204bRxGthUltra; - -architecture rtl of Jesd204bRxGthUltra is ---------------------------------------- - component gthultrascalejesdcoregen - port ( - gtwiz_userclk_tx_reset_in : in slv(0 downto 0); - gtwiz_userclk_tx_active_in : in slv(0 downto 0); - gtwiz_userclk_rx_active_in : in slv(0 downto 0); - gtwiz_reset_clk_freerun_in : in slv(0 downto 0); - gtwiz_reset_all_in : in slv(0 downto 0); - gtwiz_reset_tx_pll_and_datapath_in : in slv(0 downto 0); - gtwiz_reset_tx_datapath_in : in slv(0 downto 0); - gtwiz_reset_rx_pll_and_datapath_in : in slv(0 downto 0); - gtwiz_reset_rx_datapath_in : in slv(0 downto 0); - gtwiz_reset_rx_cdr_stable_out : out slv(0 downto 0); - gtwiz_reset_tx_done_out : out slv(0 downto 0); - gtwiz_reset_rx_done_out : out slv(0 downto 0); - gtwiz_userdata_tx_in : in slv((2*GT_WORD_SIZE_C*8)-1 downto 0); - gtwiz_userdata_rx_out : out slv((2*GT_WORD_SIZE_C*8)-1 downto 0); - drpclk_in : in slv(1 downto 0); - gthrxn_in : in slv(1 downto 0); - gthrxp_in : in slv(1 downto 0); - gtrefclk0_in : in slv(1 downto 0); - rx8b10ben_in : in slv(1 downto 0); - rxcommadeten_in : in slv(1 downto 0); - rxmcommaalignen_in : in slv(1 downto 0); - rxpcommaalignen_in : in slv(1 downto 0); - rxpolarity_in : in slv(1 downto 0); - rxusrclk_in : in slv(1 downto 0); - rxusrclk2_in : in slv(1 downto 0); - tx8b10ben_in : in slv(1 downto 0); - rxbufreset_in : in slv(1 downto 0); - txctrl0_in : in slv(31 downto 0); - txctrl1_in : in slv(31 downto 0); - txctrl2_in : in slv(15 downto 0); - txpolarity_in : in slv(1 downto 0); - txusrclk_in : in slv(1 downto 0); - txusrclk2_in : in slv(1 downto 0); - gthtxn_out : out slv(1 downto 0); - gthtxp_out : out slv(1 downto 0); - rxbyteisaligned_out : out slv(1 downto 0); - rxbyterealign_out : out slv(1 downto 0); - rxcommadet_out : out slv(1 downto 0); - rxctrl0_out : out slv(31 downto 0); - rxctrl1_out : out slv(31 downto 0); - rxctrl2_out : out slv(15 downto 0); - rxctrl3_out : out slv(15 downto 0); - rxoutclk_out : out slv(1 downto 0); - rxpmaresetdone_out : out slv(1 downto 0); - txoutclk_out : out slv(1 downto 0); - txpmaresetdone_out : out slv(1 downto 0) - ); - end component; -------------------------------------- - --- Internal signals - signal r_jesdGtRxArr : jesdGtRxLaneTypeArray(L_G-1 downto 0); - - -- Rx Channel Bonding - -- signal rxChBondLevel : slv(2 downto 0); - signal rxChBondIn : Slv5Array(L_G-1 downto 0); - signal rxChBondOut : Slv5Array(L_G-1 downto 0); - - -- GT reset - signal s_gtUserReset : slv(L_G-1 downto 0); - signal s_gtReset : sl; - - -- Generated or external - signal s_sysRef, s_sysRefDbg : sl; - - -- GT signals - signal s_rxctrl0 : slv(31 downto 0); - signal s_rxctrl1 : slv(31 downto 0); - signal s_rxctrl2 : slv(15 downto 0); - signal s_rxctrl3 : slv(15 downto 0); - - signal s_data : slv((2*GT_WORD_SIZE_C*8)-1 downto 0); - - signal s_devClkVec : slv(1 downto 0); - signal s_devClk2Vec : slv(1 downto 0); - signal s_stableClkVec : slv(1 downto 0); - signal s_gtRefClkVec : slv(1 downto 0); - signal s_rxDone : sl; - - signal s_nSync : sl; - signal s_validVec : slv(1 downto 0); - signal s_allignEnVec : slv(1 downto 0); - -begin - nSync_o <= s_nSync; - s_allignEnVec <= not s_validVec; - - -------------------------------------------------------------------------------------------------- - -- JESD receiver core - -------------------------------------------------------------------------------------------------- - Jesd204b_INST: entity work.Jesd204bRx - generic map ( - TPD_G => TPD_G, - TEST_G => TEST_G, - F_G => F_G, - K_G => K_G, - L_G => L_G) - port map ( - axiClk => axiClk, - axiRst => axiRst, - axilReadMaster => axilReadMaster, - axilReadSlave => axilReadSlave, - axilWriteMaster => axilWriteMaster, - axilWriteSlave => axilWriteSlave, - rxAxisMasterArr_o => rxAxisMasterArr, - rxCtrlArr_i => rxCtrlArr, - devClk_i => devClk_i, - devRst_i => devRst_i, - sysRef_i => s_sysRef, - sysRefDbg_o => s_sysRefDbg, - r_jesdGtRxArr => r_jesdGtRxArr, - gtRxReset_o => s_gtUserReset, - sampleDataArr_o => open, -- DAQ handled internally - dataValidVec_o => s_validVec, -- DAQ handled internally - nSync_o => s_nSync, - pulse_o => pulse_o, - leds_o => leds_o - ); - -------------------------------------------------------------------------------------------------- - -- Generate the internal or external SYSREF depending on SYSREF_GEN_G - -------------------------------------------------------------------------------------------------- - -- IF DEF SYSREF_GEN_G - SELF_TEST_GEN: if SYSREF_GEN_G = true generate - -- Generate the sysref internally - -- Sysref period will be 8x K_G. - SysrefGen_INST: entity work.LmfcGen - generic map ( - TPD_G => TPD_G, - K_G => 256, - F_G => 2) - port map ( - clk => devClk_i, - rst => devRst_i, - nSync_i => '0', - sysref_i => '0', - lmfc_o => s_sysRef - ); - sysRef_o <= s_sysRef; - end generate SELF_TEST_GEN; - -- Else - OPER_GEN: if SYSREF_GEN_G = false generate - s_sysRef <= sysRef_i; - sysRef_o <= s_sysRefDbg; - end generate OPER_GEN; - - -------------------------------------------------------------------------------------------------- - -- GTH signals assignments. Only for L_G = 2 - -------------------------------------------------------------------------------------------------- - s_gtReset <= devRst_i or uOr(s_gtUserReset); - - r_jesdGtRxArr(0).data <= s_data((GT_WORD_SIZE_C*8)-1 downto 0); - r_jesdGtRxArr(1).data <= s_data((2*GT_WORD_SIZE_C*8)-1 downto (GT_WORD_SIZE_C*8)); - - r_jesdGtRxArr(0).dataK <= s_rxctrl0(GT_WORD_SIZE_C-1 downto 0); - r_jesdGtRxArr(1).dataK <= s_rxctrl0(16+GT_WORD_SIZE_C-1 downto 16); - - r_jesdGtRxArr(0).dispErr <= s_rxctrl1(GT_WORD_SIZE_C-1 downto 0); - r_jesdGtRxArr(1).dispErr <= s_rxctrl1(16+GT_WORD_SIZE_C-1 downto 16); - - r_jesdGtRxArr(0).decErr <= s_rxctrl3(GT_WORD_SIZE_C-1 downto 0); - r_jesdGtRxArr(1).decErr <= s_rxctrl3(8+GT_WORD_SIZE_C-1 downto 8); - - r_jesdGtRxArr(0).rstDone <= s_rxDone; - r_jesdGtRxArr(1).rstDone <= s_rxDone; - - s_devClkVec <= devClk_i & devClk_i; - s_devClk2Vec <= devClk2_i & devClk2_i; - s_stableClkVec <= stableClk & stableClk; - s_gtRefClkVec <= refClk & refClk; - - qPllLock_o <= s_rxDone; - - -------------------------------------------------------------------------------------------------- - -- Include Core from Coregen Vivado 15.1 - -- Coregen settings: - -- - Lane rate 7.4 GHz - -- - Reference freq 184 MHz - -- - 8b10b enabled - -- - 32b/40b word datapath - -- - Comma detection has to be enabled to any byte boundary - IMPORTANT - -------------------------------------------------------------------------------------------------- - GT_OPER_GEN: if TEST_G = false generate - GthUltrascaleJesdCoregen_INST: GthUltrascaleJesdCoregen - port map ( - -- Clocks - gtwiz_userclk_tx_reset_in(0) => s_gtReset, - gtwiz_userclk_tx_active_in(0) => '1', - gtwiz_userclk_rx_active_in(0) => '1', - gtwiz_reset_clk_freerun_in(0) => stableClk, - - gtwiz_reset_all_in(0) => '0', - gtwiz_reset_tx_pll_and_datapath_in(0) => '0', - gtwiz_reset_tx_datapath_in(0) => s_gtReset, - gtwiz_reset_rx_pll_and_datapath_in(0) => '0', - gtwiz_reset_rx_datapath_in(0) => s_gtReset, - gtwiz_reset_rx_cdr_stable_out => open, - gtwiz_reset_tx_done_out => open, - gtwiz_reset_rx_done_out(0) => s_rxDone, - gtwiz_userdata_tx_in => (s_data'range =>'0'), - gtwiz_userdata_rx_out => s_data, - drpclk_in => s_stableClkVec, - gthrxn_in => gtRxN, - gthrxp_in => gtRxP, - gtrefclk0_in => s_gtRefClkVec, - - tx8b10ben_in => "00", - txctrl0_in => X"0000_0000", - txctrl1_in => X"0000_0000", - txctrl2_in => X"0000", - txpolarity_in => "00", - txusrclk_in => s_devClkVec, - txusrclk2_in => s_devClk2Vec, - gthtxn_out => gtTxN, - gthtxp_out => gtTxP, - txoutclk_out => open, - txpmaresetdone_out => open, - - -- RX settings - rx8b10ben_in => "11", - rxbufreset_in => "00", - rxcommadeten_in => "11", - rxmcommaalignen_in => s_allignEnVec, - rxpcommaalignen_in => s_allignEnVec, - rxpolarity_in => "11", -- TODO Check - rxusrclk_in => s_devClkVec, - rxusrclk2_in => s_devClk2Vec, - - rxbyteisaligned_out => open, - rxbyterealign_out => open, - rxcommadet_out => open, - rxctrl0_out => s_rxctrl0, -- x"000" & r_jesdGtRxArr(1).dataK & X"000" & r_jesdGtRxArr(0).dataK, - rxctrl1_out => s_rxctrl1, -- x"000" & r_jesdGtRxArr(1).dispErr & X"000" & r_jesdGtRxArr(0).dispErr, - rxctrl2_out => s_rxctrl2, -- open -- comma detected on corresponding byte - rxctrl3_out => s_rxctrl3, -- x"0" & r_jesdGtRxArr(1).decErr & X"0" & r_jesdGtRxArr(0).decErr, - rxoutclk_out => open, - rxpmaresetdone_out => open - ); - ----------------------------------------- - end generate GT_OPER_GEN; - ----------------------------------------------------- -end rtl; diff --git a/protocols/jesd204b/example/Jesd204bRxGtx7.vhd b/protocols/jesd204b/example/Jesd204bRxGtx7.vhd deleted file mode 100644 index 02382b0048..0000000000 --- a/protocols/jesd204b/example/Jesd204bRxGtx7.vhd +++ /dev/null @@ -1,413 +0,0 @@ -------------------------------------------------------------------------------- --- File : Jesd204bRxGtx7.vhd --- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-14 --- Last update: 2018-01-08 -------------------------------------------------------------------------------- --- Description: JESD204b receiver module containing the gtx7 MGT --- Framework module for JESD receiver module. --- Contains generic settings for GTX7 Receiver -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -library unisim; -use unisim.vcomponents.all; - -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; - -use work.StdRtlPkg.all; -use work.AxiLitePkg.all; -use work.AxiStreamPkg.all; -use work.SsiPkg.all; -use work.Jesd204bPkg.all; - -entity Jesd204bRxGtx7 is - generic ( - TPD_G : time := 1 ns; - - -- Test tx module instead of GTX - TEST_G : boolean := false; - - -- Internal SYSREF SYSREF_GEN_G= TRUE else - -- External SYSREF - SYSREF_GEN_G : boolean := false; - - -- GT Settings - ---------------------------------------------------------------------------------------------- - -- Sim Generics - SIM_GTRESET_SPEEDUP_G : string := "FALSE"; - SIM_VERSION_G : string := "4.0"; - STABLE_CLOCK_PERIOD_G : real := 4.0E-9; --units of seconds (default to longest timeout) - - -- CPLL Settings - CPLL_REFCLK_SEL_G : bit_vector := "001"; - CPLL_FBDIV_G : integer; -- use getGtx7CPllCfg to set - CPLL_FBDIV_45_G : integer; -- use getGtx7CPllCfg to set - CPLL_REFCLK_DIV_G : integer; -- use getGtx7CPllCfg to set - - RXOUT_DIV_G : integer; -- use getGtx7CPllCfg or to getGtx7QPllCfg set - RX_CLK25_DIV_G : integer; -- use getGtx7CPllCfg or to getGtx7QPllCfg set - - -- MGT Configurations - PMA_RSV_G : bit_vector := x"001E7080"; -- Values from coregen - RX_OS_CFG_G : bit_vector := "0000010000000"; -- Values from coregen - RXCDR_CFG_G : bit_vector := x"03000023ff10400020"; -- Values from coregen DF - RXDFEXYDEN_G : sl := '1'; -- Values from coregen DF - RX_DFE_KL_CFG2_G : bit_vector := X"301148AC"; -- Values from coregen DF - - -- Configure PLL sources - TX_PLL_G : string; -- "QPLL" or "CPLL" - RX_PLL_G : string; -- "QPLL" or "CPLL" - - -- TX defaults not currently used - TXOUT_DIV_G : integer := 2; - TX_CLK25_DIV_G : integer := 7; - TX_BUF_EN_G : boolean := true; - TX_OUTCLK_SRC_G : string := "OUTCLKPMA"; - TX_DLY_BYPASS_G : sl := '1'; - TX_PHASE_ALIGN_G : string := "NONE"; - TX_BUF_ADDR_MODE_G : string := "FULL"; - - -- JESD generics - ---------------------------------------------------------------------------------------------- - F_G : positive := 2; - K_G : positive := 32; - L_G : positive := 2 - ); - - port ( - -- GT Interface - ---------------------------------------------------------------------------------------------- - -- Recovered clock output - rxOutClkOut : out slv(L_G-1 downto 0); - txOutClkOut : out slv(L_G-1 downto 0); - - -- GT Clocking - stableClk : in sl; -- GT needs a stable clock to "boot up"(buffered refClkDiv2) - - -- QPLL - qPllRefClkIn : in sl; - qPllClkIn : in sl; - qPllLockIn : in sl; - qPllRefClkLostIn : in sl; - qPllResetOut : out slv(L_G-1 downto 0); - - -- CPLL - cPllRefClkIn : in sl; - cPllLockOut : out slv(L_G-1 downto 0); - - -- Gt Serial IO - gtTxP : out slv(L_G-1 downto 0); -- GT Serial Transmit Positive - gtTxN : out slv(L_G-1 downto 0); -- GT Serial Transmit Negative - gtRxP : in slv(L_G-1 downto 0); -- GT Serial Receive Positive - gtRxN : in slv(L_G-1 downto 0); -- GT Serial Receive Negative - - -- User clocks and resets - ---------------------------------------------------------------------------------------------- - devClk_i : in sl; -- Device clock also rxUsrClkIn for MGT - devClk2_i : in sl; -- Device clock divided by 2 also rxUsrClk2In for MGT - devRst_i : in sl; -- - - -- AXI interface - ------------------------------------------------------------------------------------------------ - axiClk : in sl; - axiRst : in sl; - - -- AXI-Lite Register Interface - axilReadMaster : in AxiLiteReadMasterType; - axilReadSlave : out AxiLiteReadSlaveType; - axilWriteMaster : in AxiLiteWriteMasterType; - axilWriteSlave : out AxiLiteWriteSlaveType; - - -- AXI Streaming Interface - rxAxisMasterArr : out AxiStreamMasterArray(L_G-1 downto 0); - rxCtrlArr : in AxiStreamCtrlArray(L_G-1 downto 0); - - -- JESD - ------------------------------------------------------------------------------------------------ - - -- SYSREF for subclass 1 fixed latency - sysRef_i : in sl; - - -- SYSREF out when it is generated internally SYSREF_GEN_G=True - sysRef_o : out sl; - - -- Synchronization output combined from all receivers - nSync_o : out sl; - - -- Out to led - leds_o : out slv(1 downto 0); - - -- Rising edge pulses for test - pulse_o : out slv(L_G-1 downto 0); - - -- GT diagnostics - rxUserRdyOut : out slv(1 downto 0); - rxMmcmResetOut : out slv(1 downto 0) - - ); -end Jesd204bRxGtx7; - -architecture rtl of Jesd204bRxGtx7 is - --- Internal signals - signal r_jesdGtRxArr : jesdGtRxLaneTypeArray(L_G-1 downto 0); - - -- Rx Channel Bonding - -- signal rxChBondLevel : slv(2 downto 0); - signal rxChBondIn : Slv5Array(L_G-1 downto 0); - signal rxChBondOut : Slv5Array(L_G-1 downto 0); - - -- GT reset - signal s_gtUserReset : slv(L_G-1 downto 0); - signal s_gtReset : slv(L_G-1 downto 0); - - -- Generated or external - signal s_sysRef, s_sysRefDbg : sl; - - -begin - - -------------------------------------------------------------------------------------------------- - -- JESD receiver core - -------------------------------------------------------------------------------------------------- - Jesd204b_INST: entity work.Jesd204bRx - generic map ( - TPD_G => TPD_G, - TEST_G => TEST_G, - F_G => F_G, - K_G => K_G, - L_G => L_G) - port map ( - axiClk => axiClk, - axiRst => axiRst, - axilReadMaster => axilReadMaster, - axilReadSlave => axilReadSlave, - axilWriteMaster => axilWriteMaster, - axilWriteSlave => axilWriteSlave, - rxAxisMasterArr_o => rxAxisMasterArr, - rxCtrlArr_i => rxCtrlArr, - devClk_i => devClk_i, - devRst_i => devRst_i, - sysRef_i => s_sysRef, - r_jesdGtRxArr => r_jesdGtRxArr, - gtRxReset_o => s_gtUserReset, - sampleDataArr_o => open, -- DAQ handled internally - dataValidVec_o => open, -- DAQ handled internally - nSync_o => nSync_o, - pulse_o => pulse_o, - sysRefDbg_o => s_sysRefDbg, - leds_o => leds_o - ); - -------------------------------------------------------------------------------------------------- - -- Generate the internal or external SYSREF depending on SYSREF_GEN_G - -------------------------------------------------------------------------------------------------- - -- IF DEF SYSREF_GEN_G - SELF_TEST_GEN: if SYSREF_GEN_G = true generate - -- Generate the sysref internally - -- Sysref period will be 8x K_G. - SysrefGen_INST: entity work.LmfcGen - generic map ( - TPD_G => TPD_G, - K_G => 256, - F_G => 2) - port map ( - clk => devClk_i, - rst => devRst_i, - nSync_i => '0', - sysref_i => '0', - lmfc_o => s_sysRef - ); - sysRef_o <= s_sysRef; - end generate SELF_TEST_GEN; - -- Else - OPER_GEN: if SYSREF_GEN_G = false generate - s_sysRef <= sysRef_i; - sysRef_o <= s_sysRefDbg; - end generate OPER_GEN; - - -------------------------------------------------------------------------------------------------- - -- Generate the GTX channels - -------------------------------------------------------------------------------------------------- - GT_OPER_GEN: if TEST_G = false generate - GTX7_CORE_GEN : for I in (L_G-1) downto 0 generate - - -- Channel Bonding - Bond_Master : if (I = 0) generate - rxChBondIn(I) <= "00000"; - end generate Bond_Master; - - Bond_Slaves : if (I /= 0) generate - rxChBondIn(I) <= rxChBondOut(I-1); - end generate Bond_Slaves; - - -- Generate GT reset from user reset and global reset - -- devRst_i - is holding the module in reset for one minute after power-up - -- User holds the core in reset when the JESD lane is disabled - s_gtReset(I) <= s_gtUserReset(I) or devRst_i; - - Gtx7Core_Inst : entity work.Gtx7Core - generic map ( - TPD_G => TPD_G, - SIM_GTRESET_SPEEDUP_G => SIM_GTRESET_SPEEDUP_G, - SIM_VERSION_G => SIM_VERSION_G, - STABLE_CLOCK_PERIOD_G => STABLE_CLOCK_PERIOD_G, - CPLL_REFCLK_SEL_G => CPLL_REFCLK_SEL_G, - CPLL_FBDIV_G => CPLL_FBDIV_G, - CPLL_FBDIV_45_G => CPLL_FBDIV_45_G, - CPLL_REFCLK_DIV_G => CPLL_REFCLK_DIV_G, - RXOUT_DIV_G => RXOUT_DIV_G, - TXOUT_DIV_G => TXOUT_DIV_G, - RX_CLK25_DIV_G => RX_CLK25_DIV_G, - TX_CLK25_DIV_G => TX_CLK25_DIV_G, - PMA_RSV_G => PMA_RSV_G, - TX_PLL_G => TX_PLL_G, - RX_PLL_G => RX_PLL_G, - - -- Data width - TX_EXT_DATA_WIDTH_G => GT_WORD_SIZE_C*8, - TX_INT_DATA_WIDTH_G => GT_WORD_SIZE_C*8+GT_WORD_SIZE_C*2, - TX_8B10B_EN_G => true, - - -- Data width - RX_EXT_DATA_WIDTH_G => GT_WORD_SIZE_C*8, - RX_INT_DATA_WIDTH_G => GT_WORD_SIZE_C*8+GT_WORD_SIZE_C*2, - RX_8B10B_EN_G => true, - - - TX_BUF_EN_G => TX_BUF_EN_G, - TX_OUTCLK_SRC_G => TX_OUTCLK_SRC_G, - TX_DLY_BYPASS_G => TX_DLY_BYPASS_G, - TX_PHASE_ALIGN_G => TX_PHASE_ALIGN_G, - TX_BUF_ADDR_MODE_G => TX_BUF_ADDR_MODE_G, - RX_BUF_EN_G => true, - RX_OUTCLK_SRC_G => "OUTCLKPMA", - RX_USRCLK_SRC_G => "RXOUTCLK", -- Not 100% sure, doesn't really matter - RX_DLY_BYPASS_G => '1', - RX_DDIEN_G => '0', - RX_BUF_ADDR_MODE_G => "FULL", - RX_ALIGN_MODE_G => "GT", -- Default - ALIGN_COMMA_DOUBLE_G => "TRUE", -- True for JESD to align comma on every polarity - ALIGN_COMMA_ENABLE_G => "1111111111", -- Default - ALIGN_COMMA_WORD_G => 1, -- 1 for JESD to align comma on every byte - ALIGN_MCOMMA_DET_G => "TRUE", - ALIGN_MCOMMA_VALUE_G => "1010000011", -- Default - ALIGN_MCOMMA_EN_G => '1', - ALIGN_PCOMMA_DET_G => "TRUE", - ALIGN_PCOMMA_VALUE_G => "0101111100", -- Default - ALIGN_PCOMMA_EN_G => '1', - SHOW_REALIGN_COMMA_G => "FALSE", - RXSLIDE_MODE_G => "AUTO", - RX_DISPERR_SEQ_MATCH_G => "TRUE", -- Default - DEC_MCOMMA_DETECT_G => "TRUE", -- Default - DEC_PCOMMA_DETECT_G => "TRUE", -- Default - DEC_VALID_COMMA_ONLY_G => "FALSE", -- Default - CBCC_DATA_SOURCE_SEL_G => "DECODED", -- Default - CLK_COR_SEQ_2_USE_G => "FALSE", -- Default - CLK_COR_KEEP_IDLE_G => "FALSE", -- Default - CLK_COR_MAX_LAT_G => 21, - CLK_COR_MIN_LAT_G => 18, - CLK_COR_PRECEDENCE_G => "TRUE", -- Default - CLK_COR_REPEAT_WAIT_G => 0, -- Default - CLK_COR_SEQ_LEN_G => 4, - CLK_COR_SEQ_1_ENABLE_G => "1111", -- Default - CLK_COR_SEQ_1_1_G => "0110111100", - CLK_COR_SEQ_1_2_G => "0100011100", - CLK_COR_SEQ_1_3_G => "0100011100", - CLK_COR_SEQ_1_4_G => "0100011100", - CLK_CORRECT_USE_G => "TRUE", - CLK_COR_SEQ_2_ENABLE_G => "0000", -- Default - CLK_COR_SEQ_2_1_G => "0000000000", -- Default - CLK_COR_SEQ_2_2_G => "0000000000", -- Default - CLK_COR_SEQ_2_3_G => "0000000000", -- Default - CLK_COR_SEQ_2_4_G => "0000000000", -- Default - RX_CHAN_BOND_EN_G => true, --true ulegat - RX_CHAN_BOND_MASTER_G => (i = 0), - CHAN_BOND_KEEP_ALIGN_G => "FALSE", -- Default - CHAN_BOND_MAX_SKEW_G => 10, - CHAN_BOND_SEQ_LEN_G => 1, -- Default - CHAN_BOND_SEQ_1_1_G => "0110111100", - CHAN_BOND_SEQ_1_2_G => "0111011100", - CHAN_BOND_SEQ_1_3_G => "0111011100", - CHAN_BOND_SEQ_1_4_G => "0111011100", - CHAN_BOND_SEQ_1_ENABLE_G => "1111", -- Default - CHAN_BOND_SEQ_2_1_G => "0000000000", -- Default - CHAN_BOND_SEQ_2_2_G => "0000000000", -- Default - CHAN_BOND_SEQ_2_3_G => "0000000000", -- Default - CHAN_BOND_SEQ_2_4_G => "0000000000", -- Default - CHAN_BOND_SEQ_2_ENABLE_G => "0000", -- Default - CHAN_BOND_SEQ_2_USE_G => "FALSE", -- Default - FTS_DESKEW_SEQ_ENABLE_G => "1111", -- Default - FTS_LANE_DESKEW_CFG_G => "1111", -- Default - FTS_LANE_DESKEW_EN_G => "FALSE", -- Default - RX_OS_CFG_G => RX_OS_CFG_G, - RXCDR_CFG_G => RXCDR_CFG_G, - RX_EQUALIZER_G => "DFE", -- Xilinx recommends this for 8b10b - RXDFEXYDEN_G => RXDFEXYDEN_G, - RX_DFE_KL_CFG2_G => RX_DFE_KL_CFG2_G) - port map ( - stableClkIn => stableClk, - cPllRefClkIn => cPllRefClkIn, - cPllLockOut => cPllLockOut(I), - - qPllRefClkIn => qPllRefClkIn, - qPllClkIn => qPllClkIn, - qPllLockIn => qPllLockIn, - qPllRefClkLostIn => qPllRefClkLostIn, - qPllResetOut => qPllResetOut(I), - - gtRxRefClkBufg => stableClk, -- TODO check - - gtTxP => gtTxP(I), - gtTxN => gtTxN(I), - gtRxP => gtRxP(I), - gtRxN => gtRxN(I), - - rxOutClkOut => rxOutClkOut(I), - rxUsrClkIn => devClk_i, - rxUsrClk2In => devClk2_i, - rxUserRdyOut => rxUserRdyOut(I), - rxMmcmResetOut => rxMmcmResetOut(I), - rxMmcmLockedIn => '1', - rxUserResetIn => s_gtReset(I), - rxResetDoneOut => r_jesdGtRxArr(I).rstDone, - rxDataValidIn => '1', - rxSlideIn => '0', - rxDataOut => r_jesdGtRxArr(I).data, - rxCharIsKOut => r_jesdGtRxArr(I).dataK, - rxDecErrOut => r_jesdGtRxArr(I).decErr, - rxDispErrOut => r_jesdGtRxArr(I).dispErr, - rxPolarityIn => '1', -- Changed to '1' after receiving weird data (sometimes ok sometimes wrong) - rxBufStatusOut => open, - rxChBondLevelIn => slv(to_unsigned((L_G-1-I), 3)), - rxChBondIn => rxChBondIn(I), - rxChBondOut => rxChBondOut(I), - txOutClkOut => txOutClkOut(I), - txUsrClkIn => devClk_i, - txUsrClk2In => devClk2_i, - txUserRdyOut => open, - txMmcmResetOut => open, - txMmcmLockedIn => '1', - txUserResetIn => '1', - txResetDoneOut => open, - txDataIn => (r_jesdGtRxArr(I).data'range => '0'), - txCharIsKIn => (r_jesdGtRxArr(I).dataK'range => '0'), - txBufStatusOut => open, - loopbackIn => "000" - ); - end generate GTX7_CORE_GEN; - ----------------------------------------- - end generate GT_OPER_GEN; - ----------------------------------------------------- -end rtl; diff --git a/protocols/jesd204b/example/Jesd204bTxGthUltra.vhd b/protocols/jesd204b/example/Jesd204bTxGthUltra.vhd deleted file mode 100644 index 7f31bde9c4..0000000000 --- a/protocols/jesd204b/example/Jesd204bTxGthUltra.vhd +++ /dev/null @@ -1,349 +0,0 @@ -------------------------------------------------------------------------------- --- File : Jesd204bTxGthUltra.vhd --- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-14 --- Last update: 2018-01-08 -------------------------------------------------------------------------------- --- Description: JESD204b module containing the GTH Ultrascale MGT transmitter modules --- Wrapper module for JESD. --- GTH coregen generated core 2 GTH modules --- Note: Intended only for two serial lanes L_G=2. --- 7.4 GHz lane rate and 370MHz reference, Freerunning clk 185 MHz --- If different amount of lanes or freq is required the Core has to be regenerated --- by Xilinx Coregen. -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -library unisim; -use unisim.vcomponents.all; - -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; - -use work.StdRtlPkg.all; -use work.AxiLitePkg.all; -use work.AxiStreamPkg.all; -use work.SsiPkg.all; -use work.Jesd204bPkg.all; - -entity Jesd204bTxGthUltra is - generic ( - TPD_G : time := 1 ns; - - -- Internal SYSREF SYSREF_GEN_G= TRUE else - -- External SYSREF - SYSREF_GEN_G : boolean := false; - - -- Simulation disconnect the GTX - SIM_G : boolean := false; - - -- JESD generics - ---------------------------------------------------------------------------------------------- - F_G : positive := 2; - K_G : positive := 32; - L_G : positive := 2 - ); - - port ( - -- GT Interface - ---------------------------------------------------------------------------------------------- - -- GT Clocking - stableClk : in sl; -- GT needs a stable clock to "boot up"(buffered refClkDiv2) - refClk : in sl; -- GT Reference clock directly from GT GTH diff. input buffer - - -- Gt Serial IO - gtTxP : out slv(L_G-1 downto 0); -- GT Serial Transmit Positive - gtTxN : out slv(L_G-1 downto 0); -- GT Serial Transmit Negative - gtRxP : in slv(L_G-1 downto 0); -- GT Serial Receive Positive - gtRxN : in slv(L_G-1 downto 0); -- GT Serial Receive Negative - - -- User clocks and resets - ---------------------------------------------------------------------------------------------- - devClk_i : in sl; -- Device clock also rxUsrClkIn for MGT - devClk2_i : in sl; -- Device clock divided by 2 also rxUsrClk2In for MGT - devRst_i : in sl; -- - - -- AXI interface - ------------------------------------------------------------------------------------------------ - axiClk : in sl; - axiRst : in sl; - - -- AXI-Lite RX Register Interface - axilReadMasterTx : in AxiLiteReadMasterType; - axilReadSlaveTx : out AxiLiteReadSlaveType; - axilWriteMasterTx : in AxiLiteWriteMasterType; - axilWriteSlaveTx : out AxiLiteWriteSlaveType; - - -- AXI Streaming Interface - txAxisMasterArr_i : in AxiStreamMasterArray(L_G-1 downto 0); - txAxisSlaveArr_o : out AxiStreamSlaveArray(L_G-1 downto 0); - - -- External sample data input - extSampleDataArray_i : in sampleDataArray(L_G-1 downto 0); - - -- JESD - ------------------------------------------------------------------------------------------------ - - -- SYSREF for subcalss 1 fixed latency - sysRef_i : in sl; - - -- SYSREF out when it is generated internally SYSREF_GEN_G=True - sysRef_o : out sl; - - -- Synchronisation output combined from all receivers - nSync_i : in sl; - - -- Test signal - pulse_o : out slv(L_G-1 downto 0); - - -- Out to led - leds_o : out slv(1 downto 0); - - -- Out to led - qPllLock_o : out sl - ); -end Jesd204bTxGthUltra; - -architecture rtl of Jesd204bTxGthUltra is - ---------------------------------------- -component gthultrascalejesdcoregen - port ( - gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_reset_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_start_user_in : in std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_buffbypass_tx_error_out : out std_logic_vector(0 downto 0); - gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); - gtwiz_reset_all_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); - gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); - gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); - gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); - gtwiz_userdata_tx_in : in std_logic_vector(63 downto 0); - gtwiz_userdata_rx_out : out std_logic_vector(63 downto 0); - gtrefclk00_in : in std_logic_vector(0 downto 0); - qpll0lock_out : out std_logic_vector(0 downto 0); - qpll0outclk_out : out std_logic_vector(0 downto 0); - qpll0outrefclk_out : out std_logic_vector(0 downto 0); - gthrxn_in : in std_logic_vector(1 downto 0); - gthrxp_in : in std_logic_vector(1 downto 0); - rx8b10ben_in : in std_logic_vector(1 downto 0); - rxcommadeten_in : in std_logic_vector(1 downto 0); - rxmcommaalignen_in : in std_logic_vector(1 downto 0); - rxpcommaalignen_in : in std_logic_vector(1 downto 0); - rxpolarity_in : in std_logic_vector(1 downto 0); - rxusrclk_in : in std_logic_vector(1 downto 0); - rxusrclk2_in : in std_logic_vector(1 downto 0); - tx8b10ben_in : in std_logic_vector(1 downto 0); - txctrl0_in : in std_logic_vector(31 downto 0); - txctrl1_in : in std_logic_vector(31 downto 0); - txctrl2_in : in std_logic_vector(15 downto 0); - txpolarity_in : in std_logic_vector(1 downto 0); - txusrclk_in : in std_logic_vector(1 downto 0); - txusrclk2_in : in std_logic_vector(1 downto 0); - gthtxn_out : out std_logic_vector(1 downto 0); - gthtxp_out : out std_logic_vector(1 downto 0); - rxbyteisaligned_out : out std_logic_vector(1 downto 0); - rxbyterealign_out : out std_logic_vector(1 downto 0); - rxcommadet_out : out std_logic_vector(1 downto 0); - rxctrl0_out : out std_logic_vector(31 downto 0); - rxctrl1_out : out std_logic_vector(31 downto 0); - rxctrl2_out : out std_logic_vector(15 downto 0); - rxctrl3_out : out std_logic_vector(15 downto 0); - rxoutclk_out : out std_logic_vector(1 downto 0); - rxpmaresetdone_out : out std_logic_vector(1 downto 0); - txoutclk_out : out std_logic_vector(1 downto 0); - txpmaresetdone_out : out std_logic_vector(1 downto 0) - ); -end component; -------------------------------------- - --- Internal signals - signal r_jesdGtTxArr : jesdGtTxLaneTypeArray(L_G-1 downto 0); - - -- Rx Channel Bonding - -- signal rxChBondLevel : slv(2 downto 0); - signal rxChBondIn : Slv5Array(L_G-1 downto 0); - signal rxChBondOut : Slv5Array(L_G-1 downto 0); - - -- GT reset - signal s_gtRxUserReset : slv(L_G-1 downto 0); - signal s_gtxRst : sl; - - signal s_gtTxUserReset : slv(L_G-1 downto 0); - signal s_gtTxReset : slv(L_G-1 downto 0); - -- - signal s_gtTxReady : slv(L_G-1 downto 0); - - -- Generated or external - signal s_sysRef : sl; - - -- GT signals - signal s_data : slv(63 downto 0); - signal s_dataK : slv(15 downto 0); - signal s_devClkVec : slv(1 downto 0); - signal s_devClk2Vec : slv(1 downto 0); - - signal s_txDone : sl; - - -begin - -- Check generics TODO add others - assert (1 <= L_G and L_G <= 8) report "L_G must be between 1 and 8" severity failure; - - -------------------------------------------------------------------------------------------------- - -- JESD transmitter core - -------------------------------------------------------------------------------------------------- - Jesd204bTx_INST: entity work.Jesd204bTx - generic map ( - TPD_G => TPD_G, - F_G => F_G, - K_G => K_G, - L_G => L_G) - port map ( - axiClk => axiClk, - axiRst => axiRst, - axilReadMaster => axilReadMasterTx, - axilReadSlave => axilReadSlaveTx, - axilWriteMaster => axilWriteMasterTx, - axilWriteSlave => axilWriteSlaveTx, - txAxisMasterArr_i => txAxisMasterArr_i, - txAxisSlaveArr_o => txAxisSlaveArr_o, - extSampleDataArray_i => extSampleDataArray_i, - devClk_i => devClk_i, - devRst_i => devRst_i, - sysRef_i => s_sysRef, - nSync_i => nSync_i, - gtTxReady_i => s_gtTxReady, - gtTxReset_o => s_gtTxUserReset, - r_jesdGtTxArr => r_jesdGtTxArr, - pulse_o => pulse_o, - leds_o => leds_o - ); - - -------------------------------------------------------------------------------------------------- - -- Generate the internal or external SYSREF depending on SYSREF_GEN_G - -------------------------------------------------------------------------------------------------- - -- IF DEF SYSREF_GEN_G - SELF_TEST_GEN: if SYSREF_GEN_G = true generate - -- Generate the sysref internally - -- Sysref period will be 8x K_G. - SysrefGen_INST: entity work.LmfcGen - generic map ( - TPD_G => TPD_G, - K_G => 256, - F_G => 2) - port map ( - clk => devClk_i, - rst => devRst_i, - nSync_i => '0', - sysref_i => '0', - lmfc_o => s_sysRef - ); - sysRef_o <= s_sysRef; - end generate SELF_TEST_GEN; - -- Else - OPER_GEN: if SYSREF_GEN_G = false generate - s_sysRef <= sysRef_i; - sysRef_o <= '0'; - end generate OPER_GEN; - - -------------------------------------------------------------------------------------------------- - -- GTH signals. Only for L_G = 2 - -------------------------------------------------------------------------------------------------- - s_gtxRst <= devRst_i or uOr(s_gtTxUserReset); - s_data <= r_jesdGtTxArr(1).data & r_jesdGtTxArr(0).data; - s_dataK <= x"0" & r_jesdGtTxArr(1).dataK & X"0" & r_jesdGtTxArr(0).dataK; - s_devClkVec <= devClk_i & devClk_i; - s_devClk2Vec <= devClk2_i & devClk2_i; - s_gtTxReady <= s_txDone & s_txDone; - -- debug - --qPllLock_o <= s_txDone; - - -------------------------------------------------------------------------------------------------- - -- Include Core from Coregen Vivado 15.1 - -- Coregen settings: - -- - Lane rate 7.4 GHz - -- - Reference freq 184 MHz - -- - 8b10b encription enabled - -- - 32b/40b word datapath - -- - TR buffer disabled for deterministic latency - IMPORTANT - -------------------------------------------------------------------------------------------------- - --GT_OPER_GEN: if SIM_G = false generate - GthUltrascaleJesdCoregen_INST: GthUltrascaleJesdCoregen - port map ( - -- Clocks --- gtwiz_userclk_tx_active_in(0) => '1', - gtwiz_userclk_rx_active_in(0) => '1', - - gtwiz_buffbypass_tx_reset_in(0) => s_gtxRst, - gtwiz_buffbypass_tx_start_user_in(0) => s_gtxRst, - gtwiz_buffbypass_tx_done_out(0) => qPllLock_o, - gtwiz_buffbypass_tx_error_out => open, - - gtwiz_reset_clk_freerun_in(0) => stableClk, - - gtwiz_reset_all_in(0) => s_gtxRst, - gtwiz_reset_tx_pll_and_datapath_in(0) => s_gtxRst, - gtwiz_reset_tx_datapath_in(0) => s_gtxRst, - gtwiz_reset_rx_pll_and_datapath_in(0) => s_gtxRst, - gtwiz_reset_rx_datapath_in(0) => s_gtxRst, - gtwiz_reset_rx_cdr_stable_out => open, - gtwiz_reset_tx_done_out(0) => s_txDone, - gtwiz_reset_rx_done_out => open, - gtwiz_userdata_tx_in => s_data, - gtwiz_userdata_rx_out => open, - gtrefclk00_in(0) => refClk, - qpll0outclk_out => open, - qpll0outrefclk_out => open, - gthrxn_in => gtRxN, - gthrxp_in => gtRxP, - qpll0lock_out => open,--qPllLock_o, - rx8b10ben_in => "11", - rxcommadeten_in => "11", - rxmcommaalignen_in => "11", - rxpcommaalignen_in => "11", - rxpolarity_in => "11", -- Changed to '1' after receiving weird data (sometimes ok sometimes wrong) - rxusrclk_in => s_devClkVec, - rxusrclk2_in => s_devClk2Vec, - tx8b10ben_in => "11", - txctrl0_in => X"0000_0000", - txctrl1_in => X"0000_0000", - txctrl2_in => s_dataK, - txpolarity_in => "00", - txusrclk_in => s_devClkVec, - txusrclk2_in => s_devClk2Vec, - gthtxn_out => gtTxN, - gthtxp_out => gtTxP, - txoutclk_out => open, - txpmaresetdone_out => open, - - -- RX settings - rxbyteisaligned_out => open, - rxbyterealign_out => open, - rxcommadet_out => open, - rxctrl0_out => open, -- x"000" & r_jesdGtRxArr(1).dataK & X"000" & r_jesdGtRxArr(0).dataK, - rxctrl1_out => open, -- x"000" & r_jesdGtRxArr(1).dispErr & X"000" & r_jesdGtRxArr(0).dispErr, - rxctrl2_out => open, -- open -- comma detected on corresponding byte - rxctrl3_out => open, -- x"0" & r_jesdGtRxArr(1).decErr & X"0" & r_jesdGtRxArr(0).decErr, - rxoutclk_out => open, - rxpmaresetdone_out => open - ); - ----------------------------------------- - -- end generate GT_OPER_GEN; - ----------------------------------------------------- -end rtl; diff --git a/protocols/jesd204b/example/Jesd204bTxGtx7.vhd b/protocols/jesd204b/example/Jesd204bTxGtx7.vhd deleted file mode 100644 index 54c18c3b8d..0000000000 --- a/protocols/jesd204b/example/Jesd204bTxGtx7.vhd +++ /dev/null @@ -1,409 +0,0 @@ -------------------------------------------------------------------------------- --- File : Jesd204bTxGtx7.vhd --- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-14 --- Last update: 2018-01-08 -------------------------------------------------------------------------------- --- Description: JESD204b module containing the gtx7 MGT transmitter module --- Framework module for JESD. --- Contains generic settings for GTX7 L_G Transmitters -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -library unisim; -use unisim.vcomponents.all; - -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; - -use work.StdRtlPkg.all; -use work.AxiLitePkg.all; -use work.AxiStreamPkg.all; -use work.SsiPkg.all; -use work.Jesd204bPkg.all; - -entity Jesd204bTxGtx7 is - generic ( - TPD_G : time := 1 ns; - - -- Internal SYSREF SYSREF_GEN_G= TRUE else - -- External SYSREF - SYSREF_GEN_G : boolean := true; - - -- Simulation disconnect the GTX - SIM_G : boolean := true; - - - -- GT Settings - ---------------------------------------------------------------------------------------------- - -- Sim Generics - SIM_GTRESET_SPEEDUP_G : string := "FALSE"; - SIM_VERSION_G : string := "4.0"; - STABLE_CLOCK_PERIOD_G : real := 4.0E-9; --units of seconds (default to longest timeout) - - -- CPLL Settings - CPLL_REFCLK_SEL_G : bit_vector := "001"; - CPLL_FBDIV_G : integer:= 4; -- use getGtx7CPllCfg to set - CPLL_FBDIV_45_G : integer:= 4; -- use getGtx7CPllCfg to set - CPLL_REFCLK_DIV_G : integer:= 1;-- use getGtx7CPllCfg to set - - RXOUT_DIV_G : integer:= 4; -- use getGtx7CPllCfg or to getGtx7QPllCfg set - RX_CLK25_DIV_G : integer:= 4;-- use getGtx7CPllCfg or to getGtx7QPllCfg set - - -- MGT Configurations - PMA_RSV_G : bit_vector := x"001E7080"; -- Values from coregen - RX_OS_CFG_G : bit_vector := "0000010000000"; -- Values from coregen - RXCDR_CFG_G : bit_vector := x"03000023ff10400020"; -- Values from coregen - RXDFEXYDEN_G : sl := '1'; -- Values from coregen - RX_DFE_KL_CFG2_G : bit_vector := X"301148AC"; -- Values from coregen - - -- Configure PLL sources - TX_PLL_G : string:= "QPLL"; -- "QPLL" or "CPLL" - RX_PLL_G : string:= "QPLL"; -- "QPLL" or "CPLL" - - -- TX defaults not currently used - TXOUT_DIV_G : integer := 2; - TX_CLK25_DIV_G : integer := 7; - TX_BUF_EN_G : boolean := true; - TX_OUTCLK_SRC_G : string := "OUTCLKPMA"; - TX_DLY_BYPASS_G : sl := '1'; - TX_PHASE_ALIGN_G : string := "NONE"; - TX_BUF_ADDR_MODE_G : string := "FULL"; - - -- JESD generics - ---------------------------------------------------------------------------------------------- - F_G : positive := 2; - K_G : positive := 32; - L_G : positive := 2 - ); - - port ( - -- GT Interface - ---------------------------------------------------------------------------------------------- - -- GT Clocking - stableClk : in sl; -- GT needs a stable clock to "boot up"(buffered refClkDiv2) - - -- QPLL - qPllRefClkIn : in sl; - qPllClkIn : in sl; - qPllLockIn : in sl; - qPllRefClkLostIn : in sl; - qPllResetOut : out slv(L_G-1 downto 0); - - -- Gt Serial IO - gtTxP : out slv(L_G-1 downto 0); -- GT Serial Transmit Positive - gtTxN : out slv(L_G-1 downto 0); -- GT Serial Transmit Negative - gtRxP : in slv(L_G-1 downto 0); -- GT Serial Receive Positive - gtRxN : in slv(L_G-1 downto 0); -- GT Serial Receive Negative - - -- User clocks and resets - ---------------------------------------------------------------------------------------------- - devClk_i : in sl; -- Device clock also rxUsrClkIn for MGT - devClk2_i : in sl; -- Device clock divided by 2 also rxUsrClk2In for MGT - devRst_i : in sl; -- - - -- AXI interface - ------------------------------------------------------------------------------------------------ - axiClk : in sl; - axiRst : in sl; - - -- AXI-Lite RX Register Interface - axilReadMasterTx : in AxiLiteReadMasterType; - axilReadSlaveTx : out AxiLiteReadSlaveType; - axilWriteMasterTx : in AxiLiteWriteMasterType; - axilWriteSlaveTx : out AxiLiteWriteSlaveType; - - -- AXI Streaming Interface - txAxisMasterArr_i : in AxiStreamMasterArray(L_G-1 downto 0); - txAxisSlaveArr_o : out AxiStreamSlaveArray(L_G-1 downto 0); - - -- External sample data input - extSampleDataArray_i : in sampleDataArray(L_G-1 downto 0); - - -- JESD - ------------------------------------------------------------------------------------------------ - - -- SYSREF for subclass 1 fixed latency - sysRef_i : in sl; - - -- SYSREF out when it is generated internally SYSREF_GEN_G=True - sysRef_o : out sl; - - -- Synchronization output combined from all receivers - nSync_i : in sl; - - -- Test signal - pulse_o : out slv(L_G-1 downto 0); - - -- Out to led - leds_o : out slv(1 downto 0) - ); -end Jesd204bTxGtx7; - -architecture rtl of Jesd204bTxGtx7 is - --- Internal signals - signal r_jesdGtTxArr : jesdGtTxLaneTypeArray(L_G-1 downto 0); - - -- Rx Channel Bonding - -- signal rxChBondLevel : slv(2 downto 0); - signal rxChBondIn : Slv5Array(L_G-1 downto 0); - signal rxChBondOut : Slv5Array(L_G-1 downto 0); - - -- GT reset - signal s_gtRxUserReset : slv(L_G-1 downto 0); - signal s_gtRxReset : slv(L_G-1 downto 0); - - signal s_gtTxUserReset : slv(L_G-1 downto 0); - signal s_gtTxReset : slv(L_G-1 downto 0); - -- - signal s_gtTxReady : slv(L_G-1 downto 0); - - -- Generated or external - signal s_sysRef : sl; - -begin - -- Check generics TODO add others - assert (1 <= L_G and L_G <= 8) report "L_G must be between 1 and 8" severity failure; - - -------------------------------------------------------------------------------------------------- - -- JESD transmitter core - -------------------------------------------------------------------------------------------------- - Jesd204bTx_INST: entity work.Jesd204bTx - generic map ( - TPD_G => TPD_G, - F_G => F_G, - K_G => K_G, - L_G => L_G) - port map ( - axiClk => axiClk, - axiRst => axiRst, - axilReadMaster => axilReadMasterTx, - axilReadSlave => axilReadSlaveTx, - axilWriteMaster => axilWriteMasterTx, - axilWriteSlave => axilWriteSlaveTx, - txAxisMasterArr_i => txAxisMasterArr_i, - txAxisSlaveArr_o => txAxisSlaveArr_o, - extSampleDataArray_i => extSampleDataArray_i, - devClk_i => devClk_i, - devRst_i => devRst_i, - sysRef_i => s_sysRef, - nSync_i => nSync_i, - gtTxReady_i => s_gtTxReady, - gtTxReset_o => s_gtTxUserReset, - r_jesdGtTxArr => r_jesdGtTxArr, - pulse_o => pulse_o, - leds_o => leds_o - ); - - -------------------------------------------------------------------------------------------------- - -- Generate the internal or external SYSREF depending on SYSREF_GEN_G - -------------------------------------------------------------------------------------------------- - -- IF DEF SYSREF_GEN_G - SELF_TEST_GEN: if SYSREF_GEN_G = true generate - -- Generate the sysref internally - -- Sysref period will be 8x K_G. - SysrefGen_INST: entity work.LmfcGen - generic map ( - TPD_G => TPD_G, - K_G => 256, - F_G => 2) - port map ( - clk => devClk_i, - rst => devRst_i, - nSync_i => '0', - sysref_i => '0', - lmfc_o => s_sysRef - ); - sysRef_o <= s_sysRef; - end generate SELF_TEST_GEN; - -- Else - OPER_GEN: if SYSREF_GEN_G = false generate - s_sysRef <= sysRef_i; - sysRef_o <= '0'; - end generate OPER_GEN; - - -------------------------------------------------------------------------------------------------- - -- Generate the GTX channels - -------------------------------------------------------------------------------------------------- - GT_OPER_GEN: if SIM_G = false generate - GTX7_CORE_GEN : for I in (L_G-1) downto 0 generate - -- Channel Bonding - Bond_Master : if (I = 0) generate - rxChBondIn(I) <= "00000"; - end generate Bond_Master; - Bond_Slaves : if (I /= 0) generate - rxChBondIn(I) <= rxChBondOut(I-1); - end generate Bond_Slaves; - - -- Generate GT reset from user reset and global reset - -- devRst_i - is holding the module in reset for one minute after power-up - -- User holds the core in reset when the JESD lane is disabled - s_gtRxReset(I) <= s_gtRxUserReset(I) or devRst_i; - s_gtTxReset(I) <= s_gtTxUserReset(I) or devRst_i; - - Gtx7Core_Inst : entity work.Gtx7Core - generic map ( - TPD_G => TPD_G, - SIM_GTRESET_SPEEDUP_G => SIM_GTRESET_SPEEDUP_G, - SIM_VERSION_G => SIM_VERSION_G, - STABLE_CLOCK_PERIOD_G => STABLE_CLOCK_PERIOD_G, - CPLL_REFCLK_SEL_G => CPLL_REFCLK_SEL_G, - CPLL_FBDIV_G => CPLL_FBDIV_G, - CPLL_FBDIV_45_G => CPLL_FBDIV_45_G, - CPLL_REFCLK_DIV_G => CPLL_REFCLK_DIV_G, - RXOUT_DIV_G => RXOUT_DIV_G, - TXOUT_DIV_G => TXOUT_DIV_G, - RX_CLK25_DIV_G => RX_CLK25_DIV_G, - TX_CLK25_DIV_G => TX_CLK25_DIV_G, - PMA_RSV_G => PMA_RSV_G, - TX_PLL_G => TX_PLL_G, - RX_PLL_G => RX_PLL_G, - - -- Data width - TX_EXT_DATA_WIDTH_G => GT_WORD_SIZE_C*8, - TX_INT_DATA_WIDTH_G => GT_WORD_SIZE_C*8+GT_WORD_SIZE_C*2, - TX_8B10B_EN_G => true, - - -- Data width - RX_EXT_DATA_WIDTH_G => GT_WORD_SIZE_C*8, - RX_INT_DATA_WIDTH_G => GT_WORD_SIZE_C*8+GT_WORD_SIZE_C*2, - RX_8B10B_EN_G => true, - - - TX_BUF_EN_G => TX_BUF_EN_G, - TX_OUTCLK_SRC_G => TX_OUTCLK_SRC_G, - TX_DLY_BYPASS_G => TX_DLY_BYPASS_G, - TX_PHASE_ALIGN_G => TX_PHASE_ALIGN_G, - TX_BUF_ADDR_MODE_G => TX_BUF_ADDR_MODE_G, - RX_BUF_EN_G => true, - RX_OUTCLK_SRC_G => "OUTCLKPMA", - RX_USRCLK_SRC_G => "RXOUTCLK", -- Not 100% sure, doesn't really matter - RX_DLY_BYPASS_G => '1', - RX_DDIEN_G => '0', - RX_BUF_ADDR_MODE_G => "FULL", - RX_ALIGN_MODE_G => "GT", -- Default - ALIGN_COMMA_DOUBLE_G => "TRUE", - ALIGN_COMMA_ENABLE_G => "1111111111", -- Default - ALIGN_COMMA_WORD_G => 1, - ALIGN_MCOMMA_DET_G => "TRUE", - ALIGN_MCOMMA_VALUE_G => "1010000011", -- Default - ALIGN_MCOMMA_EN_G => '1', - ALIGN_PCOMMA_DET_G => "TRUE", - ALIGN_PCOMMA_VALUE_G => "0101111100", -- Default - ALIGN_PCOMMA_EN_G => '1', - SHOW_REALIGN_COMMA_G => "FALSE", - RXSLIDE_MODE_G => "AUTO", - RX_DISPERR_SEQ_MATCH_G => "TRUE", -- Default - DEC_MCOMMA_DETECT_G => "TRUE", -- Default - DEC_PCOMMA_DETECT_G => "TRUE", -- Default - DEC_VALID_COMMA_ONLY_G => "FALSE", -- Default - CBCC_DATA_SOURCE_SEL_G => "DECODED", -- Default - CLK_COR_SEQ_2_USE_G => "FALSE", -- Default - CLK_COR_KEEP_IDLE_G => "FALSE", -- Default - CLK_COR_MAX_LAT_G => 21, - CLK_COR_MIN_LAT_G => 18, - CLK_COR_PRECEDENCE_G => "TRUE", -- Default - CLK_COR_REPEAT_WAIT_G => 0, -- Default - CLK_COR_SEQ_LEN_G => 4, - CLK_COR_SEQ_1_ENABLE_G => "1111", -- Default - CLK_COR_SEQ_1_1_G => "0110111100", - CLK_COR_SEQ_1_2_G => "0100011100", - CLK_COR_SEQ_1_3_G => "0100011100", - CLK_COR_SEQ_1_4_G => "0100011100", - CLK_CORRECT_USE_G => "TRUE", - CLK_COR_SEQ_2_ENABLE_G => "0000", -- Default - CLK_COR_SEQ_2_1_G => "0000000000", -- Default - CLK_COR_SEQ_2_2_G => "0000000000", -- Default - CLK_COR_SEQ_2_3_G => "0000000000", -- Default - CLK_COR_SEQ_2_4_G => "0000000000", -- Default - RX_CHAN_BOND_EN_G => true, - RX_CHAN_BOND_MASTER_G => (i = 0), - CHAN_BOND_KEEP_ALIGN_G => "FALSE", -- Default - CHAN_BOND_MAX_SKEW_G => 10, - CHAN_BOND_SEQ_LEN_G => 1, -- Default - CHAN_BOND_SEQ_1_1_G => "0110111100", - CHAN_BOND_SEQ_1_2_G => "0111011100", - CHAN_BOND_SEQ_1_3_G => "0111011100", - CHAN_BOND_SEQ_1_4_G => "0111011100", - CHAN_BOND_SEQ_1_ENABLE_G => "1111", -- Default - CHAN_BOND_SEQ_2_1_G => "0000000000", -- Default - CHAN_BOND_SEQ_2_2_G => "0000000000", -- Default - CHAN_BOND_SEQ_2_3_G => "0000000000", -- Default - CHAN_BOND_SEQ_2_4_G => "0000000000", -- Default - CHAN_BOND_SEQ_2_ENABLE_G => "0000", -- Default - CHAN_BOND_SEQ_2_USE_G => "FALSE", -- Default - FTS_DESKEW_SEQ_ENABLE_G => "1111", -- Default - FTS_LANE_DESKEW_CFG_G => "1111", -- Default - FTS_LANE_DESKEW_EN_G => "FALSE", -- Default - RX_OS_CFG_G => RX_OS_CFG_G, - RXCDR_CFG_G => RXCDR_CFG_G, - RX_EQUALIZER_G => "DFE", -- Xilinx recommends this for 8b10b - RXDFEXYDEN_G => RXDFEXYDEN_G, - RX_DFE_KL_CFG2_G => RX_DFE_KL_CFG2_G) - port map ( - stableClkIn => stableClk, - cPllRefClkIn => '0', - cPllLockOut => open, - - qPllRefClkIn => qPllRefClkIn, - qPllClkIn => qPllClkIn, - qPllLockIn => qPllLockIn, - qPllRefClkLostIn => qPllRefClkLostIn, - qPllResetOut => qPllResetOut(I), - - gtRxRefClkBufg => stableClk, - - - gtTxP => gtTxP(I), - gtTxN => gtTxN(I), - gtRxP => gtRxP(I), - gtRxN => gtRxN(I), - - rxOutClkOut => open, - rxUsrClkIn => devClk_i, - rxUsrClk2In => devClk2_i, - rxUserRdyOut => open, - rxMmcmResetOut => open, - rxMmcmLockedIn => '1', - rxUserResetIn => '1', - rxResetDoneOut => open, - rxDataValidIn => '1', - rxSlideIn => '0', - rxDataOut => open, - rxCharIsKOut => open, - rxDecErrOut => open, - rxDispErrOut => open, - rxPolarityIn => '0', - rxBufStatusOut => open, - rxChBondLevelIn => slv(to_unsigned((L_G-1-I), 3)), - rxChBondIn => rxChBondIn(I), - rxChBondOut => rxChBondOut(I), - txOutClkOut => open, - txUsrClkIn => devClk_i, - txUsrClk2In => devClk2_i, - txUserRdyOut => open, - txMmcmResetOut => open, - txMmcmLockedIn => '1', - txUserResetIn => s_gtTxReset(I), - txResetDoneOut => s_gtTxReady(I), - txDataIn => r_jesdGtTxArr(I).data, - txCharIsKIn => r_jesdGtTxArr(I).dataK, - txBufStatusOut => open, - loopbackIn => "000" - ); - end generate GTX7_CORE_GEN; - ----------------------------------------- - end generate GT_OPER_GEN; - ----------------------------------------------------- -end rtl; diff --git a/protocols/jesd204b/rtl/Jesd16bTo32b.vhd b/protocols/jesd204b/rtl/Jesd16bTo32b.vhd index 3a22a67866..83fac93ed4 100644 --- a/protocols/jesd204b/rtl/Jesd16bTo32b.vhd +++ b/protocols/jesd204b/rtl/Jesd16bTo32b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Jesd16bTo32b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-02-24 --- Last update: 2017-08-29 ------------------------------------------------------------------------------- -- Description: Converts the 16-bit interface to 32-bit JESD interface ------------------------------------------------------------------------------- diff --git a/protocols/jesd204b/rtl/Jesd204bPkg.vhd b/protocols/jesd204b/rtl/Jesd204bPkg.vhd index 2028d42b35..fbe557921e 100644 --- a/protocols/jesd204b/rtl/Jesd204bPkg.vhd +++ b/protocols/jesd204b/rtl/Jesd204bPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Jesd204bPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-07-11 --- Last update: 2017-07-06 ------------------------------------------------------------------------------- -- Description: JESD204B Package File ------------------------------------------------------------------------------- diff --git a/protocols/jesd204b/rtl/Jesd204bRx.vhd b/protocols/jesd204b/rtl/Jesd204bRx.vhd index 7522cae413..aaaed23374 100644 --- a/protocols/jesd204b/rtl/Jesd204bRx.vhd +++ b/protocols/jesd204b/rtl/Jesd204bRx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Jesd204bRx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-14 --- Last update: 2018-05-03 ------------------------------------------------------------------------------- -- Description: JESD204b multi-lane receiver module -- Receiver JESD204b module. @@ -36,9 +34,6 @@ use ieee.std_logic_unsigned.all; use work.StdRtlPkg.all; use work.AxiLitePkg.all; -use work.AxiStreamPkg.all; -use work.SsiPkg.all; - use work.Jesd204bPkg.all; entity Jesd204bRx is @@ -71,10 +66,6 @@ entity Jesd204bRx is axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType; - -- Legacy Interface that we will remove in the future - rxAxisMasterArr_o : out AxiStreamMasterArray(L_G-1 downto 0); - rxCtrlArr_i : in AxiStreamCtrlArray(L_G-1 downto 0) := (others => AXI_STREAM_CTRL_UNUSED_C); - -- Sample data output (Use if external data acquisition core is attached) sampleDataArr_o : out sampleDataArray(L_G-1 downto 0); dataValidVec_o : out slv(L_G-1 downto 0); @@ -177,9 +168,6 @@ begin assert (((K_G * F_G) mod GT_WORD_SIZE_C) = 0) report "K_G setting is incorrect" severity failure; assert (F_G = 1 or F_G = 2 or (F_G = 4 and GT_WORD_SIZE_C = 4)) report "F_G setting must be 1,2,or 4*" severity failure; - -- Legacy Interface that we will remove in the future - rxAxisMasterArr_o <= (others => AXI_STREAM_MASTER_INIT_C); - ----------------------------------------------------------- -- AXI Lite AXI clock domain crossed ----------------------------------------------------------- diff --git a/protocols/jesd204b/rtl/Jesd204bTx.vhd b/protocols/jesd204b/rtl/Jesd204bTx.vhd index ab158ebc5e..e78dc6185a 100644 --- a/protocols/jesd204b/rtl/Jesd204bTx.vhd +++ b/protocols/jesd204b/rtl/Jesd204bTx.vhd @@ -1,7 +1,6 @@ ------------------------------------------------------------------------------- -- File : Jesd204bTx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-14 ------------------------------------------------------------------------------- -- Description: JESD204b multi-lane transmitter module -- Transmitter JESD204b module. @@ -34,9 +33,6 @@ use ieee.std_logic_unsigned.all; use work.StdRtlPkg.all; use work.AxiLitePkg.all; -use work.AxiStreamPkg.all; -use work.SsiPkg.all; - use work.Jesd204bPkg.all; entity Jesd204bTx is @@ -63,10 +59,6 @@ entity Jesd204bTx is axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType; - -- Legacy Interface that we will remove in the future - txAxisMasterArr_i : in AxiStreamMasterArray(L_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - txAxisSlaveArr_o : out AxiStreamSlaveArray(L_G-1 downto 0); - -- JESD -- Clocks and Resets devClk_i : in sl; @@ -160,9 +152,6 @@ architecture rtl of Jesd204bTx is begin - -- Legacy Interface that we will remove in the future - txAxisSlaveArr_o <= (others => AXI_STREAM_SLAVE_FORCE_C); - ---------------------- -- Input data register ---------------------- diff --git a/protocols/jesd204b/rtl/Jesd32bTo16b.vhd b/protocols/jesd204b/rtl/Jesd32bTo16b.vhd index e91fcecdab..06c5ba949f 100644 --- a/protocols/jesd204b/rtl/Jesd32bTo16b.vhd +++ b/protocols/jesd204b/rtl/Jesd32bTo16b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Jesd32bTo16b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-02-24 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: Converts the 32-bit JESD interface to 16-bit interface ------------------------------------------------------------------------------- diff --git a/protocols/jesd204b/rtl/Jesd32bTo64b.vhd b/protocols/jesd204b/rtl/Jesd32bTo64b.vhd index 53805e870c..6c25816176 100644 --- a/protocols/jesd204b/rtl/Jesd32bTo64b.vhd +++ b/protocols/jesd204b/rtl/Jesd32bTo64b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Jesd32bTo64b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-10 --- Last update: 2017-11-10 ------------------------------------------------------------------------------- -- Description: Converts the 32-bit interface to 64-bit JESD interface ------------------------------------------------------------------------------- diff --git a/protocols/jesd204b/rtl/Jesd64bTo32b.vhd b/protocols/jesd204b/rtl/Jesd64bTo32b.vhd index db0d4e7bb4..9f7fef22eb 100644 --- a/protocols/jesd204b/rtl/Jesd64bTo32b.vhd +++ b/protocols/jesd204b/rtl/Jesd64bTo32b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Jesd64bTo32b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-10 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: Converts the 64-bit JESD interface to 32-bit interface ------------------------------------------------------------------------------- diff --git a/protocols/jesd204b/rtl/JesdAlignChGen.vhd b/protocols/jesd204b/rtl/JesdAlignChGen.vhd index 47e5be3d3f..22077cbdc1 100644 --- a/protocols/jesd204b/rtl/JesdAlignChGen.vhd +++ b/protocols/jesd204b/rtl/JesdAlignChGen.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdAlignChGen.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-15 --- Last update: 2016-02-22 ------------------------------------------------------------------------------- -- Description: Alignment character generator -- Scrambles incoming data if enabled diff --git a/protocols/jesd204b/rtl/JesdAlignFrRepCh.vhd b/protocols/jesd204b/rtl/JesdAlignFrRepCh.vhd index e53fb60960..962d2e72ba 100644 --- a/protocols/jesd204b/rtl/JesdAlignFrRepCh.vhd +++ b/protocols/jesd204b/rtl/JesdAlignFrRepCh.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdAlignFrRepCh.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-15 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: Align bytes and replace control characters with data -- diff --git a/protocols/jesd204b/rtl/JesdIlasGen.vhd b/protocols/jesd204b/rtl/JesdIlasGen.vhd index 33e421b35b..285252424d 100644 --- a/protocols/jesd204b/rtl/JesdIlasGen.vhd +++ b/protocols/jesd204b/rtl/JesdIlasGen.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdIlasGen.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-15 --- Last update: 2015-04-15 ------------------------------------------------------------------------------- -- Description: Initial lane alignment sequence Generator -- Adds A na R characters at the LMFC borders. diff --git a/protocols/jesd204b/rtl/JesdLmfcGen.vhd b/protocols/jesd204b/rtl/JesdLmfcGen.vhd index 610118655d..aa470d3f82 100644 --- a/protocols/jesd204b/rtl/JesdLmfcGen.vhd +++ b/protocols/jesd204b/rtl/JesdLmfcGen.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdLmfcGen.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-15 --- Last update: 2017-05-02 ------------------------------------------------------------------------------- -- Description: LMFC Generator -- Local Multi Frame Clock Generator diff --git a/protocols/jesd204b/rtl/JesdRxLane.vhd b/protocols/jesd204b/rtl/JesdRxLane.vhd index 12841231d2..e5377b7bcb 100644 --- a/protocols/jesd204b/rtl/JesdRxLane.vhd +++ b/protocols/jesd204b/rtl/JesdRxLane.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdRxLane.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-14 --- Last update: 2018-05-04 ------------------------------------------------------------------------------- -- Description: JesdRx single lane module -- Receiver JESD204b standard. diff --git a/protocols/jesd204b/rtl/JesdRxReg.vhd b/protocols/jesd204b/rtl/JesdRxReg.vhd index 17c7cc959c..fb0e703847 100644 --- a/protocols/jesd204b/rtl/JesdRxReg.vhd +++ b/protocols/jesd204b/rtl/JesdRxReg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdRxReg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-15 --- Last update: 2018-05-08 ------------------------------------------------------------------------------- -- Description: AXI-Lite interface for register access ------------------------------------------------------------------------------- diff --git a/protocols/jesd204b/rtl/JesdSyncFsmRx.vhd b/protocols/jesd204b/rtl/JesdSyncFsmRx.vhd index 612f4444c4..9aa6592bb0 100644 --- a/protocols/jesd204b/rtl/JesdSyncFsmRx.vhd +++ b/protocols/jesd204b/rtl/JesdSyncFsmRx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdSyncFsmRx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-14 --- Last update: 2015-04-14 ------------------------------------------------------------------------------- -- Description: Synchronizer Finite state machine -- Finite state machine for sub-class 1 deterministic latency diff --git a/protocols/jesd204b/rtl/JesdSyncFsmTx.vhd b/protocols/jesd204b/rtl/JesdSyncFsmTx.vhd index 21af409b4b..ebdb04a8bc 100644 --- a/protocols/jesd204b/rtl/JesdSyncFsmTx.vhd +++ b/protocols/jesd204b/rtl/JesdSyncFsmTx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdSyncFsmTx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-14 --- Last update: 2015-04-14 ------------------------------------------------------------------------------- -- Description: Synchronizer TX Finite state machine -- Finite state machine for sub-class 1 and sub-class 0 deterministic latency diff --git a/protocols/jesd204b/rtl/JesdSyncFsmTxTest.vhd b/protocols/jesd204b/rtl/JesdSyncFsmTxTest.vhd index 661c974041..3505977cd4 100644 --- a/protocols/jesd204b/rtl/JesdSyncFsmTxTest.vhd +++ b/protocols/jesd204b/rtl/JesdSyncFsmTxTest.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdSyncFsmTxTest.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-14 --- Last update: 2015-04-14 ------------------------------------------------------------------------------- -- Description: Synchronizer for simple TX Finite state machine -- Finite state machine for sub-class 1 deterministic latency diff --git a/protocols/jesd204b/rtl/JesdSysrefDly.vhd b/protocols/jesd204b/rtl/JesdSysrefDly.vhd index a1629bcf35..258cd49c3a 100644 --- a/protocols/jesd204b/rtl/JesdSysrefDly.vhd +++ b/protocols/jesd204b/rtl/JesdSysrefDly.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdSysrefDly.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-15 --- Last update: 2015-04-15 ------------------------------------------------------------------------------- -- Description: Delay sysref signal to align timing on two different receiver devices (FPGA, DAC). -- The receiver devices in this core are already aligned and separate delay for separate diff --git a/protocols/jesd204b/rtl/JesdSysrefMon.vhd b/protocols/jesd204b/rtl/JesdSysrefMon.vhd index aa93613d3f..113cd0149b 100644 --- a/protocols/jesd204b/rtl/JesdSysrefMon.vhd +++ b/protocols/jesd204b/rtl/JesdSysrefMon.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdSysrefMon.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2018-05-08 --- Last update: 2018-05-08 ------------------------------------------------------------------------------- -- Description: Monitors the time between sysref rising edge detections ------------------------------------------------------------------------------- diff --git a/protocols/jesd204b/rtl/JesdTestSigGen.vhd b/protocols/jesd204b/rtl/JesdTestSigGen.vhd index 6a2ea62cba..c0996a59ed 100644 --- a/protocols/jesd204b/rtl/JesdTestSigGen.vhd +++ b/protocols/jesd204b/rtl/JesdTestSigGen.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdTestSigGen.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-15 --- Last update: 2015-04-15 ------------------------------------------------------------------------------- -- Description: Outputs a digital signal depending on thresholds -- This is a test module so only F_G = 2 diff --git a/protocols/jesd204b/rtl/JesdTestStreamTx.vhd b/protocols/jesd204b/rtl/JesdTestStreamTx.vhd index d2b2f8c93f..9bfc2a63ef 100644 --- a/protocols/jesd204b/rtl/JesdTestStreamTx.vhd +++ b/protocols/jesd204b/rtl/JesdTestStreamTx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdTestStreamTx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-15 --- Last update: 2015-04-15 ------------------------------------------------------------------------------- -- Description: Test Data Stream Generator -- Outputs a saw, ramp, or square wave test signal data stream for testing diff --git a/protocols/jesd204b/rtl/JesdTxLane.vhd b/protocols/jesd204b/rtl/JesdTxLane.vhd index 409ebf1f8f..37823c45b1 100644 --- a/protocols/jesd204b/rtl/JesdTxLane.vhd +++ b/protocols/jesd204b/rtl/JesdTxLane.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdTxLane.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-14 --- Last update: 2015-04-24 ------------------------------------------------------------------------------- -- Description: JesdTx transmit single lane module -- Transmitter for JESD204b standard. diff --git a/protocols/jesd204b/rtl/JesdTxReg.vhd b/protocols/jesd204b/rtl/JesdTxReg.vhd index a97864769a..484902cce6 100644 --- a/protocols/jesd204b/rtl/JesdTxReg.vhd +++ b/protocols/jesd204b/rtl/JesdTxReg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdTxReg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-15 --- Last update: 2018-05-08 ------------------------------------------------------------------------------- -- Description: AXI-Lite interface for register access ------------------------------------------------------------------------------- diff --git a/protocols/jesd204b/rtl/JesdTxTest.vhd b/protocols/jesd204b/rtl/JesdTxTest.vhd index 680ed0d069..0562f5c7a0 100644 --- a/protocols/jesd204b/rtl/JesdTxTest.vhd +++ b/protocols/jesd204b/rtl/JesdTxTest.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : JesdTxTest.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-14 --- Last update: 2015-04-24 ------------------------------------------------------------------------------- -- Description: JesdTx simple module for testing RX -- Transmitter module for testing JESD RX module. diff --git a/protocols/jesd204b/sim/DescrambleTb.vhd b/protocols/jesd204b/sim/DescrambleTb.vhd index 5f98d93bc9..cdefe38582 100644 --- a/protocols/jesd204b/sim/DescrambleTb.vhd +++ b/protocols/jesd204b/sim/DescrambleTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : DescrambleTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-02-03 --- Last update: 2014-02-03 ------------------------------------------------------------------------------- -- Description: Simulation testbed for JESD Descrambling ------------------------------------------------------------------------------- diff --git a/protocols/jesd204b/sim/Jesd204bTb.vhd b/protocols/jesd204b/sim/Jesd204bTb.vhd index 1124105775..1f6276de62 100644 --- a/protocols/jesd204b/sim/Jesd204bTb.vhd +++ b/protocols/jesd204b/sim/Jesd204bTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Jesd204bTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-02-03 --- Last update: 2018-05-22 ------------------------------------------------------------------------------- -- Description: Simulation testbed for Jesd204b ------------------------------------------------------------------------------- diff --git a/protocols/jesd204b/sim/ScramblerTb.vhd b/protocols/jesd204b/sim/ScramblerTb.vhd index 1aa90ea6f8..1c92e25c3d 100644 --- a/protocols/jesd204b/sim/ScramblerTb.vhd +++ b/protocols/jesd204b/sim/ScramblerTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : ScramblerTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-07-06 --- Last update: 2017-07-06 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing JESD Scramblers ------------------------------------------------------------------------------ diff --git a/protocols/jtag/rtl/AxiStreamSelector.vhd b/protocols/jtag/rtl/AxiStreamSelector.vhd index 69d64a57e6..9d2441d596 100644 --- a/protocols/jtag/rtl/AxiStreamSelector.vhd +++ b/protocols/jtag/rtl/AxiStreamSelector.vhd @@ -4,8 +4,6 @@ -- File : AxiStreamSelector.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-12-05 --- Last update: 2017-12-05 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/jtag/rtl/AxisJtagDebugBridge.vhd b/protocols/jtag/rtl/AxisJtagDebugBridge.vhd index d666aef340..5c236ef902 100644 --- a/protocols/jtag/rtl/AxisJtagDebugBridge.vhd +++ b/protocols/jtag/rtl/AxisJtagDebugBridge.vhd @@ -4,8 +4,6 @@ -- File : AxisJtagDebugBridge.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-12-05 --- Last update: 2017-12-05 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/jtag/rtl/AxisToJtag.vhd b/protocols/jtag/rtl/AxisToJtag.vhd index 29553ce804..bee0cbedb5 100644 --- a/protocols/jtag/rtl/AxisToJtag.vhd +++ b/protocols/jtag/rtl/AxisToJtag.vhd @@ -4,8 +4,6 @@ -- File : AxisToJtagWrapper.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-12-05 --- Last update: 2017-12-05 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/jtag/rtl/AxisToJtagCore.vhd b/protocols/jtag/rtl/AxisToJtagCore.vhd index 773156ccfa..4aeba9e9ed 100644 --- a/protocols/jtag/rtl/AxisToJtagCore.vhd +++ b/protocols/jtag/rtl/AxisToJtagCore.vhd @@ -4,8 +4,6 @@ -- File : AxisToJtagCore.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-12-05 --- Last update: 2017-12-05 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/jtag/rtl/AxisToJtagPkg.vhd b/protocols/jtag/rtl/AxisToJtagPkg.vhd index a4ad41af44..39b66564a3 100644 --- a/protocols/jtag/rtl/AxisToJtagPkg.vhd +++ b/protocols/jtag/rtl/AxisToJtagPkg.vhd @@ -4,8 +4,6 @@ -- File : AxisToJtagPkg.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-12-05 --- Last update: 2017-12-05 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/jtag/rtl/JtagSerDesCore.vhd b/protocols/jtag/rtl/JtagSerDesCore.vhd index b7646b765d..75eb936950 100644 --- a/protocols/jtag/rtl/JtagSerDesCore.vhd +++ b/protocols/jtag/rtl/JtagSerDesCore.vhd @@ -3,8 +3,6 @@ -- File : JtagSerDesCore.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-12-05 --- Last update: 2017-12-05 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/jtag/tb/AxiStreamSelectorTb.vhd b/protocols/jtag/tb/AxiStreamSelectorTb.vhd index 15a5b4a8fc..d40706b4d2 100644 --- a/protocols/jtag/tb/AxiStreamSelectorTb.vhd +++ b/protocols/jtag/tb/AxiStreamSelectorTb.vhd @@ -4,8 +4,6 @@ -- File : AxisStreamSelectorTb.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-12-05 --- Last update: 2017-12-05 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/jtag/tb/AxisToJtagCoreTb.vhd b/protocols/jtag/tb/AxisToJtagCoreTb.vhd index 0dd6fcd695..7e2b44c3fe 100644 --- a/protocols/jtag/tb/AxisToJtagCoreTb.vhd +++ b/protocols/jtag/tb/AxisToJtagCoreTb.vhd @@ -4,8 +4,6 @@ -- File : AxisToJtagCoreTb.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-12-05 --- Last update: 2017-12-05 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/jtag/tb/AxisToJtagStubTb.vhd b/protocols/jtag/tb/AxisToJtagStubTb.vhd index 2a65990b83..6dc8f97e90 100644 --- a/protocols/jtag/tb/AxisToJtagStubTb.vhd +++ b/protocols/jtag/tb/AxisToJtagStubTb.vhd @@ -4,8 +4,6 @@ -- File : AxisToJtagStubTb.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-12-05 --- Last update: 2017-12-05 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/jtag/tb/AxisToJtagTb.vhd b/protocols/jtag/tb/AxisToJtagTb.vhd index b4325f41c9..04eb6dfee5 100644 --- a/protocols/jtag/tb/AxisToJtagTb.vhd +++ b/protocols/jtag/tb/AxisToJtagTb.vhd @@ -4,8 +4,6 @@ -- File : AxisToJtagTb.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-12-05 --- Last update: 2017-12-05 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/jtag/tb/JtagSerDesCoreTb.vhd b/protocols/jtag/tb/JtagSerDesCoreTb.vhd index a6cb96a419..a55031a1e6 100644 --- a/protocols/jtag/tb/JtagSerDesCoreTb.vhd +++ b/protocols/jtag/tb/JtagSerDesCoreTb.vhd @@ -4,8 +4,6 @@ -- File : JtagSerDesCoreTb.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-12-05 --- Last update: 2017-12-05 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/mdio/rtl/MdioCore.vhd b/protocols/mdio/rtl/MdioCore.vhd index 38d36021f7..a49669ee36 100644 --- a/protocols/mdio/rtl/MdioCore.vhd +++ b/protocols/mdio/rtl/MdioCore.vhd @@ -4,8 +4,6 @@ -- File : MdioCore.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-27 --- Last update: 2018-02-14 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/mdio/rtl/MdioLinkIrqHandler.vhd b/protocols/mdio/rtl/MdioLinkIrqHandler.vhd index ab4e2c8892..74b2a714c4 100644 --- a/protocols/mdio/rtl/MdioLinkIrqHandler.vhd +++ b/protocols/mdio/rtl/MdioLinkIrqHandler.vhd @@ -4,8 +4,6 @@ -- File : MdioLinkIrqHandler.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-27 --- Last update: 2017-11-27 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/mdio/rtl/MdioPkg.vhd b/protocols/mdio/rtl/MdioPkg.vhd index 8c00fa0426..8fa5287757 100644 --- a/protocols/mdio/rtl/MdioPkg.vhd +++ b/protocols/mdio/rtl/MdioPkg.vhd @@ -4,8 +4,6 @@ -- File : MdioPkg.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-27 --- Last update: 2017-11-27 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/mdio/rtl/MdioSeqCore.vhd b/protocols/mdio/rtl/MdioSeqCore.vhd index 095d246751..54b4bad223 100644 --- a/protocols/mdio/rtl/MdioSeqCore.vhd +++ b/protocols/mdio/rtl/MdioSeqCore.vhd @@ -4,8 +4,6 @@ -- File : MdioSeqCore.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-27 --- Last update: 2017-11-27 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/mdio/sim/MdioLinkIrqHandlerTb.vhd b/protocols/mdio/sim/MdioLinkIrqHandlerTb.vhd index 2f622d70e5..a36efc3102 100644 --- a/protocols/mdio/sim/MdioLinkIrqHandlerTb.vhd +++ b/protocols/mdio/sim/MdioLinkIrqHandlerTb.vhd @@ -4,8 +4,6 @@ -- File : MdioLinkIrqHandlerTb.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-27 --- Last update: 2017-11-27 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/mdio/sim/MdioSeqCoreTb.vhd b/protocols/mdio/sim/MdioSeqCoreTb.vhd index 2485dc285a..40580c9cc4 100644 --- a/protocols/mdio/sim/MdioSeqCoreTb.vhd +++ b/protocols/mdio/sim/MdioSeqCoreTb.vhd @@ -4,8 +4,6 @@ -- File : MdioSeqCoreTb.vhd -- Author : Till Straumann -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-27 --- Last update: 2017-11-27 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/packetizer/rtl/AxiStreamDepacketizer.vhd b/protocols/packetizer/rtl/AxiStreamDepacketizer.vhd index 6532285556..f9e12bdad2 100644 --- a/protocols/packetizer/rtl/AxiStreamDepacketizer.vhd +++ b/protocols/packetizer/rtl/AxiStreamDepacketizer.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamDepacketizer -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-29 --- Last update: 2018-03-29 ------------------------------------------------------------------------------- -- Description: AXI stream DePacketerizer Module (non-interleave only) -- Formats an AXI-Stream for a transport link. @@ -257,7 +255,7 @@ begin -- End of frame if (inputAxisMaster.tLast = '1') then -- Check tkeep to find tail byte (and strip it out) - v.outputAxisMaster(1).tKeep := '0' & inputAxisMaster.tKeep(15 downto 1); + v.outputAxisMaster(1).tKeep(15 downto 0) := '0' & inputAxisMaster.tKeep(15 downto 1); case (inputAxisMaster.tKeep(7 downto 0)) is when X"01" => -- Single byte tail, append tUser to previous txn which has been held diff --git a/protocols/packetizer/rtl/AxiStreamDepacketizer2.vhd b/protocols/packetizer/rtl/AxiStreamDepacketizer2.vhd index 5a31d3327a..0d7d816a30 100644 --- a/protocols/packetizer/rtl/AxiStreamDepacketizer2.vhd +++ b/protocols/packetizer/rtl/AxiStreamDepacketizer2.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamPacketizer2.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-05-02 --- Last update: 2018-05-16 ------------------------------------------------------------------------------- -- Description: Formats an AXI-Stream for a transport link. -- Sideband fields are placed into the data stream in a header. diff --git a/protocols/packetizer/rtl/AxiStreamPacketizer.vhd b/protocols/packetizer/rtl/AxiStreamPacketizer.vhd index 12b2158e94..59aaf849e3 100644 --- a/protocols/packetizer/rtl/AxiStreamPacketizer.vhd +++ b/protocols/packetizer/rtl/AxiStreamPacketizer.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamPacketizer -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-29 --- Last update: 2018-03-29 ------------------------------------------------------------------------------- -- Description: AXI stream DePacketerizer Module (non-interleave only) -- Formats an AXI-Stream for a transport link. @@ -20,8 +18,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.StdRtlPkg.all; use work.AxiStreamPkg.all; @@ -32,7 +29,7 @@ entity AxiStreamPacketizer is generic ( TPD_G : time := 1 ns; MAX_PACKET_BYTES_G : integer := 1440; -- Must be a multiple of 8 - MIN_TKEEP_G : slv(15 downto 0) := X"0001"; + MIN_TKEEP_G : slv(7 downto 0) := x"01"; OUTPUT_SSI_G : boolean := true; -- SSI compliant output (SOF on tuser) INPUT_PIPE_STAGES_G : integer := 0; OUTPUT_PIPE_STAGES_G : integer := 0); @@ -42,6 +39,9 @@ entity AxiStreamPacketizer is axisClk : in sl; axisRst : in sl; + -- Actual byte count; will be truncated to multiple of word-size + maxPktBytes : in slv(bitSize(MAX_PACKET_BYTES_G) - 1 downto 0) := toSlv(MAX_PACKET_BYTES_G, bitSize(MAX_PACKET_BYTES_G)); + sAxisMaster : in AxiStreamMasterType; sAxisSlave : out AxiStreamSlaveType; @@ -52,7 +52,13 @@ end entity AxiStreamPacketizer; architecture rtl of AxiStreamPacketizer is - constant MAX_WORD_COUNT_C : integer := (MAX_PACKET_BYTES_G / 8) - 3; + constant LD_WORD_SIZE_C : positive := 3; + constant WORD_SIZE_C : positive := 2**LD_WORD_SIZE_C; + + subtype WordCounterType is unsigned(maxPktBytes'left - LD_WORD_SIZE_C downto 0); + + constant PROTO_WORDS_C : positive := 3; + constant MAX_WORD_COUNT_C : WordCounterType := to_unsigned(MAX_PACKET_BYTES_G / WORD_SIZE_C, WordCounterType'length); constant AXIS_CONFIG_C : AxiStreamConfigType := ( TSTRB_EN_C => false, @@ -72,9 +78,10 @@ architecture rtl of AxiStreamPacketizer is type RegType is record state : StateType; - frameNumber : slv(11 downto 0); - packetNumber : slv(23 downto 0); - wordCount : slv(bitSize(MAX_WORD_COUNT_C)-1 downto 0); + frameNumber : unsigned(11 downto 0); + packetNumber : unsigned(23 downto 0); + wordCount : WordCounterType; + maxWords : WordCounterType; eof : sl; tUserLast : slv(7 downto 0); inputAxisSlave : AxiStreamSlaveType; @@ -86,6 +93,7 @@ architecture rtl of AxiStreamPacketizer is frameNumber => (others => '0'), packetNumber => (others => '0'), wordCount => (others => '0'), + maxWords => (0 => '1', others => '0'), eof => '0', tUserLast => (others => '0'), inputAxisSlave => AXI_STREAM_SLAVE_INIT_C, @@ -99,6 +107,7 @@ architecture rtl of AxiStreamPacketizer is signal outputAxisMaster : AxiStreamMasterType; signal outputAxisSlave : AxiStreamSlaveType; + signal maxWords : WordCounterType; -- attribute dont_touch : string; -- attribute dont_touch of r : signal is "TRUE"; -- attribute dont_touch of inputAxisMaster : signal is "TRUE"; @@ -111,6 +120,8 @@ begin assert ((MAX_PACKET_BYTES_G rem 8) = 0) report "MAX_PACKET_BYTES_G must be a multiple of 8" severity error; + maxWords <= WordCounterType(maxPktBytes(maxPktBytes'left downto LD_WORD_SIZE_C)); + ----------------- -- Input pipeline ----------------- @@ -126,8 +137,9 @@ begin mAxisMaster => inputAxisMaster, mAxisSlave => inputAxisSlave); - comb : process (axisRst, inputAxisMaster, outputAxisSlave, r) is - variable v : RegType; + comb : process (axisRst, inputAxisMaster, outputAxisSlave, r, maxWords) is + variable v : RegType; + variable fits : boolean; begin -- Latch the current value @@ -146,15 +158,31 @@ begin when IDLE_S => -- Reset the counter v.wordCount := (others => '0'); + + -- Check and register the max. word count + -- NOTE: wordCount is compared only after incrementing + -- (and doing some work in MOVE_S), thus at least + -- one non-protocol word must fit. + if ( maxWords <= to_unsigned(PROTO_WORDS_C, maxWords'length) ) then + fits := false; + else + fits := true; + if ( maxWords >= MAX_WORD_COUNT_C ) then + v.maxWords := MAX_WORD_COUNT_C - PROTO_WORDS_C; + else + v.maxWords := maxWords - PROTO_WORDS_C; + end if; + end if; + -- Check if ready to move data - if (inputAxisMaster.tValid = '1' and v.outputAxisMaster.tValid = '0') then + if (fits and inputAxisMaster.tValid = '1' and v.outputAxisMaster.tValid = '0') then -- Initialize the AXIS buffer v.outputAxisMaster := axiStreamMasterInit(AXIS_CONFIG_C); -- Generate the 64-bit header v.outputAxisMaster.tValid := '1'; v.outputAxisMaster.tData(3 downto 0) := VERSION_C; - v.outputAxisMaster.tData(15 downto 4) := r.frameNumber; - v.outputAxisMaster.tData(39 downto 16) := r.packetNumber; + v.outputAxisMaster.tData(15 downto 4) := slv(r.frameNumber); + v.outputAxisMaster.tData(39 downto 16) := slv(r.packetNumber); v.outputAxisMaster.tData(47 downto 40) := inputAxisMaster.tDest(7 downto 0); v.outputAxisMaster.tData(55 downto 48) := inputAxisMaster.tId(7 downto 0); v.outputAxisMaster.tData(63 downto 56) := inputAxisMaster.tUser(7 downto 0); @@ -181,13 +209,13 @@ begin v.outputAxisMaster.tUser := (others => '0'); v.outputAxisMaster.tDest := (others => '0'); v.outputAxisMaster.tId := (others => '0'); - v.outputAxisMaster.tKeep := x"00FF"; + v.outputAxisMaster.tKeep := resize(x"00FF",AXI_STREAM_MAX_TKEEP_WIDTH_C); -- Increment word count with each txn v.wordCount := r.wordCount + 1; -- Reach max packet size. Append tail. - if (r.wordCount = MAX_WORD_COUNT_C) then + if (r.wordCount = r.maxWords) then -- Next state v.state := TAIL_S; end if; @@ -205,34 +233,34 @@ begin ---------------------------------------------------------------------- -- Generate the TAIL with respect to the TKEEP ---------------------------------------------------------------------- - case (inputAxisMaster.tKeep) is - when x"0000" => - v.outputAxisMaster.tKeep := (x"0001" or MIN_TKEEP_G); + case (inputAxisMaster.tKeep(7 downto 0)) is + when x"00" => + v.outputAxisMaster.tKeep(7 downto 0) := (x"01" or MIN_TKEEP_G); v.outputAxisMaster.tData(7 downto 0) := '1' & inputAxisMaster.tUser(6 downto 0); - when x"0001" => - v.outputAxisMaster.tKeep := (x"0003" or MIN_TKEEP_G); + when x"01" => + v.outputAxisMaster.tKeep(7 downto 0) := (x"03" or MIN_TKEEP_G); v.outputAxisMaster.tData(15 downto 8) := '1' & inputAxisMaster.tUser(14 downto 8); - when x"0003" => - v.outputAxisMaster.tKeep := (x"0007" or MIN_TKEEP_G); + when x"03" => + v.outputAxisMaster.tKeep(7 downto 0) := (x"07" or MIN_TKEEP_G); v.outputAxisMaster.tData(23 downto 16) := '1' & inputAxisMaster.tUser(22 downto 16); - when x"0007" => - v.outputAxisMaster.tKeep := (x"000F" or MIN_TKEEP_G); + when x"07" => + v.outputAxisMaster.tKeep(7 downto 0) := (x"0F" or MIN_TKEEP_G); v.outputAxisMaster.tData(31 downto 24) := '1' & inputAxisMaster.tUser(30 downto 24); - when x"000F" => - v.outputAxisMaster.tKeep := (x"001F" or MIN_TKEEP_G); + when x"0F" => + v.outputAxisMaster.tKeep(7 downto 0) := (x"1F" or MIN_TKEEP_G); v.outputAxisMaster.tData(39 downto 32) := '1' & inputAxisMaster.tUser(38 downto 32); - when x"001F" => - v.outputAxisMaster.tKeep := (x"003F" or MIN_TKEEP_G); + when x"1F" => + v.outputAxisMaster.tKeep(7 downto 0) := (x"3F" or MIN_TKEEP_G); v.outputAxisMaster.tData(47 downto 40) := '1' & inputAxisMaster.tUser(46 downto 40); - when x"003F" => - v.outputAxisMaster.tKeep := (x"007F" or MIN_TKEEP_G); + when x"3F" => + v.outputAxisMaster.tKeep(7 downto 0) := (x"7F" or MIN_TKEEP_G); v.outputAxisMaster.tData(55 downto 48) := '1' & inputAxisMaster.tUser(54 downto 48); - when x"007F" => - v.outputAxisMaster.tKeep := (x"00FF" or MIN_TKEEP_G); + when x"7F" => + v.outputAxisMaster.tKeep(7 downto 0) := (x"FF" or MIN_TKEEP_G); v.outputAxisMaster.tData(63 downto 56) := '1' & inputAxisMaster.tUser(62 downto 56); when others => -- No room for TAIL this cycle and will add it in the next state - v.outputAxisMaster.tKeep := (x"00FF" or MIN_TKEEP_G); + v.outputAxisMaster.tKeep(7 downto 0) := (x"FF" or MIN_TKEEP_G); -- Save the tUser at tLast v.tUserLast := inputAxisMaster.tUser(7 downto 0); -- Set the flag @@ -252,7 +280,7 @@ begin if (v.outputAxisMaster.tValid = '0') then -- Generate the footer v.outputAxisMaster.tValid := '1'; - v.outputAxisMaster.tKeep := MIN_TKEEP_G; --X"0001"; + v.outputAxisMaster.tKeep(7 downto 0) := MIN_TKEEP_G; --x"01"; v.outputAxisMaster.tData := (others => '0'); v.outputAxisMaster.tData(7) := r.eof; v.outputAxisMaster.tData(6 downto 0) := r.tUserLast(6 downto 0); diff --git a/protocols/packetizer/rtl/AxiStreamPacketizer2.vhd b/protocols/packetizer/rtl/AxiStreamPacketizer2.vhd index 35f8f6625d..13feed3db5 100644 --- a/protocols/packetizer/rtl/AxiStreamPacketizer2.vhd +++ b/protocols/packetizer/rtl/AxiStreamPacketizer2.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamPacketizer2.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-05-02 --- Last update: 2018-08-01 ------------------------------------------------------------------------------- -- Description: Formats an AXI-Stream for a transport link. -- Sideband fields are placed into the data stream in a header. @@ -19,8 +17,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.StdRtlPkg.all; use work.AxiStreamPkg.all; @@ -43,6 +40,8 @@ entity AxiStreamPacketizer2 is axisRst : in sl; -- Status for phase locking externally rearbitrate : out sl; + -- Actual byte count; will be truncated to multiple of word-size + maxPktBytes : in slv(bitSize(MAX_PACKET_BYTES_G) - 1 downto 0) := toSlv(MAX_PACKET_BYTES_G, bitSize(MAX_PACKET_BYTES_G)); -- AXIS Interfaces sAxisMaster : in AxiStreamMasterType; sAxisSlave : out AxiStreamSlaveType; @@ -52,7 +51,14 @@ end entity AxiStreamPacketizer2; architecture rtl of AxiStreamPacketizer2 is - constant MAX_WORD_COUNT_C : positive := (MAX_PACKET_BYTES_G / 8) - 3; + + constant LD_WORD_SIZE_C : positive := 3; + constant WORD_SIZE_C : positive := 2**LD_WORD_SIZE_C; + + subtype WordCounterType is unsigned(maxPktBytes'left - LD_WORD_SIZE_C downto 0); + + constant PROTO_WORDS_C : positive := 3; + constant MAX_WORD_COUNT_C : WordCounterType := to_unsigned(MAX_PACKET_BYTES_G / WORD_SIZE_C, WordCounterType'length); constant CRC_EN_C : boolean := (CRC_MODE_G /= "NONE"); constant CRC_HEAD_TAIL_C : boolean := (CRC_MODE_G = "FULL"); constant ADDR_WIDTH_C : positive := ite((TDEST_BITS_G = 0), 1, TDEST_BITS_G); @@ -69,7 +75,8 @@ architecture rtl of AxiStreamPacketizer2 is packetActive : sl; activeTDest : slv(ADDR_WIDTH_C-1 downto 0); ramWe : sl; - wordCount : slv(bitSize(MAX_WORD_COUNT_C)-1 downto 0); + wordCount : WordCounterType; + maxWords : WordCounterType; eof : sl; lastByteCount : slv(3 downto 0); tUserLast : slv(7 downto 0); @@ -92,6 +99,7 @@ architecture rtl of AxiStreamPacketizer2 is activeTDest => (others => '0'), ramWe => '0', wordCount => (others => '0'), + maxWords => (0 => '1', others => '0'), eof => '0', lastByteCount => "1000", tUserLast => (others => '0'), @@ -123,6 +131,8 @@ architecture rtl of AxiStreamPacketizer2 is signal crcOut : slv(31 downto 0) := (others => '0'); signal crcRem : slv(31 downto 0) := (others => '1'); + signal maxWords : WordCounterType; + -- attribute dont_touch : string; -- attribute dont_touch of r : signal is "TRUE"; -- attribute dont_touch of crcOut : signal is "TRUE"; @@ -135,8 +145,8 @@ architecture rtl of AxiStreamPacketizer2 is begin - assert ((MAX_PACKET_BYTES_G rem 8) = 0) - report "MAX_PACKET_BYTES_G must be a multiple of 8" severity error; + assert ((MAX_PACKET_BYTES_G rem WORD_SIZE_C) = 0) + report "MAX_PACKET_BYTES_G must be a multiple of " & integer'image(WORD_SIZE_C) severity error; assert ((CRC_MODE_G = "NONE") or (CRC_MODE_G = "DATA") or (CRC_MODE_G = "FULL")) report "CRC_MODE_G must be NONE or DATA or FULL" severity error; @@ -144,6 +154,8 @@ begin assert (TDEST_BITS_G <= 8) report "TDEST_BITS_G must be less than or equal to 8" severity error; + maxWords <= WordCounterType(maxPktBytes(maxPktBytes'left downto LD_WORD_SIZE_C)); + ----------------- -- Input pipeline ----------------- @@ -197,7 +209,7 @@ begin generic map ( TPD_G => TPD_G, INPUT_REGISTER_G => false, - BYTE_WIDTH_G => 8, + BYTE_WIDTH_G => WORD_SIZE_C, CRC_INIT_G => X"FFFFFFFF") port map ( crcOut => crcOut, @@ -215,7 +227,7 @@ begin generic map ( TPD_G => TPD_G, INPUT_REGISTER_G => false, - BYTE_WIDTH_G => 8, + BYTE_WIDTH_G => WORD_SIZE_C, CRC_INIT_G => X"FFFFFFFF", CRC_POLY_G => CRC_POLY_G) port map ( @@ -232,9 +244,10 @@ begin end generate; comb : process (axisRst, crcOut, crcRem, inputAxisMaster, outputAxisSlave, - r, ramCrcRem, ramPacketActiveOut, ramPacketSeqOut) is + r, ramCrcRem, ramPacketActiveOut, ramPacketSeqOut, maxWords) is variable v : RegType; variable tdest : slv(7 downto 0); + variable fits : boolean; begin -- Latch the current value v := r; @@ -272,7 +285,7 @@ begin -- Reset the word counter v.wordCount := (others => '0'); -- Set default tlast.tkeep (8 Bytes) - v.lastByteCount := "1000"; + v.lastByteCount := slv(to_unsigned(WORD_SIZE_C, bitSize(WORD_SIZE_C))); -- Pre-load the CRC with the interim remainder v.crcInit := ramCrcRem; -- Reset the CRC (which pre-loads it with crcInit) @@ -280,8 +293,23 @@ begin -- Use header in CRC if enabled v.crcDataValid := toSl(CRC_HEAD_TAIL_C); + -- Check and register the max. word count + -- NOTE: wordCount is compared only after incrementing + -- (and doing some work in MOVE_S), thus at least + -- one non-protocol word must fit. + if ( maxWords <= to_unsigned(PROTO_WORDS_C, maxWords'length) ) then + fits := false; + else + fits := true; + if ( maxWords >= MAX_WORD_COUNT_C ) then + v.maxWords := MAX_WORD_COUNT_C - PROTO_WORDS_C; + else + v.maxWords := maxWords - PROTO_WORDS_C; + end if; + end if; + -- Check if ready to move data - if (inputAxisMaster.tValid = '1' and v.outputAxisMaster.tValid = '0') then + if (fits and inputAxisMaster.tValid = '1' and v.outputAxisMaster.tValid = '0') then tdest := x"00"; tdest(ADDR_WIDTH_C-1 downto 0) := inputAxisMaster.tDest(ADDR_WIDTH_C-1 downto 0); v.outputAxisMaster := @@ -301,7 +329,7 @@ begin end if; -- Increment the sequence counter - v.packetSeq := ramPacketSeqOut + 1; + v.packetSeq := slv(unsigned(ramPacketSeqOut) + 1); -- Set the flag v.packetActive := '1'; -- Latch the current TDEST for TDEST change detection in next state @@ -328,7 +356,7 @@ begin v.wordCount := r.wordCount + 1; -- Reach max packet size. Append tail. - if (r.wordCount = MAX_WORD_COUNT_C) then + if (r.wordCount = r.maxWords) then -- Next state v.state := TAIL_S; end if; @@ -354,7 +382,7 @@ begin v.packetActive := '0'; v.tUserLast := inputAxisMaster.tUser(7 downto 0); v.eof := '1'; - v.lastByteCount := toSlv(getTKeep(inputAxisMaster.tKeep(7 downto 0)), 4); + v.lastByteCount := toSlv(getTKeep(inputAxisMaster.tKeep(7 downto 0),PACKETIZER2_AXIS_CFG_C), 4); v.outputAxisMaster.tLast := '0'; -- Next state v.state := TAIL_S; @@ -410,7 +438,7 @@ begin end case; -- Always a 64-bit transfer - v.outputAxisMaster.tKeep := x"00FF"; + v.outputAxisMaster.tKeep(7 downto 0) := x"FF"; v.outputAxisMaster.tStrb := v.outputAxisMaster.tKeep; if (r.state /= TAIL_S) then diff --git a/protocols/packetizer/rtl/AxiStreamPacketizer2Pkg.vhd b/protocols/packetizer/rtl/AxiStreamPacketizer2Pkg.vhd index 8a58a2a60d..cc0b791d33 100644 --- a/protocols/packetizer/rtl/AxiStreamPacketizer2Pkg.vhd +++ b/protocols/packetizer/rtl/AxiStreamPacketizer2Pkg.vhd @@ -1,6 +1,5 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory --- Created : 2017-04-07 ------------------------------------------------------------------------------- -- Description: Support Package for Packetizer Version 2 ------------------------------------------------------------------------------- diff --git a/protocols/packetizer/rtl/AxiStreamPacketizerMux.vhd b/protocols/packetizer/rtl/AxiStreamPacketizerMux.vhd deleted file mode 100644 index 629ffee1eb..0000000000 --- a/protocols/packetizer/rtl/AxiStreamPacketizerMux.vhd +++ /dev/null @@ -1,344 +0,0 @@ -------------------------------------------------------------------------------- --- File : AxiStreamPacketizer --- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-29 --- Last update: 2016-04-30 -------------------------------------------------------------------------------- --- Description: Formats an AXI-Stream for a transport link. --- Sideband fields are placed into the data stream in a header. --- Long frames are broken into smaller packets. (non-interleave only) -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -use work.StdRtlPkg.all; -use work.ArbiterPkg.all; -use work.AxiStreamPkg.all; -use work.SsiPkg.all; - -entity AxiStreamPacketizerMux is - - generic ( - TPD_G : time := 1 ns; - MAX_PACKET_BYTES_G : integer := 1440; -- Must be a multiple of 8 - MIN_TKEEP_G : slv(15 downto 0) := X"0001"; - INPUT_PIPE_STAGES_G : integer := 0; - OUTPUT_PIPE_STAGES_G : integer := 0; - NUM_SLAVES_G : integer range 1 to 32 := 4; - TDEST_HIGH_G : integer range 0 to 7 := 7; - TDEST_LOW_G : integer range 0 to 7 := 0; - KEEP_TDEST_G : boolean := true); - - - port ( - -- AXI-Lite Interface for local registers - axisClk : in sl; - axisRst : in sl; - - sAxisMasters : in AxiStreamMasterArray(NUM_SLAVES_G-1 downto 0); - sAxisSlaves : out AxiStreamSlaveArray(NUM_SLAVES_G-1 downto 0); - disableSel : in slv(NUM_SLAVES_G-1 downto 0) := (others => '0'); - - mAxisMaster : out AxiStreamMasterType; - mAxisSlave : in AxiStreamSlaveType); - -end entity AxiStreamPacketizerMux; - -architecture rtl of AxiStreamPacketizerMux is - - -- Packetizer constants - constant MAX_WORD_COUNT_C : integer := (MAX_PACKET_BYTES_G / 8) - 3; - constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(8, TKEEP_NORMAL_C); - constant VERSION_C : slv(3 downto 0) := "0000"; - - -- Mux arbiter constants - constant DEST_SIZE_C : integer := bitSize(NUM_SLAVES_G-1); - constant ARB_BITS_C : integer := 2**DEST_SIZE_C; - - type StateType is (ARBITRATE_S, HEADER_S, MOVE_S, TAIL_S); - - type RegType is record - state : StateType; - frameNumber : slv(11 downto 0); - packetNumber : slv(23 downto 0); - packetNumberWe : sl; - wordCount : slv(bitSize(MAX_WORD_COUNT_C)-1 downto 0); - eof : sl; - tUserLast : slv(7 downto 0); - acks : slv(ARB_BITS_C-1 downto 0); - ackNum : slv(DEST_SIZE_C-1 downto 0); - valid : sl; - selDest : slv(7 downto 0); - inputAxisSlaves : AxiStreamSlaveArray(NUM_SLAVES_G-1 downto 0); - outputAxisMaster : AxiStreamMasterType; - end record RegType; - - constant REG_INIT_C : RegType := ( - state => ARBITRATE_S, - frameNumber => (others => '0'), - packetNumber => (others => '0'), - packetNumberWe => '0', - wordCount => (others => '0'), - eof => '0', - tUserLast => (others => '0'), - acks => (others => '0'), - ackNum => (others => '1'), - valid => '0', - selDest => (others => '0'), - inputAxisSlaves => (others => AXI_STREAM_SLAVE_INIT_C), - outputAxisMaster => axiStreamMasterInit(AXIS_CONFIG_C)); - - signal r : RegType := REG_INIT_C; - signal rin : RegType; - - signal packetNumberOut : slv(23 downto 0); - - signal inputAxisMasters : AxiStreamMasterArray(NUM_SLAVES_G-1 downto 0); - signal inputAxisSlaves : AxiStreamSlaveArray(NUM_SLAVES_G-1 downto 0); - signal outputAxisMaster : AxiStreamMasterType; - signal outputAxisSlave : AxiStreamSlaveType; - -begin - - assert ((MAX_PACKET_BYTES_G rem 8) = 0) - report "MAX_PACKET_BYTES_G must be a multiple of 8" severity error; - - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - -- Input pipeline - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - INPUT_PIPELINES : for i in NUM_SLAVES_G-1 downto 0 generate - U_AxiStreamPipeline_Input : entity work.AxiStreamPipeline - generic map ( - TPD_G => TPD_G, - PIPE_STAGES_G => INPUT_PIPE_STAGES_G) - port map ( - axisClk => axisClk, -- [in] - axisRst => axisRst, -- [in] - sAxisMaster => sAxisMasters(i), -- [in] - sAxisSlave => sAxisSlaves(i), -- [out] - mAxisMaster => inputAxisMasters(i), -- [out] - mAxisSlave => inputAxisSlaves(i)); -- [in] - end generate; - - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - -- Output pipeline - ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - U_AxiStreamPipeline_Output : entity work.AxiStreamPipeline - generic map ( - TPD_G => TPD_G, - PIPE_STAGES_G => OUTPUT_PIPE_STAGES_G) - port map ( - axisClk => axisClk, -- [in] - axisRst => axisRst, -- [in] - sAxisMaster => outputAxisMaster, -- [in] - sAxisSlave => outputAxisSlave, -- [out] - mAxisMaster => mAxisMaster, -- [out] - mAxisSlave => mAxisSlave); -- [in] - - ------------------------------------------------------------------------------------------------- - -- Packet Count ram - -- track current packet count for each tDest - ------------------------------------------------------------------------------------------------- - U_QuadPortRam_1 : entity work.QuadPortRam - generic map ( - TPD_G => TPD_G, - REG_EN_G => false, - BYTE_WR_EN_G => false, - DATA_WIDTH_G => 24, - ADDR_WIDTH_G => 8) - port map ( - clka => axisClk, -- [in] - wea => r.packetNumberWe, -- [in] - rsta => axisRst, -- [in] - addra => r.selDest, -- [in] - dina => r.packetNumber, -- [in] - douta => packetNumberOut); -- [out] - - ------------------------------------------------------------------------------------------------- - -- Accumulation sequencing, DMA ring buffer, and AXI-Lite logic - ------------------------------------------------------------------------------------------------- - comb : process (axisRst, disableSel, outputAxisSlave, packetNumberOut, r, sAxisMasters) is - variable v : RegType; - variable requests : slv(ARB_BITS_C-1 downto 0); - variable selData : AxiStreamMasterType; - begin - v := r; - - if (outputAxisSlave.tReady = '1') then - v.outputAxisMaster.tValid := '0'; - end if; - - -- input tReadys 0 by default - for i in 0 to NUM_SLAVES_G-1 loop - v.inputAxisSlaves(i).tReady := '0'; - end loop; - - -- Select source - selData := sAxisMasters(conv_integer(r.ackNum)); - - -- Assign tdest - if (KEEP_TDEST_G = false) then - selData.tDest(7 downto TDEST_LOW_G) := (others => '0'); - selData.tDest(DEST_SIZE_C+TDEST_LOW_G-1 downto TDEST_LOW_G) := r.ackNum; - end if; - - -- Format requests - requests := (others => '0'); - for i in 0 to (NUM_SLAVES_G-1) loop - requests(i) := sAxisMasters(i).tValid and not disableSel(i); - end loop; - - -- Don't write new packet number by default - v.packetNumberWe := '0'; - - case r.state is - when ARBITRATE_S => - -- Arbitrate between requesters - if r.valid = '0' then - arbitrate(requests, r.ackNum, v.ackNum, v.valid, v.acks); - else - -- Reset the Arbitration flag - -- Register the selected tDest - -- Go to header state - v.valid := '0'; - v.selDest := selData.tDest; - v.state := HEADER_S; - end if; - - when HEADER_S => - v.wordCount := (others => '0'); - - -- Place header on output when new data arrived and previous output clear - if (selData.tValid = '1' and v.outputAxisMaster.tValid = '0') then - v.outputAxisMaster := axiStreamMasterInit(AXIS_CONFIG_C); - v.outputAxisMaster.tValid := selData.tValid; - v.outputAxisMaster.tData(3 downto 0) := VERSION_C; - v.outputAxisMaster.tData(15 downto 4) := r.frameNumber; - v.outputAxisMaster.tData(39 downto 16) := packetNumberOut; - v.outputAxisMaster.tData(47 downto 40) := selData.tDest(7 downto 0); - v.outputAxisMaster.tData(55 downto 48) := selData.tId(7 downto 0); - v.outputAxisMaster.tData(63 downto 56) := selData.tUser(7 downto 0); - axiStreamSetUserBit(AXIS_CONFIG_C, v.outputAxisMaster, SSI_SOF_C, '1', 0); -- SOF - v.state := MOVE_S; - v.packetNumber := packetNumberOut + 1; - end if; - - when MOVE_S => - - -- Check if clear to move data - if (v.outputAxisMaster.tValid = '0') then - - -- Accept the data - v.inputAxisSlaves(conv_integer(r.ackNum)).tReady := '1'; - - -- Send data through - v.outputAxisMaster := selData; - v.outputAxisMaster.tUser := (others => '0'); - v.outputAxisMaster.tDest := (others => '0'); - v.outputAxisMaster.tId := (others => '0'); - - -- Increment word count with each txn - v.wordCount := r.wordCount + 1; - - -- Reach max packet size. Append tail. - if (r.wordCount = MAX_WORD_COUNT_C) then - v.state := TAIL_S; - end if; - - -- End of frame - if (selData.tLast = '1') then - -- Increment frame number, clear packetNumber - v.frameNumber := r.frameNumber + 1; - v.packetNumber := (others => '0'); - v.state := ARBITRATE_S; - - -- Need to either append tail to current txn or put tail on next txn (TAIL_S) - -- depending on tKeep - v.outputAxisMaster.tKeep := MIN_TKEEP_G or (selData.tKeep(14 downto 0) & '1'); - - case (selData.tKeep) is - when X"0000" => - v.outputAxisMaster.tData(7 downto 0) := '1' & selData.tUser(6 downto 0); - when X"0001" => - v.outputAxisMaster.tData(15 downto 8) := '1' & selData.tUser(14 downto 8); - when X"0003" => - v.outputAxisMaster.tData(23 downto 16) := '1' & selData.tUser(22 downto 16); - when X"0007" => - v.outputAxisMaster.tData(31 downto 24) := '1' & selData.tUser(30 downto 24); - when X"000F" => - v.outputAxisMaster.tData(39 downto 32) := '1' & selData.tUser(38 downto 32); - when X"001F" => - v.outputAxisMaster.tData(47 downto 40) := '1' & selData.tUser(46 downto 40); - when X"003F" => - v.outputAxisMaster.tData(55 downto 48) := '1' & selData.tUser(54 downto 48); - when X"007F" => - v.outputAxisMaster.tData(63 downto 56) := '1' & selData.tUser(62 downto 56); - when others => --X"0FFF" or anything else - -- Full tkeep. Add new word for tail - v.outputAxisMaster.tKeep := selData.tKeep; - v.state := TAIL_S; - v.tUserLast := selData.tUser(7 downto 0); - v.eof := '1'; - v.outputAxisMaster.tLast := '0'; - end case; - - end if; - end if; - - when TAIL_S => - -- Hold off slave side while inserting tail - v.inputAxisSlaves(conv_integer(r.ackNum)).tReady := '0'; - - -- Insert tail when master side is ready for it - if (v.outputAxisMaster.tValid = '0') then - v.outputAxisMaster.tValid := '1'; - v.outputAxisMaster.tKeep := MIN_TKEEP_G; --X"0001"; - v.outputAxisMaster.tData := (others => '0'); - v.outputAxisMaster.tData(7) := r.eof; - v.outputAxisMaster.tData(6 downto 0) := r.tUserLast(6 downto 0); - v.outputAxisMaster.tUser := (others => '0'); - v.outputAxisMaster.tLast := '1'; - v.eof := '0'; -- Clear EOF for next frame - v.tUserLast := (others => '0'); - v.packetNumberWe := '1'; - v.state := ARBITRATE_S; -- Go to idle and wait for new data - end if; - - end case; - - -- Combinatorial outputs before the reset - inputAxisSlaves <= v.inputAxisSlaves; - - -- Reset - if (axisRst = '1') then - v := REG_INIT_C; - end if; - - -- Register the variable for next clock cycle - rin <= v; - - -- Registered Outputs - outputAxisMaster <= r.outputAxisMaster; - - end process comb; - - seq : process (axisClk) is - begin - if (rising_edge(axisClk)) then - r <= rin after TPD_G; - end if; - end process seq; - -end architecture rtl; - diff --git a/protocols/packetizer/tb/AxiStreamBytePackerTbRx.vhd b/protocols/packetizer/tb/AxiStreamBytePackerTbRx.vhd index bf0a43d307..4da4306361 100644 --- a/protocols/packetizer/tb/AxiStreamBytePackerTbRx.vhd +++ b/protocols/packetizer/tb/AxiStreamBytePackerTbRx.vhd @@ -1,7 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamBytePackerTbRx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-13 ------------------------------------------------------------------------------- -- Description: -- AxiStream data packer tester, tx module @@ -62,7 +61,7 @@ begin if sAxisMaster.tValid = '1' then - inTop := getTKeep(sAxisMaster.tKeep(AXIS_CONFIG_G.TDATA_BYTES_C-1 downto 0))-1; + inTop := getTKeep(sAxisMaster.tKeep(AXIS_CONFIG_G.TDATA_BYTES_C-1 downto 0),AXIS_CONFIG_G)-1; for i in 0 to inTop loop if sAxisMaster.tData(i*8+7 downto i*8) /= toSlv(v.byteCount,8) then diff --git a/protocols/packetizer/tb/AxiStreamBytePackerTbTx.vhd b/protocols/packetizer/tb/AxiStreamBytePackerTbTx.vhd index 6d8d1c88a5..91a01a3874 100644 --- a/protocols/packetizer/tb/AxiStreamBytePackerTbTx.vhd +++ b/protocols/packetizer/tb/AxiStreamBytePackerTbTx.vhd @@ -1,7 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiStreamBytePackerTbTx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-13 ------------------------------------------------------------------------------- -- Description: -- AxiStream data packer tester, tx module diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd index ca39b34d26..beeefeb223 100644 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bAxi.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2009-05-27 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: -- AXI-Lite block to manage the PGP interface. diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bLane.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bLane.vhd index 67d080db8d..cb49717dad 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bLane.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bLane.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bLane.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2009-05-27 --- Last update: 2017-03-28 ------------------------------------------------------------------------------- -- Description: -- Top Level Transmit/Receive interface module for the Pretty Good Protocol core. diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bPkg.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bPkg.vhd index 1294258655..d52c7841e5 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bPkg.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2009-05-27 --- Last update: 2017-11-13 ------------------------------------------------------------------------------- -- Description: -- PGP ID and other global constants. diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bRx.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bRx.vhd index c1b3b90838..bc8cf6194a 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bRx.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bRx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bRx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2009-05-27 --- Last update: 2017-03-28 ------------------------------------------------------------------------------- -- Description: -- Cell Receive interface module for the Pretty Good Protocol core. diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bRxCell.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bRxCell.vhd index fd9cce16e2..80bb958c3c 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bRxCell.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bRxCell.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bRxCell.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2009-05-27 --- Last update: 2017-03-28 ------------------------------------------------------------------------------- -- Description: -- Cell Receive interface module for the Pretty Good Protocol core. diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bRxPhy.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bRxPhy.vhd index 0f110b5e21..c10ece22c7 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bRxPhy.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bRxPhy.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bRxPhy.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2009-05-27 --- Last update: 2017-03-28 ------------------------------------------------------------------------------- -- Description: -- Physical interface receive module for the Pretty Good Protocol version 2 core. diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bTx.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bTx.vhd index a92d578589..8f41674930 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bTx.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bTx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bTx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2009-05-27 --- Last update: 2017-03-28 ------------------------------------------------------------------------------- -- Description: -- Top Level Transmit interface module for the Pretty Good Protocol core. diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd index b907590753..bb86df6713 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bTxCell.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2009-05-27 --- Last update: 2017-03-28 ------------------------------------------------------------------------------- -- Description: -- Cell Transmit interface module for the Pretty Good Protocol core. diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd index f166ee940b..de6f951f9f 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bTxPhy.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2009-05-27 --- Last update: 2017-03-28 ------------------------------------------------------------------------------- -- Description: -- Physical interface receive module for the Pretty Good Protocol version 2 core. diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd index af484a75a0..4970586ec1 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bTxSched.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2009-05-27 --- Last update: 2017-03-28 ------------------------------------------------------------------------------- -- Description: -- Transmit scheduler interface module for the Pretty Good Protocol core. diff --git a/protocols/pgp/pgp2b/core/simlink/rtl/PgpSimModel.vhd b/protocols/pgp/pgp2b/core/simlink/rtl/PgpSimModel.vhd index 963ef14d3b..df0499fc38 100755 --- a/protocols/pgp/pgp2b/core/simlink/rtl/PgpSimModel.vhd +++ b/protocols/pgp/pgp2b/core/simlink/rtl/PgpSimModel.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bLane.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2009-05-27 --- Last update: 2017-03-28 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for PGP ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/core/tb/PgpParallelSimModel.vhd b/protocols/pgp/pgp2b/core/tb/PgpParallelSimModel.vhd index 76e8cd2055..be352bb94f 100644 --- a/protocols/pgp/pgp2b/core/tb/PgpParallelSimModel.vhd +++ b/protocols/pgp/pgp2b/core/tb/PgpParallelSimModel.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : PgpParallelSimModel.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2009-05-27 --- Last update: 2017-03-28 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for PGP ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/core/tb/RoguePgp2bSim.vhd b/protocols/pgp/pgp2b/core/tb/RoguePgp2bSim.vhd index d5f7215cb1..9717822fa5 100644 --- a/protocols/pgp/pgp2b/core/tb/RoguePgp2bSim.vhd +++ b/protocols/pgp/pgp2b/core/tb/RoguePgp2bSim.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RoguePgp2bSim.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-12-05 --- Last update: 2017-02-02 ------------------------------------------------------------------------------- -- Description: Wrapper on RogueStreamSim to simulate a PGP lane with 4 -- virtual channels diff --git a/protocols/pgp/pgp2b/core/tb/pgp_test.vhd b/protocols/pgp/pgp2b/core/tb/pgp_test.vhd index 46351c79c1..27fc0e4c9b 100755 --- a/protocols/pgp/pgp2b/core/tb/pgp_test.vhd +++ b/protocols/pgp/pgp2b/core/tb/pgp_test.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : pgp_test.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2009-05-27 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for PGP ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLat.vhd b/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLat.vhd index 5d54ef04e6..c2978c3c19 100644 --- a/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLat.vhd +++ b/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLat.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGth7Fixedlat.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-01 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gth7 Fixed Latency Module ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLatWrapper.vhd b/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLatWrapper.vhd index 148fc468ac..55ababe010 100644 --- a/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLatWrapper.vhd +++ b/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLatWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGth7FixedLatWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-01 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gth7 Fixed Latency Wrapper ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7MultiLane.vhd b/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7MultiLane.vhd index 377131503d..6313e5bc61 100644 --- a/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7MultiLane.vhd +++ b/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7MultiLane.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGth7MultiLane.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-01 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gth7 Variable Latency, multi-lane Module ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLat.vhd b/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLat.vhd index 4b453b7f0b..1e5bbd350d 100644 --- a/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLat.vhd +++ b/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLat.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGth7VarLat.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-01 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gth7 Variable Latency Wrapper ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLatWrapper.vhd b/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLatWrapper.vhd index df74113887..546925f230 100644 --- a/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLatWrapper.vhd +++ b/protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLatWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGth7VarLatWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-04-01 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Example PGP 3.125 Gbps front end wrapper -- Note: Default generic configurations are for the Diligent NetFPGA-SUME development board diff --git a/protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd b/protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd index 6d71c97f8b..909a52ef2c 100644 --- a/protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd +++ b/protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGthUltra.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-06-29 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd b/protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd index 46fe0e4c02..1259f56f7f 100644 --- a/protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd +++ b/protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : PgpGthCoreWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-06-29 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLat.vhd b/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLat.vhd index a5c51b6932..ce2c49fd64 100644 --- a/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLat.vhd +++ b/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLat.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGtp7FixedLat.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-06-29 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gth7 Fixed Latency Module ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLatWrapper.vhd b/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLatWrapper.vhd index 8dd3e504c9..70b8f3b4a8 100644 --- a/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLatWrapper.vhd +++ b/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLatWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGtp7FixedLatWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-01-29 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gtp7 Fixed Latency Wrapper ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7MultiLane.vhd b/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7MultiLane.vhd index 576a9730ef..3c1df972a8 100644 --- a/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7MultiLane.vhd +++ b/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7MultiLane.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGtp7MultiLane.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-06-29 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gtp7 Variable Latency, multi-lane Module ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLat.vhd b/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLat.vhd index ec3dddaa59..10321cb541 100644 --- a/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLat.vhd +++ b/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLat.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGtp7VarLat.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-06-29 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gtp7 Variable Latency Wrapper ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLatWrapper.vhd b/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLatWrapper.vhd index 309aff7e71..23d8f65826 100644 --- a/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLatWrapper.vhd +++ b/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLatWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGtp7VarLatWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-01-29 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Example PGP2b front end wrapper -- Note: Default generic configurations are for the AC701 development board diff --git a/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLat.vhd b/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLat.vhd index e3cf90badc..e18566348d 100644 --- a/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLat.vhd +++ b/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLat.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGtx7Fixedlat.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-06-29 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gtx7 Fixed Latency Module ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLatWrapper.vhd b/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLatWrapper.vhd index b2098628a5..37c188c6aa 100644 --- a/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLatWrapper.vhd +++ b/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLatWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGtx7FixedLatWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-01-29 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gtx7 Fixed Latency Wrapper ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7MultiLane.vhd b/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7MultiLane.vhd index 0aeeb60be5..d7cc1c31c7 100644 --- a/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7MultiLane.vhd +++ b/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7MultiLane.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGtx7MultiLane.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-06-29 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gtx7 Variable Latency, multi-lane Module ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLat.vhd b/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLat.vhd index 13a18be3a0..00f28ca10a 100644 --- a/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLat.vhd +++ b/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLat.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGtx7VarLat.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-01-14 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Gtx7 Variable Latency Wrapper ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLatWrapper.vhd b/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLatWrapper.vhd index 1333074f6e..1b93696255 100644 --- a/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLatWrapper.vhd +++ b/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLatWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGtx7VarLatWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-01-29 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Example PGP 3.125 Gbps front end wrapper -- Note: Default generic configurations are for the KC705 development board @@ -32,16 +30,30 @@ entity Pgp2bGtx7VarLatWrapper is generic ( TPD_G : time := 1 ns; -- MMCM Configurations (Defaults: gtClkP = 125 MHz Configuration) + -- See page 40 of https://www.xilinx.com/support/documentation/user_guides/ug362.pdf + -- CLKIN_PERIOD_G (ns) is 1/2 of the reference rate because the MMCM gets a div/2 copy + -- MMCM internal frequency is set by: + -- FVCO = 1000 * CLKFBOUT_MULT_F_G/(CLKIN1_PERIOD_G * DIVCLK_DIVIDE_G) + -- And must be within the specified operating range of the PLL (around 1Ghz) CLKIN_PERIOD_G : real := 16.0; -- gtClkP/2 DIVCLK_DIVIDE_G : natural range 1 to 106 := 2; CLKFBOUT_MULT_F_G : real range 1.0 to 64.0 := 31.875; CLKOUT0_DIVIDE_F_G : real range 1.0 to 128.0 := 6.375; -- CPLL Configurations (Defaults: gtClkP = 125 MHz Configuration) + -- See page 48 of https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf + -- fPllClkOut = fPLLClkIn * ( CPLL_FBDIV_G * CPLL_FBDIV_45_G ) / CPLL_REFCLK_DIV_G + -- CPPL_FBDIV_G = 1,2,3,4,5 + -- CPPL_FBDIV_45_G = 4,5 + -- CPLL_REFCLK_DIV_G = 1,2 + -- fPllClkOut must bet between 1.6Ghz - 3.3Ghz CPLL_REFCLK_SEL_G : bit_vector := "001"; CPLL_FBDIV_G : natural := 5; CPLL_FBDIV_45_G : natural := 5; CPLL_REFCLK_DIV_G : natural := 1; -- MGT Configurations (Defaults: gtClkP = 125 MHz Configuration) + -- Rx Line rate = (fPllClkOut * 2) / RXOUT_DIV_G (1,2,4,6,16) + -- Tx Line rate = (fPllClkOut * 2) / TXOUT_DIV_G (1,2,4,6,16) + -- Set RX_CLK25_DIV and TX_CLK25_DIV so that the input reference clock / setting is close to 25Mhz RXOUT_DIV_G : natural := 2; TXOUT_DIV_G : natural := 2; RX_CLK25_DIV_G : natural := 5; diff --git a/protocols/pgp/pgp2b/gtx7/tb/Pgp2bGtx7FixedLatWrapperTb.vhd b/protocols/pgp/pgp2b/gtx7/tb/Pgp2bGtx7FixedLatWrapperTb.vhd index 5cbef365ec..1eca0d7477 100644 --- a/protocols/pgp/pgp2b/gtx7/tb/Pgp2bGtx7FixedLatWrapperTb.vhd +++ b/protocols/pgp/pgp2b/gtx7/tb/Pgp2bGtx7FixedLatWrapperTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGtx7FixedLatWrapperTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-31 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for Pgp2bGtx7FixedLatWrapper ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gtx7/tb/Pgp2bGtx7FixedlatTb.vhd b/protocols/pgp/pgp2b/gtx7/tb/Pgp2bGtx7FixedlatTb.vhd index 780ccdf922..eb286db8ca 100644 --- a/protocols/pgp/pgp2b/gtx7/tb/Pgp2bGtx7FixedlatTb.vhd +++ b/protocols/pgp/pgp2b/gtx7/tb/Pgp2bGtx7FixedlatTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGtx7FixedLatTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-27 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for Pgp2bGtx7FixedLat ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2b/gtx7/tb/Pgp2bGtx7VarLatWrapperTb.vhd b/protocols/pgp/pgp2b/gtx7/tb/Pgp2bGtx7VarLatWrapperTb.vhd index 5cc1b68140..013073a4aa 100644 --- a/protocols/pgp/pgp2b/gtx7/tb/Pgp2bGtx7VarLatWrapperTb.vhd +++ b/protocols/pgp/pgp2b/gtx7/tb/Pgp2bGtx7VarLatWrapperTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bGtx7VarLatWrapperTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-31 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for Pgp2bGtx7VarLatWrapper ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp3/core/rtl/Pgp3AxiL.vhd b/protocols/pgp/pgp3/core/rtl/Pgp3AxiL.vhd index efa6c07936..c68538041a 100644 --- a/protocols/pgp/pgp3/core/rtl/Pgp3AxiL.vhd +++ b/protocols/pgp/pgp3/core/rtl/Pgp3AxiL.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp2bAxi.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2009-05-27 --- Last update: 2018-01-10 ------------------------------------------------------------------------------- -- Description: -- AXI-Lite block to manage the PGP3 interface. diff --git a/protocols/pgp/pgp3/core/rtl/Pgp3Core.vhd b/protocols/pgp/pgp3/core/rtl/Pgp3Core.vhd index 9722c6f711..701e7c162e 100644 --- a/protocols/pgp/pgp3/core/rtl/Pgp3Core.vhd +++ b/protocols/pgp/pgp3/core/rtl/Pgp3Core.vhd @@ -52,8 +52,8 @@ entity Pgp3Core is -- Tx PHY interface phyTxActive : in sl; phyTxReady : in sl; + phyTxValid : out sl; phyTxStart : out sl; - phyTxSequence : out slv(5 downto 0); phyTxData : out slv(63 downto 0); phyTxHeader : out slv(1 downto 0); @@ -129,8 +129,8 @@ begin remRxLinkReady => remRxLinkReady, -- [in] phyTxActive => phyTxActive, --[in] phyTxReady => phyTxReady, -- [in] + phyTxValid => phyTxValid, -- [out] phyTxStart => phyTxStart, -- [out] - phyTxSequence => phyTxSequence, -- [out] phyTxData => phyTxData, -- [out] phyTxHeader => phyTxHeader); -- [out] diff --git a/protocols/pgp/pgp3/core/rtl/Pgp3Pkg.vhd b/protocols/pgp/pgp3/core/rtl/Pgp3Pkg.vhd index 32859fe0a6..2cdc19782a 100644 --- a/protocols/pgp/pgp3/core/rtl/Pgp3Pkg.vhd +++ b/protocols/pgp/pgp3/core/rtl/Pgp3Pkg.vhd @@ -2,7 +2,6 @@ -- Title : PGP3 Support Package ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory --- Created : 2017-03-30 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- @@ -123,6 +122,7 @@ package Pgp3Pkg is locPause : slv(15 downto 0); phyTxActive : sl; linkReady : sl; + opCodeReady : sl; frameTx : sl; -- A good frame was transmitted frameTxErr : sl; -- An errored frame was transmitted end record; @@ -134,6 +134,7 @@ package Pgp3Pkg is locPause => (others => '0'), phyTxActive => '0', linkReady => '0', + opCodeReady => '0', frameTx => '0', frameTxErr => '0'); diff --git a/protocols/pgp/pgp3/core/rtl/Pgp3Rx.vhd b/protocols/pgp/pgp3/core/rtl/Pgp3Rx.vhd index 6636024e7c..a5775df6d7 100644 --- a/protocols/pgp/pgp3/core/rtl/Pgp3Rx.vhd +++ b/protocols/pgp/pgp3/core/rtl/Pgp3Rx.vhd @@ -2,8 +2,6 @@ -- Title : Pgp3 Receive Block ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory --- Created : 2017-04-07 --- Last update: 2018-03-02 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp3/core/rtl/Pgp3RxProtocol.vhd b/protocols/pgp/pgp3/core/rtl/Pgp3RxProtocol.vhd index 7b47dd5597..7ca82e5995 100644 --- a/protocols/pgp/pgp3/core/rtl/Pgp3RxProtocol.vhd +++ b/protocols/pgp/pgp3/core/rtl/Pgp3RxProtocol.vhd @@ -2,7 +2,6 @@ -- Title : PGP3 Receive Protocol ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory --- Created : 2017-03-30 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- @@ -189,6 +188,8 @@ begin -- Verify checksun if (protRxData(PGP3_USER_CHECKSUM_FIELD_C) = opCodeChecksum) then v.pgpRxOut.opCodeEn := '1'; + else + v.pgpRxOut.linkError := '1'; end if; end if; end loop; diff --git a/protocols/pgp/pgp3/core/rtl/Pgp3Tx.vhd b/protocols/pgp/pgp3/core/rtl/Pgp3Tx.vhd index a760a8ce45..404a0e898a 100644 --- a/protocols/pgp/pgp3/core/rtl/Pgp3Tx.vhd +++ b/protocols/pgp/pgp3/core/rtl/Pgp3Tx.vhd @@ -2,7 +2,6 @@ -- Title : Pgp3 Transmit ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory --- Created : 2017-03-30 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- @@ -60,8 +59,8 @@ entity Pgp3Tx is -- PHY interface phyTxActive : in sl; phyTxReady : in sl; + phyTxValid : out sl; phyTxStart : out sl; - phyTxSequence : out slv(5 downto 0); phyTxData : out slv(63 downto 0); phyTxHeader : out slv(1 downto 0)); @@ -86,7 +85,6 @@ architecture rtl of Pgp3Tx is signal phyTxActiveL : sl; signal protTxValid : sl; signal protTxReady : sl; - signal protTxSequence : slv(5 downto 0); signal protTxStart : sl; signal protTxData : slv(63 downto 0); signal protTxHeader : slv(1 downto 0); @@ -223,7 +221,6 @@ begin protTxReady => protTxReady, -- [in] protTxValid => protTxValid, -- [out] protTxStart => protTxStart, -- [out] - protTxSequence => protTxSequence, -- [out] protTxData => protTxData, -- [out] protTxHeader => protTxHeader); -- [out] @@ -233,22 +230,23 @@ begin TPD_G => TPD_G, DIRECTION_G => "SCRAMBLER", DATA_WIDTH_G => 64, - SIDEBAND_WIDTH_G => 9, + SIDEBAND_WIDTH_G => 3, TAPS_G => PGP3_SCRAMBLER_TAPS_C) port map ( clk => pgpTxClk, -- [in] rst => phyTxActiveL, -- [in] + -- Input Interface inputValid => protTxValid, -- [in] inputReady => protTxReady, -- [out] inputData => protTxData, -- [in] inputSideband(1 downto 0) => protTxHeader, -- [in] inputSideband(2) => protTxStart, -- [in] - inputSideband(8 downto 3) => protTxSequence, -- [in] + -- Output Interface + outputValid => phyTxValid, -- [out] outputReady => phyTxReady, -- [in] outputData => phyTxData, -- [out] outputSideband(1 downto 0) => phyTxHeader, -- [out] - outputSideband(2) => phyTxStart, -- [out] - outputSideband(8 downto 3) => phyTxSequence); -- [out] + outputSideband(2) => phyTxStart); -- [out] phyTxActiveL <= not(phyTxActive); diff --git a/protocols/pgp/pgp3/core/rtl/Pgp3TxProtocol.vhd b/protocols/pgp/pgp3/core/rtl/Pgp3TxProtocol.vhd index ca9e0d6ff7..5c12da1952 100644 --- a/protocols/pgp/pgp3/core/rtl/Pgp3TxProtocol.vhd +++ b/protocols/pgp/pgp3/core/rtl/Pgp3TxProtocol.vhd @@ -2,7 +2,6 @@ -- Title : PGP3 Transmit Protocol ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory --- Created : 2017-03-30 ------------------------------------------------------------------------------- -- Description: -- Takes pre-packetized AxiStream frames and creates a PGP3 66/64 protocol @@ -58,7 +57,6 @@ entity Pgp3TxProtocol is protTxReady : in sl; protTxValid : out sl; protTxStart : out sl; - protTxSequence : out slv(5 downto 0); protTxData : out slv(63 downto 0); protTxHeader : out slv(1 downto 0)); @@ -76,12 +74,12 @@ architecture rtl of Pgp3TxProtocol is skpCount : slv(31 downto 0); startupCount : integer; pgpTxSlave : AxiStreamSlaveType; + opCodeReady : sl; linkReady : sl; frameTx : sl; frameTxErr : sl; protTxValid : sl; protTxStart : sl; - protTxSequence : slv(5 downto 0); protTxData : slv(63 downto 0); protTxHeader : slv(1 downto 0); end record RegType; @@ -96,12 +94,12 @@ architecture rtl of Pgp3TxProtocol is skpCount => (others => '0'), startupCount => 0, pgpTxSlave => AXI_STREAM_SLAVE_INIT_C, + opCodeReady => '0', linkReady => '0', frameTx => '0', frameTxErr => '0', protTxValid => '0', protTxStart => '0', - protTxSequence => (others => '0'), protTxData => (others => '0'), protTxHeader => (others => '0')); @@ -154,6 +152,7 @@ begin -- Don't accept new frame data by default v.pgpTxSlave.tReady := '0'; + v.opCodeReady := '0'; v.frameTx := '0'; v.frameTxErr := '0'; @@ -173,13 +172,6 @@ begin v.linkReady := '1'; v.protTxStart := '1'; v.protTxValid := '1'; - -- Check for max seq count - if(r.protTxSequence = 32) then - v.protTxSequence := (others => '0'); - else - -- Increment the counter - v.protTxSequence := r.protTxSequence + 1; - end if; else -- Increment the counter v.startupCount := r.startupCount + 1; @@ -241,11 +233,17 @@ begin -- USER codes override data and delay SKP if they happen to coincide if (pgpTxIn.opCodeEn = '1' and dataEn = '1') then - v.pgpTxSlave.tReady := '0'; -- Override any data acceptance. + -- Override any data acceptance. + v.pgpTxSlave.tReady := '0'; + -- Accept the op-code + v.opCodeReady := '1'; + + -- Update the TX data bus v.protTxData(PGP3_BTF_FIELD_C) := PGP3_USER_C(conv_integer(pgpTxIn.opCodeNumber)); v.protTxData(PGP3_USER_CHECKSUM_FIELD_C) := pgp3OpCodeChecksum(pgpTxIn.opCodeData); v.protTxData(PGP3_USER_OPCODE_FIELD_C) := pgpTxIn.opCodeData; v.protTxHeader := PGP3_K_HEADER_C; + -- If skip was interrupted, hold it for next cycle if (r.skpCount = SKP_INTERVAL_G-1) then v.skpCount := r.skpCount; @@ -284,7 +282,6 @@ begin if (pgpTxIn.disable = '1') then v.linkReady := '0'; v.protTxStart := '0'; - v.protTxSequence := (others => '0'); v.startupCount := 0; v.protTxData := (others => '0'); v.protTxHeader := (others => '0'); @@ -296,7 +293,6 @@ begin if (phyTxActive = '0') then v.linkReady := '0'; v.protTxStart := '0'; - v.protTxSequence := (others => '0'); v.startupCount := 0; end if; @@ -308,25 +304,19 @@ begin v.overflowEventSent := (others => '0'); end if; - -- Combinatorial outputs before the reset + -- Outputs pgpTxSlave <= v.pgpTxSlave; - - if (pgpTxRst = '1') then - v := REG_INIT_C; - end if; - - rin <= v; - + protTxData <= r.protTxData; protTxHeader <= r.protTxHeader; protTxValid <= r.protTxValid; protTxStart <= r.protTxStart; - protTxSequence <= r.protTxSequence; pgpTxOut.phyTxActive <= phyTxActive; pgpTxOut.linkReady <= r.linkReady; pgpTxOut.frameTx <= r.frameTx; pgpTxOut.frameTxErr <= r.frameTxErr; + pgpTxOut.opCodeReady <= v.opCodeReady; for i in 15 downto 0 loop if (i < NUM_VC_G) then @@ -337,6 +327,14 @@ begin pgpTxOut.locPause(i) <= '0'; end if; end loop; + + -- Reset + if (pgpTxRst = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; end process comb; diff --git a/protocols/pgp/pgp3/core/tb/Pgp3Tb2.vhd b/protocols/pgp/pgp3/core/tb/Pgp3Tb2.vhd index 519ca1f5f5..076db82d62 100644 --- a/protocols/pgp/pgp3/core/tb/Pgp3Tb2.vhd +++ b/protocols/pgp/pgp3/core/tb/Pgp3Tb2.vhd @@ -174,7 +174,6 @@ begin phyTxActive => '1', -- [in] phyTxReady => '1', -- [in] phyTxStart => open, -- [out] - phyTxSequence => open, -- [out] phyTxData => phyTxData0, -- [out] phyTxHeader => phyTxHeader0, -- [out] pgpRxClk => axisClk, -- [in] @@ -241,7 +240,6 @@ begin phyTxActive => '1', -- [in] phyTxReady => '1', -- [in] phyTxStart => open, -- [out] - phyTxSequence => open, -- [out] phyTxData => phyTxData1, -- [out] phyTxHeader => phyTxHeader1, -- [out] pgpRxClk => axisClk, -- [in] diff --git a/protocols/pgp/pgp3/core/tb/RoguePgp3Sim.vhd b/protocols/pgp/pgp3/core/tb/RoguePgp3Sim.vhd index 67f0a045e0..104f0b8191 100644 --- a/protocols/pgp/pgp3/core/tb/RoguePgp3Sim.vhd +++ b/protocols/pgp/pgp3/core/tb/RoguePgp3Sim.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RoguePgp3Sim.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2018-06-19 --- Last update: 2018-06-19 ------------------------------------------------------------------------------- -- Description: Wrapper on RogueStreamSim to simulate a PGPv3 ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd index f6f297c6ae..25983fc9f4 100644 --- a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd +++ b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp3GthUs.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-06-29 --- Last update: 2018-05-08 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -50,8 +48,8 @@ entity Pgp3GthUs is TX_MUX_TDEST_LOW_G : integer range 0 to 7 := 0; TX_MUX_ILEAVE_EN_G : boolean := true; TX_MUX_ILEAVE_ON_NOTVALID_G : boolean := true; - EN_DRP_G : boolean := true; - EN_PGP_MON_G : boolean := true; + EN_DRP_G : boolean := false; + EN_PGP_MON_G : boolean := false; TX_POLARITY_G : sl := '0'; RX_POLARITY_G : sl := '0'; AXIL_BASE_ADDR_G : slv(31 downto 0) := (others => '0'); @@ -120,7 +118,6 @@ architecture rtl of Pgp3GthUs is -- signal gtTxUserReset : sl; signal phyTxActive : sl; signal phyTxStart : sl; - signal phyTxSequence : slv(5 downto 0); signal phyTxData : slv(63 downto 0); signal phyTxHeader : slv(1 downto 0); @@ -225,7 +222,6 @@ begin phyTxActive => phyTxActive, -- [in] phyTxReady => '1', -- [in] phyTxStart => phyTxStart, -- [out] - phyTxSequence => phyTxSequence, -- [out] phyTxData => phyTxData, -- [out] phyTxHeader => phyTxHeader, -- [out] -- Rx User interface @@ -297,7 +293,6 @@ begin txUsrClkRst => pgpTxRstInt, -- [out] txData => phyTxData, -- [in] txHeader => phyTxHeader, -- [in] - txSequence => phyTxSequence, -- [in] txOutClk => open, -- [out] loopback => loopback, -- [in] axilClk => axilClk, -- [in] diff --git a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd index f4e2f58bfd..39d55ee837 100644 --- a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd +++ b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp3GthUsIpWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-06-29 --- Last update: 2018-05-03 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -63,7 +61,6 @@ entity Pgp3GthUsIpWrapper is txUsrClkRst : out sl; txData : in slv(63 downto 0); txHeader : in slv(1 downto 0); - txSequence : in slv(5 downto 0); txOutClk : out sl; loopback : in slv(2 downto 0); diff --git a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd index 3b1448d2cf..018d4a9423 100644 --- a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd +++ b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp3GthUsQpll.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-10-26 --- Last update: 2018-05-03 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd index 7a95e67b49..61ef17449d 100644 --- a/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd +++ b/protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp3GthUsWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-10-27 --- Last update: 2018-06-19 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -54,9 +52,9 @@ entity Pgp3GthUsWrapper is TX_MUX_TDEST_LOW_G : integer range 0 to 7 := 0; TX_MUX_ILEAVE_EN_G : boolean := true; TX_MUX_ILEAVE_ON_NOTVALID_G : boolean := true; - EN_PGP_MON_G : boolean := true; - EN_GTH_DRP_G : boolean := true; - EN_QPLL_DRP_G : boolean := true; + EN_PGP_MON_G : boolean := false; + EN_GTH_DRP_G : boolean := false; + EN_QPLL_DRP_G : boolean := false; TX_POLARITY_G : slv(3 downto 0) := x"0"; RX_POLARITY_G : slv(3 downto 0) := x"0"; AXIL_BASE_ADDR_G : slv(31 downto 0) := (others => '0'); @@ -90,8 +88,8 @@ entity Pgp3GthUsWrapper is pgpTxSlaves : out AxiStreamSlaveArray((NUM_LANES_G*NUM_VC_G)-1 downto 0); -- Frame Receive Interface pgpRxMasters : out AxiStreamMasterArray((NUM_LANES_G*NUM_VC_G)-1 downto 0); - pgpRxCtrl : in AxiStreamCtrlArray((NUM_LANES_G*NUM_VC_G)-1 downto 0); -- Unused in implementation only - pgpRxSlaves : in AxiStreamSlaveArray((NUM_LANES_G*NUM_VC_G)-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); -- Unused in simulation only + pgpRxCtrl : in AxiStreamCtrlArray((NUM_LANES_G*NUM_VC_G)-1 downto 0); -- Used in implementation only + pgpRxSlaves : in AxiStreamSlaveArray((NUM_LANES_G*NUM_VC_G)-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); -- Used in simulation only -- AXI-Lite Register Interface (axilClk domain) axilClk : in sl := '0'; -- Stable Clock axilRst : in sl := '0'; diff --git a/protocols/pgp/pgp3/gtp7/ip/Pgp3Gtp7Ip3G.dcp b/protocols/pgp/pgp3/gtp7/ip/Pgp3Gtp7Ip3G.dcp new file mode 100644 index 0000000000..5d7d970197 --- /dev/null +++ b/protocols/pgp/pgp3/gtp7/ip/Pgp3Gtp7Ip3G.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:040feed86f6662e1c714174467de5e79f2a83d666652a339f97b65a5d9839623 +size 166474 diff --git a/protocols/pgp/pgp3/gtp7/ip/Pgp3Gtp7Ip3G.xci b/protocols/pgp/pgp3/gtp7/ip/Pgp3Gtp7Ip3G.xci new file mode 100644 index 0000000000..e2b339f1cc --- /dev/null +++ b/protocols/pgp/pgp3/gtp7/ip/Pgp3Gtp7Ip3G.xci @@ -0,0 +1,1368 @@ + + + xilinx.com + xci + unknown + 1.0 + + + Pgp3Gtp7Ip3G + + + false + xc7a200t + -2 + Pgp3Gtp7Ip3G + 0 + 5 + 5 + 2 + 2 + 2 + 1 + 4 + 1 + 2 + 2 + false + 0 + true + Auto + false + 1111111111 + Any_Byte_Boundary + true + 1010000011 + true + 0101111100 + false + false + 5000 + 1 + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + false + 1 + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + false + 1 + User_defined + 1 + 4 + 1 + 1 + 1 + false + false + false + 64B/66B + LPM-Auto + true + 125 + 64B/66B_with_Ext_Seq_Ctr + 7 + false + false + false + false + 60 + 60 + 100 + false + false + false + false + false + true + false + false + false + false + true + false + false + false + false + false + false + false + false + false + true + false + true + false + false + true + false + true + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + true + false + false + false + false + false + true + true + false + false + false + false + false + false + false + false + false + false + false + 100 + false + aurora_8b10b_single_lane_4byte + 16 + 1 + Auto + 800 + 32 + false + 16 + 3.125 + REFCLK1_Q0 + 250.000 + Programmable + false + false + AUTO + false + OFF + RXOUTCLK + 4 + 4 + Manual + 32 + 16 + 3.125 + REFCLK1_Q0 + 250.000 + true + Custom + true + false + AUTO + true + true + TXOUTCLK + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q0 + REFCLK1_Q0 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q0 + REFCLK1_Q0 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q0 + REFCLK1_Q0 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q2 + REFCLK1_Q2 + left_column + top_row + GTP + false + 100 + false + PLL0 + false + PLL0 + false + 160 + GB_100GBASE_R4 + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + 160 + GB_100GBASE_R4 + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + 160 + GB_100GBASE_R4 + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + 160 + GB_100GBASE_R4 + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + 160 + GB_100GBASE_R4 + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + 160 + GB_100GBASE_R4 + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + 160 + GB_100GBASE_R4 + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + 160 + GB_100GBASE_R4 + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + true + aurora_8b10b_single_lane_4byte + false + false + 3.125 + 250.000 + 3.125 + 250.000 + 1 + 1 + true + DRPCLK0 + true + false + false + Start_from_scratch + REFCLK0 + 25.78125 + 25.78125 + false + 0000 + 322.266 + 322.266 + LANE0 + LANE0 + LANE0 + LANE0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + LANE0 + LANE0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + false + false + One_Hop + DFE + false + false + no_silicon_version_loaded + 1000 + true + true + true + true + true + true + true + true + Pgp3Gtp7Ip3G + false + 0 + 5 + 5 + 2 + 2 + 2 + 1 + 4 + 1 + 2 + 2 + false + 0 + true + Auto + false + 1111111111 + Any_Byte_Boundary + true + 1010000011 + true + 0101111100 + false + false + 5000 + 1 + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + false + 1 + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + false + 1 + User_defined + 1 + 4 + 1 + 1 + 1 + false + false + false + 64B/66B + LPM-Auto + true + 125 + 64B/66B_with_Ext_Seq_Ctr + 7 + false + false + false + false + 60 + 60 + 100 + false + false + false + false + false + true + false + false + false + false + true + false + false + false + false + false + false + false + false + false + true + false + true + false + false + true + false + true + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + true + false + false + false + false + false + true + true + false + false + false + false + false + false + false + false + false + false + 100 + false + aurora_8b10b_single_lane_4byte + 16 + 1 + Auto + 800 + 32 + false + 16 + 3.125 + REFCLK1_Q0 + 250.000 + Programmable + false + false + false + false + OFF + RXOUTCLK + 4 + 4 + Manual + 32 + 16 + 3.125 + REFCLK1_Q0 + 250.000 + true + Custom + true + false + false + true + true + TXOUTCLK + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q0 + REFCLK1_Q0 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q0 + REFCLK1_Q0 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q0 + REFCLK1_Q0 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q2 + REFCLK1_Q2 + left_column + top_row + GTP + false + 100 + false + PLL0 + PLL0 + 160 + 100GBASER_MODE + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + 160 + 100GBASER_MODE + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + 160 + 100GBASER_MODE + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + 160 + 100GBASER_MODE + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + 160 + 100GBASER_MODE + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + 160 + 100GBASER_MODE + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + 160 + 100GBASER_MODE + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + 160 + 100GBASER_MODE + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + GTZ0 + true + aurora_8b10b_single_lane_4byte + false + false + 3.125 + 250.000 + 3.125 + 250.000 + true + DRPCLK0 + true + false + false + Start_from_scratch + REFCLK0 + 25.78125 + 25.78125 + false + OFF + 322.266 + 322.266 + RXOUTCLK_LANE0 + RXOUTCLK_LANE0 + RXOUTCLK_LANE0 + RXOUTCLK_LANE0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + TXOUTCLK_LANE0 + TXOUTCLK_LANE0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + false + false + One_Hop + DFE + false + false + no_silicon_version_loaded + 1000 + true + true + true + true + true + true + true + true + artix7 + xilinx.com:ac701:part0:1.3 + xc7a200t + fbg676 + VHDL + + MIXED + -2 + + TRUE + TRUE + IP_Flow + 9 + TRUE + . + + . + 2018.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/protocols/pgp/pgp3/gtp7/ip/Pgp3Gtp7Ip6G.dcp b/protocols/pgp/pgp3/gtp7/ip/Pgp3Gtp7Ip6G.dcp new file mode 100644 index 0000000000..88c5d4c0ee --- /dev/null +++ b/protocols/pgp/pgp3/gtp7/ip/Pgp3Gtp7Ip6G.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:5eeb54c9d267b6beda75b1872eff7ab4156d62856a5a3450fbde1daefe42d6a9 +size 165937 diff --git a/protocols/pgp/pgp3/gtp7/ip/Pgp3Gtp7Ip6G.xci b/protocols/pgp/pgp3/gtp7/ip/Pgp3Gtp7Ip6G.xci new file mode 100644 index 0000000000..40871c190c --- /dev/null +++ b/protocols/pgp/pgp3/gtp7/ip/Pgp3Gtp7Ip6G.xci @@ -0,0 +1,1367 @@ + + + xilinx.com + xci + unknown + 1.0 + + + Pgp3Gtp7Ip6G + + + false + xc7a200t + -2 + Pgp3Gtp7Ip6G + 0 + 5 + 5 + 2 + 1 + 1 + 1 + 4 + 1 + 1 + 1 + false + 0 + true + Auto + false + 1111111111 + Any_Byte_Boundary + true + 1010000011 + true + 0101111100 + false + false + 5000 + 1 + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + false + 1 + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + false + 1 + User_defined + 1 + 4 + 1 + 1 + 1 + false + false + false + 64B/66B + LPM-Auto + true + 125 + 64B/66B_with_Ext_Seq_Ctr + 7 + false + false + false + false + 60 + 60 + 100 + false + false + false + false + false + true + false + false + false + false + true + false + false + false + false + false + false + false + false + false + true + false + true + false + false + true + false + true + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + true + false + false + false + false + false + true + true + false + false + false + false + false + false + false + false + false + false + false + 100 + false + aurora_8b10b_single_lane_4byte + 16 + 1 + Auto + 800 + 32 + false + 16 + 6.25 + REFCLK1_Q0 + 250.000 + Programmable + false + false + AUTO + false + OFF + RXOUTCLK + 4 + 4 + Auto + 32 + 16 + 6.25 + REFCLK1_Q0 + 250.000 + true + Custom + true + false + AUTO + true + true + TXOUTCLK + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q0 + REFCLK1_Q0 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q0 + REFCLK1_Q0 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q0 + REFCLK1_Q0 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q2 + REFCLK1_Q2 + left_column + top_row + GTP + false + 100 + false + PLL0 + false + PLL0 + false + 160 + GB_100GBASE_R4 + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + 160 + GB_100GBASE_R4 + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + 160 + GB_100GBASE_R4 + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + 160 + GB_100GBASE_R4 + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + 160 + GB_100GBASE_R4 + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + 160 + GB_100GBASE_R4 + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + 160 + GB_100GBASE_R4 + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + 160 + GB_100GBASE_R4 + false + false + Start_from_scratch + REFCLK0 + 0.5 + 5 + 8 + 25.78125 + RXRECCLKPMA_DIV4 + RXUSRCLK0 + 0.5 + 5 + 8 + 25.78125 + TXOUTCLKPMA_DIV4 + TXUSRCLK0 + true + aurora_8b10b_single_lane_4byte + false + false + 6.25 + 250.000 + 6.25 + 250.000 + 1 + 1 + true + DRPCLK0 + true + false + false + Start_from_scratch + REFCLK0 + 25.78125 + 25.78125 + false + 0000 + 322.266 + 322.266 + LANE0 + LANE0 + LANE0 + LANE0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + LANE0 + LANE0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + false + false + One_Hop + DFE + false + false + no_silicon_version_loaded + 1000 + true + true + true + true + true + true + true + true + Pgp3Gtp7Ip6G + false + 0 + 5 + 5 + 2 + 1 + 1 + 1 + 4 + 1 + 1 + 1 + false + 0 + true + Auto + false + 1111111111 + Any_Byte_Boundary + true + 1010000011 + true + 0101111100 + false + false + 5000 + 1 + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + false + 1 + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + false + 1 + User_defined + 1 + 4 + 1 + 1 + 1 + false + false + false + 64B/66B + LPM-Auto + true + 125 + 64B/66B_with_Ext_Seq_Ctr + 7 + false + false + false + false + 60 + 60 + 100 + false + false + false + false + false + true + false + false + false + false + true + false + false + false + false + false + false + false + false + false + true + false + true + false + false + true + false + true + true + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + true + false + false + false + false + false + true + true + false + false + false + false + false + false + false + false + false + false + 100 + false + aurora_8b10b_single_lane_4byte + 16 + 1 + Auto + 800 + 32 + false + 16 + 6.25 + REFCLK1_Q0 + 250.000 + Programmable + false + false + false + false + OFF + RXOUTCLK + 4 + 4 + Auto + 32 + 16 + 6.25 + REFCLK1_Q0 + 250.000 + true + Custom + true + false + false + true + true + TXOUTCLK + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q0 + REFCLK1_Q0 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q0 + REFCLK1_Q0 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q0 + REFCLK1_Q0 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q2 + REFCLK1_Q2 + left_column + top_row + GTP + false + 100 + false + PLL0 + PLL0 + 160 + 100GBASER_MODE + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + 160 + 100GBASER_MODE + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + 160 + 100GBASER_MODE + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + 160 + 100GBASER_MODE + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + 160 + 100GBASER_MODE + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + 160 + 100GBASER_MODE + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + 160 + 100GBASER_MODE + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + 160 + 100GBASER_MODE + false + false + Start_from_scratch + REFCLK0 + 25.78125 + RX_FIFO_CLK + RXUSRCLK0 + 25.78125 + TX_FIFO_CLK + TXUSRCLK0 + GTZ0 + true + aurora_8b10b_single_lane_4byte + false + false + 6.25 + 250.000 + 6.25 + 250.000 + true + DRPCLK0 + true + false + false + Start_from_scratch + REFCLK0 + 25.78125 + 25.78125 + false + OFF + 322.266 + 322.266 + RXOUTCLK_LANE0 + RXOUTCLK_LANE0 + RXOUTCLK_LANE0 + RXOUTCLK_LANE0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + TXOUTCLK_LANE0 + TXOUTCLK_LANE0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + false + false + One_Hop + DFE + false + false + no_silicon_version_loaded + 1000 + true + true + true + true + true + true + true + true + artix7 + xilinx.com:ac701:part0:1.3 + xc7a200t + fbg676 + VHDL + + MIXED + -2 + + TRUE + TRUE + IP_Flow + 9 + TRUE + . + + . + 2018.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7.vhd b/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7.vhd new file mode 100644 index 0000000000..94f58d3c8b --- /dev/null +++ b/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7.vhd @@ -0,0 +1,347 @@ +------------------------------------------------------------------------------- +-- File : Pgp3Gtp7.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.StdRtlPkg.all; +use work.AxiStreamPkg.all; +use work.AxiLitePkg.all; +use work.Pgp3Pkg.all; + +library UNISIM; +use UNISIM.VCOMPONENTS.all; + +entity Pgp3Gtp7 is + generic ( + TPD_G : time := 1 ns; + RATE_G : string := "6.25Gbps"; -- or "3.125Gbps" + CLKIN_PERIOD_G : real; + BANDWIDTH_G : string; + CLKFBOUT_MULT_G : positive; + CLKOUT0_DIVIDE_G : positive; + CLKOUT1_DIVIDE_G : positive; + CLKOUT2_DIVIDE_G : positive; + ---------------------------------------------------------------------------------------------- + -- PGP Settings + ---------------------------------------------------------------------------------------------- + PGP_RX_ENABLE_G : boolean := true; + RX_ALIGN_GOOD_COUNT_G : integer := 128; + RX_ALIGN_BAD_COUNT_G : integer := 16; + RX_ALIGN_SLIP_WAIT_G : integer := 32; + PGP_TX_ENABLE_G : boolean := true; + NUM_VC_G : integer range 1 to 16 := 4; + TX_CELL_WORDS_MAX_G : integer := PGP3_DEFAULT_TX_CELL_WORDS_MAX_C; -- Number of 64-bit words per cell + TX_SKP_INTERVAL_G : integer := 5000; + TX_SKP_BURST_SIZE_G : integer := 8; + TX_MUX_MODE_G : string := "INDEXED"; -- Or "ROUTED" + TX_MUX_TDEST_ROUTES_G : Slv8Array := (0 => "--------"); -- Only used in ROUTED mode + TX_MUX_TDEST_LOW_G : integer range 0 to 7 := 0; + TX_MUX_ILEAVE_EN_G : boolean := true; + TX_MUX_ILEAVE_ON_NOTVALID_G : boolean := true; + EN_DRP_G : boolean := false; + EN_PGP_MON_G : boolean := false; + TX_POLARITY_G : sl := '0'; + RX_POLARITY_G : sl := '0'; + AXIL_BASE_ADDR_G : slv(31 downto 0) := (others => '0'); + AXIL_CLK_FREQ_G : real := 156.25E+6); + port ( + -- Stable Clock and Reset + stableClk : in sl; -- GT needs a stable clock to "boot up" + stableRst : in sl; + -- QPLL Interface + qPllOutClk : in slv(1 downto 0); + qPllOutRefClk : in slv(1 downto 0); + qPllLock : in slv(1 downto 0); + qPllRefClkLost : in slv(1 downto 0); + qpllRst : out slv(1 downto 0); + -- TX PLL Interface + gtTxOutClk : out sl; + gtTxPllRst : out sl; + txPllClk : in slv(2 downto 0); + txPllRst : in slv(2 downto 0); + gtTxPllLock : in sl; + -- Gt Serial IO + pgpGtTxP : out sl; + pgpGtTxN : out sl; + pgpGtRxP : in sl; + pgpGtRxN : in sl; + -- Clocking + pgpClk : out sl; + pgpClkRst : out sl; + -- Non VC Rx Signals + pgpRxIn : in Pgp3RxInType; + pgpRxOut : out Pgp3RxOutType; + -- Non VC Tx Signals + pgpTxIn : in Pgp3TxInType; + pgpTxOut : out Pgp3TxOutType; + -- Frame Transmit Interface + pgpTxMasters : in AxiStreamMasterArray(NUM_VC_G-1 downto 0); + pgpTxSlaves : out AxiStreamSlaveArray(NUM_VC_G-1 downto 0); + -- Frame Receive Interface + pgpRxMasters : out AxiStreamMasterArray(NUM_VC_G-1 downto 0); + pgpRxCtrl : in AxiStreamCtrlArray(NUM_VC_G-1 downto 0); + -- Debug Interface + txPreCursor : in slv(4 downto 0) := "00111"; + txPostCursor : in slv(4 downto 0) := "00111"; + txDiffCtrl : in slv(3 downto 0) := "1111"; + -- AXI-Lite Register Interface (axilClk domain) + axilClk : in sl := '0'; + axilRst : in sl := '0'; + axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + axilReadSlave : out AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C; + axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + axilWriteSlave : out AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C); +end Pgp3Gtp7; + +architecture rtl of Pgp3Gtp7 is + + -- Clocks and Resets + signal phyRxClk : sl := '0'; + signal phyRxRst : sl := '1'; + signal phyTxClk : sl := '0'; + signal phyTxRst : sl := '1'; + + -- PgpRx Signals + signal phyRxInit : sl := '0'; + signal phyRxActive : sl := '0'; + signal phyRxValid : sl := '0'; + signal phyRxHeader : slv(1 downto 0) := (others => '0'); + signal phyRxData : slv(63 downto 0) := (others => '0'); + signal phyRxSlip : sl := '0'; + signal locRxOut : Pgp3RxOutType; + + -- PgpTx Signals + signal phyTxActive : sl := '0'; + signal phyTxHeader : slv(1 downto 0) := (others => '0'); + signal phyTxData : slv(63 downto 0) := (others => '0'); + signal phyTxValid : sl := '0'; + signal phyTxDataRdy : sl := '0'; + + constant NUM_AXIL_MASTERS_C : integer := 2; + constant PGP_AXIL_INDEX_C : integer := 0; + constant DRP_AXIL_INDEX_C : integer := 1; + + constant XBAR_CONFIG_C : AxiLiteCrossbarMasterConfigArray(NUM_AXIL_MASTERS_C-1 downto 0) := ( + PGP_AXIL_INDEX_C => ( + baseAddr => AXIL_BASE_ADDR_G, + addrBits => 12, + connectivity => X"FFFF"), + DRP_AXIL_INDEX_C => ( + baseAddr => AXIL_BASE_ADDR_G + X"1000", + addrBits => 11, + connectivity => X"FFFF")); + + signal axilReadMasters : AxiLiteReadMasterArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_MASTER_INIT_C); + signal axilReadSlaves : AxiLiteReadSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C); + signal axilWriteMasters : AxiLiteWriteMasterArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_MASTER_INIT_C); + signal axilWriteSlaves : AxiLiteWriteSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C); + + signal loopback : slv(2 downto 0) := (others => '0'); + + -- attribute dont_touch : string; + -- attribute dont_touch of phyRxClk : signal is "TRUE"; + -- attribute dont_touch of phyRxRst : signal is "TRUE"; + -- attribute dont_touch of phyTxClk : signal is "TRUE"; + -- attribute dont_touch of phyTxRst : signal is "TRUE"; + -- attribute dont_touch of phyRxInit : signal is "TRUE"; + -- attribute dont_touch of phyRxActive : signal is "TRUE"; + -- attribute dont_touch of phyRxValid : signal is "TRUE"; + -- attribute dont_touch of phyRxHeader : signal is "TRUE"; + -- attribute dont_touch of phyRxData : signal is "TRUE"; + -- attribute dont_touch of phyRxSlip : signal is "TRUE"; + -- attribute dont_touch of phyTxActive : signal is "TRUE"; + -- attribute dont_touch of phyTxHeader : signal is "TRUE"; + -- attribute dont_touch of phyTxData : signal is "TRUE"; + -- attribute dont_touch of phyTxValid : signal is "TRUE"; + -- attribute dont_touch of phyTxDataRdy : signal is "TRUE"; + +begin + + assert ((RATE_G = "3.125Gbps") or (RATE_G = "6.25Gbps")) + report "RATE_G: Must be either 3.125Gbps, 6.25Gbps" + severity error; + + pgpClk <= phyTxClk; + pgpClkRst <= phyTxRst; + pgpRxOut <= locRxOut; + + GEN_XBAR : if (EN_DRP_G and EN_PGP_MON_G) generate + U_XBAR : entity work.AxiLiteCrossbar + generic map ( + TPD_G => TPD_G, + NUM_SLAVE_SLOTS_G => 1, + NUM_MASTER_SLOTS_G => NUM_AXIL_MASTERS_C, + MASTERS_CONFIG_G => XBAR_CONFIG_C) + port map ( + axiClk => axilClk, + axiClkRst => axilRst, + sAxiWriteMasters(0) => axilWriteMaster, + sAxiWriteSlaves(0) => axilWriteSlave, + sAxiReadMasters(0) => axilReadMaster, + sAxiReadSlaves(0) => axilReadSlave, + mAxiWriteMasters => axilWriteMasters, + mAxiWriteSlaves => axilWriteSlaves, + mAxiReadMasters => axilReadMasters, + mAxiReadSlaves => axilReadSlaves); + end generate GEN_XBAR; + + -- If DRP or PGP_MON not enabled, no crossbar needed + -- If neither enabled, default values will auto-terminate the bus + GEN_DRP_ONLY : if (EN_DRP_G and not EN_PGP_MON_G) generate + axilWriteSlave <= axilWriteSlaves(DRP_AXIL_INDEX_C); + axilWriteMasters(DRP_AXIL_INDEX_C) <= axilWriteMaster; + axilReadSlave <= axilReadSlaves(DRP_AXIL_INDEX_C); + axilReadMasters(DRP_AXIL_INDEX_C) <= axilReadMaster; + end generate GEN_DRP_ONLY; + + GEN_PGP_MON_ONLY : if (EN_PGP_MON_G and not EN_DRP_G) generate + axilWriteSlave <= axilWriteSlaves(PGP_AXIL_INDEX_C); + axilWriteMasters(PGP_AXIL_INDEX_C) <= axilWriteMaster; + axilReadSlave <= axilReadSlaves(PGP_AXIL_INDEX_C); + axilReadMasters(PGP_AXIL_INDEX_C) <= axilReadMaster; + end generate GEN_PGP_MON_ONLY; + + U_Pgp3Core : entity work.Pgp3Core + generic map ( + TPD_G => TPD_G, + NUM_VC_G => NUM_VC_G, + PGP_RX_ENABLE_G => PGP_RX_ENABLE_G, + RX_ALIGN_GOOD_COUNT_G => RX_ALIGN_GOOD_COUNT_G, + RX_ALIGN_BAD_COUNT_G => RX_ALIGN_BAD_COUNT_G, + RX_ALIGN_SLIP_WAIT_G => RX_ALIGN_SLIP_WAIT_G, + PGP_TX_ENABLE_G => PGP_TX_ENABLE_G, + TX_CELL_WORDS_MAX_G => TX_CELL_WORDS_MAX_G, + TX_SKP_INTERVAL_G => TX_SKP_INTERVAL_G, + TX_SKP_BURST_SIZE_G => TX_SKP_BURST_SIZE_G, + TX_MUX_MODE_G => TX_MUX_MODE_G, + TX_MUX_TDEST_ROUTES_G => TX_MUX_TDEST_ROUTES_G, + TX_MUX_TDEST_LOW_G => TX_MUX_TDEST_LOW_G, + TX_MUX_ILEAVE_EN_G => TX_MUX_ILEAVE_EN_G, + TX_MUX_ILEAVE_ON_NOTVALID_G => TX_MUX_ILEAVE_ON_NOTVALID_G, + EN_PGP_MON_G => EN_PGP_MON_G, + AXIL_CLK_FREQ_G => AXIL_CLK_FREQ_G) + port map ( + -- Tx User interface + pgpTxClk => phyTxClk, -- [in] + pgpTxRst => phyTxRst, -- [in] + pgpTxIn => pgpTxIn, -- [in] + pgpTxOut => pgpTxOut, -- [out] + pgpTxMasters => pgpTxMasters, -- [in] + pgpTxSlaves => pgpTxSlaves, -- [out] + -- Tx PHY interface + phyTxActive => phyTxActive, -- [in] + phyTxHeader => phyTxHeader, -- [out] + phyTxData => phyTxData, -- [out] + phyTxValid => phyTxValid, -- [out] + phyTxReady => phyTxDataRdy, -- [in] + -- Rx User interface + pgpRxClk => phyTxClk, -- [in] + pgpRxRst => phyTxRst, -- [in] + pgpRxIn => pgpRxIn, -- [in] + pgpRxOut => locRxOut, -- [out] + pgpRxMasters => pgpRxMasters, -- [out] + pgpRxCtrl => pgpRxCtrl, -- [in] + -- Rx PHY interface + phyRxClk => phyRxClk, -- [in] + phyRxRst => phyRxRst, -- [in] + phyRxInit => phyRxInit, -- [out] + phyRxActive => phyRxActive, -- [in] + phyRxValid => phyRxValid, -- [in] + phyRxHeader => phyRxHeader, -- [in] + phyRxData => phyRxData, -- [in] + phyRxStartSeq => '0', -- [in] + phyRxSlip => phyRxSlip, -- [out] + -- Debug Interface + loopback => loopback, -- [out] + -- AXI-Lite Register Interface (axilClk domain) + axilClk => axilClk, -- [in] + axilRst => axilRst, -- [in] + axilReadMaster => axilReadMasters(PGP_AXIL_INDEX_C), -- [in] + axilReadSlave => axilReadSlaves(PGP_AXIL_INDEX_C), -- [out] + axilWriteMaster => axilWriteMasters(PGP_AXIL_INDEX_C), -- [in] + axilWriteSlave => axilWriteSlaves(PGP_AXIL_INDEX_C)); -- [out] + + -------------------------- + -- Wrapper for GTH IP core + -------------------------- + U_Pgp3Gtp7IpWrapper : entity work.Pgp3Gtp7IpWrapper + generic map ( + TPD_G => TPD_G, + CLKIN_PERIOD_G => CLKIN_PERIOD_G, + BANDWIDTH_G => BANDWIDTH_G, + CLKFBOUT_MULT_G => CLKFBOUT_MULT_G, + CLKOUT0_DIVIDE_G => CLKOUT0_DIVIDE_G, + CLKOUT1_DIVIDE_G => CLKOUT1_DIVIDE_G, + CLKOUT2_DIVIDE_G => CLKOUT2_DIVIDE_G, + TX_POLARITY_G => TX_POLARITY_G, + RX_POLARITY_G => RX_POLARITY_G, + EN_DRP_G => EN_DRP_G, + RATE_G => RATE_G) + port map ( + stableClk => stableClk, + stableRst => stableRst, + -- QPLL Interface + qPllOutClk => qPllOutClk, + qPllOutRefClk => qPllOutRefClk, + qPllLock => qPllLock, + qpllRefClkLost => qpllRefClkLost, + qpllRst => qpllRst, + -- TX PLL Interface + gtTxOutClk => gtTxOutClk, + gtTxPllRst => gtTxPllRst, + txPllClk => txPllClk, + txPllRst => txPllRst, + gtTxPllLock => gtTxPllLock, + -- GTH FPGA IO + gtRxP => pgpGtRxP, + gtRxN => pgpGtRxN, + gtTxP => pgpGtTxP, + gtTxN => pgpGtTxN, + -- Rx ports + rxUsrClk => phyRxClk, + rxUsrClkRst => phyRxRst, + rxReset => phyRxInit, + rxResetDone => phyRxActive, + rxValid => phyRxValid, + rxHeader => phyRxHeader, + rxData => phyRxData, + rxSlip => phyRxSlip, + rxAligned => locRxOut.gearboxAligned, + -- Tx Ports + txUsrClk => phyTxClk, + txUsrClkRst => phyTxRst, + txReset => stableRst, + txResetDone => phyTxActive, + txHeader => phyTxHeader, + txData => phyTxData, + txValid => phyTxValid, + txReady => phyTxDataRdy, + -- Debug Interface + loopback => loopback, + txPreCursor => txPreCursor, + txPostCursor => txPostCursor, + txDiffCtrl => txDiffCtrl, + -- AXI-Lite DRP Interface + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMasters(DRP_AXIL_INDEX_C), + axilReadSlave => axilReadSlaves(DRP_AXIL_INDEX_C), + axilWriteMaster => axilWriteMasters(DRP_AXIL_INDEX_C), + axilWriteSlave => axilWriteSlaves(DRP_AXIL_INDEX_C)); + +end rtl; diff --git a/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7IpWrapper.vhd b/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7IpWrapper.vhd new file mode 100644 index 0000000000..96b803835e --- /dev/null +++ b/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7IpWrapper.vhd @@ -0,0 +1,705 @@ +------------------------------------------------------------------------------- +-- File : Pgp3Gtp7IpWrapper.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.StdRtlPkg.all; +use work.AxiLitePkg.all; + +library unisim; +use unisim.vcomponents.all; + +entity Pgp3Gtp7IpWrapper is + generic ( + TPD_G : time := 1 ns; + EN_DRP_G : boolean := true; + RATE_G : string := "6.25Gbps"; -- or "3.125Gbps" + CLKIN_PERIOD_G : real; + BANDWIDTH_G : string; + CLKFBOUT_MULT_G : positive; + CLKOUT0_DIVIDE_G : positive; + CLKOUT1_DIVIDE_G : positive; + CLKOUT2_DIVIDE_G : positive; + TX_POLARITY_G : sl := '0'; + RX_POLARITY_G : sl := '0'); + port ( + stableClk : in sl; + stableRst : in sl; + -- QPLL Interface + qPllOutClk : in slv(1 downto 0); + qPllOutRefClk : in slv(1 downto 0); + qPllLock : in slv(1 downto 0); + qPllRefClkLost : in slv(1 downto 0); + qpllRst : out slv(1 downto 0); + -- TX PLL Interface + gtTxOutClk : out sl; + gtTxPllRst : out sl; + txPllClk : in slv(2 downto 0); + txPllRst : in slv(2 downto 0); + gtTxPllLock : in sl; + -- GTH FPGA IO + gtRxP : in sl; + gtRxN : in sl; + gtTxP : out sl; + gtTxN : out sl; + -- Rx ports + rxUsrClk : out sl; + rxUsrClkRst : out sl; + rxReset : in sl; + rxResetDone : out sl; + rxValid : out sl; + rxHeader : out slv(1 downto 0); + rxData : out slv(63 downto 0); + rxSlip : in sl; + rxAligned : in sl; + -- Tx Ports + txUsrClk : out sl; + txUsrClkRst : out sl; + txReset : in sl; + txResetDone : out sl; + txHeader : in slv(1 downto 0); + txData : in slv(63 downto 0); + txValid : in sl; + txReady : out sl; + -- Debug Interface + loopback : in slv(2 downto 0); + txPreCursor : in slv(4 downto 0); + txPostCursor : in slv(4 downto 0); + txDiffCtrl : in slv(3 downto 0); + -- AXI-Lite DRP Interface + axilClk : in sl := '0'; + axilRst : in sl := '0'; + axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + axilReadSlave : out AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C; + axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + axilWriteSlave : out AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C); +end entity Pgp3Gtp7IpWrapper; + +architecture mapping of Pgp3Gtp7IpWrapper is + + component Pgp3Gtp7Ip6G + port ( + SYSCLK_IN : in std_logic; + SOFT_RESET_TX_IN : in std_logic; + SOFT_RESET_RX_IN : in std_logic; + DONT_RESET_ON_DATA_ERROR_IN : in std_logic; + GT0_TX_FSM_RESET_DONE_OUT : out std_logic; + GT0_RX_FSM_RESET_DONE_OUT : out std_logic; + GT0_DRP_BUSY_OUT : out std_logic; + GT0_DATA_VALID_IN : in std_logic; + GT0_TX_MMCM_LOCK_IN : in std_logic; + GT0_TX_MMCM_RESET_OUT : out std_logic; + GT0_RX_MMCM_LOCK_IN : in std_logic; + GT0_RX_MMCM_RESET_OUT : out std_logic; + --____________________________CHANNEL PORTS________________________________ + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in : in std_logic_vector(8 downto 0); + gt0_drpclk_in : in std_logic; + gt0_drpdi_in : in std_logic_vector(15 downto 0); + gt0_drpdo_out : out std_logic_vector(15 downto 0); + gt0_drpen_in : in std_logic; + gt0_drprdy_out : out std_logic; + gt0_drpwe_in : in std_logic; + ------------------------------- Loopback Ports ----------------------------- + gt0_loopback_in : in std_logic_vector(2 downto 0); + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in : in std_logic; + gt0_rxuserrdy_in : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out : out std_logic; + gt0_eyescantrigger_in : in std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + gt0_rxcdrovrden_in : in std_logic; + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + gt0_rxdata_out : out std_logic_vector(31 downto 0); + gt0_rxusrclk_in : in std_logic; + gt0_rxusrclk2_in : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtprxn_in : in std_logic; + gt0_gtprxp_in : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxbufreset_in : in std_logic; + gt0_rxphmonitor_out : out std_logic_vector(4 downto 0); + gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0); + ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) ----------- + gt0_dmonitorout_out : out std_logic_vector(14 downto 0); + -------------------- Receive Ports - RX Equailizer Ports ------------------- + gt0_rxlpmhfhold_in : in std_logic; + gt0_rxlpmhfovrden_in : in std_logic; + gt0_rxlpmlfhold_in : in std_logic; + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + gt0_rxoutclk_out : out std_logic; + gt0_rxoutclkfabric_out : out std_logic; + ---------------------- Receive Ports - RX Gearbox Ports -------------------- + gt0_rxdatavalid_out : out std_logic; + gt0_rxheader_out : out std_logic_vector(1 downto 0); + gt0_rxheadervalid_out : out std_logic; + --------------------- Receive Ports - RX Gearbox Ports -------------------- + gt0_rxgearboxslip_in : in std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in : in std_logic; + gt0_rxlpmreset_in : in std_logic; + gt0_rxpcsreset_in : in std_logic; + gt0_rxpmareset_in : in std_logic; + ----------------- Receive Ports - RX Polarity Control Ports ---------------- + gt0_rxpolarity_in : in std_logic; + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out : out std_logic; + ------------------------ TX Configurable Driver Ports ---------------------- + gt0_txpostcursor_in : in std_logic_vector(4 downto 0); + gt0_txprecursor_in : in std_logic_vector(4 downto 0); + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in : in std_logic; + gt0_txuserrdy_in : in std_logic; + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + gt0_txdata_in : in std_logic_vector(31 downto 0); + gt0_txusrclk_in : in std_logic; + gt0_txusrclk2_in : in std_logic; + --------------- Transmit Ports - TX Configurable Driver Ports -------------- + gt0_gtptxn_out : out std_logic; + gt0_gtptxp_out : out std_logic; + gt0_txdiffctrl_in : in std_logic_vector(3 downto 0); + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclk_out : out std_logic; + gt0_txoutclkfabric_out : out std_logic; + gt0_txoutclkpcs_out : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txheader_in : in std_logic_vector(1 downto 0); + gt0_txsequence_in : in std_logic_vector(6 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txpcsreset_in : in std_logic; + gt0_txpmareset_in : in std_logic; + gt0_txresetdone_out : out std_logic; + ----------------- Transmit Ports - TX Polarity Control Ports --------------- + gt0_txpolarity_in : in std_logic; + --____________________________COMMON PORTS________________________________ + GT0_PLL0OUTCLK_IN : in std_logic; + GT0_PLL0OUTREFCLK_IN : in std_logic; + GT0_PLL0RESET_OUT : out std_logic; + GT0_PLL0LOCK_IN : in std_logic; + GT0_PLL0REFCLKLOST_IN : in std_logic; + GT0_PLL1OUTCLK_IN : in std_logic; + GT0_PLL1OUTREFCLK_IN : in std_logic + ); + end component; + + component Pgp3Gtp7Ip3G + port ( + SYSCLK_IN : in std_logic; + SOFT_RESET_TX_IN : in std_logic; + SOFT_RESET_RX_IN : in std_logic; + DONT_RESET_ON_DATA_ERROR_IN : in std_logic; + GT0_TX_FSM_RESET_DONE_OUT : out std_logic; + GT0_RX_FSM_RESET_DONE_OUT : out std_logic; + GT0_DRP_BUSY_OUT : out std_logic; + GT0_DATA_VALID_IN : in std_logic; + GT0_TX_MMCM_LOCK_IN : in std_logic; + GT0_TX_MMCM_RESET_OUT : out std_logic; + GT0_RX_MMCM_LOCK_IN : in std_logic; + GT0_RX_MMCM_RESET_OUT : out std_logic; + --____________________________CHANNEL PORTS________________________________ + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in : in std_logic_vector(8 downto 0); + gt0_drpclk_in : in std_logic; + gt0_drpdi_in : in std_logic_vector(15 downto 0); + gt0_drpdo_out : out std_logic_vector(15 downto 0); + gt0_drpen_in : in std_logic; + gt0_drprdy_out : out std_logic; + gt0_drpwe_in : in std_logic; + ------------------------------- Loopback Ports ----------------------------- + gt0_loopback_in : in std_logic_vector(2 downto 0); + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in : in std_logic; + gt0_rxuserrdy_in : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out : out std_logic; + gt0_eyescantrigger_in : in std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + gt0_rxcdrovrden_in : in std_logic; + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + gt0_rxdata_out : out std_logic_vector(31 downto 0); + gt0_rxusrclk_in : in std_logic; + gt0_rxusrclk2_in : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtprxn_in : in std_logic; + gt0_gtprxp_in : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxbufreset_in : in std_logic; + gt0_rxphmonitor_out : out std_logic_vector(4 downto 0); + gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0); + ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) ----------- + gt0_dmonitorout_out : out std_logic_vector(14 downto 0); + -------------------- Receive Ports - RX Equailizer Ports ------------------- + gt0_rxlpmhfhold_in : in std_logic; + gt0_rxlpmhfovrden_in : in std_logic; + gt0_rxlpmlfhold_in : in std_logic; + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + gt0_rxoutclk_out : out std_logic; + gt0_rxoutclkfabric_out : out std_logic; + ---------------------- Receive Ports - RX Gearbox Ports -------------------- + gt0_rxdatavalid_out : out std_logic; + gt0_rxheader_out : out std_logic_vector(1 downto 0); + gt0_rxheadervalid_out : out std_logic; + --------------------- Receive Ports - RX Gearbox Ports -------------------- + gt0_rxgearboxslip_in : in std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in : in std_logic; + gt0_rxlpmreset_in : in std_logic; + gt0_rxpcsreset_in : in std_logic; + gt0_rxpmareset_in : in std_logic; + ----------------- Receive Ports - RX Polarity Control Ports ---------------- + gt0_rxpolarity_in : in std_logic; + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out : out std_logic; + ------------------------ TX Configurable Driver Ports ---------------------- + gt0_txpostcursor_in : in std_logic_vector(4 downto 0); + gt0_txprecursor_in : in std_logic_vector(4 downto 0); + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in : in std_logic; + gt0_txuserrdy_in : in std_logic; + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + gt0_txdata_in : in std_logic_vector(31 downto 0); + gt0_txusrclk_in : in std_logic; + gt0_txusrclk2_in : in std_logic; + --------------- Transmit Ports - TX Configurable Driver Ports -------------- + gt0_gtptxn_out : out std_logic; + gt0_gtptxp_out : out std_logic; + gt0_txdiffctrl_in : in std_logic_vector(3 downto 0); + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclk_out : out std_logic; + gt0_txoutclkfabric_out : out std_logic; + gt0_txoutclkpcs_out : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txheader_in : in std_logic_vector(1 downto 0); + gt0_txsequence_in : in std_logic_vector(6 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txpcsreset_in : in std_logic; + gt0_txpmareset_in : in std_logic; + gt0_txresetdone_out : out std_logic; + ----------------- Transmit Ports - TX Polarity Control Ports --------------- + gt0_txpolarity_in : in std_logic; + --____________________________COMMON PORTS________________________________ + GT0_PLL0OUTCLK_IN : in std_logic; + GT0_PLL0OUTREFCLK_IN : in std_logic; + GT0_PLL0RESET_OUT : out std_logic; + GT0_PLL0LOCK_IN : in std_logic; + GT0_PLL0REFCLKLOST_IN : in std_logic; + GT0_PLL1OUTCLK_IN : in std_logic; + GT0_PLL1OUTREFCLK_IN : in std_logic + ); + end component; + + signal gtRxOutClk : sl; + signal gtRxOutClkBufg : sl; + signal clkFb : sl; + signal gtRxPllRst : sl; + signal gtRxPllLock : sl; + signal rxSlipGearbox : sl; + + signal pllOut : slv(2 downto 1); + signal rxPllClk : slv(2 downto 1); + signal rxPllRst : slv(2 downto 1); + + signal rxUsrClkInt : sl; + signal rxUsrClk2Int : sl; + + signal txUsrClkInt : sl; + signal txUsrClk2Int : sl; + + signal drpAddr : slv(8 downto 0) := (others => '0'); + signal drpDi : slv(15 downto 0) := (others => '0'); + signal drpDo : slv(15 downto 0) := (others => '0'); + signal drpEn : sl := '0'; + signal drpWe : sl := '0'; + signal drpRdy : sl := '0'; + + signal txHeaderGearbox : slv(1 downto 0); + signal txDataGearbox : slv(31 downto 0); + signal txSequenceGearbox : slv(6 downto 0); + + signal rxHeaderValidGearbox : sl; + signal rxHeaderGearbox : slv(1 downto 0); + signal rxDataValidGearbox : sl; + signal rxDataGearbox : slv(31 downto 0); + +begin + + rxUsrClk <= txPllClk(0); + rxUsrClkRst <= txPllRst(0); + + txUsrClk <= txPllClk(0); + txUsrClkRst <= txPllRst(0); + + U_Bufg : BUFG + port map ( + I => gtRxOutClk, + O => gtRxOutClkBufg); + + U_RX_PLL : PLLE2_ADV + generic map ( + BANDWIDTH => BANDWIDTH_G, + CLKIN1_PERIOD => CLKIN_PERIOD_G, + DIVCLK_DIVIDE => 1, + CLKFBOUT_MULT => CLKFBOUT_MULT_G, + CLKOUT0_DIVIDE => CLKOUT0_DIVIDE_G, + CLKOUT1_DIVIDE => CLKOUT1_DIVIDE_G, + CLKOUT2_DIVIDE => CLKOUT2_DIVIDE_G) + port map ( + DCLK => axilClk, + DRDY => open, + DEN => '0', + DWE => '0', + DADDR => (others => '0'), + DI => (others => '0'), + DO => open, + PWRDWN => '0', + RST => gtRxPllRst, + CLKIN1 => gtRxOutClkBufg, + CLKIN2 => '0', + CLKINSEL => '1', + CLKFBOUT => clkFb, + CLKFBIN => clkFb, + LOCKED => gtRxPllLock, + CLKOUT0 => open, + CLKOUT1 => pllOut(1), + CLKOUT2 => pllOut(2)); + + U_rxPllClk1 : BUFG + port map ( + I => pllOut(1), + O => rxPllClk(1)); + + U_rxPllClk2 : BUFG + port map ( + I => pllOut(2), + O => rxPllClk(2)); + + GEN_RST : for i in 2 downto 1 generate + U_RstSync : entity work.RstSync + generic map ( + TPD_G => TPD_G, + IN_POLARITY_G => '0', + OUT_POLARITY_G => '1') + port map ( + clk => rxPllClk(i), + asyncRst => gtRxPllLock, + syncRst => rxPllRst(i)); + end generate; + + rxUsrClkInt <= rxPllClk(1); + rxUsrClk2Int <= rxPllClk(2); + + txUsrClkInt <= txPllClk(1); + txUsrClk2Int <= txPllClk(2); + + U_TxGearbox : entity work.Pgp3Gtp7TxGearbox + generic map ( + TPD_G => TPD_G) + port map ( + -- Slave Interface + phyTxClkSlow => txPllClk(0), + phyTxRstSlow => txPllRst(0), + phyTxHeader => txHeader, + phyTxData => txData, + phyTxValid => txValid, + phyTxDataRdy => txReady, + -- Master Interface + phyTxClkFast => txPllClk(2), + phyTxRstFast => txPllRst(2), + txHeader => txHeaderGearbox, + txData => txDataGearbox, + txSequence => txSequenceGearbox); + + U_RxGearbox : entity work.Pgp3Gtp7RxGearbox + generic map ( + TPD_G => TPD_G) + port map ( + -- Slave Interface + phyRxClkFast => rxPllClk(2), + phyRxRstFast => rxPllRst(2), + rxHeaderValid => rxHeaderValidGearbox, + rxHeader => rxHeaderGearbox, + rxDataValid => rxDataValidGearbox, + rxData => rxDataGearbox, + -- Master Interface + phyRxClkSlow => txPllClk(0), + phyRxRstSlow => txPllRst(0), + phyRxValid => rxValid, + phyRxHeader => rxHeader, + phyRxData => rxData); + + U_RxSlip : entity work.SynchronizerOneShot + generic map ( + TPD_G => TPD_G) + port map ( + clk => rxUsrClk2Int, + dataIn => rxSlip, + dataOut => rxSlipGearbox); + + GEN_6G : if (RATE_G = "6.25Gbps") generate + U_Pgp3Gtp7Ip6G : Pgp3Gtp7Ip6G + port map ( + SYSCLK_IN => stableClk, + SOFT_RESET_TX_IN => txReset, + SOFT_RESET_RX_IN => rxReset, + DONT_RESET_ON_DATA_ERROR_IN => '0', + GT0_TX_FSM_RESET_DONE_OUT => txResetDone, + GT0_RX_FSM_RESET_DONE_OUT => rxResetDone, + GT0_DATA_VALID_IN => rxAligned, + GT0_DRP_BUSY_OUT => open, + GT0_TX_MMCM_LOCK_IN => gtTxPllLock, + GT0_TX_MMCM_RESET_OUT => gtTxPllRst, + GT0_RX_MMCM_LOCK_IN => gtRxPllLock, + GT0_RX_MMCM_RESET_OUT => gtRxPllRst, + --_________________________________________________________________________ + --GT0 (X0Y0) + --____________________________CHANNEL PORTS________________________________ + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in => drpAddr, + gt0_drpclk_in => stableClk, + gt0_drpdi_in => drpDi, + gt0_drpdo_out => drpDo, + gt0_drpen_in => drpEn, + gt0_drprdy_out => drpRdy, + gt0_drpwe_in => drpWe, + --------------------------- Digital Monitor Ports -------------------------- + gt0_dmonitorout_out => open, + ------------------------------- Loopback Ports ----------------------------- + gt0_loopback_in => loopback, + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in => '0', + gt0_rxuserrdy_in => '1', + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out => open, + gt0_eyescantrigger_in => '0', + ------------------------- Receive Ports - CDR Ports ------------------------ + gt0_rxcdrovrden_in => '0', + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + gt0_rxusrclk_in => rxUsrClkInt, -- 390.62 MHz (2.56 ns period) + gt0_rxusrclk2_in => rxUsrClk2Int, -- 195.31 MHz (5.12 ns period) + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + gt0_rxdata_out => rxDataGearbox, + --------------------------- Receive Ports - RX AFE ------------------------- + gt0_gtprxp_in => gtRxP, + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtprxn_in => gtRxN, + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxbufreset_in => '0', + gt0_rxphmonitor_out => open, + gt0_rxphslipmonitor_out => open, + --------------------- Receive Ports - RX Equalizer Ports ------------------- + gt0_rxlpmhfhold_in => '0', + gt0_rxlpmhfovrden_in => '0', + gt0_rxlpmlfhold_in => '0', + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + gt0_rxoutclk_out => gtRxOutClk, -- 390.62 MHz (2.56 ns period) + gt0_rxoutclkfabric_out => open, -- 156.25 MHz (6.400 ns period) + ---------------------- Receive Ports - RX Gearbox Ports -------------------- + gt0_rxdatavalid_out => rxDataValidGearbox, + gt0_rxheader_out => rxHeaderGearbox, + gt0_rxheadervalid_out => rxHeaderValidGearbox, + --------------------- Receive Ports - RX Gearbox Ports -------------------- + gt0_rxgearboxslip_in => rxSlipGearbox, + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in => '0', + gt0_rxlpmreset_in => '0', + gt0_rxpcsreset_in => '0', + gt0_rxpmareset_in => '0', + ----------------- Receive Ports - RX Polarity Control Ports ---------------- + gt0_rxpolarity_in => RX_POLARITY_G, + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out => open, + ------------------------ TX Configurable Driver Ports ---------------------- + gt0_txpostcursor_in => txPostCursor, + gt0_txprecursor_in => txPreCursor, + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in => '0', + gt0_txuserrdy_in => '1', + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + gt0_txusrclk_in => txUsrClkInt, -- 390.62 MHz (2.56 ns period) + gt0_txusrclk2_in => txUsrClk2Int, -- 195.31 MHz (5.12 ns period) + --------------- Transmit Ports - TX Configurable Driver Ports -------------- + gt0_txdiffctrl_in => txDiffCtrl, + ------------------ Transmit Ports - TX Data Path interface ----------------- + gt0_txdata_in => txDataGearbox, + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gt0_gtptxn_out => gtTxN, + gt0_gtptxp_out => gtTxP, + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclk_out => gtTxOutClk, -- 390.62 MHz (2.56 ns period) + gt0_txoutclkfabric_out => open, -- 156.25 MHz (6.4 ns period) + gt0_txoutclkpcs_out => open, + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txheader_in => txHeaderGearbox, + gt0_txsequence_in => txSequenceGearbox, + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txpcsreset_in => '0', + gt0_txpmareset_in => '0', + gt0_txresetdone_out => open, + ----------------- Transmit Ports - TX Polarity Control Ports --------------- + gt0_txpolarity_in => TX_POLARITY_G, + --____________________________COMMON PORTS________________________________ + GT0_PLL0OUTCLK_IN => qPllOutClk(0), + GT0_PLL0OUTREFCLK_IN => qPllOutRefClk(0), + GT0_PLL0RESET_OUT => qpllRst(0), + GT0_PLL0LOCK_IN => qpllLock(0), + GT0_PLL0REFCLKLOST_IN => qPllRefClkLost(0), + GT0_PLL1OUTCLK_IN => qPllOutClk(1), + GT0_PLL1OUTREFCLK_IN => qPllOutRefClk(1)); + qpllRst(1) <= '0'; + end generate; + + GEN_3G : if (RATE_G = "3.125Gbps") generate + U_Pgp3Gtp7Ip3G : Pgp3Gtp7Ip3G + port map ( + SYSCLK_IN => stableClk, + SOFT_RESET_TX_IN => txReset, + SOFT_RESET_RX_IN => rxReset, + DONT_RESET_ON_DATA_ERROR_IN => '0', + GT0_TX_FSM_RESET_DONE_OUT => txResetDone, + GT0_RX_FSM_RESET_DONE_OUT => rxResetDone, + GT0_DATA_VALID_IN => rxAligned, + GT0_DRP_BUSY_OUT => open, + GT0_TX_MMCM_LOCK_IN => gtTxPllLock, + GT0_TX_MMCM_RESET_OUT => gtTxPllRst, + GT0_RX_MMCM_LOCK_IN => gtRxPllLock, + GT0_RX_MMCM_RESET_OUT => gtRxPllRst, + --_________________________________________________________________________ + --GT0 (X0Y0) + --____________________________CHANNEL PORTS________________________________ + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in => drpAddr, + gt0_drpclk_in => stableClk, + gt0_drpdi_in => drpDi, + gt0_drpdo_out => drpDo, + gt0_drpen_in => drpEn, + gt0_drprdy_out => drpRdy, + gt0_drpwe_in => drpWe, + --------------------------- Digital Monitor Ports -------------------------- + gt0_dmonitorout_out => open, + ------------------------------- Loopback Ports ----------------------------- + gt0_loopback_in => loopback, + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in => '0', + gt0_rxuserrdy_in => '1', + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out => open, + gt0_eyescantrigger_in => '0', + ------------------------- Receive Ports - CDR Ports ------------------------ + gt0_rxcdrovrden_in => '0', + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + gt0_rxusrclk_in => rxUsrClkInt, -- 195.31 MHz (5.12 ns period) + gt0_rxusrclk2_in => rxUsrClk2Int, -- 97.655 MHz (10.24 ns period) + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + gt0_rxdata_out => rxDataGearbox, + --------------------------- Receive Ports - RX AFE ------------------------- + gt0_gtprxp_in => gtRxP, + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtprxn_in => gtRxN, + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxbufreset_in => '0', + gt0_rxphmonitor_out => open, + gt0_rxphslipmonitor_out => open, + --------------------- Receive Ports - RX Equalizer Ports ------------------- + gt0_rxlpmhfhold_in => '0', + gt0_rxlpmhfovrden_in => '0', + gt0_rxlpmlfhold_in => '0', + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + gt0_rxoutclk_out => gtRxOutClk, -- 195.31 MHz (5.12 ns period) + gt0_rxoutclkfabric_out => open, -- 156.25 MHz (6.400 ns period) + ---------------------- Receive Ports - RX Gearbox Ports -------------------- + gt0_rxdatavalid_out => rxDataValidGearbox, + gt0_rxheader_out => rxHeaderGearbox, + gt0_rxheadervalid_out => rxHeaderValidGearbox, + --------------------- Receive Ports - RX Gearbox Ports -------------------- + gt0_rxgearboxslip_in => rxSlipGearbox, + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in => '0', + gt0_rxlpmreset_in => '0', + gt0_rxpcsreset_in => '0', + gt0_rxpmareset_in => '0', + ----------------- Receive Ports - RX Polarity Control Ports ---------------- + gt0_rxpolarity_in => RX_POLARITY_G, + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out => open, + ------------------------ TX Configurable Driver Ports ---------------------- + gt0_txpostcursor_in => txPostCursor, + gt0_txprecursor_in => txPreCursor, + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in => '0', + gt0_txuserrdy_in => '1', + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + gt0_txusrclk_in => txUsrClkInt, -- 195.31 MHz (5.12 ns period) + gt0_txusrclk2_in => txUsrClk2Int, -- 97.655 MHz (10.24 ns period) + --------------- Transmit Ports - TX Configurable Driver Ports -------------- + gt0_txdiffctrl_in => txDiffCtrl, + ------------------ Transmit Ports - TX Data Path interface ----------------- + gt0_txdata_in => txDataGearbox, + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gt0_gtptxn_out => gtTxN, + gt0_gtptxp_out => gtTxP, + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclk_out => gtTxOutClk, -- 195.31 MHz (5.12 ns period) + gt0_txoutclkfabric_out => open, -- 156.25 MHz (6.4 ns period) + gt0_txoutclkpcs_out => open, + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txheader_in => txHeaderGearbox, + gt0_txsequence_in => txSequenceGearbox, + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txpcsreset_in => '0', + gt0_txpmareset_in => '0', + gt0_txresetdone_out => open, + ----------------- Transmit Ports - TX Polarity Control Ports --------------- + gt0_txpolarity_in => TX_POLARITY_G, + --____________________________COMMON PORTS________________________________ + GT0_PLL0OUTCLK_IN => qPllOutClk(0), + GT0_PLL0OUTREFCLK_IN => qPllOutRefClk(0), + GT0_PLL0RESET_OUT => qpllRst(0), + GT0_PLL0LOCK_IN => qpllLock(0), + GT0_PLL0REFCLKLOST_IN => qPllRefClkLost(0), + GT0_PLL1OUTCLK_IN => qPllOutClk(1), + GT0_PLL1OUTREFCLK_IN => qPllOutRefClk(1)); + qpllRst(1) <= '0'; + end generate; + + GEN_DRP : if (EN_DRP_G) generate + U_AxiLiteToDrp_1 : entity work.AxiLiteToDrp + generic map ( + TPD_G => TPD_G, + COMMON_CLK_G => false, + EN_ARBITRATION_G => false, + ADDR_WIDTH_G => 9, + DATA_WIDTH_G => 16) + port map ( + axilClk => axilClk, -- [in] + axilRst => axilRst, -- [in] + axilReadMaster => axilReadMaster, -- [in] + axilReadSlave => axilReadSlave, -- [out] + axilWriteMaster => axilWriteMaster, -- [in] + axilWriteSlave => axilWriteSlave, -- [out] + drpClk => stableClk, -- [in] + drpRst => stableRst, -- [in] + drpReq => open, -- [out] + drpRdy => drpRdy, -- [in] + drpEn => drpEn, -- [out] + drpWe => drpWe, -- [out] + drpUsrRst => open, -- [out] + drpAddr => drpAddr, -- [out] + drpDi => drpDi, -- [out] + drpDo => drpDo); -- [in] + end generate; + +end mapping; diff --git a/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7Qpll.vhd b/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7Qpll.vhd new file mode 100644 index 0000000000..ecbe0fe752 --- /dev/null +++ b/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7Qpll.vhd @@ -0,0 +1,162 @@ +------------------------------------------------------------------------------- +-- File : Pgp3Gtp7Qpll.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.StdRtlPkg.all; +use work.AxiLitePkg.all; +use work.Pgp3Pkg.all; + +library unisim; +use unisim.vcomponents.all; + +entity Pgp3Gtp7Qpll is + generic ( + TPD_G : time := 1 ns; + EN_DRP_G : boolean := true; + REFCLK_TYPE_G : Pgp3RefClkType := PGP3_REFCLK_250_C; + RATE_G : string := "6.25Gbps"); -- or "3.125Gbps" + port ( + -- Stable Clock and Reset + stableClk : in sl; -- GT needs a stable clock to "boot up" + stableRst : in sl; + -- QPLL Clocking + pgpRefClk : in sl; + qPllOutClk : out Slv2Array(3 downto 0); + qPllOutRefClk : out Slv2Array(3 downto 0); + qPllLock : out Slv2Array(3 downto 0); + qPllRefClkLost : out Slv2Array(3 downto 0); + qpllRst : in Slv2Array(3 downto 0); + -- AXI-Lite Interface + axilClk : in sl := '0'; + axilRst : in sl := '0'; + axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + axilReadSlave : out AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C; + axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + axilWriteSlave : out AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C); +end Pgp3Gtp7Qpll; + +architecture mapping of Pgp3Gtp7Qpll is + + ---------------------------------------------------------------- + -- | Ref Clk | FBDIV_IN_C | FBDIV_45_IN_C | REFCLK_DIV_IN_C | -- + ---------------------------------------------------------------- + -- | 312 | 4 | 5 | 2 | -- + -- | 156 | 4 | 5 | 1 | -- + -- | 250 | 5 | 5 | 2 | -- + -- | 125 | 5 | 5 | 1 | -- + ---------------------------------------------------------------- + + impure function GenQpllFbDiv return integer is + begin + if (REFCLK_TYPE_G = PGP3_REFCLK_312_C) or (REFCLK_TYPE_G = PGP3_REFCLK_156_C) then + return 4; + elsif (REFCLK_TYPE_G = PGP3_REFCLK_250_C) or (REFCLK_TYPE_G = PGP3_REFCLK_125_C) then + return 5; + else + return -1; + end if; + end function; + constant FBDIV_IN_C : positive := GenQpllFbDiv; + + constant FBDIV_45_IN_C : positive := 5; + + impure function GenQpllRefDiv return integer is + begin + if (REFCLK_TYPE_G = PGP3_REFCLK_312_C) or (REFCLK_TYPE_G = PGP3_REFCLK_250_C) then + return 2; + elsif (REFCLK_TYPE_G = PGP3_REFCLK_156_C) or (REFCLK_TYPE_G = PGP3_REFCLK_125_C) then + return 1; + else + return -1; + end if; + end function; + constant REFCLK_DIV_IN_C : positive := GenQpllRefDiv; + + signal qPllRefClk : slv(1 downto 0); + signal qPllLockDetClk : slv(1 downto 0); + signal pllOutClk : slv(1 downto 0); + signal pllOutRefClk : slv(1 downto 0); + signal pllLock : slv(1 downto 0); + signal pllRefClkLost : slv(1 downto 0); + signal pllReset : slv(1 downto 0); + signal lockedStrobe : Slv2Array(3 downto 0); + signal gtQPllReset : Slv2Array(3 downto 0); + +begin + + GEN_VEC : + for i in 3 downto 0 generate + GEN_SUB : + for j in 1 downto 0 generate + + qPllOutClk(i)(j) <= pllOutClk(j); + qPllOutRefClk(i)(j) <= pllOutRefClk(j); + qpllRefClkLost(i)(j) <= pllRefClkLost(j); + + qpllLock(i)(j) <= pllLock(j) and not(lockedStrobe(i)(j)); -- trick the GT state machine of lock transition + + ---------------------------------------------------------------------------- + -- Prevent the gtQPllRst of this lane disrupting the other lanes in the QUAD + ---------------------------------------------------------------------------- + U_PwrUpRst : entity work.PwrUpRst + generic map ( + TPD_G => TPD_G, + DURATION_G => 12500) + port map ( + arst => qpllRst(i)(j), + clk => stableClk, + rstOut => lockedStrobe(i)(j)); + + gtQPllReset(i)(j) <= qpllRst(i)(j) and not (pllLock(j)); + + end generate GEN_SUB; + end generate GEN_VEC; + + pllReset(0) <= gtQPllReset(0)(0) or gtQPllReset(1)(0) or gtQPllReset(2)(0) or gtQPllReset(3)(0) or stableRst; + pllReset(1) <= stableRst; + + qPllRefClk <= pgpRefClk & pgpRefClk; + qPllLockDetClk <= stableClk & stableClk; + + U_QPLL : entity work.Gtp7QuadPll + generic map ( + TPD_G => TPD_G, + PLL0_FBDIV_IN_G => FBDIV_IN_C, + PLL0_FBDIV_45_IN_G => FBDIV_45_IN_C, + PLL0_REFCLK_DIV_IN_G => REFCLK_DIV_IN_C, + PLL1_FBDIV_IN_G => FBDIV_IN_C, + PLL1_FBDIV_45_IN_G => FBDIV_45_IN_C, + PLL1_REFCLK_DIV_IN_G => REFCLK_DIV_IN_C) + port map ( + qPllRefClk => qPllRefClk, + qPllOutClk => pllOutClk, + qPllOutRefClk => pllOutRefClk, + qPllLock => pllLock, + qPllLockDetClk => qPllLockDetClk, + qPllRefClkLost => pllRefClkLost, + qPllReset => pllReset, + -- AXI Lite interface + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + +end mapping; diff --git a/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7RxGearbox.vhd b/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7RxGearbox.vhd new file mode 100644 index 0000000000..a34b6b71d9 --- /dev/null +++ b/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7RxGearbox.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------- +-- File : Pgp3Gtp7RxGearbox.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.StdRtlPkg.all; + +entity Pgp3Gtp7RxGearbox is + generic ( + TPD_G : time := 1 ns); + port ( + -- Slave Interface + phyRxClkFast : in sl; + phyRxRstFast : in sl; + rxHeaderValid : in sl; + rxHeader : in slv(1 downto 0); + rxDataValid : in sl; + rxData : in slv(31 downto 0); + -- Master Interface + phyRxClkSlow : in sl; + phyRxRstSlow : in sl; + phyRxValid : out sl; + phyRxHeader : out slv(1 downto 0); + phyRxData : out slv(63 downto 0)); +end Pgp3Gtp7RxGearbox; + +architecture rtl of Pgp3Gtp7RxGearbox is + + type RegType is record + fifoWrite : sl; + fifoData : slv(65 downto 0); + end record; + + constant REG_INIT_C : RegType := ( + fifoWrite => '0', + fifoData => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + +begin + + comb : process (phyRxRstFast, r, rxData, rxDataValid, rxHeader, + rxHeaderValid) is + variable v : RegType; + variable i : natural; + begin + -- Latch the current value + v := r; + + -- Reset the flags + v.fifoWrite := '0'; + + -- Check for valid data + if (rxDataValid = '1') then + if (rxHeaderValid = '1') then + v.fifoData(65 downto 64) := rxHeader; + v.fifoData(63 downto 32) := rxData; + else + v.fifoWrite := '1'; + v.fifoData(31 downto 0) := rxData; + end if; + end if; + + -- Reset + if (phyRxRstFast = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (phyRxClkFast) is + begin + if rising_edge(phyRxClkFast) then + r <= rin after TPD_G; + end if; + end process seq; + + U_FifoAsync : entity work.FifoAsync + generic map ( + TPD_G => TPD_G, + FWFT_EN_G => true, + DATA_WIDTH_G => 66, + BRAM_EN_G => false, + ADDR_WIDTH_G => 4) + port map ( + rst => phyRxRstFast, + -- Write Ports + wr_clk => phyRxClkFast, + wr_en => r.fifoWrite, + din => r.fifoData, + -- Read Ports + rd_clk => phyRxClkSlow, + rd_en => '1', + dout(65 downto 64) => phyRxHeader, + dout(63 downto 0) => phyRxData, + valid => phyRxValid); + +end rtl; diff --git a/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7TxGearbox.vhd b/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7TxGearbox.vhd new file mode 100644 index 0000000000..463252b171 --- /dev/null +++ b/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7TxGearbox.vhd @@ -0,0 +1,159 @@ +------------------------------------------------------------------------------- +-- File : Pgp3Gtp7TxGearbox.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.StdRtlPkg.all; + +entity Pgp3Gtp7TxGearbox is + generic ( + TPD_G : time := 1 ns); + port ( + -- Slave Interface + phyTxClkSlow : in sl; + phyTxRstSlow : in sl; + phyTxHeader : in slv(1 downto 0); + phyTxData : in slv(63 downto 0); + phyTxValid : in sl; + phyTxDataRdy : out sl; + -- Master Interface + phyTxClkFast : in sl; + phyTxRstFast : in sl; + txHeader : out slv(1 downto 0); + txData : out slv(31 downto 0); + txSequence : out slv(6 downto 0)); +end Pgp3Gtp7TxGearbox; + +architecture rtl of Pgp3Gtp7TxGearbox is + + type RegType is record + fifoRead : sl; + txHeader : slv(1 downto 0); + txData : slv(31 downto 0); + txSequence : slv(6 downto 0); + end record; + + constant REG_INIT_C : RegType := ( + fifoRead => '0', + txHeader => (others => '0'), + txSequence => (others => '0'), + txData => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal writeEnable : sl; + signal almostFull : sl; + signal slaveReady : sl; + signal fifoRead : sl; + signal fifoValid : sl; + signal fifoData : slv(65 downto 0); + +begin + + U_FifoAsync : entity work.FifoAsync + generic map ( + TPD_G => TPD_G, + FWFT_EN_G => true, + DATA_WIDTH_G => 66, + BRAM_EN_G => false, + ADDR_WIDTH_G => 4) + port map ( + rst => phyTxRstFast, + -- Write Ports + wr_clk => phyTxClkSlow, + wr_en => writeEnable, + din(65 downto 64) => phyTxHeader, + din(63 downto 0) => phyTxData, + almost_full => almostFull, + -- Read Ports + rd_clk => phyTxClkFast, + rd_en => fifoRead, + dout => fifoData, + valid => fifoValid); + + phyTxDataRdy <= not(almostFull); + writeEnable <= phyTxValid and not(almostFull); + + comb : process (fifoData, fifoValid, phyTxRstFast, r) is + variable v : RegType; + variable i : natural; + begin + -- Latch the current value + v := r; + + -- Reset the flags + v.fifoRead := '0'; + + -- Check for valid data + if (fifoValid = '1') then + + -- Increment the counter + v.txSequence := r.txSequence + 1; + + -- Check if last cycle was a pause cycle + if (r.txSequence = 32) then + -- Reset the counter + v.txSequence := (others => '0'); + end if; + + -------------------------------------------------------------------------------------- + -- UG482 (v1.9) Figure 3-9 shows how a pause occurs at counter value 31 when using + -- an 4-byte fabric interface in external sequence counter mode with 64B/66B encoding. + -------------------------------------------------------------------------------------- + -- Check if not a "pause" cycle + if (v.txSequence /= 32) then + v.txHeader := fifoData(65 downto 64); + -- Check the phase of the 32-bit chucking + if (v.txSequence(0) = '0') then + v.txData := fifoData(63 downto 32); + else + v.txData := fifoData(31 downto 0); + -- Read the FIFO + v.fifoRead := '1'; + end if; + end if; + + end if; + + -- Combinatorial outputs before the reset + fifoRead <= v.fifoRead; + + -- Reset + if (phyTxRstFast = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + -- Registered Outputs + txHeader <= r.txHeader; + txData <= r.txData; + txSequence <= r.txSequence; + + end process comb; + + seq : process (phyTxClkFast) is + begin + if rising_edge(phyTxClkFast) then + r <= rin after TPD_G; + end if; + end process seq; + +end rtl; diff --git a/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7Wrapper.vhd b/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7Wrapper.vhd new file mode 100644 index 0000000000..1aaf2e8b5c --- /dev/null +++ b/protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7Wrapper.vhd @@ -0,0 +1,438 @@ +------------------------------------------------------------------------------- +-- File : Pgp3Gtp7Wrapper.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.StdRtlPkg.all; +use work.AxiStreamPkg.all; +use work.AxiLitePkg.all; +use work.Pgp3Pkg.all; + +library unisim; +use unisim.vcomponents.all; + +entity Pgp3Gtp7Wrapper is + generic ( + TPD_G : time := 1 ns; + ROGUE_SIM_EN_G : boolean := false; + ROGUE_SIM_USER_ID_G : integer range 0 to 100 := 1; + NUM_LANES_G : positive range 1 to 4 := 1; + NUM_VC_G : positive range 1 to 16 := 4; + SPEED_GRADE_G : positive range 1 to 3 := 3; + RATE_G : string := "6.25Gbps"; -- or "3.125Gbps" + REFCLK_TYPE_G : Pgp3RefClkType := PGP3_REFCLK_250_C; + REFCLK_G : boolean := false; -- FALSE: use pgpRefClkP/N, TRUE: use pgpRefClkIn + ---------------------------------------------------------------------------------------------- + -- PGP Settings + ---------------------------------------------------------------------------------------------- + PGP_RX_ENABLE_G : boolean := true; + RX_ALIGN_GOOD_COUNT_G : integer := 128; + RX_ALIGN_BAD_COUNT_G : integer := 16; + RX_ALIGN_SLIP_WAIT_G : integer := 32; + PGP_TX_ENABLE_G : boolean := true; + TX_CELL_WORDS_MAX_G : integer := PGP3_DEFAULT_TX_CELL_WORDS_MAX_C; -- Number of 64-bit words per cell + TX_SKP_INTERVAL_G : integer := 5000; + TX_SKP_BURST_SIZE_G : integer := 8; + TX_MUX_MODE_G : string := "INDEXED"; -- Or "ROUTED" + TX_MUX_TDEST_ROUTES_G : Slv8Array := (0 => "--------"); -- Only used in ROUTED mode + TX_MUX_TDEST_LOW_G : integer range 0 to 7 := 0; + TX_MUX_ILEAVE_EN_G : boolean := true; + TX_MUX_ILEAVE_ON_NOTVALID_G : boolean := false; + EN_PGP_MON_G : boolean := false; + EN_GTH_DRP_G : boolean := false; + EN_QPLL_DRP_G : boolean := false; + TX_POLARITY_G : slv(3 downto 0) := x"0"; + RX_POLARITY_G : slv(3 downto 0) := x"0"; + AXIL_BASE_ADDR_G : slv(31 downto 0) := (others => '0'); + AXIL_CLK_FREQ_G : real := 156.25E+6); + port ( + -- Stable Clock and Reset + stableClk : in sl; -- GT needs a stable clock to "boot up" + stableRst : in sl; + -- Gt Serial IO + pgpGtTxP : out slv(NUM_LANES_G-1 downto 0); + pgpGtTxN : out slv(NUM_LANES_G-1 downto 0); + pgpGtRxP : in slv(NUM_LANES_G-1 downto 0); + pgpGtRxN : in slv(NUM_LANES_G-1 downto 0); + -- GT Clocking + pgpRefClkP : in sl := '0'; + pgpRefClkN : in sl := '1'; + pgpRefClkIn : in sl := '0'; + pgpRefClkOut : out sl; + pgpRefClkDiv2Bufg : out sl; + -- Clocking + pgpClk : out slv(NUM_LANES_G-1 downto 0); + pgpClkRst : out slv(NUM_LANES_G-1 downto 0); + -- Non VC Rx Signals + pgpRxIn : in Pgp3RxInArray(NUM_LANES_G-1 downto 0); + pgpRxOut : out Pgp3RxOutArray(NUM_LANES_G-1 downto 0); + -- Non VC Tx Signals + pgpTxIn : in Pgp3TxInArray(NUM_LANES_G-1 downto 0); + pgpTxOut : out Pgp3TxOutArray(NUM_LANES_G-1 downto 0); + -- Frame Transmit Interface + pgpTxMasters : in AxiStreamMasterArray((NUM_LANES_G*NUM_VC_G)-1 downto 0); + pgpTxSlaves : out AxiStreamSlaveArray((NUM_LANES_G*NUM_VC_G)-1 downto 0); + -- Frame Receive Interface + pgpRxMasters : out AxiStreamMasterArray((NUM_LANES_G*NUM_VC_G)-1 downto 0); + pgpRxCtrl : in AxiStreamCtrlArray((NUM_LANES_G*NUM_VC_G)-1 downto 0); -- Used in implementation only + pgpRxSlaves : in AxiStreamSlaveArray((NUM_LANES_G*NUM_VC_G)-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); -- Used in simulation only + -- Debug Interface + txPreCursor : in Slv5Array(NUM_LANES_G-1 downto 0) := (others => "00111"); + txPostCursor : in Slv5Array(NUM_LANES_G-1 downto 0) := (others => "00111"); + txDiffCtrl : in Slv4Array(NUM_LANES_G-1 downto 0) := (others => "1111"); + debugClk : out slv(2 downto 0); -- Copy of the TX PLL Clocks + debugRst : out slv(2 downto 0); -- Copy of the TX PLL Resets + -- AXI-Lite Register Interface (axilClk domain) + axilClk : in sl := '0'; -- Stable Clock + axilRst : in sl := '0'; + axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + axilReadSlave : out AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C; + axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + axilWriteSlave : out AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C); +end Pgp3Gtp7Wrapper; + +architecture rtl of Pgp3Gtp7Wrapper is + + constant CLKIN_PERIOD_C : real := ite((RATE_G = "6.25Gbps"), 2.56, 5.12); -- 390.625 MHz for 6.25Gbps configuration + + constant BANDWIDTH_C : string := ite((SPEED_GRADE_G = 3), "HIGH", "OPTIMIZED"); + + constant CLKFBOUT_MULT_C : positive := ite((SPEED_GRADE_G = 3), ite((RATE_G = "6.25Gbps"), 4, 8), ite((RATE_G = "6.25Gbps"), 3, 6)); + + constant CLKOUT0_DIVIDE_C : positive := ite((SPEED_GRADE_G = 3), ite((RATE_G = "6.25Gbps"), 16, 32), ite((RATE_G = "6.25Gbps"), 12, 24)); -- 97.656 MHz for 6.25Gbps configuration + + constant CLKOUT1_DIVIDE_C : positive := ite((SPEED_GRADE_G = 3), ite((RATE_G = "6.25Gbps"), 4, 8), ite((RATE_G = "6.25Gbps"), 3, 6)); -- 390.625 MHz for 6.25Gbps configuration + + constant CLKOUT2_DIVIDE_C : positive := ite((SPEED_GRADE_G = 3), ite((RATE_G = "6.25Gbps"), 8, 16), ite((RATE_G = "6.25Gbps"), 6, 12)); -- 195.312 MHz for 6.25Gbps configuration + + signal qPllOutClk : Slv2Array(3 downto 0) := (others => "00"); + signal qPllOutRefClk : Slv2Array(3 downto 0) := (others => "00"); + signal qPllLock : Slv2Array(3 downto 0) := (others => "00"); + signal qPllRefClkLost : Slv2Array(3 downto 0) := (others => "00"); + signal qpllRst : Slv2Array(3 downto 0) := (others => "00"); + + signal gtTxOutClk : slv(3 downto 0) := (others => '0'); + signal gtTxPllRst : slv(3 downto 0) := (others => '0'); + signal gtTxPllLock : slv(3 downto 0) := (others => '0'); + signal pllOut : slv(2 downto 0) := (others => '0'); + signal txPllClk : slv(2 downto 0) := (others => '0'); + signal txPllRst : slv(2 downto 0) := (others => '0'); + signal lockedStrobe : slv(3 downto 0) := (others => '0'); + signal pllLock : sl; + + signal pgpRefClkDiv2 : sl; + signal pgpRefClk : sl; + signal clkFb : sl; + signal gtTxOutClkBufg : sl; + + constant NUM_AXIL_MASTERS_C : integer := NUM_LANES_G+1; + constant QPLL_AXIL_INDEX_C : integer := NUM_AXIL_MASTERS_C-1; + + constant XBAR_CONFIG_C : AxiLiteCrossbarMasterConfigArray(NUM_AXIL_MASTERS_C-1 downto 0) := + genAxiLiteConfig(NUM_AXIL_MASTERS_C, AXIL_BASE_ADDR_G, 16, 13); + + signal axilReadMasters : AxiLiteReadMasterArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_MASTER_INIT_C); + signal axilReadSlaves : AxiLiteReadSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C); + signal axilWriteMasters : AxiLiteWriteMasterArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_MASTER_INIT_C); + signal axilWriteSlaves : AxiLiteWriteSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C); + +begin + + pgpRefClkOut <= pgpRefClk; + + INT_REFCLK : if (REFCLK_G = false) generate + + U_BUFG : BUFG + port map ( + I => pgpRefClkDiv2, + O => pgpRefClkDiv2Bufg); + + U_pgpRefClk : IBUFDS_GTE2 + port map ( + I => pgpRefClkP, + IB => pgpRefClkN, + CEB => '0', + ODIV2 => pgpRefClkDiv2, + O => pgpRefClk); + + end generate; + + EXT_REFCLK : if (REFCLK_G = true) generate + + pgpRefClkDiv2Bufg <= '0'; + pgpRefClk <= pgpRefClkIn; + + end generate; + + REAL_PGP : if (not ROGUE_SIM_EN_G) generate + + + U_XBAR : entity work.AxiLiteCrossbar + generic map ( + TPD_G => TPD_G, + NUM_SLAVE_SLOTS_G => 1, + NUM_MASTER_SLOTS_G => NUM_AXIL_MASTERS_C, + MASTERS_CONFIG_G => XBAR_CONFIG_C) + port map ( + axiClk => axilClk, + axiClkRst => axilRst, + sAxiWriteMasters(0) => axilWriteMaster, + sAxiWriteSlaves(0) => axilWriteSlave, + sAxiReadMasters(0) => axilReadMaster, + sAxiReadSlaves(0) => axilReadSlave, + mAxiWriteMasters => axilWriteMasters, + mAxiWriteSlaves => axilWriteSlaves, + mAxiReadMasters => axilReadMasters, + mAxiReadSlaves => axilReadSlaves); + + U_QPLL : entity work.Pgp3Gtp7Qpll + generic map ( + TPD_G => TPD_G, + EN_DRP_G => EN_QPLL_DRP_G, + REFCLK_TYPE_G => REFCLK_TYPE_G, + RATE_G => RATE_G) + port map ( + -- Stable Clock and Reset + stableClk => stableClk, -- [in] + stableRst => stableRst, -- [in] + -- QPLL Interface + pgpRefClk => pgpRefClk, + qPllOutClk => qPllOutClk, + qPllOutRefClk => qPllOutRefClk, + qPllLock => qPllLock, + qpllRefClkLost => qpllRefClkLost, + qpllRst => qpllRst, + -- AXI-Lite Interface + axilClk => axilClk, -- [in] + axilRst => axilRst, -- [in] + axilReadMaster => axilReadMasters(QPLL_AXIL_INDEX_C), -- [in] + axilReadSlave => axilReadSlaves(QPLL_AXIL_INDEX_C), -- [out] + axilWriteMaster => axilWriteMasters(QPLL_AXIL_INDEX_C), -- [in] + axilWriteSlave => axilWriteSlaves(QPLL_AXIL_INDEX_C)); -- [out] + + ----------- + -- PGP Core + ----------- + GEN_LANE : for i in NUM_LANES_G-1 downto 0 generate + U_Pgp : entity work.Pgp3Gtp7 + generic map ( + TPD_G => TPD_G, + RATE_G => RATE_G, + CLKIN_PERIOD_G => CLKIN_PERIOD_C, + BANDWIDTH_G => BANDWIDTH_C, + CLKFBOUT_MULT_G => CLKFBOUT_MULT_C, + CLKOUT0_DIVIDE_G => CLKOUT0_DIVIDE_C, + CLKOUT1_DIVIDE_G => CLKOUT1_DIVIDE_C, + CLKOUT2_DIVIDE_G => CLKOUT2_DIVIDE_C, + ---------------------------------------------------------------------------------------------- + -- PGP Settings + ---------------------------------------------------------------------------------------------- + PGP_RX_ENABLE_G => PGP_RX_ENABLE_G, + RX_ALIGN_GOOD_COUNT_G => RX_ALIGN_GOOD_COUNT_G, + RX_ALIGN_BAD_COUNT_G => RX_ALIGN_BAD_COUNT_G, + RX_ALIGN_SLIP_WAIT_G => RX_ALIGN_SLIP_WAIT_G, + PGP_TX_ENABLE_G => PGP_TX_ENABLE_G, + NUM_VC_G => NUM_VC_G, + TX_CELL_WORDS_MAX_G => TX_CELL_WORDS_MAX_G, + TX_SKP_INTERVAL_G => TX_SKP_INTERVAL_G, + TX_SKP_BURST_SIZE_G => TX_SKP_BURST_SIZE_G, + TX_MUX_MODE_G => TX_MUX_MODE_G, + TX_MUX_TDEST_ROUTES_G => TX_MUX_TDEST_ROUTES_G, + TX_MUX_TDEST_LOW_G => TX_MUX_TDEST_LOW_G, + TX_MUX_ILEAVE_EN_G => TX_MUX_ILEAVE_EN_G, + TX_MUX_ILEAVE_ON_NOTVALID_G => TX_MUX_ILEAVE_ON_NOTVALID_G, + EN_PGP_MON_G => EN_PGP_MON_G, + EN_DRP_G => EN_GTH_DRP_G, + TX_POLARITY_G => TX_POLARITY_G(i), + RX_POLARITY_G => RX_POLARITY_G(i), + AXIL_BASE_ADDR_G => XBAR_CONFIG_C(i).baseAddr, + AXIL_CLK_FREQ_G => AXIL_CLK_FREQ_G) + port map ( + -- Stable Clock and Reset + stableClk => stableClk, + stableRst => stableRst, + -- QPLL Interface + qPllOutClk => qPllOutClk(i), + qPllOutRefClk => qPllOutRefClk(i), + qPllLock => qPllLock(i), + qpllRefClkLost => qpllRefClkLost(i), + qpllRst => qpllRst(i), + -- TX PLL Interface + gtTxOutClk => gtTxOutClk(i), + gtTxPllRst => gtTxPllRst(i), + txPllClk => txPllClk, + txPllRst => txPllRst, + gtTxPllLock => gtTxPllLock(i), + -- Gt Serial IO + pgpGtTxP => pgpGtTxP(i), + pgpGtTxN => pgpGtTxN(i), + pgpGtRxP => pgpGtRxP(i), + pgpGtRxN => pgpGtRxN(i), + -- Clocking + pgpClk => pgpClk(i), + pgpClkRst => pgpClkRst(i), + -- Non VC Rx Signals + pgpRxIn => pgpRxIn(i), + pgpRxOut => pgpRxOut(i), + -- Non VC Tx Signals + pgpTxIn => pgpTxIn(i), + pgpTxOut => pgpTxOut(i), + -- Frame Transmit Interface + pgpTxMasters => pgpTxMasters(((i+1)*NUM_VC_G)-1 downto (i*NUM_VC_G)), + pgpTxSlaves => pgpTxSlaves(((i+1)*NUM_VC_G)-1 downto (i*NUM_VC_G)), + -- Frame Receive Interface + pgpRxMasters => pgpRxMasters(((i+1)*NUM_VC_G)-1 downto (i*NUM_VC_G)), + pgpRxCtrl => pgpRxCtrl(((i+1)*NUM_VC_G)-1 downto (i*NUM_VC_G)), + -- Debug Interface + txPreCursor => txPreCursor(i), + txPostCursor => txPostCursor(i), + txDiffCtrl => txDiffCtrl(i), + -- AXI-Lite Register Interface (axilClk domain) + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMasters(i), + axilReadSlave => axilReadSlaves(i), + axilWriteMaster => axilWriteMasters(i), + axilWriteSlave => axilWriteSlaves(i)); + + MASTER_LOCK : if (i = 0) generate + gtTxPllLock(0) <= pllLock; + end generate; + + SLAVE_LOCK : if (i /= 0) generate + -- Prevent the gtTxPllRst of this lane disrupting the other lanes in the QUAD + U_PwrUpRst : entity work.PwrUpRst + generic map ( + TPD_G => TPD_G, + DURATION_G => 125) + port map ( + arst => gtTxPllRst(i), + clk => stableClk, + rstOut => lockedStrobe(i)); + -- Trick the GT state machine of lock transition + gtTxPllLock(i) <= pllLock and not(lockedStrobe(i)); + end generate; + + end generate GEN_LANE; + + U_Bufg : BUFH + port map ( + I => gtTxOutClk(0), + O => gtTxOutClkBufg); + + U_TX_PLL : PLLE2_ADV + generic map ( + BANDWIDTH => BANDWIDTH_C, + CLKIN1_PERIOD => CLKIN_PERIOD_C, + DIVCLK_DIVIDE => 1, + CLKFBOUT_MULT => CLKFBOUT_MULT_C, + CLKOUT0_DIVIDE => CLKOUT0_DIVIDE_C, + CLKOUT1_DIVIDE => CLKOUT1_DIVIDE_C, + CLKOUT2_DIVIDE => CLKOUT2_DIVIDE_C) + port map ( + DCLK => axilClk, + DRDY => open, + DEN => '0', + DWE => '0', + DADDR => (others => '0'), + DI => (others => '0'), + DO => open, + PWRDWN => '0', + RST => gtTxPllRst(0), + CLKIN1 => gtTxOutClkBufg, + CLKIN2 => '0', + CLKINSEL => '1', + CLKFBOUT => clkFb, + CLKFBIN => clkFb, + LOCKED => pllLock, + CLKOUT0 => pllOut(0), + CLKOUT1 => pllOut(1), + CLKOUT2 => pllOut(2)); + + U_txPllClk0 : BUFG + port map ( + I => pllOut(0), + O => txPllClk(0)); + + U_txPllClk1 : BUFG + port map ( + I => pllOut(1), + O => txPllClk(1)); + + U_txPllClk2 : BUFG + port map ( + I => pllOut(2), + O => txPllClk(2)); + + GEN_RST : for i in 2 downto 0 generate + U_RstSync : entity work.RstSync + generic map ( + TPD_G => TPD_G, + IN_POLARITY_G => '0', + OUT_POLARITY_G => '1') + port map ( + clk => txPllClk(i), + asyncRst => pllLock, + syncRst => txPllRst(i)); + end generate; + + debugClk <= txPllClk; + debugRst <= txPllRst; + + end generate REAL_PGP; + + SIM_PGP : if (ROGUE_SIM_EN_G) generate + GEN_LANE : for i in NUM_LANES_G-1 downto 0 generate + U_Rogue : entity work.RoguePgp3Sim + generic map( + TPD_G => TPD_G, + USER_ID_G => (ROGUE_SIM_USER_ID_G+i), + NUM_VC_G => NUM_VC_G) + port map( + -- GT Ports + pgpRefClk => pgpRefClk, + pgpGtTxP => pgpGtTxP(i), + pgpGtTxN => pgpGtTxN(i), + pgpGtRxP => pgpGtRxP(i), + pgpGtRxN => pgpGtRxN(i), + -- PGP Clock and Reset + pgpClk => pgpClk(i), + pgpClkRst => pgpClkRst(i), + -- Non VC Rx Signals + pgpRxIn => pgpRxIn(i), + pgpRxOut => pgpRxOut(i), + -- Non VC Tx Signals + pgpTxIn => pgpTxIn(i), + pgpTxOut => pgpTxOut(i), + -- Frame Transmit Interface + pgpTxMasters => pgpTxMasters(((i+1)*NUM_VC_G)-1 downto (i*NUM_VC_G)), + pgpTxSlaves => pgpTxSlaves(((i+1)*NUM_VC_G)-1 downto (i*NUM_VC_G)), + -- Frame Receive Interface + pgpRxMasters => pgpRxMasters(((i+1)*NUM_VC_G)-1 downto (i*NUM_VC_G)), + pgpRxSlaves => pgpRxSlaves(((i+1)*NUM_VC_G)-1 downto (i*NUM_VC_G)), + -- AXI-Lite Register Interface (axilClk domain) + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMasters(i), + axilReadSlave => axilReadSlaves(i), + axilWriteMaster => axilWriteMasters(i), + axilWriteSlave => axilWriteSlaves(i)); + end generate GEN_LANE; + end generate SIM_PGP; + +end rtl; diff --git a/protocols/pgp/pgp3/gtp7/ruckus.tcl b/protocols/pgp/pgp3/gtp7/ruckus.tcl new file mode 100644 index 0000000000..906bf3296f --- /dev/null +++ b/protocols/pgp/pgp3/gtp7/ruckus.tcl @@ -0,0 +1,41 @@ +# Load RUCKUS library +source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl + +# Load Source Code +if { $::env(VIVADO_VERSION) >= 2018.2 } { + + # Load Source Code + loadSource -dir "$::DIR_PATH/rtl" + loadSource -sim_only -dir "$::DIR_PATH/tb" + + loadSource -path "$::DIR_PATH/ip/Pgp3Gtp7Ip6G.dcp" + # loadIpCore -path "$::DIR_PATH/ip/Pgp3Gtp7Ip6G.xci" + + loadSource -path "$::DIR_PATH/ip/Pgp3Gtp7Ip3G.dcp" + # loadIpCore -path "$::DIR_PATH/ip/Pgp3Gtp7Ip3G.xci" + + if { [info exists ::env(INCLUDE_PGP3_6G)] != 1 || $::env(INCLUDE_PGP3_6G) == 0 } { + set nop 0 + } else { + + loadConstraints -path "$::DIR_PATH/xdc/Pgp3Gtp7Ip6G.xdc" + set_property PROCESSING_ORDER {EARLY} [get_files {Pgp3Gtp7Ip6G.xdc}] + set_property SCOPED_TO_REF {Pgp3Gtp7Ip6G} [get_files {Pgp3Gtp7Ip6G.xdc}] + set_property SCOPED_TO_CELLS {U0} [get_files {Pgp3Gtp7Ip6G.xdc}] + + } + + if { [info exists ::env(INCLUDE_PGP3_3G)] != 1 || $::env(INCLUDE_PGP3_3G) == 0 } { + set nop 0 + } else { + + loadConstraints -path "$::DIR_PATH/xdc/Pgp3Gtp7Ip3G.xdc" + set_property PROCESSING_ORDER {EARLY} [get_files {Pgp3Gtp7Ip3G.xdc}] + set_property SCOPED_TO_REF {Pgp3Gtp7Ip3G} [get_files {Pgp3Gtp7Ip3G.xdc}] + set_property SCOPED_TO_CELLS {U0} [get_files {Pgp3Gtp7Ip3G.xdc}] + + } + +} else { + puts "\n\nWARNING: $::DIR_PATH requires Vivado 2018.2 (or later)\n\n" +} diff --git a/protocols/pgp/pgp3/gtp7/tb/Pgp3Gtp7Tb.vhd b/protocols/pgp/pgp3/gtp7/tb/Pgp3Gtp7Tb.vhd new file mode 100644 index 0000000000..0bd0d467a4 --- /dev/null +++ b/protocols/pgp/pgp3/gtp7/tb/Pgp3Gtp7Tb.vhd @@ -0,0 +1,111 @@ +------------------------------------------------------------------------------- +-- File : Pgp3Gtp7Tb.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Simulation Testbed for Pgp3Gtp7 +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.StdRtlPkg.all; +use work.AxiStreamPkg.all; +use work.Pgp3Pkg.all; + +entity Pgp3Gtp7Tb is end Pgp3Gtp7Tb; + +architecture testbed of Pgp3Gtp7Tb is + + constant CLK_PERIOD_C : time := 4 ns; + constant TPD_G : time := CLK_PERIOD_C/4; + + signal gtClkP : sl := '0'; + signal gtClkN : sl := '1'; + + signal stableClk : sl := '0'; + signal stableRst : sl := '1'; + + signal loopP : sl := '0'; + signal loopN : sl := '1'; + + signal pgpClk : sl := '0'; + signal pgpRst : sl := '1'; + + signal pgpRxIn : Pgp3RxInType := PGP3_RX_IN_INIT_C; + signal pgpRxOut : Pgp3RxOutType := PGP3_RX_OUT_INIT_C; + + signal pgpTxIn : Pgp3TxInType := PGP3_TX_IN_INIT_C; + signal pgpTxOut : Pgp3TxOutType := PGP3_TX_OUT_INIT_C; + + signal pgpTxMasters : AxiStreamMasterArray(3 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal pgpTxSlaves : AxiStreamSlaveArray(3 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); + + signal pgpRxMasters : AxiStreamMasterArray(3 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal pgpRxCtrl : AxiStreamCtrlArray(3 downto 0) := (others => AXI_STREAM_CTRL_UNUSED_C); + +begin + + ----------------------------- + -- Generate clocks and resets + ----------------------------- + U_ClkRst : entity work.ClkRst + generic map ( + CLK_PERIOD_G => CLK_PERIOD_C, + RST_START_DELAY_G => 0 ns, -- Wait this long into simulation before asserting reset + RST_HOLD_TIME_G => 1000 ns) -- Hold reset for this long) + port map ( + clkP => gtClkP, + clkN => gtClkN, + rst => stableRst); + + ----------------------- + -- PGP Core for ARTIX-7 + ----------------------- + U_PGP : entity work.Pgp3Gtp7Wrapper + generic map ( + TPD_G => TPD_G, + SIM_PLL_EMULATION_G => true, + NUM_LANES_G => 1, + NUM_VC_G => 4, + RATE_G => "6.25Gbps", + REFCLK_TYPE_G => PGP3_REFCLK_250_C) + port map ( + -- Stable Clock and Reset + stableClk => stableClk, + stableRst => stableRst, + -- Gt Serial IO + pgpGtTxP(0) => loopP, + pgpGtTxN(0) => loopN, + pgpGtRxP(0) => loopP, + pgpGtRxN(0) => loopN, + -- GT Clocking + pgpRefClkP => gtClkP, + pgpRefClkN => gtClkN, + pgpRefClkDiv2Bufg => stableClk, + -- Clocking + pgpClk(0) => pgpClk, + pgpClkRst(0) => pgpRst, + -- Non VC TX Signals + pgpTxIn(0) => pgpTxIn, + pgpTxOut(0) => pgpTxOut, + -- Non VC RX Signals + pgpRxIn(0) => pgpRxIn, + pgpRxOut(0) => pgpRxOut, + -- Frame Transmit Interface + pgpTxMasters => pgpTxMasters, + pgpTxSlaves => pgpTxSlaves, + -- Frame Receive Interface + pgpRxMasters => pgpRxMasters, + pgpRxCtrl => pgpRxCtrl); + +end testbed; diff --git a/protocols/pgp/pgp3/gtp7/xdc/Pgp3Gtp7Ip3G.xdc b/protocols/pgp/pgp3/gtp7/xdc/Pgp3Gtp7Ip3G.xdc new file mode 100644 index 0000000000..965f7e2e26 --- /dev/null +++ b/protocols/pgp/pgp3/gtp7/xdc/Pgp3Gtp7Ip3G.xdc @@ -0,0 +1,16 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +create_clock -period 5.120 [get_pins -hier -filter {name=~*gt0_Pgp3Gtp7Ip3G_i*gtpe2_i*TXOUTCLK}] +create_clock -period 5.120 [get_pins -hier -filter {name=~*gt0_Pgp3Gtp7Ip3G_i*gtpe2_i*RXOUTCLK}] +set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}] +set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}] +set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxfsmresetdone_r*/CLR}] +set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxfsmresetdone_r*/D}] diff --git a/protocols/pgp/pgp3/gtp7/xdc/Pgp3Gtp7Ip6G.xdc b/protocols/pgp/pgp3/gtp7/xdc/Pgp3Gtp7Ip6G.xdc new file mode 100644 index 0000000000..f4c9c18bfd --- /dev/null +++ b/protocols/pgp/pgp3/gtp7/xdc/Pgp3Gtp7Ip6G.xdc @@ -0,0 +1,16 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +create_clock -period 2.560 [get_pins -hier -filter {name=~*gt0_Pgp3Gtp7Ip6G_i*gtpe2_i*TXOUTCLK}] +create_clock -period 2.560 [get_pins -hier -filter {name=~*gt0_Pgp3Gtp7Ip6G_i*gtpe2_i*RXOUTCLK}] +set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}] +set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}] +set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxfsmresetdone_r*/CLR}] +set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxfsmresetdone_r*/D}] diff --git a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7.vhd b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7.vhd index a4e163d2b9..5f7f26074e 100644 --- a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7.vhd +++ b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp3Gtx7.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-06-29 --- Last update: 2018-06-11 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -50,8 +48,8 @@ entity Pgp3Gtx7 is TX_MUX_TDEST_LOW_G : integer range 0 to 7 := 0; TX_MUX_ILEAVE_EN_G : boolean := true; TX_MUX_ILEAVE_ON_NOTVALID_G : boolean := true; - EN_DRP_G : boolean := true; - EN_PGP_MON_G : boolean := true; + EN_DRP_G : boolean := false; + EN_PGP_MON_G : boolean := false; TX_POLARITY_G : sl := '0'; RX_POLARITY_G : sl := '0'; AXIL_BASE_ADDR_G : slv(31 downto 0) := (others => '0'); @@ -128,7 +126,6 @@ architecture rtl of Pgp3Gtx7 is signal phyTxActive : sl; signal phyTxStart : sl; signal phyTxDataRdy : sl; - signal phyTxSequence : slv(5 downto 0); signal phyTxData : slv(63 downto 0); signal phyTxHeader : slv(1 downto 0); @@ -230,7 +227,6 @@ begin phyTxActive => phyTxActive, -- [in] phyTxReady => phyTxDataRdy, -- [in] phyTxStart => phyTxStart, -- [out] - phyTxSequence => phyTxSequence, -- [out] phyTxData => phyTxData, -- [out] phyTxHeader => phyTxHeader, -- [out] -- Rx User interface diff --git a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7IpWrapper.vhd b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7IpWrapper.vhd index 5204912363..ae97ce6a3c 100644 --- a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7IpWrapper.vhd +++ b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7IpWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp3Gtx7IpWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-12-20 --- Last update: 2018-06-10 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Qpll.vhd b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Qpll.vhd index 2b06f5d02b..54b74d32b1 100644 --- a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Qpll.vhd +++ b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Qpll.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp3Gtx7Qpll.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-10-26 --- Last update: 2018-06-10 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Wrapper.vhd b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Wrapper.vhd index a9b9b80b69..3d8940ac67 100644 --- a/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Wrapper.vhd +++ b/protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Wrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Pgp3Gtx7Wrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-10-27 --- Last update: 2018-06-19 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -54,9 +52,9 @@ entity Pgp3Gtx7Wrapper is TX_MUX_TDEST_LOW_G : integer range 0 to 7 := 0; TX_MUX_ILEAVE_EN_G : boolean := true; TX_MUX_ILEAVE_ON_NOTVALID_G : boolean := true; - EN_PGP_MON_G : boolean := true; - EN_GTH_DRP_G : boolean := true; - EN_QPLL_DRP_G : boolean := true; + EN_PGP_MON_G : boolean := false; + EN_GTH_DRP_G : boolean := false; + EN_QPLL_DRP_G : boolean := false; TX_POLARITY_G : slv(3 downto 0) := x"0"; RX_POLARITY_G : slv(3 downto 0) := x"0"; AXIL_BASE_ADDR_G : slv(31 downto 0) := (others => '0'); @@ -90,8 +88,8 @@ entity Pgp3Gtx7Wrapper is pgpTxSlaves : out AxiStreamSlaveArray((NUM_LANES_G*NUM_VC_G)-1 downto 0); -- Frame Receive Interface pgpRxMasters : out AxiStreamMasterArray((NUM_LANES_G*NUM_VC_G)-1 downto 0); - pgpRxCtrl : in AxiStreamCtrlArray((NUM_LANES_G*NUM_VC_G)-1 downto 0); -- Unused in implementation only - pgpRxSlaves : in AxiStreamSlaveArray((NUM_LANES_G*NUM_VC_G)-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); -- Unused in simulation only + pgpRxCtrl : in AxiStreamCtrlArray((NUM_LANES_G*NUM_VC_G)-1 downto 0); -- Used in implementation only + pgpRxSlaves : in AxiStreamSlaveArray((NUM_LANES_G*NUM_VC_G)-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); -- Used in simulation only -- Debug Interface txPreCursor : in Slv5Array(NUM_LANES_G-1 downto 0) := (others => "00111"); txPostCursor : in Slv5Array(NUM_LANES_G-1 downto 0) := (others => "00111"); diff --git a/protocols/pgp/pgp3/ruckus.tcl b/protocols/pgp/pgp3/ruckus.tcl index 5dfdfdb6d6..66b33abd9e 100644 --- a/protocols/pgp/pgp3/ruckus.tcl +++ b/protocols/pgp/pgp3/ruckus.tcl @@ -7,6 +7,10 @@ loadRuckusTcl "$::DIR_PATH/core" # Get the family type set family [getFpgaFamily] +if { ${family} eq {artix7} } { + loadRuckusTcl "$::DIR_PATH/gtp7" +} + if { ${family} eq {kintex7} || ${family} eq {zynq} } { loadRuckusTcl "$::DIR_PATH/gtx7" diff --git a/protocols/rssi/rtl/RssiAxiLiteRegItf.vhd b/protocols/rssi/rtl/RssiAxiLiteRegItf.vhd index 3c44769330..3234dacc8b 100644 --- a/protocols/rssi/rtl/RssiAxiLiteRegItf.vhd +++ b/protocols/rssi/rtl/RssiAxiLiteRegItf.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RssiAxiLiteRegItf.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-01-15 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Register decoding for RSSI core -- 0x00 (RW)- Control register [4:0]: @@ -78,7 +76,7 @@ entity RssiAxiLiteRegItf is generic ( -- General Configurations TPD_G : time := 1 ns; - SEGMENT_ADDR_SIZE_G : positive := 3; -- 2^SEGMENT_ADDR_SIZE_G = Number of 64 bit wide data words + SEGMENT_ADDR_SIZE_G : positive := 7; -- 2^SEGMENT_ADDR_SIZE_G = Number of 64 bit wide data words -- Defaults form generics TIMEOUT_UNIT_G : real := 1.0E-6; INIT_SEQ_N_G : natural := 16#80#; @@ -160,7 +158,7 @@ architecture rtl of RssiAxiLiteRegItf is initSeqN => toSlv(INIT_SEQ_N_G, 8), version => toSlv(VERSION_G, 4), maxOutsSeg => toSlv(MAX_NUM_OUTS_SEG_G, 8), - maxSegSize => toSlv((2**SEGMENT_ADDR_SIZE_G)*RSSI_WORD_WIDTH_C, 16), + maxSegSize => toSlv(MAX_SEG_SIZE_G, 16), retransTout => toSlv(RETRANS_TOUT_G, 16), cumulAckTout => toSlv(ACK_TOUT_G, 16), nullSegTout => toSlv(NULL_TOUT_G, 16), @@ -221,6 +219,11 @@ begin v.maxOutsSeg := axilWriteMaster.wdata(7 downto 0); when 16#04# => -- ADDR (16) v.maxSegSize := axilWriteMaster.wdata(15 downto 0); + if (unsigned(v.maxSegSize) < 8) then + v.maxSegSize := toSlv( 8, v.maxSegSize'length); + elsif (unsigned(v.maxSegSize) > (2**SEGMENT_ADDR_SIZE_G)*8 ) then + v.maxSegSize := toSlv( (2**SEGMENT_ADDR_SIZE_G)*8, v.maxSegSize'length ); + end if; when 16#05# => v.retransTout := axilWriteMaster.wdata(15 downto 0); when 16#06# => diff --git a/protocols/rssi/rtl/RssiChksum.vhd b/protocols/rssi/rtl/RssiChksum.vhd index fb572cc47d..0340299ab8 100644 --- a/protocols/rssi/rtl/RssiChksum.vhd +++ b/protocols/rssi/rtl/RssiChksum.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RssiChksum.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-09 --- Last update: 2015-08-09 ------------------------------------------------------------------------------- -- Description: Calculates and checks the RUDP packet checksum. -- Checksum for IP/UDP/TCP/RUDP. diff --git a/protocols/rssi/rtl/RssiConnFsm.vhd b/protocols/rssi/rtl/RssiConnFsm.vhd index 8e2afef97a..8ef2e54a2b 100644 --- a/protocols/rssi/rtl/RssiConnFsm.vhd +++ b/protocols/rssi/rtl/RssiConnFsm.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RssiConnFsm.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-09 --- Last update: 2016-06-23 ------------------------------------------------------------------------------- -- Description: Connection establishment mechanism: -- - Connection open/close request, diff --git a/protocols/rssi/rtl/RssiCore.vhd b/protocols/rssi/rtl/RssiCore.vhd index 1f38332ce4..9a9231144b 100644 --- a/protocols/rssi/rtl/RssiCore.vhd +++ b/protocols/rssi/rtl/RssiCore.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RssiCore.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-09 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: The module is based upon RUDP (Cisco implementation) RFC-908, RFC-1151, draft-ietf-sigtran-reliable-udp-00. -- The specifications in the drafts are modified by internal simplifications and improvements. @@ -116,7 +114,9 @@ entity RssiCore is axilWriteSlave : out AxiLiteWriteSlaveType; -- Internal statuses - statusReg_o : out slv(6 downto 0)); + statusReg_o : out slv(6 downto 0); + + maxSegSize_o : out slv(15 downto 0)); end entity RssiCore; architecture rtl of RssiCore is @@ -125,10 +125,8 @@ architecture rtl of RssiCore is constant FIFO_ADDR_WIDTH_C : positive := ite((SEGMENT_ADDR_SIZE_G < 7), 9, SEGMENT_ADDR_SIZE_G+2); -- min. 4 segment buffering constant FIFO_PAUSE_THRESH_C : positive := (2**FIFO_ADDR_WIDTH_C) - (2**(SEGMENT_ADDR_SIZE_G+1)); -- pause threshold = FIFO_FULL - (2 x segment buffers) - constant FIFO_BUSY_THRESH_C : positive := (2**SEGMENT_ADDR_SIZE_G); -- busy threshold = (1 x segment buffers) - signal s_fifoWrCnt : slv(FIFO_ADDR_WIDTH_C-1 downto 0); - signal s_localBusy : sl; + signal s_rxBuffBusy : sl; -- RSSI Parameters signal s_appRssiParam : RssiParamType; @@ -502,6 +500,7 @@ begin rst_i => rst_i, connActive_i => s_connActive, + rxBuffBusy_i => s_rxBuffBusy, rssiParam_i => s_rssiParam, rxFlags_i => s_rxFlags, rxValid_i => s_rxValidSeg, @@ -553,7 +552,7 @@ begin dataHeadSt_i => s_dataHeadSt, nullHeadSt_i => s_nullHeadSt, ackHeadSt_i => s_ackHeadSt, - busyHeadSt_i => s_localBusy, + busyHeadSt_i => s_rxBuffBusy, ack_i => s_txAckF, -- Connected to ConnectFSM txSeqN_i => s_txSeqN, @@ -594,7 +593,6 @@ begin sndRst_i => s_sndRst, sndResend_i => s_sndResend, sndNull_i => s_sndNull, - remoteBusy_i=> s_rxFlags.busy, windowSize_i => s_txWindowSize, bufferSize_i => s_txBufferSize, @@ -693,6 +691,7 @@ begin port map ( clk_i => clk_i, rst_i => rst_i, + rxBuffBusy_o => s_rxBuffBusy, connActive_i => s_connActive, rxWindowSize_i => s_rxWindowSize, rxBufferSize_i => s_rxBufferSize, @@ -803,15 +802,12 @@ begin sAxisMaster => s_mAppAxisMaster, sAxisSlave => s_mAppAxisSlave, sAxisCtrl => s_mAppAxisCtrl, - fifoWrCnt => s_fifoWrCnt, -- mAxisClk => clk_i, mAxisRst => s_rstFifo, mAxisMaster => monMasters(1), mAxisSlave => monSlaves(1), - mTLastTUser => open); - - s_localBusy <= '1' when((s_fifoWrCnt >= FIFO_BUSY_THRESH_C) and (s_connActive = '1')) else '0'; + mTLastTUser => open); mAppAxisMaster_o <= monMasters(1); monSlaves(1) <= mAppAxisSlave_i; @@ -868,5 +864,7 @@ begin frameRate => frameRate(i), bandwidth => bandwidth(i)); end generate PACKET_RATE; + + maxSegSize_o <= s_rxRssiParam.maxSegSize; end architecture rtl; diff --git a/protocols/rssi/rtl/RssiCoreWrapper.vhd b/protocols/rssi/rtl/RssiCoreWrapper.vhd index 9fe0d9def6..d54c0bb1b1 100644 --- a/protocols/rssi/rtl/RssiCoreWrapper.vhd +++ b/protocols/rssi/rtl/RssiCoreWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RssiCoreWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-02-25 --- Last update: 2018-05-16 ------------------------------------------------------------------------------- -- Description: Wrapper for RSSI + AXIS packetizer ------------------------------------------------------------------------------- @@ -17,6 +15,7 @@ library ieee; use ieee.std_logic_1164.all; +use ieee.numeric_std.all; use work.StdRtlPkg.all; use work.RssiPkg.all; @@ -26,38 +25,39 @@ use work.AxiLitePkg.all; entity RssiCoreWrapper is generic ( - TPD_G : time := 1 ns; - CLK_FREQUENCY_G : real := 100.0E+6; -- In units of Hz - TIMEOUT_UNIT_G : real := 1.0E-6; -- In units of seconds - SERVER_G : boolean := true; -- Module is server or client - RETRANSMIT_ENABLE_G : boolean := true; -- Enable/Disable retransmissions in tx module - WINDOW_ADDR_SIZE_G : positive := 3; -- 2^WINDOW_ADDR_SIZE_G = Max number of segments in buffer - SEGMENT_ADDR_SIZE_G : positive := 7; -- 2^SEGMENT_ADDR_SIZE_G = Number of 64 bit wide data words - BYPASS_CHUNKER_G : boolean := false; -- Bypass the AXIS chunker layer - PIPE_STAGES_G : natural := 0; - APP_STREAMS_G : positive := 1; - APP_STREAM_ROUTES_G : Slv8Array := (0 => "--------"); - APP_ILEAVE_EN_G : boolean := false; - BYP_TX_BUFFER_G : boolean := false; - BYP_RX_BUFFER_G : boolean := false; + TPD_G : time := 1 ns; + CLK_FREQUENCY_G : real := 100.0E+6; -- In units of Hz + TIMEOUT_UNIT_G : real := 1.0E-6; -- In units of seconds + SERVER_G : boolean := true; -- Module is server or client + RETRANSMIT_ENABLE_G : boolean := true; -- Enable/Disable retransmissions in tx module + WINDOW_ADDR_SIZE_G : positive := 3; -- 2^WINDOW_ADDR_SIZE_G = Max number of segments in buffer + SEGMENT_ADDR_SIZE_G : positive := 7; -- 2^SEGMENT_ADDR_SIZE_G = Number of 64 bit wide data words + BYPASS_CHUNKER_G : boolean := false; -- Bypass the AXIS chunker layer + PIPE_STAGES_G : natural := 0; + APP_STREAMS_G : positive := 1; + APP_STREAM_ROUTES_G : Slv8Array := (0 => "--------"); + APP_ILEAVE_EN_G : boolean := false; + BYP_TX_BUFFER_G : boolean := false; + BYP_RX_BUFFER_G : boolean := false; + ILEAVE_ON_NOTVALID_G : boolean := false; -- AXIS Configurations - APP_AXIS_CONFIG_G : AxiStreamConfigArray := (0 => ssiAxiStreamConfig(8, TKEEP_NORMAL_C)); - TSP_AXIS_CONFIG_G : AxiStreamConfigType := ssiAxiStreamConfig(16, TKEEP_NORMAL_C); + APP_AXIS_CONFIG_G : AxiStreamConfigArray := (0 => ssiAxiStreamConfig(8, TKEEP_NORMAL_C)); + TSP_AXIS_CONFIG_G : AxiStreamConfigType := ssiAxiStreamConfig(16, TKEEP_NORMAL_C); -- Version and connection ID - INIT_SEQ_N_G : natural := 16#80#; - CONN_ID_G : positive := 16#12345678#; - VERSION_G : positive := 1; - HEADER_CHKSUM_EN_G : boolean := true; + INIT_SEQ_N_G : natural := 16#80#; + CONN_ID_G : positive := 16#12345678#; + VERSION_G : positive := 1; + HEADER_CHKSUM_EN_G : boolean := true; -- Window parameters of receiver module - MAX_NUM_OUTS_SEG_G : positive := 8; -- <=(2**WINDOW_ADDR_SIZE_G) - MAX_SEG_SIZE_G : positive := 1024; -- <= (2**SEGMENT_ADDR_SIZE_G)*8 Number of bytes + MAX_NUM_OUTS_SEG_G : positive := 8; -- <=(2**WINDOW_ADDR_SIZE_G) + MAX_SEG_SIZE_G : positive := 1024; -- <= (2**SEGMENT_ADDR_SIZE_G)*8 Number of bytes -- RSSI Timeouts - ACK_TOUT_G : positive := 25; -- unit depends on TIMEOUT_UNIT_G - RETRANS_TOUT_G : positive := 50; -- unit depends on TIMEOUT_UNIT_G (Recommended >= MAX_NUM_OUTS_SEG_G*Data segment transmission time) - NULL_TOUT_G : positive := 200; -- unit depends on TIMEOUT_UNIT_G (Recommended >= 4*RETRANS_TOUT_G) + ACK_TOUT_G : positive := 25; -- unit depends on TIMEOUT_UNIT_G + RETRANS_TOUT_G : positive := 50; -- unit depends on TIMEOUT_UNIT_G (Recommended >= MAX_NUM_OUTS_SEG_G*Data segment transmission time) + NULL_TOUT_G : positive := 200; -- unit depends on TIMEOUT_UNIT_G (Recommended >= 4*RETRANS_TOUT_G) -- Counters - MAX_RETRANS_CNT_G : positive := 2; - MAX_CUM_ACK_CNT_G : positive := 3); + MAX_RETRANS_CNT_G : positive := 2; + MAX_CUM_ACK_CNT_G : positive := 3); port ( -- Clock and Reset clk_i : in sl; @@ -105,6 +105,8 @@ architecture mapping of RssiCoreWrapper is signal rssiNotConnected : sl; signal rssiConnected : sl; + signal maxObSegSize : slv(15 downto 0); + -- This should really go in a AxiStreamPacketizerPkg constant PACKETIZER_AXIS_CONFIG_C : AxiStreamConfigType := ( TSTRB_EN_C => false, @@ -150,7 +152,7 @@ begin MODE_G => "ROUTED", TDEST_ROUTES_G => APP_STREAM_ROUTES_G, ILEAVE_EN_G => APP_ILEAVE_EN_G, - ILEAVE_ON_NOTVALID_G => false, + ILEAVE_ON_NOTVALID_G => ILEAVE_ON_NOTVALID_G, ILEAVE_REARB_G => (MAX_SEG_SIZE_G/CONV_AXIS_CONFIG_C.TDATA_BYTES_C), PIPE_STAGES_G => 1) port map ( @@ -165,6 +167,14 @@ begin mAxisSlave => packetizerSlaves(0)); GEN_PACKER : if (BYPASS_CHUNKER_G = false) generate + constant MAX_SEGS_BITS_C : positive := bitSize(MAX_SEG_SIZE_G); + signal maxSegs : slv(MAX_SEGS_BITS_C - 1 downto 0); + begin + + maxSegs <= ite(unsigned(maxObSegSize) >= MAX_SEG_SIZE_G, + slv(to_unsigned(MAX_SEG_SIZE_G, maxSegs'length)), + maxObSegSize(maxSegs'range)); + PACKER_V1 : if (APP_ILEAVE_EN_G = false) generate U_Packetizer : entity work.AxiStreamPacketizer generic map ( @@ -175,6 +185,7 @@ begin port map ( axisClk => clk_i, axisRst => rst_i, + maxPktBytes => maxSegs, sAxisMaster => packetizerMasters(0), sAxisSlave => packetizerSlaves(0), mAxisMaster => packetizerMasters(1), @@ -194,6 +205,7 @@ begin port map ( axisClk => clk_i, axisRst => rst_i, + maxPktBytes => maxSegs, sAxisMaster => packetizerMasters(0), sAxisSlave => packetizerSlaves(0), mAxisMaster => packetizerMasters(1), @@ -261,7 +273,8 @@ begin axilWriteMaster => axilWriteMaster, axilWriteSlave => axilWriteSlave, -- Internal statuses - statusReg_o => statusReg); + statusReg_o => statusReg, + maxSegSize_o => maxObSegSize); statusReg_o <= statusReg; rssiConnected <= statusReg(0); diff --git a/protocols/rssi/rtl/RssiHeaderReg.vhd b/protocols/rssi/rtl/RssiHeaderReg.vhd index 9da9870a87..89c77b9793 100644 --- a/protocols/rssi/rtl/RssiHeaderReg.vhd +++ b/protocols/rssi/rtl/RssiHeaderReg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RssiHeaderReg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-09 --- Last update: 2016-01-27 ------------------------------------------------------------------------------- -- Description: Combines and decodes the header values from input parameters headerValues_i -- Header is selected by xxxHeadSt_i and addressed by addr_i diff --git a/protocols/rssi/rtl/RssiMonitor.vhd b/protocols/rssi/rtl/RssiMonitor.vhd index 7f299ea514..61dda7a3de 100644 --- a/protocols/rssi/rtl/RssiMonitor.vhd +++ b/protocols/rssi/rtl/RssiMonitor.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RssiMonitor.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-09 --- Last update: 2016-01-27 ------------------------------------------------------------------------------- -- Description: -- Handles RSSI counters, timeouts, and statuses: @@ -58,6 +56,9 @@ entity RssiMonitor is -- Connection FSM indicating active connection connActive_i : in sl; + + -- RX Buffer Full + rxBuffBusy_i : in sl; -- Timeout and counter values rssiParam_i : in RssiParamType; @@ -127,6 +128,7 @@ architecture rtl of RssiMonitor is nullToutCnt : slv(rssiParam_i.nullSegTout'left + bitSize(SAMPLES_PER_TIME_C) downto 0); sndNull : sl; nullTout : sl; + rxBuffBusy : sl; -- Ack packet cumulative/timeout ackToutCnt : slv(rssiParam_i.cumulAckTout'left + bitSize(SAMPLES_PER_TIME_C) downto 0); @@ -157,6 +159,7 @@ architecture rtl of RssiMonitor is nullToutCnt => (others=>'0'), sndnull => '0', nullTout => '0', + rxBuffBusy => '0', -- Ack packet cumulative/timeout ackToutCnt => (others=>'0'), @@ -187,7 +190,7 @@ begin s_status(4) <= peerConnTout_i; s_status(5) <= paramReject_i; - comb : process (r, rst_i, rxFlags_i, rssiParam_i, rxValid_i, rxDrop_i, dataHeadSt_i, rstHeadSt_i, nullHeadSt_i, ackHeadSt_i, + comb : process (r, rst_i, rxFlags_i, rssiParam_i, rxValid_i, rxDrop_i, dataHeadSt_i, rstHeadSt_i, nullHeadSt_i, ackHeadSt_i, rxBuffBusy_i, connActive_i, rxLastSeqN_i, rxWindowSize_i, txBufferEmpty_i, s_status) is variable v : RegType; begin @@ -289,6 +292,8 @@ begin v.sndNull := '0'; elsif (r.nullToutCnt >= (conv_integer(rssiParam_i.nullSegTout) * SAMPLES_PER_TIME_DIV3_C) ) then -- send null segments if timeout/2 reached v.sndNull := '1'; + elsif (rxBuffBusy_i = '1') and (r.rxBuffBusy = '0') then -- Check for RX buffer full event + v.sndNull := '1'; end if; -- Timeout not applicable @@ -315,10 +320,21 @@ begin elsif (r.nullToutCnt >= (conv_integer(rssiParam_i.nullSegTout) * SAMPLES_PER_TIME_C) ) then v.nullTout := '1'; end if; - - -- Null sending not applicable - v.sndNull := '0'; + + -- Null request SRFF + if (connActive_i = '0' or + dataHeadSt_i = '1' or + rstHeadSt_i = '1' or + nullHeadSt_i = '1') then + v.sndNull := '0'; + elsif (rxBuffBusy_i = '1') and (r.rxBuffBusy = '0') then -- Check for RX buffer full event + v.sndNull := '1'; + end if; + end if; + + -- Check a delayed copy + v.rxBuffBusy := rxBuffBusy_i; -- ///////////////////////////////////////////////////////// ------------------------------------------------------------ @@ -349,7 +365,7 @@ begin (rxLastSeqN_i - r.lastAckSeqN) = 0 ) then v.ackToutCnt := (others=>'0'); - elsif ((rxLastSeqN_i - r.lastAckSeqN) > 0 and (rxLastSeqN_i - r.lastAckSeqN) <= rxWindowSize_i) then + elsif ((rxLastSeqN_i - r.lastAckSeqN) > 0 and (rxLastSeqN_i - r.lastAckSeqN) <= rxWindowSize_i) or (rxBuffBusy_i = '1') then if (r.ackToutCnt /= MAX_ACK_TOUT_CNT_C) then v.ackToutCnt := r.ackToutCnt+1; end if; diff --git a/protocols/rssi/rtl/RssiPkg.vhd b/protocols/rssi/rtl/RssiPkg.vhd index 8edea08353..ce33963dc1 100644 --- a/protocols/rssi/rtl/RssiPkg.vhd +++ b/protocols/rssi/rtl/RssiPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RssiPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-09 --- Last update: 2016-07-12 ------------------------------------------------------------------------------- -- Description: RSSI Package File ------------------------------------------------------------------------------- @@ -95,7 +93,7 @@ package RssiPkg is type WindowType is record seqN : slv(7 downto 0); segType : slv(2 downto 0); - keep : slv(15 downto 0); + keep : slv(RSSI_WORD_WIDTH_C-1 downto 0); segSize : natural; occupied : sl; end record WindowType; diff --git a/protocols/rssi/rtl/RssiRxFsm.vhd b/protocols/rssi/rtl/RssiRxFsm.vhd index 616d71b0a2..9b823f8d23 100644 --- a/protocols/rssi/rtl/RssiRxFsm.vhd +++ b/protocols/rssi/rtl/RssiRxFsm.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RssiRxFsm.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-06-11 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: Receiver FSM -- Receiver has the following functionality: @@ -61,6 +59,9 @@ entity RssiRxFsm is clk_i : in sl; rst_i : in sl; + -- RX Buffer Full + rxBuffBusy_o : out sl; + -- Connection FSM indicating active connection connActive_i : in sl; @@ -146,7 +147,8 @@ architecture rtl of RssiRxFsm is type RegType is record -- Resception buffer window - windowArray : WindowTypeArray(0 to 2 ** WINDOW_ADDR_SIZE_G-1); + windowArray : WindowTypeArray(0 to 2 ** WINDOW_ADDR_SIZE_G-1); + pending : slv(WINDOW_ADDR_SIZE_G downto 0); -- Transport side FSM (Receive and check segments) ----------------------------------------------------------- @@ -204,7 +206,8 @@ architecture rtl of RssiRxFsm is constant REG_INIT_C : RegType := ( -- Rx buffer window - windowArray => (0 to 2 ** WINDOW_ADDR_SIZE_G-1 => WINDOW_INIT_C), + windowArray => (0 to 2 ** WINDOW_ADDR_SIZE_G-1 => WINDOW_INIT_C), + pending => (others => '0'), -- Transport side FSM (Receive and check segments) ----------------------------------------------------------- @@ -506,7 +509,7 @@ begin if (tspSsiMaster_i.eof = '1' and tspSsiMaster_i.valid = '1') then -- Save tKeep of the last packet - v.windowArray(conv_integer(r.rxBufferAddr)).keep := tspSsiMaster_i.keep; + v.windowArray(conv_integer(r.rxBufferAddr)).keep := tspSsiMaster_i.keep(RSSI_WORD_WIDTH_C-1 downto 0); -- Save packet length (+1 because it has not incremented for EOF yet) v.windowArray(conv_integer(r.rxBufferAddr)).segSize := conv_integer(r.rxSegmentAddr(SEGMENT_ADDR_SIZE_G-1 downto 0))+1; @@ -543,6 +546,7 @@ begin v.inOrderSeqN := r.rxSeqN; v.rxBufferAddr := (others => '0'); v.windowArray := REG_INIT_C.windowArray; + v.pending := (others => '0'); -- Check if next valid SEQn is received. If yes: -- 1. increment the in order SEQn @@ -567,6 +571,10 @@ begin v.rxBufferAddr := (others => '0'); end if; -- + if v.pending < rxWindowSize_i then + v.pending := v.pending + 1; + end if; + -- else v.rxBufferAddr := r.rxBufferAddr; v.inOrderSeqN := r.inOrderSeqN; @@ -633,15 +641,15 @@ begin if (appSsiSlave_i.pause = '0') then - v.appSsiMaster.sof := '1'; - v.appSsiMaster.valid := '1'; - v.appSsiMaster.strb := (others => '1'); - v.appSsiMaster.dest := (others => '0'); - v.appSsiMaster.keep := r.windowArray(conv_integer(r.txBufferAddr)).keep; - v.appSsiMaster.eof := '1'; - v.appSsiMaster.eofe := '0'; + v.appSsiMaster.sof := '1'; + v.appSsiMaster.valid := '1'; + v.appSsiMaster.strb := (others => '1'); + v.appSsiMaster.dest := (others => '0'); + v.appSsiMaster.keep(RSSI_WORD_WIDTH_C-1 downto 0) := r.windowArray(conv_integer(r.txBufferAddr)).keep; + v.appSsiMaster.eof := '1'; + v.appSsiMaster.eofe := '0'; v.appSsiMaster.data(RSSI_WORD_WIDTH_C*8-1 downto 0) := rdBuffData_i; - v.txSegmentAddr := r.txSegmentAddr; + v.txSegmentAddr := r.txSegmentAddr; v.appState := SENT_S; end if; @@ -697,11 +705,11 @@ begin if (r.txSegmentAddr >= r.windowArray(conv_integer(r.txBufferAddr)).segSize) then -- Send EOF at the end of the segment - v.appSsiMaster.valid := '1'; - v.appSsiMaster.eof := '1'; - v.appSsiMaster.keep := r.windowArray(conv_integer(r.txBufferAddr)).keep; - v.appSsiMaster.eofe := '0'; - v.txSegmentAddr := r.txSegmentAddr; + v.appSsiMaster.valid := '1'; + v.appSsiMaster.eof := '1'; + v.appSsiMaster.keep(RSSI_WORD_WIDTH_C-1 downto 0) := r.windowArray(conv_integer(r.txBufferAddr)).keep; + v.appSsiMaster.eofe := '0'; + v.txSegmentAddr := r.txSegmentAddr; v.appState := SENT_S; @@ -729,6 +737,11 @@ begin else v.txBufferAddr := (others => '0'); end if; + -- + if v.pending /= 0 then + v.pending := v.pending - 1; + end if; + -- v.windowArray(conv_integer(r.txBufferAddr)).occupied := '0'; -- Release buffer @@ -779,6 +792,11 @@ begin chksumStrobe_o <= r.chkStb; chksumLength_o <= r.chkLen; rxParam_o <= r.rxParam; + if (r.pending > 1) then + rxBuffBusy_o <= '1'; + else + rxBuffBusy_o <= '0'; + end if; -- Application side SSI output appSsiMaster_o <= r.appSsiMaster; diff --git a/protocols/rssi/rtl/RssiTxFsm.vhd b/protocols/rssi/rtl/RssiTxFsm.vhd index 5233f72d1d..f65031f172 100644 --- a/protocols/rssi/rtl/RssiTxFsm.vhd +++ b/protocols/rssi/rtl/RssiTxFsm.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RssiTxFsm.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-09 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: Transmitter FSM -- Transmitter has the following functionality: @@ -82,7 +80,6 @@ entity RssiTxFsm is sndRst_i : in sl; sndResend_i : in sl; sndNull_i : in sl; - remoteBusy_i: in sl; -- Window buff size (Depends on the number of outstanding segments) windowSize_i : in integer range 1 to 2 ** (WINDOW_ADDR_SIZE_G); @@ -358,7 +355,7 @@ begin s_headerAndChksum <= rdHeaderData_i(63 downto 16) & s_chksum(15 downto 0); ----------------------------------------------------------------------------------------------- - comb : process (r, rst_i, appSsiMaster_i, sndSyn_i, sndAck_i, connActive_i, closed_i, sndRst_i, initSeqN_i, windowSize_i, headerRdy_i, ack_i, ackN_i, bufferSize_i, remoteBusy_i, + comb : process (r, rst_i, appSsiMaster_i, sndSyn_i, sndAck_i, connActive_i, closed_i, sndRst_i, initSeqN_i, windowSize_i, headerRdy_i, ack_i, ackN_i, bufferSize_i, sndResend_i, sndNull_i, tspSsiSlave_i, rdHeaderData_i, rdBuffData_i, s_headerAndChksum, chksumValid_i, headerLength_i, injectFault_i) is variable v : RegType; @@ -600,7 +597,7 @@ begin v.rxSegmentWe := '1'; -- Save packet tKeep of last data word - v.windowArray(conv_integer(r.rxBufferAddr)).keep := appSsiMaster_i.keep; + v.windowArray(conv_integer(r.rxBufferAddr)).keep := appSsiMaster_i.keep(RSSI_WORD_WIDTH_C-1 downto 0); v.windowArray(conv_integer(r.rxBufferAddr)).segSize := conv_integer(r.rxSegmentAddr(SEGMENT_ADDR_SIZE_G-1 downto 0)); v.appState := SEG_RDY_S; @@ -640,7 +637,7 @@ begin if (appSsiMaster_i.eof = '1' and appSsiMaster_i.valid = '1') then -- Save packet tKeep of last data word - v.windowArray(conv_integer(r.rxBufferAddr)).keep := appSsiMaster_i.keep; + v.windowArray(conv_integer(r.rxBufferAddr)).keep := appSsiMaster_i.keep(RSSI_WORD_WIDTH_C-1 downto 0); -- Save packet length (+1 because it has not incremented for EOF yet) v.windowArray(conv_integer(r.rxBufferAddr)).segSize := conv_integer(r.rxSegmentAddr(SEGMENT_ADDR_SIZE_G-1 downto 0))+1; @@ -839,7 +836,7 @@ begin -- Next state condition if (sndRst_i = '1') then v.tspState := RST_WE_S; - elsif (r.sndData = '1') and (r.bufferFull = '0') and (remoteBusy_i = '0') then + elsif (r.sndData = '1') and (r.bufferFull = '0') then v.ackSndData := '1'; v.tspState := DATA_WE_S; elsif (sndResend_i = '1' and r.bufferEmpty = '0') then @@ -1251,10 +1248,10 @@ begin if (r.txSegmentAddr >= r.windowArray(conv_integer(r.txBufferAddr)).segSize) then -- Send EOF at the end of the segment - v.tspSsiMaster.valid := '1'; - v.tspSsiMaster.eof := '1'; - v.tspSsiMaster.eofe := '0'; - v.tspSsiMaster.keep := r.windowArray(conv_integer(r.txBufferAddr)).keep; + v.tspSsiMaster.valid := '1'; + v.tspSsiMaster.eof := '1'; + v.tspSsiMaster.eofe := '0'; + v.tspSsiMaster.keep(RSSI_WORD_WIDTH_C-1 downto 0) := r.windowArray(conv_integer(r.txBufferAddr)).keep; -- v.txSegmentAddr := r.txSegmentAddr; -- @@ -1437,10 +1434,10 @@ begin if (r.txSegmentAddr >= r.windowArray(conv_integer(r.txBufferAddr)).segSize) then -- Send EOF at the end of the segment - v.tspSsiMaster.valid := '1'; - v.tspSsiMaster.eof := '1'; - v.tspSsiMaster.eofe := '0'; - v.tspSsiMaster.keep := r.windowArray(conv_integer(r.txBufferAddr)).keep; + v.tspSsiMaster.valid := '1'; + v.tspSsiMaster.eof := '1'; + v.tspSsiMaster.eofe := '0'; + v.tspSsiMaster.keep(RSSI_WORD_WIDTH_C-1 downto 0) := r.windowArray(conv_integer(r.txBufferAddr)).keep; -- v.txSegmentAddr := r.txSegmentAddr; -- diff --git a/protocols/rssi/sim/Chksum_tb.vhd b/protocols/rssi/sim/Chksum_tb.vhd index e24ce1b150..06336c4ba1 100644 --- a/protocols/rssi/sim/Chksum_tb.vhd +++ b/protocols/rssi/sim/Chksum_tb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : chksum_tb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-10-28 --- Last update: 2015-10-28 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the RSSI chksum ------------------------------------------------------------------------------- diff --git a/protocols/rssi/sim/RssiCoreTb.vhd b/protocols/rssi/sim/RssiCoreTb.vhd index 355d03ea4a..dfb8af2311 100644 --- a/protocols/rssi/sim/RssiCoreTb.vhd +++ b/protocols/rssi/sim/RssiCoreTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : RssiCoreTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-10-28 --- Last update: 2018-05-16 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the RssiCore ------------------------------------------------------------------------------- diff --git a/protocols/ruckus.tcl b/protocols/ruckus.tcl index 0c78fedcdd..3cd12de1d6 100644 --- a/protocols/ruckus.tcl +++ b/protocols/ruckus.tcl @@ -2,6 +2,7 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Load ruckus files +loadRuckusTcl "$::DIR_PATH/batcher" loadRuckusTcl "$::DIR_PATH/clink" loadRuckusTcl "$::DIR_PATH/glink" loadRuckusTcl "$::DIR_PATH/i2c" diff --git a/protocols/saci/rtl/AxiLiteSaciMaster.vhd b/protocols/saci/rtl/AxiLiteSaciMaster.vhd index 0a4dc8536d..55b349ee92 100644 --- a/protocols/saci/rtl/AxiLiteSaciMaster.vhd +++ b/protocols/saci/rtl/AxiLiteSaciMaster.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLiteSaciMaster2.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-06-01 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: New and improved version of the AxiLiteSaciMaster. ------------------------------------------------------------------------------- diff --git a/protocols/saci/rtl/SaciMaster.vhd b/protocols/saci/rtl/SaciMaster.vhd index fba32540ab..0e1fb10016 100644 --- a/protocols/saci/rtl/SaciMaster.vhd +++ b/protocols/saci/rtl/SaciMaster.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaciMaster.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-08-10 --- Last update: 2013-03-01 ------------------------------------------------------------------------------- -- Description: Saci Master Module ------------------------------------------------------------------------------- diff --git a/protocols/saci/rtl/SaciMaster2.vhd b/protocols/saci/rtl/SaciMaster2.vhd index 2c6eda3eaa..0280a007a2 100644 --- a/protocols/saci/rtl/SaciMaster2.vhd +++ b/protocols/saci/rtl/SaciMaster2.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaciMaster2.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-08-10 --- Last update: 2016-06-17 ------------------------------------------------------------------------------- -- Description: New and improved version of the SaciMaster. ------------------------------------------------------------------------------- diff --git a/protocols/saci/rtl/SaciMasterPkg.vhd b/protocols/saci/rtl/SaciMasterPkg.vhd index caa89600d4..11e9db9a2b 100644 --- a/protocols/saci/rtl/SaciMasterPkg.vhd +++ b/protocols/saci/rtl/SaciMasterPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaciMasterPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-08-14 --- Last update: 2012-09-27 ------------------------------------------------------------------------------- -- Description: Saci Master Package File ------------------------------------------------------------------------------- diff --git a/protocols/saci/rtl/SaciMasterSync.vhd b/protocols/saci/rtl/SaciMasterSync.vhd index 5117efe45a..62a95d271c 100644 --- a/protocols/saci/rtl/SaciMasterSync.vhd +++ b/protocols/saci/rtl/SaciMasterSync.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaciMasterSync.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-08-10 --- Last update: 2017-05-10 ------------------------------------------------------------------------------- -- Description: Saci Master Synchronization Wrapper ------------------------------------------------------------------------------- diff --git a/protocols/saci/rtl/SaciMultiPixel.vhd b/protocols/saci/rtl/SaciMultiPixel.vhd index 9a3075edfe..f0857585f6 100644 --- a/protocols/saci/rtl/SaciMultiPixel.vhd +++ b/protocols/saci/rtl/SaciMultiPixel.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : PgpParallelSimModel.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 07/21/2016 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the diff --git a/protocols/saci/rtl/SaciMultiPixelPkg.vhd b/protocols/saci/rtl/SaciMultiPixelPkg.vhd index 34349119d0..194e5e258e 100644 --- a/protocols/saci/rtl/SaciMultiPixelPkg.vhd +++ b/protocols/saci/rtl/SaciMultiPixelPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaciMultiPixelPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 07/21/2016 --- Last update: 07/21/2016 ------------------------------------------------------------------------------- -- Description: SaciMultiPixel Package File ------------------------------------------------------------------------------- diff --git a/protocols/saci/rtl/SaciPrepRdout.vhd b/protocols/saci/rtl/SaciPrepRdout.vhd index 7e15219831..ee0e6ccfd8 100644 --- a/protocols/saci/rtl/SaciPrepRdout.vhd +++ b/protocols/saci/rtl/SaciPrepRdout.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaciPrepRdout.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 07/21/2016 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: The AXI lite master to issue SACI prepare for readout command ------------------------------------------------------------------------------- diff --git a/protocols/saci/rtl/SaciSlave.vhd b/protocols/saci/rtl/SaciSlave.vhd index f00bc727b3..8b0f1e8bae 100644 --- a/protocols/saci/rtl/SaciSlave.vhd +++ b/protocols/saci/rtl/SaciSlave.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaciSlave.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-07-12 --- Last update: 2016-06-17 ------------------------------------------------------------------------------- -- Description: Slave module for SACI interface. ------------------------------------------------------------------------------- diff --git a/protocols/saci/rtl/SaciSlaveOld.vhd b/protocols/saci/rtl/SaciSlaveOld.vhd index fffdb9b57e..612dcdcd38 100644 --- a/protocols/saci/rtl/SaciSlaveOld.vhd +++ b/protocols/saci/rtl/SaciSlaveOld.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaciSlaveOld.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-07-12 --- Last update: 2016-06-17 ------------------------------------------------------------------------------- -- Description: Slave module for SACI interface. Legacy (bloated) version. ------------------------------------------------------------------------------- diff --git a/protocols/saci/sim/AxiLiteSaciMasterTb.vhd b/protocols/saci/sim/AxiLiteSaciMasterTb.vhd index ecc65c2a91..75b35e8588 100644 --- a/protocols/saci/sim/AxiLiteSaciMasterTb.vhd +++ b/protocols/saci/sim/AxiLiteSaciMasterTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLiteSaciMasterTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-06-17 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Simulation testbed for AxiLiteSaciMaster2 ------------------------------------------------------------------------------- diff --git a/protocols/saci/sim/FrontEndSaciAnalogTb.vhd b/protocols/saci/sim/FrontEndSaciAnalogTb.vhd index 96e97720fc..d9aa1a1fdc 100644 --- a/protocols/saci/sim/FrontEndSaciAnalogTb.vhd +++ b/protocols/saci/sim/FrontEndSaciAnalogTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : FrontEndSaciAnalogTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-10-02 --- Last update: 2018-05-16 ------------------------------------------------------------------------------- -- Description: Simple Saci testbench with Saci Master connected to the -- standard Front End Register interface. diff --git a/protocols/saci/sim/FrontEndSaciPkg.vhd b/protocols/saci/sim/FrontEndSaciPkg.vhd index f7d9ca1531..07f1b64670 100644 --- a/protocols/saci/sim/FrontEndSaciPkg.vhd +++ b/protocols/saci/sim/FrontEndSaciPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : FrontEndSaciPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-05-03 --- Last update: 2012-09-26 ------------------------------------------------------------------------------- -- Description: Port types for Generic Front End interface ------------------------------------------------------------------------------- diff --git a/protocols/saci/sim/FrontEndSaciRegDecoder.vhd b/protocols/saci/sim/FrontEndSaciRegDecoder.vhd index c9fdf68f59..faad47626b 100644 --- a/protocols/saci/sim/FrontEndSaciRegDecoder.vhd +++ b/protocols/saci/sim/FrontEndSaciRegDecoder.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : FrontEndSaciRegDecoder.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-05-07 --- Last update: 2018-05-16 ------------------------------------------------------------------------------- -- Description: Decodes register addresses from the Front End interface. ------------------------------------------------------------------------------- diff --git a/protocols/saci/sim/FrontEndSaciTb.vhd b/protocols/saci/sim/FrontEndSaciTb.vhd index aa67a1baee..cf1b463ef7 100644 --- a/protocols/saci/sim/FrontEndSaciTb.vhd +++ b/protocols/saci/sim/FrontEndSaciTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : FrontEndSaciTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-10-02 --- Last update: 2018-05-16 ------------------------------------------------------------------------------- -- Description: Simple Saci testbench with Saci Master connected to the -- standard Front End Register interface. diff --git a/protocols/saci/sim/SaciSlave2.vhd b/protocols/saci/sim/SaciSlave2.vhd index 9615db9aa9..fe4cb4c61a 100644 --- a/protocols/saci/sim/SaciSlave2.vhd +++ b/protocols/saci/sim/SaciSlave2.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaciSlave.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-07-12 --- Last update: 2013-03-05 ------------------------------------------------------------------------------- -- Description: Slave module for SACI interface. ------------------------------------------------------------------------------- diff --git a/protocols/saci/sim/SaciSlaveRam.vhd b/protocols/saci/sim/SaciSlaveRam.vhd index ea53438a19..47f88b436b 100644 --- a/protocols/saci/sim/SaciSlaveRam.vhd +++ b/protocols/saci/sim/SaciSlaveRam.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaciSlaveRam.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2012-09-19 --- Last update: 2013-03-01 ------------------------------------------------------------------------------- -- Description: Simulation testbed for SaciSlaveRam ------------------------------------------------------------------------------- diff --git a/protocols/saci/sim/SaciSlaveWrapper.vhd b/protocols/saci/sim/SaciSlaveWrapper.vhd index d2f838d4cf..a3f163c9d2 100644 --- a/protocols/saci/sim/SaciSlaveWrapper.vhd +++ b/protocols/saci/sim/SaciSlaveWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaciSlaveWrapper.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-06-17 --- Last update: 2016-06-17 ------------------------------------------------------------------------------- -- Description: Simulation testbed for SaciSlaveWrapper ------------------------------------------------------------------------------- diff --git a/protocols/saci/sim/SaciSlaveWrapperAnalog.vhd b/protocols/saci/sim/SaciSlaveWrapperAnalog.vhd index adb2aed7c5..7c523df189 100644 --- a/protocols/saci/sim/SaciSlaveWrapperAnalog.vhd +++ b/protocols/saci/sim/SaciSlaveWrapperAnalog.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaciSlaveWrapperAnalog.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-06-17 --- Last update: 2016-06-17 ------------------------------------------------------------------------------- -- Description: Simulation testbed for SaciSlaveWrapperAnalog ------------------------------------------------------------------------------- diff --git a/protocols/salt/core/rtl/SaltDelayCtrl.vhd b/protocols/salt/core/rtl/SaltDelayCtrl.vhd index 836ecba192..d59bccba64 100644 --- a/protocols/salt/core/rtl/SaltDelayCtrl.vhd +++ b/protocols/salt/core/rtl/SaltDelayCtrl.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaltDelayCtrl.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-06-16 --- Last update: 2016-06-21 ------------------------------------------------------------------------------- -- Description: Wrapper for IDELAYCTRL ------------------------------------------------------------------------------- diff --git a/protocols/salt/core/rtl/SaltPkg.vhd b/protocols/salt/core/rtl/SaltPkg.vhd index 7e09ed4d16..6377b9121f 100644 --- a/protocols/salt/core/rtl/SaltPkg.vhd +++ b/protocols/salt/core/rtl/SaltPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaltPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-01 --- Last update: 2017-11-08 ------------------------------------------------------------------------------- -- Description: SLAC Asynchronous Logic Transceiver (SALT) Package File ------------------------------------------------------------------------------- diff --git a/protocols/salt/core/rtl/SaltRx.vhd b/protocols/salt/core/rtl/SaltRx.vhd index d75b48b4d5..34c9382564 100644 --- a/protocols/salt/core/rtl/SaltRx.vhd +++ b/protocols/salt/core/rtl/SaltRx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaltRx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-01 --- Last update: 2018-01-11 ------------------------------------------------------------------------------- -- Description: SALT RX Engine Module ------------------------------------------------------------------------------- diff --git a/protocols/salt/core/rtl/SaltTx.vhd b/protocols/salt/core/rtl/SaltTx.vhd index 220848463c..b0095e6dcf 100644 --- a/protocols/salt/core/rtl/SaltTx.vhd +++ b/protocols/salt/core/rtl/SaltTx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaltTx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-01 --- Last update: 2018-01-11 ------------------------------------------------------------------------------- -- Description: SALT TX Engine Module ------------------------------------------------------------------------------- @@ -190,7 +188,7 @@ begin end if; -- Update the variable - tKeep := x"000" & rxMaster.tKeep(3 downto 0); + tKeep(15 downto 0) := x"000" & rxMaster.tKeep(3 downto 0); -- State Machine case r.state is @@ -235,7 +233,7 @@ begin -- Mask off tLast for intergap monitoring v.sMaster.tLast := '0'; -- Increment the counters - v.length := r.length + getTKeep(tKeep); + v.length := r.length + getTKeep(tKeep,SSI_SALT_CONFIG_C); v.size := r.size + 1; -- Check for EOF if rxMaster.tLast = '1' then diff --git a/protocols/salt/core/rtl/SaltTxResize.vhd b/protocols/salt/core/rtl/SaltTxResize.vhd index 60bf994a9d..477d57495a 100644 --- a/protocols/salt/core/rtl/SaltTxResize.vhd +++ b/protocols/salt/core/rtl/SaltTxResize.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaltTxResize.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-11-08 --- Last update: 2017-11-08 ------------------------------------------------------------------------------- -- Description: SALT TX Engine Resizer Module ------------------------------------------------------------------------------- diff --git a/protocols/salt/xilinx7/ip/.gitattributes b/protocols/salt/xilinx7/ip/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/protocols/salt/xilinx7/ip/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/protocols/salt/xilinx7/rtl/Salt7Series.vhd b/protocols/salt/xilinx7/rtl/Salt7Series.vhd index 1c462ab30b..ee4d212f7f 100644 --- a/protocols/salt/xilinx7/rtl/Salt7Series.vhd +++ b/protocols/salt/xilinx7/rtl/Salt7Series.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Salt7Series.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-06-15 --- Last update: 2017-12-22 ------------------------------------------------------------------------------- -- Description: SLAC Asynchronous Logic Transceiver (SALT) 7-series Core ------------------------------------------------------------------------------- diff --git a/protocols/salt/xilinx7/tb/Salt7SeriesTb.vhd b/protocols/salt/xilinx7/tb/Salt7SeriesTb.vhd index 8b6365aa0f..041aa39921 100644 --- a/protocols/salt/xilinx7/tb/Salt7SeriesTb.vhd +++ b/protocols/salt/xilinx7/tb/Salt7SeriesTb.vhd @@ -2,8 +2,6 @@ -- File : Salt7SeriesTb.vhd -- Author : Larry Ruckman -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-03 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the Salt7Series ------------------------------------------------------------------------------- diff --git a/protocols/salt/xilinxUltraScale/images/.gitattributes b/protocols/salt/xilinxUltraScale/images/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/protocols/salt/xilinxUltraScale/images/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/protocols/salt/xilinxUltraScale/ip/.gitattributes b/protocols/salt/xilinxUltraScale/ip/.gitattributes deleted file mode 100644 index ad0d5eb77a..0000000000 --- a/protocols/salt/xilinxUltraScale/ip/.gitattributes +++ /dev/null @@ -1 +0,0 @@ -*.dcp filter=lfs diff=lfs merge=lfs -text \ No newline at end of file diff --git a/protocols/salt/xilinxUltraScale/rtl/SaltUltraScale.vhd b/protocols/salt/xilinxUltraScale/rtl/SaltUltraScale.vhd index c7547f2450..48d11dccca 100644 --- a/protocols/salt/xilinxUltraScale/rtl/SaltUltraScale.vhd +++ b/protocols/salt/xilinxUltraScale/rtl/SaltUltraScale.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaltUltraScale.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-06-15 --- Last update: 2017-12-22 ------------------------------------------------------------------------------- -- Description: SLAC Asynchronous Logic Transceiver (SALT) UltraScale Core ------------------------------------------------------------------------------- diff --git a/protocols/salt/xilinxUltraScale/tb/SaltUltraScaleTb.vhd b/protocols/salt/xilinxUltraScale/tb/SaltUltraScaleTb.vhd index a457b3de97..9bafab4998 100644 --- a/protocols/salt/xilinxUltraScale/tb/SaltUltraScaleTb.vhd +++ b/protocols/salt/xilinxUltraScale/tb/SaltUltraScaleTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SaltUltraScaleTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-09-03 --- Last update: 2018-01-11 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the SaltUltraScale ------------------------------------------------------------------------------- diff --git a/protocols/spi/rtl/AxiSpiMaster.vhd b/protocols/spi/rtl/AxiSpiMaster.vhd index c46dfb68f2..42776fbcda 100644 --- a/protocols/spi/rtl/AxiSpiMaster.vhd +++ b/protocols/spi/rtl/AxiSpiMaster.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiSpiMaster.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-01-12 --- Last update: 2018-02-01 ------------------------------------------------------------------------------- -- Description: Axi lite interface for a single chip "generic SPI master" -- For multiple chips on single bus connect multiple cores diff --git a/protocols/spi/rtl/SpiMaster.vhd b/protocols/spi/rtl/SpiMaster.vhd index a62814ad5c..22233a0e28 100644 --- a/protocols/spi/rtl/SpiMaster.vhd +++ b/protocols/spi/rtl/SpiMaster.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SpiMaster.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2013-05-24 --- Last update: 2016-12-06 ------------------------------------------------------------------------------- -- Description: Generic SPI Master Module ------------------------------------------------------------------------------- @@ -33,21 +31,22 @@ entity SpiMaster is SPI_SCLK_PERIOD_G : real := 1.0E-6); -- 1 MHz port ( --Global Signals - clk : in sl; - sRst : in sl; + clk : in sl; + sRst : in sl; -- Parallel interface - chipSel : in slv(log2(NUM_CHIPS_G)-1 downto 0); - wrEn : in sl; - wrData : in slv(DATA_SIZE_G-1 downto 0); - dataSize : in slv(log2(DATA_SIZE_G)-1 downto 0) := toSlv(DATA_SIZE_G-1, log2(DATA_SIZE_G)); - rdEn : out sl; - rdData : out slv(DATA_SIZE_G-1 downto 0); + freeRunClk : in sl := '0'; + chipSel : in slv(log2(NUM_CHIPS_G)-1 downto 0); + wrEn : in sl; + wrData : in slv(DATA_SIZE_G-1 downto 0); + dataSize : in slv(log2(DATA_SIZE_G)-1 downto 0) := toSlv(DATA_SIZE_G-1, log2(DATA_SIZE_G)); + rdEn : out sl; + rdData : out slv(DATA_SIZE_G-1 downto 0); shiftCount : out slv(bitSize(DATA_SIZE_G)-1 downto 0); --SPI interface - spiCsL : out slv(NUM_CHIPS_G-1 downto 0); - spiSclk : out sl; - spiSdi : out sl; - spiSdo : in sl); + spiCsL : out slv(NUM_CHIPS_G-1 downto 0); + spiSclk : out sl; + spiSdi : out sl; + spiSdo : in sl); end SpiMaster; architecture rtl of SpiMaster is @@ -59,6 +58,7 @@ architecture rtl of SpiMaster is -- Types type StateType is ( IDLE_S, + FREE_RUNNING_CLK_S, SHIFT_S, SAMPLE_S, DONE_S); @@ -96,101 +96,150 @@ begin spiSdoRes <= to_x01z(spiSdo); - comb : process (chipSel, dataSize, r, sRst, spiSdoRes, wrData, wrEn) is + comb : process (chipSel, dataSize, freeRunClk, r, sRst, spiSdoRes, wrData, + wrEn) is variable v : RegType; begin + -- Latch the current value v := r; + -- State Machine case (r.state) is + ---------------------------------------------------------------------- when IDLE_S => - + -- Reset the signals v.spiSclk := CPOL_G; v.spiSdi := '0'; v.dataCounter := (others => '0'); v.sclkCounter := (others => '0'); v.rdEn := '1'; -- rdEn always valid between txns, indicates ready for next txn - + -- Check for the start of a transaction if (wrEn = '1') then + -- Setup for the SPI transaction v.rdEn := '0'; v.wrData := wrData; v.rdData := (others => '0'); v.spiCsL := not (decode(chipSel)(NUM_CHIPS_G-1 downto 0)); - + -- Check if rising edge sampling if (CPHA_G = '0') then -- Sample on first sclk edge so shift here before that happens v.spiSdi := wrData(DATA_SIZE_G-1); v.wrData := wrData(DATA_SIZE_G-2 downto 0) & '0'; + -- Next state v.state := SAMPLE_S; else + -- Next state v.state := SHIFT_S; end if; + -- Check if free running the SCLK between commands + elsif (freeRunClk = '1') then + -- Next state + v.state := FREE_RUNNING_CLK_S; end if; - + ---------------------------------------------------------------------- + when FREE_RUNNING_CLK_S => + -- Wait half a clock period then shift out the next data bit + v.sclkCounter := r.sclkCounter + 1; + -- Check for max count + if (r.sclkCounter = SPI_CLK_PERIOD_DIV2_CYCLES_C) then + -- Reset the counter + v.sclkCounter := (others => '0'); + -- Toggle the clock + v.spiSclk := not(r.spiSclk); + -- Check if next cycle in phase of IDLE + if (v.spiSclk = CPOL_G) then + -- Next state + v.state := IDLE_S; + end if; + end if; + ---------------------------------------------------------------------- when SHIFT_S => -- Wait half a clock period then shift out the next data bit v.sclkCounter := r.sclkCounter + 1; + -- Check for max count if (r.sclkCounter = SPI_CLK_PERIOD_DIV2_CYCLES_C) then + -- Reset the counter v.sclkCounter := (others => '0'); - v.spiSclk := not r.spiSclk; + -- Toggle the clock + v.spiSclk := not(r.spiSclk); + -- Shift the data v.spiSdi := r.wrData(DATA_SIZE_G-1); v.wrData := r.wrData(DATA_SIZE_G-2 downto 0) & '0'; + -- Next state (default) v.state := SAMPLE_S; - + -- Check if rising edge sampling if (CPHA_G = '0') then + -- Increment the counter v.dataCounter := r.dataCounter + 1; + -- Check if last bit sent if (r.dataCounter = dataSize) then + -- Next state v.state := DONE_S; end if; end if; end if; - + ---------------------------------------------------------------------- when SAMPLE_S => -- Wait half a clock period then sample the next data bit v.sclkCounter := r.sclkCounter + 1; + -- Check for max count if (r.sclkCounter = SPI_CLK_PERIOD_DIV2_CYCLES_C) then + -- Reset the counter v.sclkCounter := (others => '0'); - v.spiSclk := not r.spiSclk; + -- Toggle the clock + v.spiSclk := not(r.spiSclk); + -- Shift the data v.rdData := r.rdData(DATA_SIZE_G-2 downto 0) & spiSdoRes; + -- Next state (default) v.state := SHIFT_S; - + -- Check if falling edge sampling if (CPHA_G = '1') then + -- Increment the counter v.dataCounter := r.dataCounter + 1; + -- Check if last bit sent if (r.dataCounter = dataSize) then + -- Next state v.state := DONE_S; end if; end if; end if; - + ---------------------------------------------------------------------- when DONE_S => -- Assert rdEn after half a SPI clk period -- Go back to idle after one SPI clk period -- Otherwise back to back operations happen too fast. v.sclkCounter := r.sclkCounter + 1; + -- Check for max count if (r.sclkCounter = SPI_CLK_PERIOD_DIV2_CYCLES_C) then + -- Reset the counter v.sclkCounter := (others => '0'); + -- De-assert the chip select bus v.spiCsL := (others => '1'); - + -- Check if falling edge sampling if (r.spiCsL = slvOne(NUM_CHIPS_G)) then + -- Next state v.state := IDLE_S; end if; end if; - when others => null; + ---------------------------------------------------------------------- end case; + -- Outputs + spiSclk <= r.spiSclk; + spiSdi <= r.spiSdi; + spiCsL <= r.spiCsL; + rdEn <= r.rdEn; + rdData <= r.rdData; + shiftCount <= r.dataCounter; + + -- Reset if (sRst = '1') then v := REG_INIT_C; end if; + -- Register the variable for next clock cycle rin <= v; - spiSclk <= r.spiSclk; - spiSdi <= r.spiSdi; - spiCsL <= r.spiCsL; - - rdEn <= r.rdEn; - rdData <= r.rdData; - shiftCount <= r.dataCounter; - end process comb; seq : process (clk) is diff --git a/protocols/spi/rtl/SpiSlave.vhd b/protocols/spi/rtl/SpiSlave.vhd index 6dae82593a..6ec31c76c5 100644 --- a/protocols/spi/rtl/SpiSlave.vhd +++ b/protocols/spi/rtl/SpiSlave.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SpiSlave.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-01-27 --- Last update: 2014-03-14 ------------------------------------------------------------------------------- -- Description: Generic SPI Slave Module ------------------------------------------------------------------------------- diff --git a/protocols/srp/rtl/AxiLiteSrpV0.vhd b/protocols/srp/rtl/AxiLiteSrpV0.vhd index 550430124d..412465017a 100644 --- a/protocols/srp/rtl/AxiLiteSrpV0.vhd +++ b/protocols/srp/rtl/AxiLiteSrpV0.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLiteSrpV0.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-09 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: SLAC Register Protocol Version 0, AXI-Lite Interface -- @@ -213,7 +211,7 @@ begin v.txFifoAxisMaster.tData(63 downto 62) := "01"; v.txFifoAxisMaster.tData(95 downto 64) := sAxilWriteMaster.wdata(31 downto 0); v.txFifoAxisMaster.tData(127 downto 96) := (others => '0'); - v.txFifoAxisMaster.tKeep := X"FFFF"; + v.txFifoAxisMaster.tKeep(15 downto 0) := X"FFFF"; v.txFifoAxisMaster.tValid := '1'; v.txFifoAxisMaster.tLast := '1'; ssiSetUserSof(INTERNAL_AXIS_CFG_C, v.txFifoAxisMaster, '1'); @@ -224,7 +222,7 @@ begin v.txFifoAxisMaster.tData(63 downto 62) := "00"; v.txFifoAxisMaster.tData(95 downto 64) := (others => '0'); v.txFifoAxisMaster.tData(127 downto 96) := (others => '0'); - v.txFifoAxisMaster.tKeep := X"FFFF"; + v.txFifoAxisMaster.tKeep(15 downto 0) := X"FFFF"; v.txFifoAxisMaster.tValid := '1'; v.txFifoAxisMaster.tLast := '1'; ssiSetUserSof(INTERNAL_AXIS_CFG_C, v.txFifoAxisMaster, '1'); @@ -244,7 +242,7 @@ begin rxFifoAxisMaster.tData(63 downto 62) = "01" and rxFifoAxisMaster.tData(95 downto 64) = sAxilWriteMaster.wdata and rxFifoAxisMaster.tData(127 downto 96) = 0 and - rxFifoAxisMaster.tKeep = X"FFFF" and + rxFifoAxisMaster.tKeep(15 downto 0) = X"FFFF" and rxFifoAxisMaster.tLast = '1' and ssiGetUserSof(INTERNAL_AXIS_CFG_C, rxFifoAxisMaster) = '1') then @@ -264,7 +262,7 @@ begin rxFifoAxisMaster.tData(61 downto 32) = sAxilReadMaster.araddr(31 downto 2) and rxFifoAxisMaster.tData(63 downto 62) = "00" and rxFifoAxisMaster.tData(127 downto 96) = 0 and - rxFifoAxisMaster.tKeep = X"FFFF" and + rxFifoAxisMaster.tKeep(15 downto 0) = X"FFFF" and rxFifoAxisMaster.tLast = '1' and ssiGetUserSof(INTERNAL_AXIS_CFG_C, rxFifoAxisMaster) = '1') then diff --git a/protocols/srp/rtl/SrpV0AxiLite.vhd b/protocols/srp/rtl/SrpV0AxiLite.vhd index ad538b03d4..9d5a73d681 100644 --- a/protocols/srp/rtl/SrpV0AxiLite.vhd +++ b/protocols/srp/rtl/SrpV0AxiLite.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SrpV0AxiLite.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-09 --- Last update: 2016-05-11 ------------------------------------------------------------------------------- -- Description: SLAC Register Protocol Version 0, AXI-Lite Interface -- diff --git a/protocols/srp/rtl/SrpV3Axi.vhd b/protocols/srp/rtl/SrpV3Axi.vhd index 5c35fdb54d..b1f0e9bc13 100644 --- a/protocols/srp/rtl/SrpV3Axi.vhd +++ b/protocols/srp/rtl/SrpV3Axi.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SrpV3Axi.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-04-14 --- Last update: 2016-05-04 ------------------------------------------------------------------------------- -- Description: SLAC Register Protocol Version 3, AXI Interface -- @@ -41,7 +39,7 @@ entity SrpV3Axi is ALTERA_SYN_G : boolean := false; ALTERA_RAM_G : string := "M9K"; AXI_CLK_FREQ_G : real := 156.25E+6; -- units of Hz - AXI_CONFIG_G : AxiConfigType := (33, 4, 1, 8); + AXI_CONFIG_G : AxiConfigType := axiConfig(33, 4, 1, 8); AXI_BURST_G : slv(1 downto 0) := "01"; AXI_CACHE_G : slv(3 downto 0) := "1111"; ACK_WAIT_BVALID_G : boolean := true; @@ -199,6 +197,7 @@ begin v.wrDmaReq.request := srpReq.request and toSl(srpReq.opcode = SRP_WRITE_C or srpReq.opcode = SRP_POSTED_WRITE_C) and not addrError; v.wrDmaReq.address := srpReq.addr; + v.wrDmaReq.prot := srpReq.prot; -- This helps the DMA engines trim their unaligned access logic if (UNALIGNED_ACCESS_G = false and BYTE_ACCESS_G = false) then v.wrDmaReq.address(1 downto 0) := (others => '0'); @@ -207,6 +206,7 @@ begin v.rdDmaReq.request := srpReq.request and toSl(srpReq.opcode = SRP_READ_C) and not addrError; v.rdDmaReq.address := srpReq.addr; + v.rdDmaReq.prot := srpReq.prot; if (UNALIGNED_ACCESS_G = false and BYTE_ACCESS_G = false) then v.rdDmaReq.address(1 downto 0) := (others => '0'); end if; diff --git a/protocols/srp/rtl/SrpV3AxiLite.vhd b/protocols/srp/rtl/SrpV3AxiLite.vhd index 245ee38292..57511852ef 100644 --- a/protocols/srp/rtl/SrpV3AxiLite.vhd +++ b/protocols/srp/rtl/SrpV3AxiLite.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SrpV3AxiLite.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-03-22 --- Last update: 2018-05-16 ------------------------------------------------------------------------------- -- Description: SLAC Register Protocol Version 3, AXI-Lite Interface -- @@ -95,6 +93,7 @@ architecture rtl of SrpV3AxiLite is hdrCnt : slv(3 downto 0); remVer : slv(7 downto 0); opCode : slv(1 downto 0); + prot : slv(2 downto 0); timeoutSize : slv(7 downto 0); timeoutCnt : slv(7 downto 0); tid : slv(31 downto 0); @@ -124,6 +123,7 @@ architecture rtl of SrpV3AxiLite is hdrCnt => (others => '0'), remVer => (others => '0'), opCode => (others => '0'), + prot => (others => '0'), timeoutSize => (others => '0'), timeoutCnt => (others => '0'), tid => (others => '0'), @@ -347,6 +347,7 @@ begin v.remVer := rxMaster.tData(7 downto 0); v.opCode := rxMaster.tData(9 downto 8); v.ignoreMemResp := rxMaster.tData(14); + v.prot := rxMaster.tData(23 downto 21); v.timeoutSize := rxMaster.tData(31 downto 24); -- Reset other header fields v.tid := (others => '0'); @@ -470,7 +471,8 @@ begin v.txMaster.tData(12) := '0'; -- WriteEn: 0 = write operations are not supported v.txMaster.tData(13) := '0'; -- ReadEn: 0 = read operations are not supported v.txMaster.tData(14) := r.ignoreMemResp; - v.txMaster.tData(23 downto 15) := (others => '0'); -- Reserved + v.txMaster.tData(20 downto 15) := (others => '0'); -- Reserved + v.txMaster.tData(23 downto 21) := r.prot; v.txMaster.tData(31 downto 24) := r.timeoutSize; when x"1" => v.txMaster.tData(31 downto 0) := r.tid(31 downto 0); when x"2" => v.txMaster.tData(31 downto 0) := r.addr(31 downto 0); @@ -575,6 +577,8 @@ begin -- Start AXI-Lite transaction v.mAxilReadMaster.arvalid := '1'; v.mAxilReadMaster.rready := '1'; + -- Update the Protection control + v.mAxilReadMaster.arprot := r.prot; -- Reset the timer v.timer := 0; v.timeoutCnt := (others => '0'); @@ -680,6 +684,8 @@ begin v.mAxilWriteMaster.awvalid := '1'; v.mAxilWriteMaster.wvalid := '1'; v.mAxilWriteMaster.bready := '1'; + -- Update the Protection control + v.mAxilWriteMaster.awprot := r.prot; -- Reset the timer v.timer := 0; v.timeoutCnt := (others => '0'); diff --git a/protocols/srp/rtl/SrpV3AxiLiteFull.vhd b/protocols/srp/rtl/SrpV3AxiLiteFull.vhd index 28fc991bd2..b57c9511be 100644 --- a/protocols/srp/rtl/SrpV3AxiLiteFull.vhd +++ b/protocols/srp/rtl/SrpV3AxiLiteFull.vhd @@ -1,16 +1,11 @@ ------------------------------------------------------------------------------- --- File : SrpV3AxiLite.vhd +-- File : SrpV3AxiLiteFull.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-03-22 --- Last update: 2016-04-25 ------------------------------------------------------------------------------- -- Description: SLAC Register Protocol Version 3, AXI-Lite Interface -- -- Documentation: https://confluence.slac.stanford.edu/x/cRmVD -- --- Note: This module only supports 32-bit aligned addresses and 32-bit transactions. --- For non 32-bit aligned addresses or non 32-bit transactions, use --- the SrpV3Axi.vhd module with the AxiToAxiLite.vhd bridge ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the @@ -85,7 +80,7 @@ begin ALTERA_SYN_G => ALTERA_SYN_G, ALTERA_RAM_G => ALTERA_RAM_G, AXI_CLK_FREQ_G => AXIL_CLK_FREQ_G, - AXI_CONFIG_G => (32, 4, 1, 0), + AXI_CONFIG_G => axiConfig(32, 4, 1, 0), -- AXI_BURST_G => AXI_BURST_G, -- AXI_CACHE_G => AXI_CACHE_G, -- ACK_WAIT_BVALID_G => ACK_WAIT_BVALID_G, diff --git a/protocols/srp/rtl/SrpV3Core.vhd b/protocols/srp/rtl/SrpV3Core.vhd index 978f0832ad..e8b01c3899 100644 --- a/protocols/srp/rtl/SrpV3Core.vhd +++ b/protocols/srp/rtl/SrpV3Core.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SrpV3Core.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-03-22 --- Last update: 2016-11-07 ------------------------------------------------------------------------------- -- Description: SLAC Register Protocol Version 3, AXI-Lite Interface -- @@ -331,7 +329,8 @@ begin v.txMaster.tDest := rxMaster.tDest; v.srpReq.remVer := rxMaster.tData(7 downto 0); v.srpReq.opCode := rxMaster.tData(9 downto 8); - v.srpReq.spare := rxMaster.tData(23 downto 10); + v.srpReq.spare := rxMaster.tData(20 downto 10); + v.srpReq.prot := rxMaster.tData(23 downto 21); v.timeoutSize := rxMaster.tData(31 downto 24); when X"1" => v.srpReq.tid(31 downto 0) := rxMaster.tData(31 downto 0); @@ -387,7 +386,8 @@ begin -- Set data bus v.txMaster.tData(7 downto 0) := SRP_VERSION_C; v.txMaster.tData(9 downto 8) := r.srpReq.opCode; - v.txMaster.tData(23 downto 10) := r.srpReq.spare; + v.txMaster.tData(20 downto 10) := r.srpReq.spare; + v.txMaster.tData(23 downto 21) := r.srpReq.prot; v.txMaster.tData(31 downto 24) := r.timeoutSize; when x"1" => v.txMaster.tData(31 downto 0) := r.srpReq.tid(31 downto 0); diff --git a/protocols/srp/rtl/SrpV3Pkg.vhd b/protocols/srp/rtl/SrpV3Pkg.vhd index cfe0c58b0e..2162fbbc89 100644 --- a/protocols/srp/rtl/SrpV3Pkg.vhd +++ b/protocols/srp/rtl/SrpV3Pkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SrpV3Pkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-04-19 --- Last update: 2016-05-04 ------------------------------------------------------------------------------- -- Description: SRPv3 Package File ------------------------------------------------------------------------------- @@ -45,7 +43,8 @@ package SrpV3Pkg is request : sl; remVer : slv(7 downto 0); opCode : slv(1 downto 0); - spare : slv(13 downto 0); + spare : slv(10 downto 0); + prot : slv(2 downto 0); tid : slv(31 downto 0); addr : slv(63 downto 0); reqSize : slv(31 downto 0); @@ -56,6 +55,7 @@ package SrpV3Pkg is remVer => (others => '0'), opCode => (others => '0'), spare => (others => '0'), + prot => (others => '0'), tid => (others => '0'), addr => (others => '0'), reqSize => (others => '0')); diff --git a/protocols/srp/tb/AxiLiteSrpV0Tb.vhd b/protocols/srp/tb/AxiLiteSrpV0Tb.vhd index d4c9fb5f96..40d238cb1f 100644 --- a/protocols/srp/tb/AxiLiteSrpV0Tb.vhd +++ b/protocols/srp/tb/AxiLiteSrpV0Tb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : AxiLiteSrpV0Tb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-06-08 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Simulation testbed for AxiLiteSrpV0 ------------------------------------------------------------------------------- diff --git a/protocols/srp/tb/SrpV3AxiLiteTb.vhd b/protocols/srp/tb/SrpV3AxiLiteTb.vhd index cb3d594241..9917d765c1 100644 --- a/protocols/srp/tb/SrpV3AxiLiteTb.vhd +++ b/protocols/srp/tb/SrpV3AxiLiteTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SrpV3AxiLiteTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-06-18 --- Last update: 2018-01-22 ------------------------------------------------------------------------------- -- Description: Simulation testbed for AxiLiteSrpV0 ------------------------------------------------------------------------------- @@ -248,7 +246,7 @@ begin v.sAxisMaster.tData(11 downto 0) := r.reqSize; v.sAxisMaster.tData(127 downto 12) := (others => '0'); v.sAxisMaster.tLast := '1'; - v.sAxisMaster.tKeep := x"000F"; + v.sAxisMaster.tKeep(15 downto 0) := x"000F"; v.tid := r.tid + 1; v.addr := r.addr + 4; v.reqSize := r.reqSize + 4; diff --git a/protocols/ssi/rtl/SsiAxiLiteMaster.vhd b/protocols/ssi/rtl/SsiAxiLiteMaster.vhd index bd3a50637f..b166908d0e 100644 --- a/protocols/ssi/rtl/SsiAxiLiteMaster.vhd +++ b/protocols/ssi/rtl/SsiAxiLiteMaster.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiAxiLiteMaster.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-09 --- Last update: 2015-05-29 ------------------------------------------------------------------------------- -- Description: -- Block for Register protocol. diff --git a/protocols/ssi/rtl/SsiCmdMaster.vhd b/protocols/ssi/rtl/SsiCmdMaster.vhd index 804170baf2..995b249832 100644 --- a/protocols/ssi/rtl/SsiCmdMaster.vhd +++ b/protocols/ssi/rtl/SsiCmdMaster.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiCmdMaster.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-09 --- Last update: 2015-06-23 ------------------------------------------------------------------------------- -- Description: -- Block for Command protocol over the VC. diff --git a/protocols/ssi/rtl/SsiCmdMasterPkg.vhd b/protocols/ssi/rtl/SsiCmdMasterPkg.vhd index 76757f6124..af042ea47a 100644 --- a/protocols/ssi/rtl/SsiCmdMasterPkg.vhd +++ b/protocols/ssi/rtl/SsiCmdMasterPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiCmdMasterPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-25 --- Last update: 2014-04-30 ------------------------------------------------------------------------------- -- Description: SSI Command Master Pulser Module Package File ------------------------------------------------------------------------------- diff --git a/protocols/ssi/rtl/SsiCmdMasterPulser.vhd b/protocols/ssi/rtl/SsiCmdMasterPulser.vhd index 630e56e8ae..5467e4fc24 100644 --- a/protocols/ssi/rtl/SsiCmdMasterPulser.vhd +++ b/protocols/ssi/rtl/SsiCmdMasterPulser.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiCmdMasterPulser.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-01-30 --- Last update: 2014-05-15 ------------------------------------------------------------------------------- -- Description: SSI Command Master Pulser Module ------------------------------------------------------------------------------- diff --git a/protocols/ssi/rtl/SsiDbgTap.vhd b/protocols/ssi/rtl/SsiDbgTap.vhd index c42b3b3b8a..231d80a27f 100644 --- a/protocols/ssi/rtl/SsiDbgTap.vhd +++ b/protocols/ssi/rtl/SsiDbgTap.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiDbgTap.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-06-18 --- Last update: 2017-06-18 ------------------------------------------------------------------------------- -- Description: SSI debug tap, intended to be connect to chipscope for debugging ------------------------------------------------------------------------------- diff --git a/protocols/ssi/rtl/SsiFifo.vhd b/protocols/ssi/rtl/SsiFifo.vhd index de470c8958..bad11511a2 100644 --- a/protocols/ssi/rtl/SsiFifo.vhd +++ b/protocols/ssi/rtl/SsiFifo.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiFifo.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-02 --- Last update: 2016-10-17 ------------------------------------------------------------------------------- -- Description: This module is the AXIS FIFO with a frame filter -- diff --git a/protocols/ssi/rtl/SsiFrameLimiter.vhd b/protocols/ssi/rtl/SsiFrameLimiter.vhd index 07e67997e2..ca6f3ec643 100644 --- a/protocols/ssi/rtl/SsiFrameLimiter.vhd +++ b/protocols/ssi/rtl/SsiFrameLimiter.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiFrameLimiter.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-05-20 --- Last update: 2018-05-15 ------------------------------------------------------------------------------- -- Description: Limits the amount of data being sent across a SSI AXIS bus ------------------------------------------------------------------------------- diff --git a/protocols/ssi/rtl/SsiIbFrameFilter.vhd b/protocols/ssi/rtl/SsiIbFrameFilter.vhd index 9086c812df..690bbd6e74 100644 --- a/protocols/ssi/rtl/SsiIbFrameFilter.vhd +++ b/protocols/ssi/rtl/SsiIbFrameFilter.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiIbFrameFilter.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-02 --- Last update: 2017-06-01 ------------------------------------------------------------------------------- -- Description: This module is used to filter out bad SSI frames. -- diff --git a/protocols/ssi/rtl/SsiIncrementingTx.vhd b/protocols/ssi/rtl/SsiIncrementingTx.vhd index 23a8dd9c33..17ef41c1b9 100644 --- a/protocols/ssi/rtl/SsiIncrementingTx.vhd +++ b/protocols/ssi/rtl/SsiIncrementingTx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiIncrementingTx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-02 --- Last update: 2014-07-18 ------------------------------------------------------------------------------- -- Description: This module generates -- PseudoRandom Binary Sequence (INCREMENTING) on Virtual Channel Lane. diff --git a/protocols/ssi/rtl/SsiInsertSof.vhd b/protocols/ssi/rtl/SsiInsertSof.vhd index fd1921c545..5aa2dedf53 100644 --- a/protocols/ssi/rtl/SsiInsertSof.vhd +++ b/protocols/ssi/rtl/SsiInsertSof.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiInsertSof.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-08-18 --- Last update: 2015-10-23 ------------------------------------------------------------------------------- -- Description: Inserts the SOF for converting a generic AXIS into a SSI bus ------------------------------------------------------------------------------- @@ -27,7 +25,7 @@ use work.SsiPkg.all; entity SsiInsertSof is generic ( TPD_G : time := 1 ns; - TUSER_MASK_G : slv(127 downto 0) := (others => '1'); -- '1' = masked off bit + TUSER_MASK_G : slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0) := (others => '1'); -- '1' = masked off bit COMMON_CLK_G : boolean := false; -- True if sAxisClk and mAxisClk are the same clock INSERT_USER_HDR_G : boolean := false; -- If True the module adds one user header word (mUserHdr = user header data) SLAVE_FIFO_G : boolean := true; @@ -43,7 +41,7 @@ entity SsiInsertSof is -- Master Port mAxisClk : in sl; mAxisRst : in sl; - mUserHdr : in slv(127 downto 0) := (others => '0'); + mUserHdr : in slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0) := (others => '0'); mAxisMaster : out AxiStreamMasterType; mAxisSlave : in AxiStreamSlaveType); end SsiInsertSof; @@ -135,7 +133,7 @@ begin -- Move the data v.txMaster := rxMaster; -- Mask off the TUSER bits - for i in 127 downto 0 loop + for i in AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0 loop if TUSER_MASK_G(i) = '1' then v.txMaster.tUser(i) := '0'; end if; @@ -168,7 +166,7 @@ begin -- Move the data v.txMaster := rxMaster; -- Mask off the TUSER bits - for i in 127 downto 0 loop + for i in AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0 loop if TUSER_MASK_G(i) = '1' then v.txMaster.tUser(i) := '0'; end if; diff --git a/protocols/ssi/rtl/SsiObFrameFilter.vhd b/protocols/ssi/rtl/SsiObFrameFilter.vhd index 8121c0d688..4787019b22 100644 --- a/protocols/ssi/rtl/SsiObFrameFilter.vhd +++ b/protocols/ssi/rtl/SsiObFrameFilter.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiObFrameFilter.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-05-02 --- Last update: 2017-06-01 ------------------------------------------------------------------------------- -- Description: This module is used to filter out bad SSI frames. -- diff --git a/protocols/ssi/rtl/SsiPkg.vhd b/protocols/ssi/rtl/SsiPkg.vhd index d12406efe5..5d54d445b6 100644 --- a/protocols/ssi/rtl/SsiPkg.vhd +++ b/protocols/ssi/rtl/SsiPkg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiPkg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-25 --- Last update: 2016-05-04 ------------------------------------------------------------------------------- -- Description: SSI Package File ------------------------------------------------------------------------------- @@ -25,13 +23,13 @@ use work.AxiStreamPkg.all; package SsiPkg is - constant SSI_EOFE_C : integer := 0; - constant SSI_SOF_C : integer := 1; + constant SSI_EOFE_C : natural := 0; + constant SSI_SOF_C : natural := 1; - constant SSI_TUSER_BITS_C : integer := 2; - constant SSI_TDEST_BITS_C : integer := 4; - constant SSI_TID_BITS_C : integer := 0; - constant SSI_TSTRB_EN_C : boolean := false; + constant SSI_TUSER_BITS_C : positive := 2; + constant SSI_TDEST_BITS_C : positive := 4; + constant SSI_TID_BITS_C : natural := 0; + constant SSI_TSTRB_EN_C : boolean := false; constant SSI_MASTER_FORCE_EOFE_C : AxiStreamMasterType := ( tValid => '1', -- Force @@ -41,17 +39,17 @@ package SsiPkg is tLast => '1', -- EOF tDest => (others => '0'), tId => (others => '0'), - tUser => x"01010101010101010101010101010101"); -- EOFE + tUser => (others => '1')); -- EOFE ------------------------------------------------------------------------------------------------- -- Build an SSI configuration ------------------------------------------------------------------------------------------------- function ssiAxiStreamConfig ( - dataBytes : natural; - tKeepMode : TKeepModeType := TKEEP_COMP_C; - tUserMode : TUserModeType := TUSER_FIRST_LAST_C; - tDestBits : integer range 0 to 8 := 4; - tUserBits : integer range 2 to 8 := 2) + dataBytes : positive; + tKeepMode : TKeepModeType := TKEEP_COMP_C; + tUserMode : TUserModeType := TUSER_FIRST_LAST_C; + tDestBits : natural range 0 to 8 := 4; + tUserBits : positive range 2 to 8 := 2) return AxiStreamConfigType; -- A default SSI config is useful to have @@ -62,9 +60,9 @@ package SsiPkg is ------------------------------------------------------------------------------------------------- type SsiMasterType is record valid : sl; - data : slv(127 downto 0); - strb : slv(15 downto 0); - keep : slv(15 downto 0); + data : slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0); + strb : slv(AXI_STREAM_MAX_TKEEP_WIDTH_C-1 downto 0); + keep : slv(AXI_STREAM_MAX_TKEEP_WIDTH_C-1 downto 0); dest : slv(SSI_TDEST_BITS_C-1 downto 0); packed : sl; sof : sl; @@ -145,11 +143,11 @@ end package SsiPkg; package body SsiPkg is function ssiAxiStreamConfig ( - dataBytes : natural; - tKeepMode : TKeepModeType := TKEEP_COMP_C; - tUserMode : TUserModeType := TUSER_FIRST_LAST_C; - tDestBits : integer range 0 to 8 := 4; - tUserBits : integer range 2 to 8 := 2) + dataBytes : positive; + tKeepMode : TKeepModeType := TKEEP_COMP_C; + tUserMode : TUserModeType := TUSER_FIRST_LAST_C; + tDestBits : natural range 0 to 8 := 4; + tUserBits : positive range 2 to 8 := 2) return AxiStreamConfigType is variable ret : AxiStreamConfigType; begin diff --git a/protocols/ssi/rtl/SsiPrbsRateGen.vhd b/protocols/ssi/rtl/SsiPrbsRateGen.vhd index 884abee19a..2d5f2260cf 100644 --- a/protocols/ssi/rtl/SsiPrbsRateGen.vhd +++ b/protocols/ssi/rtl/SsiPrbsRateGen.vhd @@ -1,7 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiPrbsRateGen.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2017-04-28 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- diff --git a/protocols/ssi/rtl/SsiPrbsRx.vhd b/protocols/ssi/rtl/SsiPrbsRx.vhd index 9e0012261f..20ee0613ff 100644 --- a/protocols/ssi/rtl/SsiPrbsRx.vhd +++ b/protocols/ssi/rtl/SsiPrbsRx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiPrbsRx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-02 --- Last update: 2018-06-12 ------------------------------------------------------------------------------- -- Description: This module generates -- PseudoRandom Binary Sequence (PRBS) on Virtual Channel Lane. @@ -43,13 +41,11 @@ entity SsiPrbsRx is FIFO_ADDR_WIDTH_G : positive := 9; FIFO_PAUSE_THRESH_G : positive := 2**8; -- PRBS Config - PRBS_SEED_SIZE_G : positive range 32 to 128 := 32; + PRBS_SEED_SIZE_G : positive range 32 to 256 := 32; PRBS_TAPS_G : NaturalArray := (0 => 31, 1 => 6, 2 => 2, 3 => 1); -- AXI Stream IO Config SLAVE_AXI_STREAM_CONFIG_G : AxiStreamConfigType := ssiAxiStreamConfig(4); - SLAVE_AXI_PIPE_STAGES_G : natural range 0 to 16 := 0; - MASTER_AXI_STREAM_CONFIG_G : AxiStreamConfigType := ssiAxiStreamConfig(4); - MASTER_AXI_PIPE_STAGES_G : natural range 0 to 16 := 0); + SLAVE_AXI_PIPE_STAGES_G : natural range 0 to 16 := 0); port ( -- Streaming RX Data Interface (sAxisClk domain) sAxisClk : in sl; @@ -57,11 +53,6 @@ entity SsiPrbsRx is sAxisMaster : in AxiStreamMasterType; sAxisSlave : out AxiStreamSlaveType; sAxisCtrl : out AxiStreamCtrlType; - -- Optional: Streaming TX Data Interface (mAxisClk domain) - mAxisClk : in sl; -- Note: a clock must always be applied to this port - mAxisRst : in sl := '0'; - mAxisMaster : out AxiStreamMasterType; - mAxisSlave : in AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; -- Optional: AXI-Lite Register Interface (axiClk domain) axiClk : in sl := '0'; axiRst : in sl := '0'; @@ -94,8 +85,7 @@ architecture rtl of SsiPrbsRx is IDLE_S, LENGTH_S, DATA_S, - BIT_ERR_S, - SEND_RESULT_S); + BIT_ERR_S); type RegType is record busy : sl; @@ -121,7 +111,6 @@ architecture rtl of SsiPrbsRx is startTime : slv(31 downto 0); packetRate : slv(31 downto 0); rxAxisSlave : AxiStreamSlaveType; - txAxisMaster : AxiStreamMasterType; state : StateType; end record; @@ -149,19 +138,15 @@ architecture rtl of SsiPrbsRx is startTime => (others => '1'), packetRate => (others => '1'), rxAxisSlave => AXI_STREAM_SLAVE_INIT_C, - txAxisMaster => AXI_STREAM_MASTER_INIT_C, state => IDLE_S); signal r : RegType := REG_INIT_C; signal rin : RegType; - signal txAxisMaster, - rxAxisMaster : AxiStreamMasterType; + signal rxAxisMaster : AxiStreamMasterType; + signal rxAxisSlave : AxiStreamSlaveType; - signal txAxisSlave, - rxAxisSlave : AxiStreamSlaveType; - - signal axisCtrl : AxiStreamCtrlArray(0 to 1); + signal axisCtrl : AxiStreamCtrlArray(1 downto 0) := (others => AXI_STREAM_CTRL_UNUSED_C); constant STATUS_SIZE_C : positive := 10; @@ -213,7 +198,7 @@ architecture rtl of SsiPrbsRx is begin - assert ((PRBS_SEED_SIZE_G = 32) or (PRBS_SEED_SIZE_G = 64) or (PRBS_SEED_SIZE_G = 128)) report "PRBS_SEED_SIZE_G must be either [32,64,128]" severity failure; + assert ((PRBS_SEED_SIZE_G = 32) or (PRBS_SEED_SIZE_G = 64) or (PRBS_SEED_SIZE_G = 128) or (PRBS_SEED_SIZE_G = 256)) report "PRBS_SEED_SIZE_G must be either [32,64,128,256]" severity failure; sAxisCtrl <= axisCtrl(0); @@ -251,27 +236,13 @@ begin mAxisMaster => rxAxisMaster, mAxisSlave => rxAxisSlave); - - comb : process (r, rxAxisMaster, sAxisRst, txAxisSlave) is + comb : process (r, rxAxisMaster, sAxisRst) is variable i : integer; variable v : RegType; begin -- Latch the current value v := r; - -- Set the AXIS configurations - v.txAxisMaster.tKeep := (others => '0'); - v.txAxisMaster.tStrb := (others => '0'); - for i in 0 to MASTER_PRBS_SSI_CONFIG_C.TDATA_BYTES_C-1 loop - v.txAxisMaster.tKeep(i) := '1'; - v.txAxisMaster.tStrb(i) := '1'; - end loop; - if txAxisSlave.tReady = '1' then - v.txAxisMaster.tValid := '0'; - v.txAxisMaster.tLast := '0'; - v.txAxisMaster.tUser := (others => '0'); - end if; - -- Reset strobe signals v.updatedResults := '0'; v.errWordStrb := '0'; @@ -375,8 +346,10 @@ begin end if; -- Reset the counter v.dataCnt := (others => '0'); + -- Update strobe for the results + v.updatedResults := '1'; -- Next State - v.state := SEND_RESULT_S; + v.state := IDLE_S; elsif r.dataCnt /= MAX_CNT_C then -- Increment the counter v.dataCnt := r.dataCnt + 1; @@ -418,69 +391,20 @@ begin v.bitPntr := (others => '0'); -- Check if there was an eof flag if r.eof = '1' then + -- Update strobe for the results + v.updatedResults := '1'; -- Next State - v.state := SEND_RESULT_S; + v.state := IDLE_S; else -- Next State v.state := DATA_S; end if; end if; - ---------------------------------------------------------------------- - when SEND_RESULT_S => - -- Check the upstream buffer status - if (v.txAxisMaster.tValid = '0') then - -- Sending Data - v.txAxisMaster.tValid := '1'; - -- Increment the data counter - v.txCnt := r.txCnt + 1; - -- Send data w.r.t. the counter - case (r.txCnt) is - when x"0" => - -- Update strobe for the results - v.updatedResults := '1'; - -- Write the data to the TX virtual channel - v.txAxisMaster.tData(31 downto 16) := x"FFFF"; -- static pattern for software alignment - v.txAxisMaster.tData(15 downto 0) := (others => '0'); - when x"1" => - v.txAxisMaster.tData(31 downto 0) := r.packetLength; - when x"2" => - v.txAxisMaster.tData(31 downto 0) := r.packetRate; - when x"3" => - v.txAxisMaster.tData(31 downto 0) := r.errWordCnt; - when x"4" => - v.txAxisMaster.tData(31 downto 0) := r.errbitCnt; - when others => - -- Reset the counter - v.txCnt := (others => '0'); - -- Send the last word - v.txAxisMaster.tLast := '1'; - v.txAxisMaster.tData(31 downto 4) := (others => '0'); - v.txAxisMaster.tData(3) := r.errDataBus; - v.txAxisMaster.tData(2) := r.eofe; - v.txAxisMaster.tData(1) := r.errLength; - v.txAxisMaster.tData(0) := r.errMissedPacket; - -- Reset the busy flag - v.busy := '0'; - -- Next State - v.state := IDLE_S; - end case; - end if; ---------------------------------------------------------------------- end case; - -- Combinatorial Outputs - rxAxisSlave <= v.rxAxisSlave; - - -- Reset - if (sAxisRst = '1') then - v := REG_INIT_C; - end if; - - -- Register the variable for next clock cycle - rin <= v; - -- Outputs - txAxisMaster <= r.txAxisMaster; + rxAxisSlave <= v.rxAxisSlave; updatedResults <= r.updatedResults; errMissedPacket <= r.errMissedPacket; errLength <= r.errLength; @@ -493,6 +417,14 @@ begin packetLength <= r.packetLength; errorDet <= r.errorDet; + -- Reset + if (sAxisRst = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + end process comb; seq : process (sAxisClk) is @@ -502,39 +434,6 @@ begin end if; end process seq; - AxiStreamFifo_Tx : entity work.AxiStreamFifoV2 - generic map( - -- General Configurations - TPD_G => TPD_G, - INT_PIPE_STAGES_G => MASTER_AXI_PIPE_STAGES_G, - PIPE_STAGES_G => MASTER_AXI_PIPE_STAGES_G, - -- FIFO configurations - BRAM_EN_G => BRAM_EN_G, - XIL_DEVICE_G => XIL_DEVICE_G, - USE_BUILT_IN_G => USE_BUILT_IN_G, - GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_G, - ALTERA_SYN_G => ALTERA_SYN_G, - ALTERA_RAM_G => ALTERA_RAM_G, - CASCADE_SIZE_G => CASCADE_SIZE_G, - FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, - FIFO_FIXED_THRESH_G => true, - FIFO_PAUSE_THRESH_G => FIFO_PAUSE_THRESH_G, - -- AXI Stream Port Configurations - SLAVE_AXI_CONFIG_G => MASTER_PRBS_SSI_CONFIG_C, - MASTER_AXI_CONFIG_G => MASTER_AXI_STREAM_CONFIG_G) - port map ( - -- Slave Port - sAxisClk => sAxisClk, - sAxisRst => sAxisRst, - sAxisMaster => txAxisMaster, - sAxisSlave => txAxisSlave, - sAxisCtrl => axisCtrl(1), - -- Master Port - mAxisClk => mAxisClk, - mAxisRst => mAxisRst, - mAxisMaster => mAxisMaster, - mAxisSlave => mAxisSlave); - SyncFifo_Inst : entity work.SynchronizerFifo generic map ( TPD_G => TPD_G, diff --git a/protocols/ssi/rtl/SsiPrbsTx.vhd b/protocols/ssi/rtl/SsiPrbsTx.vhd index 21f52d9952..6b114e678d 100644 --- a/protocols/ssi/rtl/SsiPrbsTx.vhd +++ b/protocols/ssi/rtl/SsiPrbsTx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiPrbsTx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-02 --- Last update: 2018-05-20 ------------------------------------------------------------------------------- -- Description: This module generates -- PseudoRandom Binary Sequence (PRBS) on Virtual Channel Lane. @@ -44,7 +42,7 @@ entity SsiPrbsTx is FIFO_ADDR_WIDTH_G : positive := 9; FIFO_PAUSE_THRESH_G : positive := 2**8; -- PRBS Configurations - PRBS_SEED_SIZE_G : natural range 32 to 128 := 32; + PRBS_SEED_SIZE_G : natural range 32 to 256 := 32; PRBS_TAPS_G : NaturalArray := (0 => 31, 1 => 6, 2 => 2, 3 => 1); PRBS_INCREMENT_G : boolean := false; -- Increment mode by default instead of PRBS -- AXI Stream Configurations @@ -137,7 +135,7 @@ architecture rtl of SsiPrbsTx is begin - assert ((PRBS_SEED_SIZE_G = 32) or (PRBS_SEED_SIZE_G = 64) or (PRBS_SEED_SIZE_G = 128)) report "PRBS_SEED_SIZE_G must be either [32,64,128]" severity failure; + assert ((PRBS_SEED_SIZE_G = 32) or (PRBS_SEED_SIZE_G = 64) or (PRBS_SEED_SIZE_G = 128) or (PRBS_SEED_SIZE_G = 256)) report "PRBS_SEED_SIZE_G must be either [32,64,128,256]" severity failure; comb : process (axilReadMaster, axilWriteMaster, forceEofe, locRst, packetLength, r, tDest, tId, trig, txCtrl, txSlave) is diff --git a/protocols/ssi/rtl/SsiPrbsTxOld.vhd b/protocols/ssi/rtl/SsiPrbsTxOld.vhd index 158fac35bf..4aface91d9 100644 --- a/protocols/ssi/rtl/SsiPrbsTxOld.vhd +++ b/protocols/ssi/rtl/SsiPrbsTxOld.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiPrbsTxOld.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-02 --- Last update: 2014-11-07 ------------------------------------------------------------------------------- -- Description: This module generates -- PseudoRandom Binary Sequence (PRBS) on Virtual Channel Lane. diff --git a/protocols/ssi/tb/SsiFifoTb.vhd b/protocols/ssi/tb/SsiFifoTb.vhd index b32490258b..475c2f7141 100644 --- a/protocols/ssi/tb/SsiFifoTb.vhd +++ b/protocols/ssi/tb/SsiFifoTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiFifoTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-24 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the SsiFifo module ------------------------------------------------------------------------------- diff --git a/protocols/ssi/tb/SsiFilterTb.vhd b/protocols/ssi/tb/SsiFilterTb.vhd index 9559c15190..8502ab7457 100644 --- a/protocols/ssi/tb/SsiFilterTb.vhd +++ b/protocols/ssi/tb/SsiFilterTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiFilterTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2015-03-24 --- Last update: 2016-10-11 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the SsiFifo module ------------------------------------------------------------------------------- diff --git a/protocols/ssi/tb/SsiPrbsTb.vhd b/protocols/ssi/tb/SsiPrbsTb.vhd index 2d27629128..10480dd188 100644 --- a/protocols/ssi/tb/SsiPrbsTb.vhd +++ b/protocols/ssi/tb/SsiPrbsTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SsiPrbsTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-04-29 --- Last update: 2018-01-08 ------------------------------------------------------------------------------- -- Description: Simulation Testbed for testing the VcPrbsTx and VcPrbsRx modules ------------------------------------------------------------------------------- @@ -122,6 +120,7 @@ begin generic map ( -- General Configurations TPD_G => TPD_C, + AXI_EN_G => '0', -- FIFO configurations BRAM_EN_G => BRAM_EN_C, XIL_DEVICE_G => XIL_DEVICE_C, diff --git a/protocols/ssp/rtl/SspDecoder10b12b.vhd b/protocols/ssp/rtl/SspDecoder10b12b.vhd index 01fc474d83..ddc9651780 100644 --- a/protocols/ssp/rtl/SspDecoder10b12b.vhd +++ b/protocols/ssp/rtl/SspDecoder10b12b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SspDecoder10b12b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-07-14 --- Last update: 2017-05-01 ------------------------------------------------------------------------------- -- Description: SimpleStreamingProtocol - A simple protocol layer for inserting -- idle and framing control characters into a raw data stream. This module diff --git a/protocols/ssp/rtl/SspDecoder12b14b.vhd b/protocols/ssp/rtl/SspDecoder12b14b.vhd index 8bf905d1ef..39282da33e 100644 --- a/protocols/ssp/rtl/SspDecoder12b14b.vhd +++ b/protocols/ssp/rtl/SspDecoder12b14b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SspDecoder12b14b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-07-14 --- Last update: 2017-05-01 ------------------------------------------------------------------------------- -- Description: SimpleStreamingProtocol - A simple protocol layer for inserting -- idle and framing control characters into a raw data stream. This module diff --git a/protocols/ssp/rtl/SspDecoder8b10b.vhd b/protocols/ssp/rtl/SspDecoder8b10b.vhd index 9eaed181d5..49441f9abf 100644 --- a/protocols/ssp/rtl/SspDecoder8b10b.vhd +++ b/protocols/ssp/rtl/SspDecoder8b10b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SspDecoder8b10b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-07-14 --- Last update: 2017-05-01 ------------------------------------------------------------------------------- -- Description: SimpleStreamingProtocol - A simple protocol layer for inserting -- idle and framing control characters into a raw data stream. This module diff --git a/protocols/ssp/rtl/SspDeframer.vhd b/protocols/ssp/rtl/SspDeframer.vhd index 0ec42b77e0..9c7ec5ca99 100644 --- a/protocols/ssp/rtl/SspDeframer.vhd +++ b/protocols/ssp/rtl/SspDeframer.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SspDeframer.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-07-14 --- Last update: 2017-05-01 ------------------------------------------------------------------------------- -- Description: SimpleStreamingProtocol - A simple protocol layer for inserting -- idle and framing control characters into a raw data stream. The input of diff --git a/protocols/ssp/rtl/SspEncoder10b12b.vhd b/protocols/ssp/rtl/SspEncoder10b12b.vhd index b6ad97ea7a..d814323591 100644 --- a/protocols/ssp/rtl/SspEncoder10b12b.vhd +++ b/protocols/ssp/rtl/SspEncoder10b12b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SspEncoder10b12b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-07-14 --- Last update: 2017-05-01 ------------------------------------------------------------------------------- -- Description: SimpleStreamingProtocol - A simple protocol layer for inserting -- idle and framing control characters into a raw data stream. This module diff --git a/protocols/ssp/rtl/SspEncoder12b14b.vhd b/protocols/ssp/rtl/SspEncoder12b14b.vhd index ac9a7b9ecc..3e1bbfa610 100644 --- a/protocols/ssp/rtl/SspEncoder12b14b.vhd +++ b/protocols/ssp/rtl/SspEncoder12b14b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SspEncoder12b14b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-07-14 --- Last update: 2017-05-01 ------------------------------------------------------------------------------- -- Description: SimpleStreamingProtocol - A simple protocol layer for inserting -- idle and framing control characters into a raw data stream. This module diff --git a/protocols/ssp/rtl/SspEncoder8b10b.vhd b/protocols/ssp/rtl/SspEncoder8b10b.vhd index 3d890caf18..d90a586a43 100644 --- a/protocols/ssp/rtl/SspEncoder8b10b.vhd +++ b/protocols/ssp/rtl/SspEncoder8b10b.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SspEncoder8b10b.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-07-14 --- Last update: 2017-05-05 ------------------------------------------------------------------------------- -- Description: SimpleStreamingProtocol - A simple protocol layer for inserting -- idle and framing control characters into a raw data stream. This module diff --git a/protocols/ssp/rtl/SspFramer.vhd b/protocols/ssp/rtl/SspFramer.vhd index 72be33c254..716687aefe 100644 --- a/protocols/ssp/rtl/SspFramer.vhd +++ b/protocols/ssp/rtl/SspFramer.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SspFramer.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-07-14 --- Last update: 2018-02-14 ------------------------------------------------------------------------------- -- Description: SimpleStreamingProtocol - A simple protocol layer for inserting -- idle and framing control characters into a raw data stream. The output of diff --git a/protocols/ssp/tb/Ssp10b12bTb.vhd b/protocols/ssp/tb/Ssp10b12bTb.vhd index 8ed39733be..f8946e285f 100644 --- a/protocols/ssp/tb/Ssp10b12bTb.vhd +++ b/protocols/ssp/tb/Ssp10b12bTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Ssp10b12bTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-26 --- Last update: 2017-05-01 ------------------------------------------------------------------------------- -- Description: Simulation testbed for Ssp10b12b ------------------------------------------------------------------------------- diff --git a/protocols/ssp/tb/Ssp12b14bTb.vhd b/protocols/ssp/tb/Ssp12b14bTb.vhd index f4149c507f..f7f2ac900f 100644 --- a/protocols/ssp/tb/Ssp12b14bTb.vhd +++ b/protocols/ssp/tb/Ssp12b14bTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : Ssp12b14bTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-10-26 --- Last update: 2017-05-01 ------------------------------------------------------------------------------- -- Description: Simulation testbed for Ssp12b14b ------------------------------------------------------------------------------- diff --git a/protocols/ssp/tb/SspDecoder8b10bTb.vhd b/protocols/ssp/tb/SspDecoder8b10bTb.vhd index 123601bb47..2d71006f5f 100644 --- a/protocols/ssp/tb/SspDecoder8b10bTb.vhd +++ b/protocols/ssp/tb/SspDecoder8b10bTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SspDecoder8b10bTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-08-27 --- Last update: 2017-05-01 ------------------------------------------------------------------------------- -- Description: Testbench for design "SspDecoder8b10b" ------------------------------------------------------------------------------- diff --git a/protocols/ssp/tb/SspEncoderTb.vhd b/protocols/ssp/tb/SspEncoderTb.vhd index c7792bfce3..631d104ef4 100644 --- a/protocols/ssp/tb/SspEncoderTb.vhd +++ b/protocols/ssp/tb/SspEncoderTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : SspEncoderTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2014-08-27 --- Last update: 2016-09-06 ------------------------------------------------------------------------------- -- Description: Testbench for design "SspEncoder" ------------------------------------------------------------------------------- diff --git a/protocols/uart/rtl/UartAxiLiteMaster.vhd b/protocols/uart/rtl/UartAxiLiteMaster.vhd index d81e26fb14..02018fd442 100644 --- a/protocols/uart/rtl/UartAxiLiteMaster.vhd +++ b/protocols/uart/rtl/UartAxiLiteMaster.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : UartAxiLiteMaster.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-06-09 --- Last update: 2018-06-09 ------------------------------------------------------------------------------- -- Description: Ties together everything needed for a full duplex UART. -- This includes Baud Rate Generator, Transmitter, Receiver and FIFOs. @@ -24,7 +22,6 @@ use ieee.std_logic_unsigned.all; use work.StdRtlPkg.all; use work.TextUtilPkg.all; use work.AxiLitePkg.all; -use work.AxiLiteMasterPkg.all; entity UartAxiLiteMaster is @@ -67,7 +64,7 @@ architecture rtl of UartAxiLiteMaster is type RegType is record state : StateType; count : slv(2 downto 0); - axilReq : AxiLiteMasterReqType; + axilReq : AxiLiteReqType; rdData : slv(31 downto 0); uartTxData : slv(7 downto 0); uartTxValid : sl; @@ -77,7 +74,7 @@ architecture rtl of UartAxiLiteMaster is constant REG_INIT_C : RegType := ( state => WAIT_START_S, count => (others => '0'), - axilReq => AXI_LITE_MASTER_REQ_INIT_C, + axilReq => AXI_LITE_REQ_INIT_C, rdData => (others => '0'), uartTxData => (others => '0'), uartTxValid => '0', @@ -86,8 +83,8 @@ architecture rtl of UartAxiLiteMaster is signal r : RegType := REG_INIT_C; signal rin : RegType; --- signal axilReq : AxiLiteMasterReqType; - signal axilAck : AxiLiteMasterAckType; +-- signal axilReq : AxiLiteReqType; + signal axilAck : AxiLiteAckType; signal uartRxData : slv(7 downto 0); signal uartRxValid : sl; diff --git a/protocols/uart/rtl/UartBrg.vhd b/protocols/uart/rtl/UartBrg.vhd index a31d3b70ed..90a784d39e 100644 --- a/protocols/uart/rtl/UartBrg.vhd +++ b/protocols/uart/rtl/UartBrg.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : UartBrg.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-05-13 --- Last update: 2016-06-09 ------------------------------------------------------------------------------- -- Description: UART Baud Rate Generator ------------------------------------------------------------------------------- diff --git a/protocols/uart/rtl/UartRx.vhd b/protocols/uart/rtl/UartRx.vhd index a1fe749c4d..4904bc9af9 100644 --- a/protocols/uart/rtl/UartRx.vhd +++ b/protocols/uart/rtl/UartRx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : UartRx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-05-13 --- Last update: 2018-06-05 ------------------------------------------------------------------------------- -- Description: UART Receiver ------------------------------------------------------------------------------- diff --git a/protocols/uart/rtl/UartTx.vhd b/protocols/uart/rtl/UartTx.vhd index fc9d8600e8..2f309a7a51 100644 --- a/protocols/uart/rtl/UartTx.vhd +++ b/protocols/uart/rtl/UartTx.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : UartTx.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-05-13 --- Last update: 2018-06-05 ------------------------------------------------------------------------------- -- Description: Uart Transmitter ------------------------------------------------------------------------------- diff --git a/protocols/uart/rtl/UartWrapper.vhd b/protocols/uart/rtl/UartWrapper.vhd index c2ad48324c..55e6704f25 100644 --- a/protocols/uart/rtl/UartWrapper.vhd +++ b/protocols/uart/rtl/UartWrapper.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : UartAxiLiteMaster.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-06-09 --- Last update: 2018-06-09 ------------------------------------------------------------------------------- -- Description: Ties together everything needed for a full duplex UART. -- This includes Baud Rate Generator, Transmitter, Receiver and FIFOs. diff --git a/protocols/uart/sim/UartAxiLiteMasterTb.vhd b/protocols/uart/sim/UartAxiLiteMasterTb.vhd index db6b110b1a..e2c272db58 100644 --- a/protocols/uart/sim/UartAxiLiteMasterTb.vhd +++ b/protocols/uart/sim/UartAxiLiteMasterTb.vhd @@ -1,8 +1,6 @@ ------------------------------------------------------------------------------- -- File : UartAxiLiteMasterTb.vhd -- Company : SLAC National Accelerator Laboratory --- Created : 2016-06-27 --- Last update: 2016-06-28 ------------------------------------------------------------------------------- -- Description: Testbench for design "UartAxiLiteMaster" ------------------------------------------------------------------------------- diff --git a/python/surf/axi/_AxiMemTester.py b/python/surf/axi/_AxiMemTester.py index ab1be9be19..ea0c90727a 100644 --- a/python/surf/axi/_AxiMemTester.py +++ b/python/surf/axi/_AxiMemTester.py @@ -119,4 +119,56 @@ def __init__( self, base = pr.UInt, mode = "RO", )) + + self.add(pr.RemoteVariable( + name = "WrErrResp", + description = "AXI4 Bus Write Error Response", + offset = 0x12C, + bitSize = 1, + bitOffset = 0, + base = pr.Bool, + mode = "RO", + )) + + self.add(pr.RemoteVariable( + name = "RdErrResp", + description = "AXI4 Bus Read Error Response", + offset = 0x12C, + bitSize = 1, + bitOffset = 1, + base = pr.Bool, + mode = "RO", + )) + + self.add(pr.RemoteVariable( + name = "RdErrData", + description = "Read Data Error", + offset = 0x12C, + bitSize = 1, + bitOffset = 2, + base = pr.Bool, + mode = "RO", + )) + + for i in range(32): + self.add(pr.RemoteVariable( + name = f'RdData[{i:d}]', + description = f'Readback Data Word {i:d}', + offset = 0x130 + (i*4), + bitSize = 32, + bitOffset = 0, + base = pr.UInt, + mode = 'RO', + )) + + for i in range(32): + self.add(pr.RemoteVariable( + name = f'RandomData[{i:d}]', + description = f'Random Data Pattern Word {i:d}', + offset = 0x1B0 + (i*4), + bitSize = 32, + bitOffset = 0, + base = pr.UInt, + mode = 'RO', + )) diff --git a/python/surf/axi/_AxiStreamDmaV2.py b/python/surf/axi/_AxiStreamDmaV2.py new file mode 100644 index 0000000000..8bb17b67b5 --- /dev/null +++ b/python/surf/axi/_AxiStreamDmaV2.py @@ -0,0 +1,188 @@ +import pyrogue as pr + +class AxiStreamDmaV2Desc(pr.Device): + def __init__(self, **kwargs): + super().__init__(description='', **kwargs) + + + self.add(pr.RemoteVariable( + name='HwEnable', + mode = 'RO', + offset=0x0, + bitOffset=0, + bitSize=1, + )) + + self.add(pr.RemoteVariable( + name='Version', + mode = 'RO', + offset=0x0, + bitOffset=24, + bitSize=8, + )) + + self.add(pr.RemoteVariable( + name='IntEnable', + mode = 'RO', + offset=0x4, + bitOffset=0, + bitSize=1, + )) + + self.add(pr.RemoteVariable( + name='ContEn', + mode = 'RO', + offset=0x8, + bitOffset=0, + bitSize=1, + )) + + self.add(pr.RemoteVariable( + name='DropEn', + mode = 'RO', + offset=0xC, + bitOffset=0, + bitSize=1, + )) + + self.add(pr.RemoteVariable( + name='WrBaseAddr', + mode = 'RO', + offset=0x10, + bitOffset=0, + bitSize=64, + )) + + self.add(pr.RemoteVariable( + name='RdBaseAddr', + mode = 'RO', + offset=0x14, + bitOffset=0, + bitSize=64, + )) + + self.add(pr.RemoteVariable( + name='FifoReset', + mode = 'RO', + offset=0x20, + bitOffset=0, + bitSize=1, + )) + self.add(pr.RemoteVariable( + name='BufBaseAddr', + mode = 'RO', + offset=0x24, + bitOffset=0, + bitSize=32, + )) + + self.add(pr.RemoteVariable( + name='MaxSize', + mode = 'RO', + offset=0x28, + bitOffset=0, + bitSize=24, + disp='{:d}', + )) + + self.add(pr.RemoteVariable( + name='Online', + mode = 'RO', + offset=0x2C, + bitOffset=0, + bitSize=1, + )) + + self.add(pr.RemoteVariable( + name='Acknowledge', + mode = 'RO', + offset=0x30, + bitOffset=0, + bitSize=1, + )) + + self.add(pr.RemoteVariable( + name='ChanCount', + mode = 'RO', + offset=0x34, + bitOffset=0, + bitSize=8, + )) + + self.add(pr.RemoteVariable( + name='DescAwidth', + mode = 'RO', + offset=0x38, + bitOffset=0, + bitSize=8, + )) + + self.add(pr.RemoteVariable( + name='DescCache', + mode = 'RO', + offset=0x3C, + bitOffset=0, + bitSize=4, + )) + self.add(pr.RemoteVariable( + name='BuffCache', + mode = 'RO', + offset=0x3C, + bitOffset=8, + bitSize=4, + )) + + self.add(pr.RemoteVariable( + name='FifoDin', + mode = 'RO', + offset=0x40, + bitOffset=0, + bitSize=32, + )) + + self.add(pr.RemoteVariable( + name='IntAckCount', + mode = 'RO', + offset=0x4C, + bitOffset=0, + bitSize=16, + )) + + self.add(pr.RemoteVariable( + name='IntEnableDup', + mode = 'RO', + offset=0x4C, + bitOffset=17, + bitSize=1, + )) + + self.add(pr.RemoteVariable( + name='IntReqCount', + mode = 'RO', + offset=0x50, + bitOffset=0, + bitSize=32, + )) + + self.add(pr.RemoteVariable( + name='WrIndex', + mode = 'RO', + offset=0x54, + bitOffset=0, + bitSize=32, + )) + self.add(pr.RemoteVariable( + name='RdIndex', + mode = 'RO', + offset=0x58, + bitOffset=0, + bitSize=32, + )) + + self.add(pr.RemoteVariable( + name='WrReqMissed', + mode = 'RO', + offset=0x5C, + bitOffset=0, + bitSize=32, + )) diff --git a/python/surf/axi/_AxiVersion.py b/python/surf/axi/_AxiVersion.py index 3a6326e9c5..46015f146b 100644 --- a/python/surf/axi/_AxiVersion.py +++ b/python/surf/axi/_AxiVersion.py @@ -63,7 +63,7 @@ def __init__( bitOffset = 0x00, base = pr.UInt, mode = 'RW', - disp = '{:#08x}' + disp = '{:#08x}', )) self.add(pr.RemoteVariable( @@ -77,14 +77,16 @@ def __init__( mode = 'RO', disp = '{:d}', units = 'seconds', - pollInterval = 1 + pollInterval = 1, )) self.add(pr.LinkVariable( - name = 'UpTime', - mode = 'RO', + name = 'UpTime', + description = 'Time since power up or last firmware reload', + mode = 'RO', dependencies = [self.UpTimeCnt], - linkedGet = lambda: str(datetime.timedelta(seconds=self.UpTimeCnt.value())) + linkedGet = lambda: str(datetime.timedelta(seconds=self.UpTimeCnt.value())), + units = 'HH:MM:SS', )) self.add(pr.RemoteVariable( @@ -148,6 +150,7 @@ def UserRst(): bitOffset = 0x00, base = pr.UInt, mode = 'RO', + hidden = True, )) self.addRemoteVariables( @@ -190,7 +193,7 @@ def UserRst(): mode = 'RO', dependencies = [self.GitHash], disp = '{:07x}', - linkedGet = lambda: self.GitHash.value() >> 132 + linkedGet = lambda: self.GitHash.value() >> 132, )) self.add(pr.RemoteVariable( @@ -259,18 +262,22 @@ def countReset(self): print('AxiVersion count reset called') def printStatus(self): - self.UpTimeCnt.get() - self.BuildStamp.get() - gitHash = self.GitHash.get() - print("FwVersion = {}".format(hex(self.FpgaVersion.get()))) - print("UpTime = {}".format(self.UpTime.get())) - if (gitHash != 0): - print("GitHash = {}".format(hex(self.GitHash.get()))) - else: - print("GitHash = dirty (uncommitted code)") - print("XilinxDnaId = {}".format(hex(self.DeviceDna.get()))) - print("FwTarget = {}".format(self.ImageName.get())) - print("BuildEnv = {}".format(self.BuildEnv.get())) - print("BuildServer = {}".format(self.BuildServer.get())) - print("BuildDate = {}".format(self.BuildDate.get())) - print("Builder = {}".format(self.Builder.get())) + try: + self.UpTimeCnt.get() + self.BuildStamp.get() + gitHash = self.GitHash.get() + print("FwVersion = {}".format(hex(self.FpgaVersion.get()))) + print("UpTime = {}".format(self.UpTime.get())) + if (gitHash != 0): + print("GitHash = {}".format(hex(self.GitHash.get()))) + else: + print("GitHash = dirty (uncommitted code)") + print("XilinxDnaId = {}".format(hex(self.DeviceDna.get()))) + print("FwTarget = {}".format(self.ImageName.get())) + print("BuildEnv = {}".format(self.BuildEnv.get())) + print("BuildServer = {}".format(self.BuildServer.get())) + print("BuildDate = {}".format(self.BuildDate.get())) + print("Builder = {}".format(self.Builder.get())) + except Exception as e: + print("Failed to get AxiVersion status") + diff --git a/python/surf/axi/__init__.py b/python/surf/axi/__init__.py index 47b47fb8ab..ef86382067 100644 --- a/python/surf/axi/__init__.py +++ b/python/surf/axi/__init__.py @@ -14,3 +14,4 @@ from surf.axi._AxiStreamMonitoring import * from surf.axi._AxiVersion import * from surf.axi._AxiVersionLegacy import * +from surf.axi._AxiStreamDmaV2 import * diff --git a/python/surf/devices/analog_devices/_ad5780.py b/python/surf/devices/analog_devices/_Ad5780.py similarity index 100% rename from python/surf/devices/analog_devices/_ad5780.py rename to python/surf/devices/analog_devices/_Ad5780.py diff --git a/python/surf/devices/analog_devices/_ad9249.py b/python/surf/devices/analog_devices/_Ad9249.py similarity index 86% rename from python/surf/devices/analog_devices/_ad9249.py rename to python/surf/devices/analog_devices/_Ad9249.py index 2b3a7ba9ba..4513b0298c 100644 --- a/python/surf/devices/analog_devices/_ad9249.py +++ b/python/surf/devices/analog_devices/_Ad9249.py @@ -232,30 +232,40 @@ class Ad9249ReadoutGroup(pr.Device): def __init__(self, name = 'Ad9249ReadoutGroup', description = 'Configure readout of 1 bank of an AD9249', + fpga = '7series', channels = 8, **kwargs): assert (channels > 0 and channels <= 8), f'channels ({channels}) must be between 0 and 8' super().__init__(name=name, description=description, **kwargs) + if fpga == '7series': + delayBits = 6 + elif fpga == 'ultrascale': + delayBits = 10 + else: + delayBits = 6 + for i in range(channels): self.add(pr.RemoteVariable( - name = f'ChannelDelay[{i}]', - description = f'IDELAY value for serial channel {i}', - offset = i*4, - bitSize = 5, - bitOffset = 0, - base = pr.UInt, - mode = 'RW', + name = f'ChannelDelay[{i}]', + description = f'IDELAY value for serial channel {i}', + offset = i*4, + bitSize = delayBits, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + verify = False, )) self.add(pr.RemoteVariable( name = 'FrameDelay', description = 'IDELAY value for FCO', offset = 0x20, - bitSize = 5, + bitSize = delayBits, bitOffset = 0, base = pr.UInt, mode = 'RW', + verify = False, )) self.add(pr.RemoteVariable( @@ -318,17 +328,34 @@ def __init__(self, bitOffset=0, base=pr.UInt, function=pr.RemoteCommand.touch)) + + @staticmethod + def setDelay(var, value, write): + iValue = value + 512 + var.dependencies[0].set(iValue, write) + var.dependencies[0].set(value, write) + + @staticmethod + def getDelay(var, read): + return var.dependencies[0].get(read) - def readBlocks(self, recurse=True, variable=None): - if variable is not None: - variable._block.backgroundTransaction(rim.Read) - else: - self.FreezeDebug(1) - for block in self._blocks: - if block.bulkEn: - block.backgroundTransaction(rim.Read) - self.FreezeDebug(0) + def readBlocks(self, recurse=True, variable=None, checkEach=False): + if variable is not None: + freeze = isinstance(variable, list) and any(v.name.startswith('AdcChannel') for v in variable) + if freeze: + self.FreezeDebug(1) + for b in self._getBlocks(variable): + b.startTransaction(rim.Read, checkEach) + if freeze: + self.FreezeDebug(0) + else: + self.FreezeDebug(1) + for block in self._blocks: + if block.bulkEn: + block.startTransaction(rim.Read, checkEach) + self.FreezeDebug(0) + - if recurse: - for key, value in self.devices.items(): - value.readBlocks(recurse=True) + if recurse: + for key, value in self.devices.items(): + value.readBlocks(recurse=True, checkEach=checkEach) diff --git a/python/surf/devices/analog_devices/__init__.py b/python/surf/devices/analog_devices/__init__.py index c975ceb39b..a7a5efea24 100644 --- a/python/surf/devices/analog_devices/__init__.py +++ b/python/surf/devices/analog_devices/__init__.py @@ -8,5 +8,5 @@ ## may be copied, modified, propagated, or distributed except according to ## the terms contained in the LICENSE.txt file. ############################################################################## -from surf.devices.analog_devices._ad9249 import * -from surf.devices.analog_devices._ad5780 import * +from surf.devices.analog_devices._Ad9249 import * +from surf.devices.analog_devices._Ad5780 import * diff --git a/python/surf/devices/cypress/_CypressS25Fl.py b/python/surf/devices/cypress/_CypressS25Fl.py new file mode 100644 index 0000000000..aad3a3eba4 --- /dev/null +++ b/python/surf/devices/cypress/_CypressS25Fl.py @@ -0,0 +1,114 @@ +#!/usr/bin/env python +#----------------------------------------------------------------------------- +# Description: PyRogue Cypress S25FL PROM Series +# +# Note: Used with surf/devices/Micron/n25q firmware +# +#----------------------------------------------------------------------------- +# This file is part of the rogue software platform. It is subject to +# the license terms in the LICENSE.txt file found in the top-level directory +# of this distribution and at: +# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +# No part of the rogue software platform, including this file, may be +# copied, modified, propagated, or distributed except according to the terms +# contained in the LICENSE.txt file. +#----------------------------------------------------------------------------- + +import pyrogue as pr +import surf.devices.micron as micron +import surf.misc as misc +import click +import time +import datetime + +class CypressS25Fl(micron.AxiMicronN25Q): + def __init__(self, + name = "CypressS25Fl", + description = "Container for Cypress S25FL PROM device", + addrMode = False, # False = 24-bit Address mode, True = 32-bit Address Mode + **kwargs + ): + super().__init__( + name = name, + description = description, + **kwargs + ) + + ######################################## + # Overwrite with Cypress S25FL Constants + ######################################## + self.FLAG_STATUS_REG = (0x05 << 16) + self.FLAG_STATUS_RDY = (0x01) + self.BRAC_CMD = (0xB9 << 16) + + def _LoadMcsFile(self,arg): + + click.secho(('LoadMcsFile: %s' % arg), fg='green') + self._progDone = False + + # Start time measurement for profiling + start = time.time() + + # Reset the SPI interface + self.resetFlash() + + # Print the status registers + print("CypressS25Fl Manufacturer ID Code = {}".format(hex(self.getManufacturerId()))) + print("CypressS25Fl Manufacturer Type = {}".format(hex(self.getManufacturerType()))) + print("CypressS25Fl Manufacturer Capacity = {}".format(hex(self.getManufacturerCapacity()))) + print("CypressS25Fl Status Register = {}".format(hex(self.getPromStatusReg()))) + + # Open the MCS file + self._mcs.open(arg) + + # Erase the PROM + self.eraseProm() + + # Write to the PROM + self.writeProm() + + # Verify the PROM + self.verifyProm() + + # End time measurement for profiling + end = time.time() + elapsed = end - start + click.secho('LoadMcsFile() took %s to program the PROM' % datetime.timedelta(seconds=int(elapsed)), fg='green') + + # Add a power cycle reminder + self._progDone = True + click.secho( + "\n\n\ + ***************************************************\n\ + ***************************************************\n\ + The MCS data has been written into the PROM. \n\ + To reprogram the FPGA with the new PROM data, \n\ + a IPROG CMD or power cycle is be required.\n\ + ***************************************************\n\ + ***************************************************\n\n"\ + , bg='green', + ) + + def resetFlash(self): + # Send the "Mode Bit Reset" command + self.setCmdReg(self.WRITE_MASK|(0xFF << 16)) + time.sleep(0.001) + # Send the "Software Reset" Command + self.setCmdReg(self.WRITE_MASK|(0xF0 << 16)) + time.sleep(0.001) + # Set the addressing mode + self.setModeReg() + # Check the address mode + if (self._addrMode): + self.setCmd(self.WRITE_MASK|self.BRAC_CMD|0x80) + else: + self.setCmd(self.WRITE_MASK|self.BRAC_CMD) + + def waitForFlashReady(self): + while True: + # Get the status register + self.setCmdReg(self.READ_MASK|self.FLAG_STATUS_REG|0x1) + status = (self.getCmdReg()&0xFF) + # Check if not busy + if ( (status & self.FLAG_STATUS_RDY) == 0 ): # active Low READY + break diff --git a/python/surf/devices/cypress/__init__.py b/python/surf/devices/cypress/__init__.py new file mode 100644 index 0000000000..d47ffa9f73 --- /dev/null +++ b/python/surf/devices/cypress/__init__.py @@ -0,0 +1,11 @@ +#!/usr/bin/env python +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## +from surf.devices.cypress._CypressS25Fl import * diff --git a/python/surf/devices/linear/_ltc2270.py b/python/surf/devices/linear/_Ltc2270.py similarity index 100% rename from python/surf/devices/linear/_ltc2270.py rename to python/surf/devices/linear/_Ltc2270.py diff --git a/python/surf/devices/linear/_Ltc4151.py b/python/surf/devices/linear/_Ltc4151.py index c368caca84..fe7b2261f8 100644 --- a/python/surf/devices/linear/_Ltc4151.py +++ b/python/surf/devices/linear/_Ltc4151.py @@ -57,7 +57,7 @@ def __init__(self, self.add(pr.LinkVariable( name = 'Iin', - description = 'Current Measurment', + description = 'Current Measurement', mode = 'RO', units = 'A', disp = '{:1.3f}', @@ -91,7 +91,7 @@ def __init__(self, self.add(pr.LinkVariable( name = 'Vin', - description = 'Voltage Measurment', + description = 'Voltage Measurement', mode = 'RO', units = 'V', disp = '{:1.3f}', @@ -101,7 +101,7 @@ def __init__(self, self.add(pr.LinkVariable( name = 'Pin', - description = 'Power Measurment', + description = 'Power Measurement', mode = 'RO', units = 'W', disp = '{:1.3f}', @@ -135,7 +135,7 @@ def __init__(self, self.add(pr.LinkVariable( name = 'ADC Input', - description = 'ADC Voltage Measurment', + description = 'ADC Voltage Measurement', mode = 'RO', units = 'V', disp = '{:1.3f}', @@ -151,5 +151,6 @@ def __init__(self, bitOffset = 0, base = pr.UInt, mode = 'RW', + hidden = True, )) \ No newline at end of file diff --git a/python/surf/devices/linear/__init__.py b/python/surf/devices/linear/__init__.py index 091310662c..8074fd7f1c 100644 --- a/python/surf/devices/linear/__init__.py +++ b/python/surf/devices/linear/__init__.py @@ -8,6 +8,6 @@ ## may be copied, modified, propagated, or distributed except according to ## the terms contained in the LICENSE.txt file. ############################################################################## -from surf.devices.linear._ltc2270 import * +from surf.devices.linear._Ltc2270 import * from surf.devices.linear._Ltc2945 import * from surf.devices.linear._Ltc4151 import * diff --git a/python/surf/devices/microchip/_Axi24LC64FT.py b/python/surf/devices/microchip/_Axi24LC64FT.py index d0933a3bea..0cfe5643f3 100644 --- a/python/surf/devices/microchip/_Axi24LC64FT.py +++ b/python/surf/devices/microchip/_Axi24LC64FT.py @@ -19,8 +19,6 @@ import pyrogue as pr -from surf.misc._GenericMemory import * - class Axi24LC64FT(pr.Device): def __init__(self, name = "Axi24LC64FT", @@ -33,8 +31,11 @@ def __init__(self, ############################## # Variables ############################## - self.add(GenericMemory( - offset = 0x00, - nelms = nelms, - instantiate = instantiate, - )) \ No newline at end of file + if (instantiate): + pr.MemoryDevice( + name = "Mem", + description = "Memory Array", + size = (4*nelms), + # nelms = nelms, + ) + \ No newline at end of file diff --git a/python/surf/devices/micron/_AxiMicronMt28ew.py b/python/surf/devices/micron/_AxiMicronMt28ew.py index a998433713..93b78f5255 100644 --- a/python/surf/devices/micron/_AxiMicronMt28ew.py +++ b/python/surf/devices/micron/_AxiMicronMt28ew.py @@ -17,8 +17,8 @@ # contained in the LICENSE.txt file. #----------------------------------------------------------------------------- -import pyrogue as pr -from surf.misc._mcsreader import * +import pyrogue as pr +import surf.misc as misc import click import time import datetime @@ -34,7 +34,7 @@ def __init__(self, size = (0x1 << 12), **kwargs) - self._mcs = McsReader() + self._mcs = misc.McsReader() self._progDone = False ############################## diff --git a/python/surf/devices/micron/_AxiMicronN25Q.py b/python/surf/devices/micron/_AxiMicronN25Q.py index edebcac364..5cfa61f700 100644 --- a/python/surf/devices/micron/_AxiMicronN25Q.py +++ b/python/surf/devices/micron/_AxiMicronN25Q.py @@ -17,8 +17,8 @@ # contained in the LICENSE.txt file. #----------------------------------------------------------------------------- -import pyrogue as pr -from surf.misc._mcsreader import * +import pyrogue as pr +import surf.misc as misc import click import time import datetime @@ -35,7 +35,7 @@ def __init__(self, size = (0x1 << 10), **kwargs) - self._mcs = McsReader() + self._mcs = misc.McsReader() self._addrMode = addrMode self._progDone = False @@ -100,56 +100,63 @@ def __init__(self, self.READ_MASK = 0x00000000 self.WRITE_MASK = 0x80000000 self.VERIFY_MASK = 0x40000000 + + self.add(pr.LocalCommand( + name = 'LoadMcsFile', + function = self._LoadMcsFile, + description = 'Load the .MCS into PROM', + value = '', + )) - @self.command(value='',description="Load the .MCS into PROM",) - def LoadMcsFile(arg): - - click.secho(('LoadMcsFile: %s' % arg), fg='green') - self._progDone = False - - # Start time measurement for profiling - start = time.time() - - # Reset the SPI interface - self.resetFlash() - - # Print the status registers - print("MicronN25Q Manufacturer ID Code = {}".format(hex(self.getManufacturerId()))) - print("MicronN25Q Manufacturer Type = {}".format(hex(self.getManufacturerType()))) - print("MicronN25Q Manufacturer Capacity = {}".format(hex(self.getManufacturerCapacity()))) - print("MicronN25Q Status Register = {}".format(hex(self.getPromStatusReg()))) - print("MicronN25Q Volatile Config Reg = {}".format(hex(self.getPromConfigReg()))) - - # Open the MCS file - self._mcs.open(arg) - - # Erase the PROM - self.eraseProm() - - # Write to the PROM - self.writeProm() - - # Verify the PROM - self.verifyProm() - - # End time measurement for profiling - end = time.time() - elapsed = end - start - click.secho('LoadMcsFile() took %s to program the PROM' % datetime.timedelta(seconds=int(elapsed)), fg='green') - - # Add a power cycle reminder - self._progDone = True - click.secho( - "\n\n\ - ***************************************************\n\ - ***************************************************\n\ - The MCS data has been written into the PROM. \n\ - To reprogram the FPGA with the new PROM data, \n\ - a IPROG CMD or power cycle is be required.\n\ - ***************************************************\n\ - ***************************************************\n\n"\ - , bg='green', - ) + def _LoadMcsFile(self,arg): + # arg = value + + click.secho(('LoadMcsFile: %s' % arg), fg='green') + self._progDone = False + + # Start time measurement for profiling + start = time.time() + + # Reset the SPI interface + self.resetFlash() + + # Print the status registers + print("MicronN25Q Manufacturer ID Code = {}".format(hex(self.getManufacturerId()))) + print("MicronN25Q Manufacturer Type = {}".format(hex(self.getManufacturerType()))) + print("MicronN25Q Manufacturer Capacity = {}".format(hex(self.getManufacturerCapacity()))) + print("MicronN25Q Status Register = {}".format(hex(self.getPromStatusReg()))) + print("MicronN25Q Volatile Config Reg = {}".format(hex(self.getPromConfigReg()))) + + # Open the MCS file + self._mcs.open(arg) + + # Erase the PROM + self.eraseProm() + + # Write to the PROM + self.writeProm() + + # Verify the PROM + self.verifyProm() + + # End time measurement for profiling + end = time.time() + elapsed = end - start + click.secho('LoadMcsFile() took %s to program the PROM' % datetime.timedelta(seconds=int(elapsed)), fg='green') + + # Add a power cycle reminder + self._progDone = True + click.secho( + "\n\n\ + ***************************************************\n\ + ***************************************************\n\ + The MCS data has been written into the PROM. \n\ + To reprogram the FPGA with the new PROM data, \n\ + a IPROG CMD or power cycle is be required.\n\ + ***************************************************\n\ + ***************************************************\n\n"\ + , bg='green', + ) def eraseProm(self): # Set the starting address index @@ -167,7 +174,7 @@ def eraseProm(self): # Increment by one block address += ERASE_SIZE # Check the corner case - if ( address