diff --git a/.github/workflows/surf_ci.yml b/.github/workflows/surf_ci.yml index e7e146608a..b1701dde26 100644 --- a/.github/workflows/surf_ci.yml +++ b/.github/workflows/surf_ci.yml @@ -125,6 +125,9 @@ jobs: export PATH="${HOME}/miniconda/bin:$PATH" source ${HOME}/miniconda/etc/profile.d/conda.sh conda config --set always_yes yes + conda config --set channel_priority strict + conda install -n base conda-libmamba-solver + conda config --set solver libmamba conda install conda-build anaconda-client conda-verify conda update -q conda conda-build conda update --all @@ -149,5 +152,5 @@ jobs: export PATH="${HOME}/miniconda/bin:$PATH" source ${HOME}/miniconda/etc/profile.d/conda.sh conda build --debug conda-recipe --output-folder bld-dir -c tidair-tag -c tidair-packages -c conda-forge - anaconda -t ${{ steps.get_image_info.outputs.token }} upload --force bld-dir/${{ steps.get_image_info.outputs.os }}/*.tar.bz2 + anaconda -t ${{ steps.get_image_info.outputs.token }} upload --force bld-dir/noarch/*.tar.bz2 diff --git a/.gitignore b/.gitignore index 82dc520b9a..6310ee05e8 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,6 @@ +# EMACS temp files +*~ + # Compiled source files *.o *.pyc diff --git a/axi/axi-lite/rtl/AxiVersionLegacy.vhd b/axi/axi-lite/rtl/AxiVersionLegacy.vhd deleted file mode 100644 index d2d483902c..0000000000 --- a/axi/axi-lite/rtl/AxiVersionLegacy.vhd +++ /dev/null @@ -1,250 +0,0 @@ -------------------------------------------------------------------------------- --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: Creates AXI accessible registers containing configuration --- information. This is a legacy version for backward compatibility. -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - - -library surf; -use surf.StdRtlPkg.all; -use surf.AxiLitePkg.all; - -entity AxiVersionLegacy is - generic ( - TPD_G : time := 1 ns; - BUILD_INFO_G : BuildInfoType; - SIM_DNA_VALUE_G : slv := X"000000000000000000000000"; - DEVICE_ID_G : slv(31 downto 0) := (others => '0'); - CLK_PERIOD_G : real := 8.0E-9; -- units of seconds - XIL_DEVICE_G : string := "7SERIES"; -- Either "7SERIES" or "ULTRASCALE" - EN_DEVICE_DNA_G : boolean := false; - EN_DS2411_G : boolean := false; - EN_ICAP_G : boolean := false; - USE_SLOWCLK_G : boolean := false; - BUFR_CLK_DIV_G : positive := 8; - AUTO_RELOAD_EN_G : boolean := false; - AUTO_RELOAD_TIME_G : positive := 10; -- units of seconds - AUTO_RELOAD_ADDR_G : slv(31 downto 0) := (others => '0')); - port ( - -- AXI-Lite Interface - axiClk : in sl; - axiRst : in sl; - axiReadMaster : in AxiLiteReadMasterType; - axiReadSlave : out AxiLiteReadSlaveType; - axiWriteMaster : in AxiLiteWriteMasterType; - axiWriteSlave : out AxiLiteWriteSlaveType; - -- Optional: User Reset - userReset : out sl; - -- Optional: FPGA Reloading Interface - fpgaEnReload : in sl := '1'; - fpgaReload : out sl; - fpgaReloadAddr : out slv(31 downto 0); - upTimeCnt : out slv(31 downto 0); - -- Optional: Serial Number outputs - slowClk : in sl := '0'; - dnaValueOut : out slv(127 downto 0); - fdValueOut : out slv(63 downto 0); - -- Optional: user values - userValues : in Slv32Array(0 to 63) := (others => X"00000000"); - -- Optional: DS2411 interface - fdSerSdio : inout sl := 'Z'); -end AxiVersionLegacy; - -architecture rtl of AxiVersionLegacy is - - constant TIMEOUT_1HZ_C : natural := (getTimeRatio(1.0, CLK_PERIOD_G) -1); - constant COUNTER_ZERO_C : slv(31 downto 0) := X"00000000"; - - constant BUILD_INFO_C : BuildInfoRetType := toBuildInfo(BUILD_INFO_G); - constant BUILD_STRING_ROM_C : Slv32Array(0 to 63) := BUILD_INFO_C.buildString; - - type RegType is record - upTimeCnt : slv(31 downto 0); - timer : natural range 0 to TIMEOUT_1HZ_C; - scratchPad : slv(31 downto 0); - reloadTimer : slv(31 downto 0); - userReset : sl; - fpgaReload : sl; - haltReload : sl; - fpgaReloadAddr : slv(31 downto 0); - axiReadSlave : AxiLiteReadSlaveType; - axiWriteSlave : AxiLiteWriteSlaveType; - end record RegType; - - constant REG_INIT_C : RegType := ( - upTimeCnt => (others => '0'), - timer => 0, - scratchPad => (others => '0'), - reloadTimer => (others => '0'), - userReset => '1', -- Asserted on powerup - fpgaReload => '0', - haltReload => '0', - fpgaReloadAddr => AUTO_RELOAD_ADDR_G, - axiReadSlave => AXI_LITE_READ_SLAVE_INIT_C, - axiWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C); - - signal r : RegType := REG_INIT_C; - signal rin : RegType; - - signal dnaValue : slv(127 downto 0) := (others => '0'); - signal fdValue : slv(63 downto 0) := (others => '0'); - - attribute rom_style : string; - attribute rom_style of BUILD_STRING_ROM_C : constant is "distributed"; - attribute rom_extract : string; - attribute rom_extract of BUILD_STRING_ROM_C : constant is "TRUE"; - attribute syn_keep : string; - attribute syn_keep of BUILD_STRING_ROM_C : constant is "TRUE"; - -begin - - dnaValueOut <= dnaValue; - fdValueOut <= fdValue; - - GEN_DEVICE_DNA : if (EN_DEVICE_DNA_G) generate - DeviceDna_1 : entity surf.DeviceDna - generic map ( - TPD_G => TPD_G, - USE_SLOWCLK_G => USE_SLOWCLK_G, - BUFR_CLK_DIV_G => BUFR_CLK_DIV_G, - XIL_DEVICE_G => XIL_DEVICE_G, - SIM_DNA_VALUE_G => SIM_DNA_VALUE_G) - port map ( - clk => axiClk, - rst => axiRst, - slowClk => slowClk, - dnaValue => dnaValue); - end generate GEN_DEVICE_DNA; - - GEN_DS2411 : if (EN_DS2411_G) generate - DS2411Core_1 : entity surf.DS2411Core - generic map ( - TPD_G => TPD_G, - CLK_PERIOD_G => CLK_PERIOD_G) - port map ( - clk => axiClk, - rst => axiRst, - fdSerSdio => fdSerSdio, - fdValue => fdValue); - end generate GEN_DS2411; - - GEN_ICAP : if (EN_ICAP_G) generate - Iprog_1 : entity surf.Iprog - generic map ( - TPD_G => TPD_G, - USE_SLOWCLK_G => USE_SLOWCLK_G, - BUFR_CLK_DIV_G => BUFR_CLK_DIV_G, - XIL_DEVICE_G => XIL_DEVICE_G) - port map ( - clk => axiClk, - rst => axiRst, - slowClk => slowClk, - start => r.fpgaReload, - bootAddress => r.fpgaReloadAddr); - end generate; - - comb : process (axiReadMaster, axiRst, axiWriteMaster, dnaValue, fdValue, - fpgaEnReload, r, userValues) is - variable v : RegType; - variable axilEp : AxiLiteEndpointType; - begin - -- Latch the current value - v := r; - - ------------------------ - -- AXI-Lite Transactions - ------------------------ - - -- Determine the transaction type - axiSlaveWaitTxn(axilEp, axiWriteMaster, axiReadMaster, v.axiWriteSlave, v.axiReadSlave); - - axiSlaveRegisterR(axilEp, X"000", 0, BUILD_INFO_C.fwVersion); - axiSlaveRegister(axilEp, X"004", 0, v.scratchPad); - axiSlaveRegisterR(axilEp, X"008", 0, dnaValue(63 downto 0)); - axiSlaveRegisterR(axilEp, X"010", 0, fdValue); - axiSlaveRegister(axilEp, X"018", 0, v.userReset); - - axiSlaveRegister(axilEp, X"01C", 0, v.fpgaReload); - axiSlaveRegister(axilEp, X"020", 0, v.fpgaReloadAddr); - axiSlaveRegister(axilEp, X"024", 0, v.reloadTimer, COUNTER_ZERO_C); - axiSlaveRegister(axilEp, X"028", 0, v.haltReload); - axiSlaveRegisterR(axilEp, X"02C", 0, r.upTimeCnt); - axiSlaveRegisterR(axilEp, X"030", 0, DEVICE_ID_G); - - axiSlaveRegisterR(axilEp, X"100", 0, BUILD_INFO_C.gitHash(63 downto 32)); - - axiSlaveRegisterR(axilEp, X"400", userValues); - axiSlaveRegisterR(axilEp, X"800", BUILD_STRING_ROM_C); - - -- Close the transaction - axiSlaveDefault(axilEp, v.axiWriteSlave, v.axiReadSlave, AXI_RESP_DECERR_C); - - --------------------------------- - -- Uptime counter - --------------------------------- - if r.timer = TIMEOUT_1HZ_C then - -- Reset the counter - v.timer := 0; - - -- Increment the Counter - v.upTimeCnt := r.upTimeCnt + 1; - - --------------------------------- - -- First Stage Boot Loader (FSBL) - --------------------------------- - -- Check if timer enabled - if (fpgaEnReload = '1') and (r.reloadTimer /= AUTO_RELOAD_TIME_G) then - v.reloadTimer := r.reloadTimer + 1; - end if; - - -- Check for reload condition - if AUTO_RELOAD_EN_G and (r.reloadTimer = AUTO_RELOAD_TIME_G) and (fpgaEnReload = '1') and (r.haltReload = '0') then - v.fpgaReload := '1'; - end if; - - else - v.timer := r.timer + 1; - end if; - - -------- - -- Reset - -------- - if (axiRst = '1') then - v := REG_INIT_C; - end if; - - -- Register the variable for next clock cycle - rin <= v; - - -- Outputs - axiReadSlave <= r.axiReadSlave; - axiWriteSlave <= r.axiWriteSlave; - fpgaReload <= r.fpgaReload; - fpgaReloadAddr <= r.fpgaReloadAddr; - userReset <= r.userReset; - upTimeCnt <= r.upTimeCnt; - - end process comb; - - seq : process (axiClk) is - begin - if (rising_edge(axiClk)) then - r <= rin after TPD_G; - end if; - end process seq; - -end architecture rtl; diff --git a/conda-recipe/build.sh b/conda-recipe/build.sh index 50810c1593..95121e5942 100644 --- a/conda-recipe/build.sh +++ b/conda-recipe/build.sh @@ -1,4 +1,4 @@ #!/usr/bin/bash - -python setup.py install + +$PYTHON -m pip install . diff --git a/conda-recipe/meta.yaml b/conda-recipe/meta.yaml index ada14515f6..712dd325ff 100644 --- a/conda-recipe/meta.yaml +++ b/conda-recipe/meta.yaml @@ -7,17 +7,17 @@ source: build: number: {{ GIT_DESCRIBE_NUMBER|int }} + noarch: python requirements: - build: - - python<3.8 - - rogue + + host: + - python>=3.7 - git - gitpython - - numpy run: - - python + - python>=3.7 - rogue - numpy diff --git a/protocols/ssi/rtl/SsiPrbsTxOld.vhd b/protocols/ssi/rtl/SsiPrbsTxOld.vhd deleted file mode 100644 index b0b88835aa..0000000000 --- a/protocols/ssi/rtl/SsiPrbsTxOld.vhd +++ /dev/null @@ -1,259 +0,0 @@ -------------------------------------------------------------------------------- --- Title : SSI Protocol: https://confluence.slac.stanford.edu/x/0oyfD -------------------------------------------------------------------------------- --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: This module generates --- PseudoRandom Binary Sequence (PRBS) on Virtual Channel Lane. -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - - -library surf; -use surf.StdRtlPkg.all; -use surf.AxiStreamPkg.all; -use surf.SsiPkg.all; - -entity SsiPrbsTxOld is - generic ( - -- General Configurations - TPD_G : time := 1 ns; - -- FIFO Configurations - MEMORY_TYPE_G : string := "block"; - GEN_SYNC_FIFO_G : boolean := false; - CASCADE_SIZE_G : natural range 1 to (2**24) := 1; - FIFO_ADDR_WIDTH_G : natural range 4 to 48 := 9; - FIFO_PAUSE_THRESH_G : natural range 1 to (2**24) := 2**8; - -- PRBS Configurations - PRBS_SEED_SIZE_G : natural range 32 to 128 := 32; - PRBS_TAPS_G : NaturalArray := (0 => 31, 1 => 6, 2 => 2, 3 => 1); - -- AXI Stream Configurations - MASTER_AXI_STREAM_CONFIG_G : AxiStreamConfigType; - MASTER_AXI_PIPE_STAGES_G : natural range 0 to 16 := 0); - port ( - -- Master Port (mAxisClk) - mAxisClk : in sl; - mAxisRst : in sl; - mAxisMaster : out AxiStreamMasterType; - mAxisSlave : in AxiStreamSlaveType; - -- Trigger Signal (locClk domain) - locClk : in sl; - locRst : in sl := '0'; - trig : in sl := '1'; - packetLength : in slv(31 downto 0) := X"FFFFFFFF"; - forceEofe : in sl := '0'; - busy : out sl; - tDest : in slv(7 downto 0) := X"00"; - tId : in slv(7 downto 0) := X"00"); -end SsiPrbsTxOld; - -architecture rtl of SsiPrbsTxOld is - - constant PRBS_BYTES_C : natural := (PRBS_SEED_SIZE_G/8); - constant PRBS_SSI_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(PRBS_BYTES_C, TKEEP_COMP_C); - - type StateType is ( - IDLE_S, - SEED_RAND_S, - LENGTH_S, - DATA_S); - - type RegType is record - busy : sl; - overflow : sl; - packetLength : slv(31 downto 0); - dataCnt : slv(31 downto 0); - eventCnt : slv(PRBS_SEED_SIZE_G-1 downto 0); - randomData : slv(PRBS_SEED_SIZE_G-1 downto 0); - txMaster : AxiStreamMasterType; - state : StateType; - end record; - - constant REG_INIT_C : RegType := ( - '1', - '0', - (others => '0'), - (others => '0'), - (others => '0'), - (others => '0'), - AXI_STREAM_MASTER_INIT_C, - IDLE_S); - - signal r : RegType := REG_INIT_C; - signal rin : RegType; - - signal txCtrl : AxiStreamCtrlType; - -begin - - assert (PRBS_SEED_SIZE_G mod 8 = 0) report "PRBS_SEED_SIZE_G must be a multiple of 8" severity failure; - - comb : process (forceEofe, locRst, packetLength, r, tDest, tId, trig, txCtrl) is - variable v : RegType; - begin - -- Latch the current value - v := r; - - -- Reset strobing signals - ssiResetFlags(v.txMaster); - v.txMaster.tData := (others => '0'); - - -- Check for overflow condition or forced EOFE - if (txCtrl.overflow = '1') or (forceEofe = '1') then - -- Latch the overflow error bit for the data packet - v.overflow := '1'; - end if; - - -- State Machine - case (r.state) is - ---------------------------------------------------------------------- - when IDLE_S => - -- Reset the busy flag - v.busy := '0'; - -- Check for a trigger - if trig = '1' then - -- Latch the generator seed - v.randomData := r.eventCnt; - -- Set the busy flag - v.busy := '1'; - -- Reset the overflow flag - v.overflow := '0'; - -- Latch the configuration - v.txMaster.tDest := tDest; - v.txMaster.tId := tId; - -- Check the packet length request value - if packetLength = 0 then - -- Force minimum packet length of 2 (+1) - v.packetLength := toSlv(2, 32); - elsif packetLength = 1 then - -- Force minimum packet length of 2 (+1) - v.packetLength := toSlv(2, 32); - else - -- Latch the packet length - v.packetLength := packetLength; - end if; - -- Next State - v.state := SEED_RAND_S; - end if; - ---------------------------------------------------------------------- - when SEED_RAND_S => - -- Check if the FIFO is ready - if txCtrl.pause = '0' then - -- Send the random seed word - v.txMaster.tvalid := '1'; - v.txMaster.tData(PRBS_SEED_SIZE_G-1 downto 0) := r.eventCnt; - -- Generate the next random data word - v.randomData := lfsrShift(r.randomData, PRBS_TAPS_G); - -- Increment the counter - v.eventCnt := r.eventCnt + 1; - -- Increment the counter - v.dataCnt := r.dataCnt + 1; - -- Set the SOF bit - ssiSetUserSof(PRBS_SSI_CONFIG_C, v.txMaster, '1'); - -- Next State - v.state := LENGTH_S; - end if; - ---------------------------------------------------------------------- - when LENGTH_S => - -- Check if the FIFO is ready - if txCtrl.pause = '0' then - -- Send the upper packetLength value - v.txMaster.tvalid := '1'; - v.txMaster.tData(31 downto 0) := r.packetLength; - -- Increment the counter - v.dataCnt := r.dataCnt + 1; - -- Next State - v.state := DATA_S; - end if; - ---------------------------------------------------------------------- - when DATA_S => - -- Check if the FIFO is ready - if txCtrl.pause = '0' then - -- Send the random data word - v.txMaster.tValid := '1'; - v.txMaster.tData(PRBS_SEED_SIZE_G-1 downto 0) := r.randomData; - -- Generate the next random data word - v.randomData := lfsrShift(r.randomData, PRBS_TAPS_G); - -- Increment the counter - v.dataCnt := r.dataCnt + 1; - -- Check the counter - if r.dataCnt = r.packetLength then - -- Reset the counter - v.dataCnt := (others => '0'); - -- Set the EOF bit - v.txMaster.tLast := '1'; - -- Set the EOFE bit - ssiSetUserEofe(PRBS_SSI_CONFIG_C, v.txMaster, r.overflow); - -- Reset the busy flag - v.busy := '0'; - -- Next State - v.state := IDLE_S; - end if; - end if; - ---------------------------------------------------------------------- - end case; - - -- Reset - if (locRst = '1') then - v := REG_INIT_C; - end if; - - -- Register the variable for next clock cycle - rin <= v; - - -- Outputs - busy <= r.busy; - - end process comb; - - seq : process (locClk) is - begin - if rising_edge(locClk) then - r <= rin after TPD_G; - end if; - end process seq; - - AxiStreamFifo_Inst : entity surf.AxiStreamFifoV2 - generic map( - -- General Configurations - TPD_G => TPD_G, - PIPE_STAGES_G => MASTER_AXI_PIPE_STAGES_G, - SLAVE_READY_EN_G => false, - VALID_THOLD_G => 1, - -- FIFO configurations - MEMORY_TYPE_G => MEMORY_TYPE_G, - GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_G, - CASCADE_SIZE_G => CASCADE_SIZE_G, - FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, - FIFO_FIXED_THRESH_G => true, - FIFO_PAUSE_THRESH_G => FIFO_PAUSE_THRESH_G, - CASCADE_PAUSE_SEL_G => (CASCADE_SIZE_G-1), - -- AXI Stream Port Configurations - SLAVE_AXI_CONFIG_G => PRBS_SSI_CONFIG_C, - MASTER_AXI_CONFIG_G => MASTER_AXI_STREAM_CONFIG_G) - port map ( - -- Slave Port - sAxisClk => locClk, - sAxisRst => locRst, - sAxisMaster => r.txMaster, - sAxisSlave => open, - sAxisCtrl => txCtrl, - -- Master Port - mAxisClk => mAxisClk, - mAxisRst => mAxisRst, - mAxisMaster => mAxisMaster, - mAxisSlave => mAxisSlave); - -end rtl; diff --git a/python/surf/axi/_AxiVersionLegacy.py b/python/surf/axi/_AxiVersionLegacy.py deleted file mode 100644 index 0667610608..0000000000 --- a/python/surf/axi/_AxiVersionLegacy.py +++ /dev/null @@ -1,225 +0,0 @@ -#----------------------------------------------------------------------------- -# Title : PyRogue AXI-Lite Version Module -#----------------------------------------------------------------------------- -# Description: -# PyRogue AXI-Lite Version Module -#----------------------------------------------------------------------------- -# This file is part of the 'SLAC Firmware Standard Library'. It is subject to -# the license terms in the LICENSE.txt file found in the top-level directory -# of this distribution and at: -# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -# No part of the 'SLAC Firmware Standard Library', including this file, may be -# copied, modified, propagated, or distributed except according to the terms -# contained in the LICENSE.txt file. -#----------------------------------------------------------------------------- - -# Comment added by rherbst for demonstration purposes. - -import pyrogue as pr - -import datetime - -# Another comment added by rherbst for demonstration -# Yet Another comment added by rherbst for demonstration - -class AxiVersionLegacy(pr.Device): - - # Last comment added by rherbst for demonstration. - def __init__( - self, *, - numUserConstants = 0, - hasUpTimeCnt=True, - hasFpgaReloadHalt=True, - hasDeviceId=True, - hasGitHash=True, - dnaBigEndian=False, - **kwargs): - - super().__init__(**kwargs) - - ############################## - # Variables - ############################## - - - - self.add(pr.RemoteVariable( - name = 'FpgaVersion', - description = 'FPGA Firmware Version Number', - offset = 0x00, - bitSize = 32, - bitOffset = 0x00, - base = pr.UInt, - mode = 'RO', - disp = '{:#08x}', - )) - - self.add(pr.RemoteVariable( - name = 'ScratchPad', - description = 'Register to test reads and writes', - offset = 0x04, - bitSize = 32, - bitOffset = 0x00, - base = pr.UInt, - mode = 'RW', - disp = '{:#08x}', - )) - - if hasUpTimeCnt: - self.add(pr.RemoteVariable( - name = 'UpTimeCnt', - description = 'Number of seconds since last reset', - hidden = True, - offset = 0x02C, - bitSize = 32, - bitOffset = 0x00, - base = pr.UInt, - mode = 'RO', - disp = '{:d}', - units = 'seconds', - pollInterval = 1, - )) - - self.add(pr.LinkVariable( - name = 'UpTime', - dependencies = [self.UpTimeCnt], - linkedGet = lambda: str(datetime.timedelta(seconds=self.UpTimeCnt.value())) - )) - - - if hasFpgaReloadHalt: - self.add(pr.RemoteVariable( - name = 'FpgaReloadHalt', - description = 'Used to halt automatic reloads via AxiVersion', - offset = 0x28, - bitSize = 1, - bitOffset = 0x00, - base = pr.UInt, - mode = 'RW', - hidden = True, - )) - - self.add(pr.RemoteCommand( - name = 'FpgaReload', - description = 'Optional Reload the FPGA from the attached PROM', - offset = 0x1C, - bitSize = 1, - bitOffset = 0x00, - base = pr.UInt, - function = pr.RemoteCommand.postedTouchOne - )) - - self.add(pr.RemoteVariable( - name = 'FpgaReloadAddress', - description = 'Reload start address', - offset = 0x020, - bitSize = 32, - bitOffset = 0x00, - base = pr.UInt, - mode = 'RW', - )) - -# self.add(pr.RemoteVariable( -# name = 'UserReset', -# description = 'Optional User Reset', -# offset = 0x018, -# bitSize = 1, -# bitOffset = 0x00, -# base = pr.UInt, -# mode = 'RW', -# )) - - def endianSwap(var): - base = var.dependencies[0].value() - if dnaBigEndian: - return ((base >>32)&0xFFFFFFFF) | ((base << 32)&0xFFFFFFFF00000000) - else: - return base - - self.add(pr.RemoteVariable( - name = 'FdSerialRaw', - description = 'Board ID value read from DS2411 chip', - offset = 0x10, - bitSize = 64, - bitOffset = 0x00, - base = pr.UInt, - mode = 'RO', - disp = '{:#08x}', - hidden = True, - )) - - self.add(pr.LinkVariable( - name = 'FdSerial', - disp = '{:#08x}', - dependencies = [self.FdSerialRaw], - linkedGet = endianSwap)) - - self.add(pr.RemoteVariable( - name = 'DeviceDnaRaw', - description = 'Xilinx Device DNA value burned into FPGA', - offset = 0x8, - bitSize = 64, - bitOffset = 0x00, - base = pr.UInt, - mode = 'RO', - hidden = True - )) - - self.add(pr.LinkVariable( - name = 'DeviceDna', - disp = '{:#08x}', - dependencies = [self.DeviceDnaRaw], - linkedGet = endianSwap)) - - if hasDeviceId: - self.add(pr.RemoteVariable( - name = 'DeviceId', - description = 'Device Identification (configued by generic)', - offset = 0x030, - bitSize = 32, - bitOffset = 0x00, - base = pr.UInt, - mode = 'RO', - )) - - if hasGitHash: - self.add(pr.RemoteVariable( - name = 'GitHash', - description = 'GIT SHA-1 Hash', - offset = 0x100, - bitSize = 160, - bitOffset = 0x00, - base = pr.UInt, - mode = 'RO', - hidden = True, - )) - - self.add(pr.LinkVariable( - name = 'GitHashShort', - dependencies = [self.GitHash], - disp = '{:07x}', - linkedGet = lambda: self.GitHash.value() >> 132 - )) - - self.add(pr.RemoteVariable( - name = 'BuildStamp', - description = 'Firmware Build String', - offset = 0x800, - bitSize = 8*256, - bitOffset = 0x00, - base = pr.String, - mode = 'RO', - )) - - self.addRemoteVariables( - name = 'UserConstants', - description = 'Optional user input values', - offset = 0x400, - bitSize = 32, - bitOffset = 0x00, - base = pr.UInt, - mode = 'RO', - number = numUserConstants, - stride = 4, - hidden = True, - ) diff --git a/python/surf/axi/__init__.py b/python/surf/axi/__init__.py index e893cbf94b..8ce40fc787 100644 --- a/python/surf/axi/__init__.py +++ b/python/surf/axi/__init__.py @@ -15,7 +15,6 @@ from surf.axi._AxiMonAxiL import * from surf.axi._AxiRateGen import * from surf.axi._AxiVersion import * -from surf.axi._AxiVersionLegacy import * from surf.axi._AxiStreamDmaFifo import * from surf.axi._AxiStreamDmaV2Fifo import * from surf.axi._AxiStreamDmaV2 import * diff --git a/python/surf/xilinx/_AxiPciePhy.py b/python/surf/xilinx/_AxiPciePhy.py index 4d5ac70028..4cd76480ff 100644 --- a/python/surf/xilinx/_AxiPciePhy.py +++ b/python/surf/xilinx/_AxiPciePhy.py @@ -261,7 +261,7 @@ def __init__( self.add(pr.RemoteVariable( name = 'LnkStaWidth', offset = 0x70 + 0x12, - bitSize = 4, + bitSize = 8, bitOffset = 4, mode = 'RO', units = 'lanes', diff --git a/python/surf/xilinx/_RfDataConverter.py b/python/surf/xilinx/_RfDataConverter.py index 1180bab72b..ce327e91f2 100644 --- a/python/surf/xilinx/_RfDataConverter.py +++ b/python/surf/xilinx/_RfDataConverter.py @@ -14,7 +14,8 @@ #----------------------------------------------------------------------------- import pyrogue as pr -import surf.xilinx +import surf.xilinx as xil +import time class RfDataConverter(pr.Device): def __init__( @@ -103,7 +104,7 @@ def __init__( )) for i in range(4): - self.add(surf.xilinx.RfTile( + self.add(xil.RfTile( name = f'dacTile[{i}]', isAdc = False, gen3 = gen3, @@ -112,10 +113,32 @@ def __init__( )) for i in range(4): - self.add(surf.xilinx.RfTile( + self.add(xil.RfTile( name = f'adcTile[{i}]', isAdc = True, gen3 = gen3, offset = 0x14000 + 0x4000*i, expand = False, )) + + def Init(self, dynamicNco=False): + + # Useful pointers + rfTile = self.find(typ=xil.RfTile) + + # Reset the RF Data Converter + for tile in rfTile: + tile.RestartStateStart.set(0) + tile.RestartStateEnd.set(15) + tile.RestartSM.set(0x1) + self.Reset.set(0x1) + for tile in rfTile: + tile.RestartSM.set(0x1) + while tile.RestartStateEnd.get() != 15: + time.sleep(0.1) + + # Check for dynamic NCO + if dynamicNco: + # Change the RestartStateStart for dynamic NCO changes + for tile in rfTile: + tile.RestartStateStart.setDisp('Clock_Configuration[0]') diff --git a/setup.py b/setup.py index fbdce6cf9f..d8767c7aba 100644 --- a/setup.py +++ b/setup.py @@ -1,5 +1,6 @@ -from distutils.core import setup +from setuptools import setup + from git import Repo repo = Repo()