diff --git a/axi/axi-stream/rtl/AxiStreamMon.vhd b/axi/axi-stream/rtl/AxiStreamMon.vhd index 42cca81c37..2d1660f804 100644 --- a/axi/axi-stream/rtl/AxiStreamMon.vhd +++ b/axi/axi-stream/rtl/AxiStreamMon.vhd @@ -17,7 +17,6 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; - library surf; use surf.StdRtlPkg.all; use surf.AxiStreamPkg.all; @@ -38,6 +37,9 @@ entity AxiStreamMon is statusClk : in sl; statusRst : in sl; frameCnt : out slv(63 downto 0); -- units of frames + frameSize : out slv(31 downto 0); -- units of Byte + frameSizeMax : out slv(31 downto 0); -- units of Byte + frameSizeMin : out slv(31 downto 0); -- units of Byte frameRate : out slv(31 downto 0); -- units of Hz frameRateMax : out slv(31 downto 0); -- units of Hz frameRateMin : out slv(31 downto 0); -- units of Hz @@ -52,25 +54,33 @@ architecture rtl of AxiStreamMon is constant TIMEOUT_C : natural := getTimeRatio(AXIS_CLK_FREQ_G, 1.0)-1; type RegType is record - frameSent : sl; - tValid : sl; - tKeep : slv(AXI_STREAM_MAX_TKEEP_WIDTH_C-1 downto 0); - updated : sl; - timer : natural range 0 to TIMEOUT_C; - accum : slv(39 downto 0); - bandwidth : slv(39 downto 0); - frameCnt : slv(63 downto 0); + frameSent : sl; + sizeValid : sl; + armed : sl; + tValid : sl; + tKeep : slv(AXI_STREAM_MAX_TKEEP_WIDTH_C-1 downto 0); + updated : sl; + timer : natural range 0 to TIMEOUT_C; + accum : slv(39 downto 0); + bandwidth : slv(39 downto 0); + frameAccum : slv(31 downto 0); + frameSize : slv(31 downto 0); + frameCnt : slv(63 downto 0); end record; constant REG_INIT_C : RegType := ( - frameSent => '0', - tValid => '0', - tKeep => (others => '0'), - updated => '0', - timer => 0, - accum => (others => '0'), - bandwidth => (others => '0'), - frameCnt => (others => '0')); + frameSent => '0', + sizeValid => '0', + armed => '0', + tValid => '0', + tKeep => (others => '0'), + updated => '0', + timer => 0, + accum => (others => '0'), + bandwidth => (others => '0'), + frameAccum => (others => '0'), + frameSize => (others => '0'), + frameCnt => (others => '0')); signal r : RegType := REG_INIT_C; signal rin : RegType; @@ -164,8 +174,9 @@ begin v := r; -- Reset strobing signals - v.tValid := '0'; - v.updated := '0'; + v.tValid := '0'; + v.updated := '0'; + v.sizeValid := '0'; -- Check for end of frame v.frameSent := axisMaster.tValid and axisMaster.tLast and axisSlave.tReady; @@ -184,13 +195,28 @@ begin end if; -- Check if last cycle had data moving - if r.tValid = '1' then + if (r.tValid = '1') then + -- Update the accumulator if (AXIS_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - v.accum := r.accum + conv_integer(r.tKeep(bitSize(AXIS_CONFIG_G.TDATA_BYTES_C)-1 downto 0)); + v.accum := r.accum + conv_integer(r.tKeep(bitSize(AXIS_CONFIG_G.TDATA_BYTES_C)-1 downto 0)); + v.frameAccum := r.frameAccum + conv_integer(r.tKeep(bitSize(AXIS_CONFIG_G.TDATA_BYTES_C)-1 downto 0)); else - v.accum := r.accum + getTKeep(r.tKeep, AXIS_CONFIG_G); + v.accum := r.accum + getTKeep(r.tKeep, AXIS_CONFIG_G); + v.frameAccum := r.frameAccum + getTKeep(r.tKeep, AXIS_CONFIG_G); + end if; + + -- Check for end of frame + if (r.frameSent = '1') then + -- Set the flag + v.sizeValid := r.armed; + v.frameSize := v.frameAccum; + -- Reset the accumulator + v.frameAccum := (others => '0'); + -- Confirmed that not in the middle of a frame since reset + v.armed := '1'; end if; + end if; -- Increment the timer @@ -232,6 +258,24 @@ begin end if; end process seq; + Sync_frameSize : entity surf.SyncMinMax + generic map ( + TPD_G => TPD_G, + COMMON_CLK_G => COMMON_CLK_G, + WIDTH_G => 32) + port map ( + -- ASYNC statistics reset + rstStat => axisRst, + -- Write Interface (wrClk domain) + wrClk => axisClk, + wrEn => r.sizeValid, + dataIn => r.frameSize, + -- Read Interface (rdClk domain) + rdClk => statusClk, + dataOut => frameSize, + dataMin => frameSizeMin, + dataMax => frameSizeMax); + Sync_bandwidth : entity surf.SyncMinMax generic map ( TPD_G => TPD_G, diff --git a/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd b/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd index 96073110a9..8e089b02ed 100644 --- a/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd +++ b/axi/axi-stream/rtl/AxiStreamMonAxiL.vhd @@ -17,7 +17,6 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; - library surf; use surf.StdRtlPkg.all; use surf.AxiStreamPkg.all; @@ -52,17 +51,17 @@ architecture rtl of AxiStreamMonAxiL is type RegType is record we : sl; data : slv(31 downto 0); + cnt : slv(ADDR_WIDTH_C-1 downto 0); addr : slv(ADDR_WIDTH_C-1 downto 0); ch : natural range 0 to AXIS_NUM_SLOTS_G-1; - wrd : natural range 0 to 15; end record; constant REG_INIT_C : RegType := ( we => '0', data => (others => '0'), + cnt => (others => '1'), -- pre-set to all ones so 1st write after reset is address=0x0 addr => (others => '1'), -- pre-set to all ones so 1st write after reset is address=0x0 - ch => 0, - wrd => 0); + ch => 0); signal r : RegType := REG_INIT_C; signal rin : RegType; @@ -71,16 +70,35 @@ architecture rtl of AxiStreamMonAxiL is signal localReset : sl; signal axisReset : sl; - signal frameCnt : Slv64Array(AXIS_NUM_SLOTS_G-1 downto 0); + signal frameCnt : Slv64Array(AXIS_NUM_SLOTS_G-1 downto 0); + + signal frameSize : Slv32Array(AXIS_NUM_SLOTS_G-1 downto 0); + signal frameSizeMax : Slv32Array(AXIS_NUM_SLOTS_G-1 downto 0); + signal frameSizeMin : Slv32Array(AXIS_NUM_SLOTS_G-1 downto 0); + signal frameRate : Slv32Array(AXIS_NUM_SLOTS_G-1 downto 0); signal frameRateMax : Slv32Array(AXIS_NUM_SLOTS_G-1 downto 0); signal frameRateMin : Slv32Array(AXIS_NUM_SLOTS_G-1 downto 0); + signal bandwidth : Slv64Array(AXIS_NUM_SLOTS_G-1 downto 0); signal bandwidthMax : Slv64Array(AXIS_NUM_SLOTS_G-1 downto 0); signal bandwidthMin : Slv64Array(AXIS_NUM_SLOTS_G-1 downto 0); - -- attribute dont_touch : string; - -- attribute dont_touch of r : signal is "true"; + -- attribute dont_touch : string; + -- attribute dont_touch of r : signal is "true"; + -- attribute dont_touch of rstCnt : signal is "true"; + -- attribute dont_touch of localReset : signal is "true"; + -- attribute dont_touch of axisReset : signal is "true"; + -- attribute dont_touch of frameCnt : signal is "true"; + -- attribute dont_touch of frameSize : signal is "true"; + -- attribute dont_touch of frameSizeMax : signal is "true"; + -- attribute dont_touch of frameSizeMin : signal is "true"; + -- attribute dont_touch of frameRate : signal is "true"; + -- attribute dont_touch of frameRateMax : signal is "true"; + -- attribute dont_touch of frameRateMin : signal is "true"; + -- attribute dont_touch of bandwidth : signal is "true"; + -- attribute dont_touch of bandwidthMax : signal is "true"; + -- attribute dont_touch of bandwidthMin : signal is "true"; begin @@ -112,13 +130,20 @@ begin axisRst => axisReset, axisMaster => axisMasters(i), axisSlave => axisSlaves(i), - -- Status Interface + -- Status Clock and reset statusClk => axisClk, statusRst => axisReset, + -- Status: Total number of frame received since statusRst frameCnt => frameCnt(i), + -- Status: Frame Size (units of Byte) + frameSize => frameSize(i), + frameSizeMax => frameSizeMax(i), + frameSizeMin => frameSizeMin(i), + -- Status: Frame rate (units of Hz) frameRate => frameRate(i), frameRateMax => frameRateMax(i), frameRateMin => frameRateMin(i), + -- Status: Bandwidth (units of Byte/s) bandwidth => bandwidth(i), bandwidthMax => bandwidthMax(i), bandwidthMin => bandwidthMin(i)); @@ -152,50 +177,96 @@ begin din => r.data); comb : process (axisRst, bandwidth, bandwidthMax, bandwidthMin, frameCnt, - frameRate, frameRateMax, frameRateMin, r) is - variable v : RegType; + frameRate, frameRateMax, frameRateMin, frameSize, + frameSizeMax, frameSizeMin, r) is + variable v : RegType; + variable wrd : slv(3 downto 0); begin -- Latch the current value v := r; + -- Increment the counter + v.cnt := r.cnt + 1; + -- Write the status counter to RAM v.we := '1'; - v.addr := r.addr + 1; - case (r.wrd) is - ---------------------------------------------------------------------- - when 1 => v.data := frameCnt(r.ch)(31 downto 0); -- i*0x40 + 0x04 - when 2 => v.data := frameCnt(r.ch)(63 downto 32); -- i*0x40 + 0x08 - when 3 => v.data := frameRate(r.ch); -- i*0x40 + 0x0C - when 4 => v.data := frameRateMax(r.ch); -- i*0x40 + 0x10 - when 5 => v.data := frameRateMin(r.ch); -- i*0x40 + 0x14 - when 6 => v.data := bandwidth(r.ch)(31 downto 0); -- i*0x40 + 0x18 - when 7 => v.data := bandwidth(r.ch)(63 downto 32); -- i*0x40 + 0x1C - when 8 => v.data := bandwidthMax(r.ch)(31 downto 0); -- i*0x40 + 0x20 - when 9 => v.data := bandwidthMax(r.ch)(63 downto 32); -- i*0x40 + 0x24 - when 10 => v.data := bandwidthMin(r.ch)(31 downto 0); -- i*0x40 + 0x28 - when 11 => v.data := bandwidthMin(r.ch)(63 downto 32); -- i*0x40 + 0x2C - when others => v.we := '0'; - ---------------------------------------------------------------------- + v.addr := v.cnt; + + -- Case on the word index + wrd := v.addr(3 downto 0); + case (wrd) is + ---------------------------------------------------------------------- + when x"0" => -- i*0x40 + 0x00: DMA AXI Stream Configuration (debugging) + + v.data(31 downto 24) := toSlv(AXIS_CONFIG_G.TDATA_BYTES_C, 8); + v.data(23 downto 20) := toSlv(AXIS_CONFIG_G.TDEST_BITS_C, 4); + v.data(19 downto 16) := toSlv(AXIS_CONFIG_G.TUSER_BITS_C, 4); + v.data(15 downto 12) := toSlv(AXIS_CONFIG_G.TID_BITS_C, 4); + + case AXIS_CONFIG_G.TKEEP_MODE_C is + when TKEEP_NORMAL_C => v.data(11 downto 8) := x"0"; + when TKEEP_COMP_C => v.data(11 downto 8) := x"1"; + when TKEEP_FIXED_C => v.data(11 downto 8) := x"2"; + when TKEEP_COUNT_C => v.data(11 downto 8) := x"3"; + when others => v.data(11 downto 8) := x"F"; + end case; + + case AXIS_CONFIG_G.TUSER_MODE_C is + when TUSER_NORMAL_C => v.data(7 downto 4) := x"0"; + when TUSER_FIRST_LAST_C => v.data(7 downto 4) := x"1"; + when TUSER_LAST_C => v.data(7 downto 4) := x"2"; + when TUSER_NONE_C => v.data(7 downto 4) := x"3"; + when others => v.data(7 downto 4) := x"F"; + end case; + + v.data(3) := '0'; + v.data(2) := '0'; + v.data(1) := ite(AXIS_CONFIG_G.TSTRB_EN_C, '1', '0'); + v.data(0) := ite(COMMON_CLK_G, '1', '0'); + + ---------------------------------------------------------------------- + when x"1" => v.data := frameCnt(r.ch)(31 downto 0); -- i*0x40 + 0x04 + when x"2" => v.data := frameCnt(r.ch)(63 downto 32); -- i*0x40 + 0x08 + ---------------------------------------------------------------------- + when x"3" => v.data := frameRate(r.ch); -- i*0x40 + 0x0C + when x"4" => v.data := frameRateMax(r.ch); -- i*0x40 + 0x10 + when x"5" => v.data := frameRateMin(r.ch); -- i*0x40 + 0x14 + ---------------------------------------------------------------------- + when x"6" => v.data := bandwidth(r.ch)(31 downto 0); -- i*0x40 + 0x18 + when x"7" => v.data := bandwidth(r.ch)(63 downto 32); -- i*0x40 + 0x1C + when x"8" => v.data := bandwidthMax(r.ch)(31 downto 0); -- i*0x40 + 0x20 + when x"9" => v.data := bandwidthMax(r.ch)(63 downto 32); -- i*0x40 + 0x24 + when x"A" => v.data := bandwidthMin(r.ch)(31 downto 0); -- i*0x40 + 0x28 + when x"B" => v.data := bandwidthMin(r.ch)(63 downto 32); -- i*0x40 + 0x2C + ---------------------------------------------------------------------- + when x"C" => v.data := frameSize(r.ch); -- i*0x40 + 0x30 + when x"D" => v.data := frameSizeMax(r.ch); -- i*0x40 + 0x34 + when x"E" => v.data := frameSizeMin(r.ch); -- i*0x40 + 0x38 + ---------------------------------------------------------------------- + when x"F" => -- i*0x40 + 0x3C: Debugging + v.data(7 downto 0) := toSlv(AXIS_NUM_SLOTS_G, 8); + v.data(15 downto 8) := toSlv(ADDR_WIDTH_C, 8); + v.data(23 downto 16) := toSlv(r.ch, 8); + v.data(31 downto 16) := (others => '0'); + ----------------------------------------------------------------------- + when others => + v.we := '0'; + ----------------------------------------------------------------------- end case; -- Check for last word - if (r.wrd = 15) then - - -- Reset the counter - v.wrd := 0; + if (wrd = x"F") then -- Check for last word if (r.ch = AXIS_NUM_SLOTS_G-1) then - -- Reset the counter - v.ch := 0; + -- Reset the counters + v.ch := 0; + v.cnt := (others => '1'); -- pre-set to all ones so 1st write after reset is address=0x0 else -- Increment the counters v.ch := r.ch + 1; end if; - else - -- Increment the counters - v.wrd := r.wrd + 1; end if; -- Synchronous Reset diff --git a/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd b/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd index f9e0f82d76..cb3acbdd4a 100644 --- a/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd +++ b/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd @@ -78,6 +78,8 @@ architecture rtl of Ad9249ReadoutGroup is readoutDebug1 : slv16Array(NUM_CHANNELS_G-1 downto 0); lockedCountRst : sl; invert : sl; + curDelayFrame : slv(4 downto 0); + curDelayData : slv5Array(NUM_CHANNELS_G-1 downto 0); end record; constant AXIL_REG_INIT_C : AxilRegType := ( @@ -90,7 +92,9 @@ architecture rtl of Ad9249ReadoutGroup is readoutDebug0 => (others => (others => '0')), readoutDebug1 => (others => (others => '0')), lockedCountRst => '0', - invert => '0' + invert => '0', + curDelayFrame => (others => '0'), + curDelayData => (others => (others => '0')) ); signal lockedSync : sl; @@ -212,7 +216,9 @@ begin v.dataDelaySet := (others => '0'); v.frameDelaySet := '0'; - v.axilReadSlave.rdata := (others => '0'); + + v.curDelayFrame := curDelayFrame; + v.curDelayData := curDelayData; -- Store last two samples read from ADC if (debugDataValid = '1' and axilR.freezeDebug = '0') then @@ -235,9 +241,9 @@ begin -- Override read from r.delay and use curDealy output from delay primative instead for i in 0 to NUM_CHANNELS_G-1 loop - axiSlaveRegisterR(axilEp, X"00"+toSlv((i*4), 8), 0, curDelayData(i)); + axiSlaveRegisterR(axilEp, X"00"+toSlv((i*4), 8), 0, axilR.curDelayData(i)); end loop; - axiSlaveRegisterR(axilEp, X"20", 0, curDelayFrame); + axiSlaveRegisterR(axilEp, X"20", 0, axilR.curDelayFrame); -- Debug output to see how many times the shift has needed a relock diff --git a/protocols/saci/rtl/SaciMaster2.vhd b/protocols/saci/rtl/SaciMaster2.vhd index c8592778ea..ef2d38fa2a 100644 --- a/protocols/saci/rtl/SaciMaster2.vhd +++ b/protocols/saci/rtl/SaciMaster2.vhd @@ -69,7 +69,7 @@ architecture rtl of SaciMaster2 is shiftCount : slv(5 downto 0); --Saci clk gen - clkCount : slv(SACI_CLK_COUNTER_SIZE_C-1 downto 0); + clkCount : slv(SACI_CLK_COUNTER_SIZE_C downto 0); saciClkRising : sl; saciClkFalling : sl; diff --git a/python/surf/axi/_AxiStreamMonAxiL.py b/python/surf/axi/_AxiStreamMonAxiL.py new file mode 100644 index 0000000000..9090126d3e --- /dev/null +++ b/python/surf/axi/_AxiStreamMonAxiL.py @@ -0,0 +1,306 @@ +#!/usr/bin/env python +#----------------------------------------------------------------------------- +# Title : PyRogue AXI-Lite Version Module +#----------------------------------------------------------------------------- +# File : AxiVersion.py +# Created : 2017-04-12 +#----------------------------------------------------------------------------- +# Description: +# PyRogue AXI-Lite Version Module +#----------------------------------------------------------------------------- +# This file is part of the rogue software platform. It is subject to +# the license terms in the LICENSE.txt file found in the top-level directory +# of this distribution and at: +# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +# No part of the rogue software platform, including this file, may be +# copied, modified, propagated, or distributed except according to the terms +# contained in the LICENSE.txt file. +#----------------------------------------------------------------------------- + +import pyrogue as pr + +class AxiStreamMonChannel(pr.Device): + def __init__(self, + name = "AxiStreamMonChannel", + description = "AxiStreamMonChannel Container", + **kwargs): + super().__init__(name=name, description=description, **kwargs) + + def addPair(name,offset,bitSize,units,bitOffset,description,function,pollInterval = 0,): + self.add(pr.RemoteVariable( + name = ("Raw"+name), + offset = offset, + bitSize = bitSize, + bitOffset = bitOffset, + base = pr.UInt, + mode = 'RO', + description = description, + pollInterval = pollInterval, + hidden = True, + )) + self.add(pr.LinkVariable( + name = name, + mode = 'RO', + units = units, + linkedGet = function, + disp = '{:1.1f}', + dependencies = [self.variables["Raw"+name]], + )) + + self.add(pr.RemoteVariable( + name = 'FrameCnt', + description = 'Increments every time a tValid + tLast + tReady detected', + offset = 0x04, + bitSize = 64, + mode = 'RO', + pollInterval = 1, + )) + + self.add(pr.RemoteVariable( + name = 'FrameRate', + description = "Current Frame Rate", + offset = 0x0C, + bitSize = 32, + bitOffset = 0, + mode = "RO", + base = pr.Int, + units = 'Hz', + pollInterval = 1, + )) + + self.add(pr.RemoteVariable( + name = 'FrameRateMax', + description = "Max Frame Rate", + offset = 0x10, + bitSize = 32, + bitOffset = 0, + mode = "RO", + base = pr.Int, + units = 'Hz', + pollInterval = 1, + )) + + self.add(pr.RemoteVariable( + name = 'FrameRateMin', + description = "Min Frame Rate", + offset = 0x14, + bitSize = 32, + bitOffset = 0, + mode = "RO", + base = pr.Int, + units = 'Hz', + pollInterval = 1, + )) + + addPair( + name = 'Bandwidth', + description = "Current Bandwidth", + offset = 0x18, + bitSize = 64, + bitOffset = 0, + function = self.convMbps, + units = 'Mbps', + pollInterval = 1, + ) + + addPair( + name = 'BandwidthMax', + description = "Max Bandwidth", + offset = 0x20, + bitSize = 64, + bitOffset = 0, + function = self.convMbps, + units = 'Mbps', + pollInterval = 1, + ) + + addPair( + name = 'BandwidthMin', + description = "Min Bandwidth", + offset = 0x28, + bitSize = 64, + bitOffset = 0, + function = self.convMbps, + units = 'Mbps', + pollInterval = 1, + ) + + self.add(pr.RemoteVariable( + name = 'FrameSize', + description = 'Current Frame Size. Note: Only valid for non-interleaved AXI stream frames', + offset = 0x30, + bitSize = 32, + bitOffset = 0, + mode = 'RO', + base = pr.Int, + units = 'Byte', + pollInterval = 1, + )) + + self.add(pr.RemoteVariable( + name = 'FrameSizeMax', + description = 'Max Frame Size. Note: Only valid for non-interleaved AXI stream frames', + offset = 0x34, + bitSize = 32, + bitOffset = 0, + mode = 'RO', + base = pr.Int, + units = 'Byte', + pollInterval = 1, + )) + + self.add(pr.RemoteVariable( + name = 'FrameSizeMin', + description = 'Min Frame Size. Note: Only valid for non-interleaved AXI stream frames', + offset = 0x38, + bitSize = 32, + bitOffset = 0, + mode = 'RO', + base = pr.Int, + units = 'Byte', + pollInterval = 1, + )) + + @staticmethod + def convMbps(var): + return var.dependencies[0].value() * 8e-6 + +class AxiStreamMonAxiL(pr.Device): + def __init__(self, + name = "AxiStreamMonAxiL", + description = "AxiStreamMonAxiL Container", + numberLanes = 1, + **kwargs): + super().__init__(name=name, description=description, **kwargs) + + self.add(pr.RemoteCommand( + name = 'CntRst', + description = "Counter Reset", + offset = 0x0, + bitSize = 1, + function = lambda cmd: cmd.post(1), + overlapEn = True, + )) + + self.add(pr.RemoteVariable( + name = 'AXIS_CONFIG_G_TDATA_BYTES_C', + offset = 0x0, + bitSize = 8, + bitOffset = 24, + mode = 'RO', + disp = '{:d}', + overlapEn = True, + )) + + self.add(pr.RemoteVariable( + name = 'AXIS_CONFIG_G_TDEST_BITS_C', + offset = 0x0, + bitSize = 4, + bitOffset = 20, + mode = 'RO', + disp = '{:d}', + overlapEn = True, + )) + + self.add(pr.RemoteVariable( + name = 'AXIS_CONFIG_G_TUSER_BITS_C', + offset = 0x0, + bitSize = 4, + bitOffset = 16, + mode = 'RO', + disp = '{:d}', + overlapEn = True, + )) + + self.add(pr.RemoteVariable( + name = 'AXIS_CONFIG_G_TID_BITS_C', + offset = 0x0, + bitSize = 4, + bitOffset = 12, + mode = 'RO', + overlapEn = True, + )) + + self.add(pr.RemoteVariable( + name = 'AXIS_CONFIG_G_TKEEP_MODE_C', + offset = 0x0, + bitSize = 4, + bitOffset = 8, + mode = 'RO', + enum = { + 0x0: 'TKEEP_NORMAL_C', + 0x1: 'TKEEP_COMP_C', + 0x2: 'TKEEP_FIXED_C', + 0x3: 'TKEEP_COUNT_C', + 0xF: 'UNDEFINED', + }, + overlapEn = True, + )) + + self.add(pr.RemoteVariable( + name = 'AXIS_CONFIG_G_TUSER_MODE_C', + offset = 0x0, + bitSize = 4, + bitOffset = 4, + mode = 'RO', + enum = { + 0x0: 'TUSER_NORMAL_C', + 0x1: 'TUSER_FIRST_LAST_C', + 0x2: 'TUSER_LAST_C', + 0x3: 'TUSER_NONE_C', + 0xF: 'UNDEFINED', + }, + overlapEn = True, + )) + + self.add(pr.RemoteVariable( + name = 'AXIS_CONFIG_G_TSTRB_EN_C', + offset = 0x0, + bitSize = 1, + bitOffset = 1, + mode = 'RO', + base = pr.Bool, + overlapEn = True, + )) + + self.add(pr.RemoteVariable( + name = 'COMMON_CLK_G', + offset = 0x0, + bitSize = 1, + bitOffset = 0, + mode = 'RO', + base = pr.Bool, + overlapEn = True, + )) + + for i in range(numberLanes): + self.add(AxiStreamMonChannel( + name = f'Ch[{i}]', + offset = (i*0x40), + expand = True, + )) + + def hardReset(self): + self.CntRst() + + def initialize(self): + self.CntRst() + + def countReset(self): + self.CntRst() + +class AxiStreamMonitoring(AxiStreamMonAxiL): + def __init__(self, + name = "AxiStreamMonitoring", + description = "AxiStreamMonitoring Container", + numberLanes = 1, + **kwargs + ): + super().__init__( + name = name, + description = description, + numberLanes = numberLanes, + **kwargs + ) + print( f'{self.path}: AxiStreamMonitoring device is now deprecated. Please use AxiStreamMonAxiL instead' ) + diff --git a/python/surf/axi/_AxiStreamMonitoring.py b/python/surf/axi/_AxiStreamMonitoring.py deleted file mode 100644 index 407190ef6e..0000000000 --- a/python/surf/axi/_AxiStreamMonitoring.py +++ /dev/null @@ -1,154 +0,0 @@ -#!/usr/bin/env python -#----------------------------------------------------------------------------- -# Title : PyRogue AXI-Lite Version Module -#----------------------------------------------------------------------------- -# File : AxiVersion.py -# Created : 2017-04-12 -#----------------------------------------------------------------------------- -# Description: -# PyRogue AXI-Lite Version Module -#----------------------------------------------------------------------------- -# This file is part of the rogue software platform. It is subject to -# the license terms in the LICENSE.txt file found in the top-level directory -# of this distribution and at: -# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -# No part of the rogue software platform, including this file, may be -# copied, modified, propagated, or distributed except according to the terms -# contained in the LICENSE.txt file. -#----------------------------------------------------------------------------- - -import pyrogue as pr - -class AxiStreamMonitoring(pr.Device): - def __init__(self, - name = "AxiStreamMonitoring", - description = "AxiStreamMonitoring Container", - numberLanes = 1, - **kwargs): - super().__init__(name=name, description=description, **kwargs) - - self.add(pr.RemoteCommand( - name = 'CntRst', - description = "Counter Reset", - offset = 0x0, - bitSize = 1, - function = lambda cmd: cmd.post(1), - )) - - def addPair(name,offset,bitSize,units,bitOffset,description,function,pollInterval = 0,): - self.add(pr.RemoteVariable( - name = ("Raw"+name), - offset = offset, - bitSize = bitSize, - bitOffset = bitOffset, - base = pr.UInt, - mode = 'RO', - description = description, - pollInterval = pollInterval, - hidden = True, - )) - self.add(pr.LinkVariable( - name = name, - mode = 'RO', - units = units, - linkedGet = function, - disp = '{:1.1f}', - dependencies = [self.variables["Raw"+name]], - )) - - ############################################# - # Create block / variable combinations - ############################################# - - for i in range(numberLanes): - - self.add(pr.RemoteVariable( - name = f'FrameCnt[{i}]', - description = 'Increments every time a tValid + tLast + tReady detected', - offset = (i*0x40 + 0x04), - bitSize = 64, - mode = 'RO', - pollInterval = 1, - )) - - self.add(pr.RemoteVariable( - name = f'FrameRate[{i}]', - description = "Current Frame Rate", - offset = (i*0x40 + 0x0C), - bitSize = 32, - bitOffset = 0, - mode = "RO", - base = pr.Int, - units = 'Hz', - pollInterval = 1, - )) - - self.add(pr.RemoteVariable( - name = f'FrameRateMax[{i}]', - description = "Max Frame Rate", - offset = (i*0x40 + 0x10), - bitSize = 32, - bitOffset = 0, - mode = "RO", - base = pr.Int, - units = 'Hz', - pollInterval = 1, - )) - - self.add(pr.RemoteVariable( - name = f'FrameRateMin[{i}]', - description = "Min Frame Rate", - offset = (i*0x40 + 0x14), - bitSize = 32, - bitOffset = 0, - mode = "RO", - base = pr.Int, - units = 'Hz', - pollInterval = 1, - )) - - addPair( - name = f'Bandwidth[{i}]', - description = "Current Bandwidth", - offset = (i*0x40 + 0x18), - bitSize = 64, - bitOffset = 0, - function = self.convMbps, - units = 'Mbps', - pollInterval = 1, - ) - - addPair( - name = f'BandwidthMax[{i}]', - description = "Max Bandwidth", - offset = (i*0x40 + 0x20), - bitSize = 64, - bitOffset = 0, - function = self.convMbps, - units = 'Mbps', - pollInterval = 1, - ) - - addPair( - name = f'BandwidthMin[{i}]', - description = "Min Bandwidth", - offset = (i*0x40 + 0x28), - bitSize = 64, - bitOffset = 0, - function = self.convMbps, - units = 'Mbps', - pollInterval = 1, - ) - - @staticmethod - def convMbps(var): - return var.dependencies[0].value() * 8e-6 - - def hardReset(self): - self.CntRst() - - def initialize(self): - self.CntRst() - - def countReset(self): - self.CntRst() diff --git a/python/surf/axi/__init__.py b/python/surf/axi/__init__.py index f5cd817f0f..a63af75243 100644 --- a/python/surf/axi/__init__.py +++ b/python/surf/axi/__init__.py @@ -12,7 +12,7 @@ from surf.axi._AxiLiteRingBuffer import * from surf.axi._AxiMemTester import * from surf.axi._AxiStreamDmaRingWrite import * -from surf.axi._AxiStreamMonitoring import * +from surf.axi._AxiStreamMonAxiL import * from surf.axi._AxiVersion import * from surf.axi._AxiVersionLegacy import * from surf.axi._AxiStreamDmaFifo import * diff --git a/python/apply_slac_license.py b/python/tools/apply_slac_license.py similarity index 100% rename from python/apply_slac_license.py rename to python/tools/apply_slac_license.py diff --git a/xilinx/general/sdk/common/ssi_printf.c b/xilinx/general/sdk/common/ssi_printf.c index 62669ec137..f95471c7b8 100644 --- a/xilinx/general/sdk/common/ssi_printf.c +++ b/xilinx/general/sdk/common/ssi_printf.c @@ -35,7 +35,12 @@ void ssi_putc ( void* p, char c) { // Dual port ram buffer if enabled if ( pp->buffSize > 0 ) { - Xil_Out8(pp->buffBase+4+pp->buffPtr, c); + //Xil_Out8(pp->buffBase+4+pp->buffPtr, c); + if (pp->buffPtr%4 == 0) + pp->buffWord = c; + else + pp->buffWord |= (c << (pp->buffPtr%4)*8); + Xil_Out32(pp->buffBase+4+(pp->buffPtr/4)*4, pp->buffWord); // Adjust pointer pp->buffPtr++; diff --git a/xilinx/general/sdk/common/ssi_printf.h b/xilinx/general/sdk/common/ssi_printf.h index 9f1bf4b2a3..c28aa6402d 100644 --- a/xilinx/general/sdk/common/ssi_printf.h +++ b/xilinx/general/sdk/common/ssi_printf.h @@ -22,6 +22,7 @@ struct ssi_printf_type { uint16_t buffSize; uint16_t buffPtr; uint16_t buffTot; + uint32_t buffWord; }; void ssi_putc ( void* p, const char c);