Release Progress Tracking 202205

202205 Features Tracking

Please scroll right to see additional information (SAI, Priority & Description)

Go back to Roadmap Page

Feature	HLD Review Date	Test Plan Ready for Review ETA	Owner	Code Review Owner	Code Review Date	Test PR Ready for Review ETA	Design/ Code Master PR	SAI Change	Priority/Conf (High/Low)	Description
NVGRE/GRE	Scheduled on 10/12		Nvidia	Intel/ Dell			869	Yes		NVGRE is a Layer 3 tunneling protocol that utilizes a standard GRE header to encapsulate a Layer 2 packet.
System with zero port support	N/A		Nvidia	Juniper	Jul 13: ready		900	No		Allows to bring up system and finish the init flow
Align crmorch with sai_object_type_get_availability	N/A		Nvidia	TBD				No PR 942		Will not require a new SAI API, but vendors will have to implement this API for using this functionality
Move Nvidia syncd and pmon to Debian11- "Bullseye"	N/A		Nvidia			Jan 30		No		Migrate syncd and pmon containers to Debian 11 - "Bullseye"
Dynamic Policy Based Hashing (edit flow) HLD	Done	Jan 30	Nvidia		Jan 30	Feb 15	909	No		Dynamic policy based hashing with edit flow
counter delay via config_db and not via systemd HLD	30-Dec	NA	Nvidia		Feb 28	NA	918	No
Route Flow counters (based on generic counters) HLD	Reviewed on Dec 14	Reviewed on Dec 14	Nvidia	Aviz	Mar 15	Mar 30	908	Yes Need this API  implemented
hostcfgd Redesign-split hostcfgd into multiple services	Jan 15	NA	Nvidia	Aviz	Mar 15	NA		No		Currently hostcfgd is handling a lot of tables and this leads to performance issues. This has lead to many bugs like 8619. So It is necessary to split hostcfgd into multiple services.The requirement is to come up with a design of how to split hostcfgd and what approach to use, either multi threaded or multi process. Based on design approval this needs to be implemented
Password Hardening HLD	Reviewed on Jan 18		Nvidia	MSFT			874	No		a user password is the key credential used in order to verify the user accessing the switch and acts as the first line of defense in regards to securing the switch. The complexity of the password, it's replacement capabilities and change frequency define the security level of the first perimeter of the switch. Therefore - in order to further improve and harden the switch - a secure mechanism is required to enforce PW policies.
Queue statistics based on queue configurations and not max	NA		Nvidia	MSFT	Jan 30			No		Performance optimization to query only relevant queue in MC aware mode (8-15 are unused)
Add system date row to ‘show version’	NA		Nvidia		Feb 28			No		Provide a baseline to improve debug flows
Command for showing specific MAC from DB	NA		Nvidia		Jan 30			No		show mac –verbose fetches the whole FDB table When we have large table of Mac the respond will take very long time
Event-mgmt Infra Deferred from 202111	Reviewed on Apr 27 2021 - require a reviewer to sign-off		Dell	BRCM	July 13 - ready for review		761, 7813, 48, 85, 490	No		A centralized framework for applications in SONiC network operating system to raise “events” and store them for NBIs to consume.
Klish CLI for show-tech support HLD Deferred from 202111	Apr 6 2021		DELL	MSFT	Jun 30 2021		All code PRs are merged 86, 49, 7816, 756	No		Klish CLI for show-tech support using the new mgmt.-infra framework
Storm Control (BUM) HLD Deferred from 202111	Apr 6 2021		BRCM	MSFT/ Innovium	Apr 10 2021		1306, 346, 928, 441 - Merged	No		Independently rate limit ingress Broadcast, Multicast and Unknown Unicast traffic on a bits-per-second basis. IS-CLI configuration
CMIS Diagnostics HLD Deferred from 202111	Reviewed on 10/5		BRCM	Dell/ Nvidia/ Google	10/29/2021			876	No
System Ready Enhancements Deferred from 202111	Reviewed on 10/5		BRCM	Dell/ Nvidia	9/29/2021		875, 930	No		Today there is no easy way to know when the device is ready in terms of control/dataplane. The change allows declaration of System ready (Syslog/CLI) when all the services(dockers+host) are up and ready. Also define a framework for each service to declare itself ready based on their application criteria.
Build Time Improvement	Jan 31		BRCM	Nvidia (stepanblyschak)		Feb 29
Link Training HLD	Jan 15		BRCM			Feb 7	925			Link Training is a process by which the transmitter and receiver on a high-speed serial link communicate with each other in order to tune their equalization settings. In theory, link training enables automatic tuning of the finite impulse response (FIR) filter for each channel in an application-specific integrated circuit (ASIC) to achieve the desired bit error rate (BER).In the SONiC system, the ODM vendors rarely provide pre-calibrated pre-emphasis for QSFP(DD) CR/KR modules, which could result in the link reliability issues. With this feature, both IEEE clause 72 and 93 will be activated to dynamically tune the transmitted signal to improve the link quality over the copper cables. This feature could be activated with or without AutoNeg.
Auto Neg Enhancement HLD	Jan 22		BRCM			Feb 14	924			Autonegotiation is a signaling mechanism and procedure used by Ethernet over twisted pair or optical media by which two connected devices choose common transmission parameters, such as speed, duplex mode, and flow control. In the case of SONiC, this feature supports two different types of AutoNeg 1. QSFP(DD) CR/KR modules: This feature provides autonegotiation support for speed, FEC and TX_FIR, the LinkTraining will always be activated when autonegotiation is enabled, and users could enable standalone-link-training to activate the clause 72/93 when autonegotiation is disabled. 2. Native RJ45 ports of non-Gearbox design: This feature provides autonegotiation support for speed and duplex to the native RJ45 coppers if they're manageable by the SAI without external PHY drivers on the Gearbox.
SNMPd Enhancements	N/A		BRCM				6276			Enable ipv6 snmpd support. Generate coldStart/warmStart trap based on reboot reason to differentiate. Removed default SNMP community public for security. Add strerror to SNMP file open failure. There is a possibility for snmpd try to open a device file (for reading statistics) which is already deleted by other applications.
SONiC fanout support Deferred from 202111	Stretch goal		MSFT	TBD				No		Change fanout switch o.s to SONiC
100% SONiC YANG model Deferred from 202111	NA		MSFT	MSFT/ YANG WG	Sep 30 2021		Yang Project	No		Build a full and complete YANG model for SONiC configDB
Deprecating Python2 platform daemons Deferred from 202111	NA		MSFT	Dell	Aug 30 2021			N/A		All platform daemons will run using Python 3. Python 2 support will be removed. Vendors must build and install Python 3 sonic-platform packages. Question: Will there be new platform APIs to be added in 202111? @Guohan to confirm
MACSEC enhancement: primary & fallback case HLD Deferred from 202111	N/A		MSFT	BRCM Juniper	N/A		652	No		MACsec can enable primary and fallback Connectivity Association Keys(CAK) at a same time. Meanwhile the primary and fallback key can be switched or replaced without any outage.
SONiC management repo  Python3 compliance			MSFT
Active Active ToRs			MSFT							Link manager, Warm reboot support for active-active dual ToRs
Vxlan enhancement			MSFT							Dual ToR with vxlan tunnel
BGP config incremental update			MSFT							BGP config incremental update
Symcrypt integration with OpenSSL			MSFT	Nvidia						Prepare OpenSSL with Symcrypt engine for FIPs 140-3 certification
Sorted next hop ECMP			MSFT	Nvidia
400G DR support			MSFT
ACL UDF			MSFT							Support user defined fields in ACL.
Streaming Telemetry support for Syslog			MSFT
FRR version update from 7.5 to 8.1			MSFT
ACMS and Restful API for Arista 7060			MSFT
PINS test coverage improvement with more test cases			Google							Add tests in P4RT application, P4Orch and PacketIO
PINS - Critical State and Enhanced error reporting			Google							PINS improvement with critical state and enhanced error reporting
PINS - Batched programming requests for higher throughput			Google							PINS supports batched programming requests for higher throughput
PINS - Augment PacketIO support			Google							Augment PINS PacketIO support
SAG Deferred from 202111	Reviewed on 8/24/2021		Edgecore	Dell/ Intel BRCM	Aug 30		837	No		Static Anycast Gateway. To provide anycast gateway for host/VMs. Can be used independently, or with MCLAG to provide single gateway for MC-LAG member host. To provide the possibility for host VM mobility. Both IPv4 and v6
L2 Dot1Q tunneling support			EdgeCore
VLAN Stacking HLD	Reviewed on Jan 25		EdgeCore				915	Yes		This feature provides Q-in-Q and VLAN translation for service providers who carry traffic of multiple customers across their networks and are required to maintain the VLAN and Layer 2 protocol configurations of each customer without impacting the traffic of other customers.
Config Reload Enhancement: Introduce the Transaction Mechanism HLD			EdgeCore	Nvidia (Junchao-Mellanox)						In the current design of 'config reload', it does not mean the sonic configurations to be reloaded had been finished when the execution of 'config reload' has done. When the execution of 'config reload' is done, it is possible that some sonic services have not been fully populated and the system in terms of sonic services is not in ready state. It is just wasting time to initiate another 'config reload' transaction when the previous transaction has not been done. It is better to have a transaction protection to avoid that condition.
EVPN-MH Phase #1			EdgeCore	Nvidia
Further extensions and uses of application extension framework			MetaSwitch	Nvidia/ MSFT (Renuka)
MPLS scalability enhancement in SAI and SWSS			MetaSwitch
Global setting to allow IPv6 link-local neighbours to always be programmed			MetaSwitch
Docker image on Bulleyes										SONiC docker image on Bulleyes
Platform support for Edgecore AS4630/AS7326/AS7816/AS5835	NA	Feb 1	Target	Edgecore	Feb 15	Mar 1		No		1. [AS7726-32X] Add to support mulit PSU SN in PDDF 2. [AS7326-56X] Support mulit PSU SN in PDDF 3. [AS7712-32X] Add to support PDDF 4. [AS4630-54PE] Add to support PDDF 5. [as5835-54x] Add to support PDDF 6. [AS9716-32d] Modify check eeprom via pre_pddf sh 7. [as7816-64x] Modify to check specific DUT
PINS SAI Extensions			Intel
PINS SAI.P4 enhancements for Layer2 support and VxLAN			Intel
SRv6 policy steering w/ FRR protocols integration			Intel/ Alibaba
SRv6 sBFD, DT46			Intel/ Alibaba
DASH – SAI PTF extension for SmartNIC			Intel
SONiC with P4 DPDK (PNA architecture) – Basic SoftSwitch with DPDK			Intel
Deterministic interface Link bring-up HLD	Reviewed on Jan 18		Cisco	Nvidia (dgsudharsan)			916