From 42d5e6ac512b04da10e9e65d5b3df1c0a1069dbc Mon Sep 17 00:00:00 2001 From: "Mack, Jacob Anthony" Date: Mon, 27 Nov 2023 02:38:31 -0500 Subject: [PATCH] DES ISSCC24 Submission --- .../des-openlane/des_openlane.ipynb | 1999 +++++++++++++++++ 1 file changed, 1999 insertions(+) create mode 100644 ISSCC24/submitted_notebooks/des-openlane/des_openlane.ipynb diff --git a/ISSCC24/submitted_notebooks/des-openlane/des_openlane.ipynb b/ISSCC24/submitted_notebooks/des-openlane/des_openlane.ipynb new file mode 100644 index 00000000..d4d6df0a --- /dev/null +++ b/ISSCC24/submitted_notebooks/des-openlane/des_openlane.ipynb @@ -0,0 +1,1999 @@ +{ + "cells": [ + { + "cell_type": "markdown", + "metadata": { + "id": "HkFeU0R-0hzi" + }, + "source": [ + "# Data-Encryption-Standard (DES) with OpenLane\n", + "\n", + "```\n", + "SPDX-License-Identifier: Apache-2.0\n", + "```" + ] + }, + { + "cell_type": "markdown", + "source": [ + "|Name|Affiliation| Email |IEEE Member|SSCS Member|\n", + "|:--:|:----------:|:----------:|:----------:|:----------:|\n", + "|Jacob Mack|University of Michigan|jmackmi@umich.edu|Yes|Yes|\n", + "\n", + "\n" + ], + "metadata": { + "id": "tqAHkKOpbIzo" + } + }, + { + "cell_type": "markdown", + "source": [ + "## Introduction\n", + "\n", + "\n", + "---\n", + "\n" + ], + "metadata": { + "id": "SeI3ywIANTeP" + } + }, + { + "cell_type": "markdown", + "source": [ + "This notebook introduces the Data Encryption Standard (DES), demonstrates DES operation, and implements a DES design thru the [OpenLane](https://github.com/The-OpenROAD-Project/OpenLane/) GDS to RTL flow targeting the [open source SKY130 PDK](https://github.com/google/skywater-pdk/).\n", + "\n", + "This notebook is broken down into answering three questions:\n", + "- What is DES and how is it implemented?\n", + "- How to run a RTL and C++ simulation of DES and how do the results compare?\n", + "- How to run the OpenLane Flow and generate design metrics?" + ], + "metadata": { + "id": "MPTB54wHqROr" + } + }, + { + "cell_type": "markdown", + "source": [ + "### DES\n", + "\n", + "\n", + "---\n", + "\n", + "\n", + "DES stands for **D**ata **E**ncryption **S**tandard and is a symmetric-key algorithm for the encryption of digital data. DES uses the same key for both encryption and decryption which makes it a symmetric-key algorithm. DES was developed in early 1970s by IBM and was published as an official Federal Information Processing Standard for the United States in 1977.\n", + "

\n", + "The input to be encrypted is called the **plain text** and the output scrambled text is called the **cipher text**.\n", + "

\n", + "For our example, the plain text is the hexidecimal number 01234567890ABCDEF and the **key** is the hexadecimal number 133457799BBCDFF1.\n", + "

\n", + "The three main components of DES are **Key Generation**, **Encryption of Plain Text**, and **Decryption of Cipher Text**." + ], + "metadata": { + "id": "QBgZXHJIpSiU" + } + }, + { + "cell_type": "markdown", + "source": [ + "#### Key Generation\n", + "\n", + "\n", + "---\n", + "\n", + "\n", + "16 sub-keys are created from the original key for the 16 rounds of encryption of plain text.\n", + "

\n", + "Starting with the original key, 133457799BBCDFF1, it is permutated according to the Permutated Choice 1 (PC-1):\n", + "\n", + "![PC1](https://github.com/jmack2201/code-a-chip-des/blob/pipeline/img/PC1.png?raw=true)\n", + "\n", + "Before PC-1:\n", + "\n", + "Key: 133457799BBCDFF1\n", + "\n", + "After PC-1:\n", + "\n", + "Key: F0CCAAF556678F\n", + "\n", + "During PC-1, some bits of the key are not used (8,16,24,32,40,48,56,64) and are used as parity bits.\n", + "

\n", + "The permutated key is then divided into left and right halves:\n", + "\n", + "Left: FOCCAAF\n", + "\n", + "Right: AACCF1E\n", + "\n", + "Depending on what round the sub-key is generated for, the left and right halves will circular left shift either by one or two:\n", + "\n", + "| Round Number | Shift Amount |\n", + "| ----------- | ----------- |\n", + "| 1,2,8,16 | 1 |\n", + "| 4,5,6,7,9,10,11,12,13,14,15 | 2 |\n", + "\n", + "The sub-key halves for round one will circle shift by one:\n", + "\n", + "Left: E19955F\n", + "\n", + "Right: AACCF1E\n", + "

\n", + "Subsequent sub-keys are based on the previous sub-keys such that the sub-key for round two is derived from round one and the sub-key for round three is derived from round two etc.\n", + "

\n", + "For round two, it takes the left and right halves of the previous round (one) and circle left shifts according to shift amount table:\n", + "\n", + "\n", + "Left: C332ABF\n", + "\n", + "Right: 5599E3D\n", + "

\n", + "This process is repeated for all 16 rounds and this table shows the result of that process:\n", + "\n", + "| Round Number | Left | Right |\n", + "| ----------- | ----------- | -----------|\n", + "| 1 | E19955F |AACCF1E |\n", + "| 2 | C332ABF |5599E3D |\n", + "| 3 | 0CCAAFF |56678F5 |\n", + "| 4 | 332ABFC |599E3D5 |\n", + "| 5 | CCAAFF0 |6678F55 |\n", + "| 6 | 32ABFC3 |99E3D55 |\n", + "| 7 | CAAFF0C | 678F556|\n", + "| 8 | 2ABFC33 |9E3D559 |\n", + "| 9 | 557F866 | 3C7AAB3|\n", + "| 10 | 55FE199 |F1EAACC |\n", + "| 11 | 57F8665 |C7AAB33 |\n", + "| 12 | 5FE1995 |1EAACCF |\n", + "| 13 | 7F86655 |7AAB33C |\n", + "| 14 | FE19955 |EAACCF1 |\n", + "| 15 | F866557 |AAB33C7 |\n", + "| 16 | F0CCAAF |556678F |\n", + "\n", + "Before the sub-keys are sent to be used in the encryption of the plain text, each sub-key left and right half is combined and then permutated according to Permutated Choice 2 (PC-2):\n", + "\n", + "\n", + "![PC2](https://github.com/jmack2201/code-a-chip-des/blob/pipeline/img/PC2.png?raw=true)\n", + "\n", + "\n", + "This is the result of PC-2 on the combined left and right halves for round one:\n", + "\n", + "Before: E19955FAACCF1E\n", + "\n", + "After: 1B02EFFC7072\n", + "

\n", + "The final sub-keys for each round after PC-2 are:\n", + "\n", + "| Round Number | Sub-Key |\n", + "| ----------- | ----------- |\n", + "| 1 | 1B02EFFC7072 |\n", + "| 2 | 79AED9DBC9E5 |\n", + "| 3 | 55FC8A42CF99 |\n", + "| 4 | 72ADD6DB351D |\n", + "| 5 | 7CEC07EB53A8 |\n", + "| 6 | 63A53E507B2F |\n", + "| 7 | EC84B7F618BC |\n", + "| 8 | F78A3AC13BFB |\n", + "| 9 | E0DBEBEDE781 |\n", + "| 10 | B1F347BA464F |\n", + "| 11 | 215FD3DED386 |\n", + "| 12 | 7571F59467E9 |\n", + "| 13 | 97C5D1FABA41 |\n", + "| 14 | 5F43B7F2E73A |\n", + "| 15 | BF918D3D3F0A |\n", + "| 16 | CB3D8B0E17F5 |\n", + "\n" + ], + "metadata": { + "id": "kK4vIbghr4tb" + } + }, + { + "cell_type": "markdown", + "source": [ + "#### Encryption of Plain Text\n", + "\n", + "\n", + "---\n", + "\n", + "\n", + "To start the encryption, the plain text goes through an inital permutation:\n", + "\n", + "![IP](https://github.com/jmack2201/code-a-chip-des/blob/pipeline/img/IP.png?raw=true)\n", + "\n", + "Before: 0123456789ABCDEF\n", + "\n", + "After: CC00CCFFF0AAF0AA\n", + "\n", + "
\n", + "\n", + "\n", + "\n", + "The output of the initial permutation is divided into left and right halves:\n", + "\n", + "Left: CC00CCFF\n", + "\n", + "Right: F0AAF0AA\n", + "\n", + "
\n", + "\n", + "\n", + "A round of encryption's output is the following left and right halves:\n", + "\n", + "Left: Previous round's right half\n", + "\n", + "Right: Previous round's left half XOR fiestel(Previous round's right half, Round Sub-Key)\n", + "\n", + "(For the first round, the previous left and right halves come from the initial permutation.)\n", + "\n", + "
\n", + "\n", + "\n", + "\n", + "\n", + "To compute the fiestel function, the previous round's right half is first expanded according to this permutation: ![E](https://github.com/jmack2201/code-a-chip-des/blob/pipeline/img/E.png?raw=true)\n", + "\n", + "\n", + "Before: F0AAF0AA\n", + "\n", + "After: 7A15557A1555\n", + "\n", + "
\n", + "\n", + "Next this expanded value is XORed with the round sub-key (for round one, the sub-key is 1B02EFFC7072):\n", + "\n", + "7A15557A1555 XOR 1B02EFFC7072 = 6117BA866527\n", + "\n", + "
\n", + "\n", + "After XORing with the sub-key, the value is divided into eight 6-bit slices (1st, 2nd, 3rd, ... 8th 6-bit slice) for S-Box subsitition:\n", + "011000,\n", + "010001,\n", + "011110,\n", + "111010,\n", + "100001,\n", + "100110,\n", + "010100,\n", + "100111.\n", + "\n", + "
\n", + "\n", + "An S-Box is a look up table that contains a 4-bit value and is indexed by the following:\n", + "\n", + "Row = Outer Two Bits, Example: 100001 -> 11\n", + "\n", + "Column = Inner Four Bits, Example: 100001 -> 0000\n", + "\n", + "
\n", + "\n", + "There are eight S-Boxes corresponding to the eight 6-bit slices and each S-Box has different values from each other. The eight S-Boxes are:\n", + "\n", + "S-Box 1\n", + "\n", + "| Row/Column | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F |\n", + "|------------|----|----|----|---|----|----|----|----|----|----|----|----|----|----|---|----|\n", + "| 0 | 14 | 4 | 13 | 1 | 2 | 15 | 11 | 8 | 3 | 10 | 6 | 12 | 5 | 9 | 0 | 7 |\n", + "| 1 | 0 | 15 | 7 | 4 | 14 | 2 | 13 | 1 | 10 | 6 | 12 | 11 | 9 | 5 | 3 | 8 |\n", + "| 2 | 4 | 1 | 14 | 8 | 13 | 6 | 2 | 11 | 15 | 12 | 9 | 7 | 3 | 10 | 5 | 0 |\n", + "| 3 | 15 | 12 | 8 | 2 | 4 | 9 | 1 | 7 | 5 | 11 | 3 | 14 | 10 | 0 | 6 | 13 |\n", + "\n", + "S-Box 2\n", + "\n", + "| Row/Column | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F |\n", + "|------------|----|----|----|----|----|----|----|----|----|---|----|----|----|---|----|----|\n", + "| 0 | 15 | 1 | 8 | 14 | 6 | 11 | 3 | 4 | 9 | 7 | 2 | 13 | 12 | 0 | 5 | 10 |\n", + "| 1 | 3 | 13 | 4 | 7 | 15 | 2 | 8 | 14 | 12 | 0 | 1 | 10 | 6 | 9 | 11 | 5 |\n", + "| 2 | 0 | 14 | 7 | 11 | 10 | 4 | 13 | 1 | 5 | 8 | 12 | 6 | 9 | 3 | 2 | 15 |\n", + "| 3 | 13 | 8 | 10 | 1 | 3 | 15 | 4 | 2 | 11 | 6 | 7 | 12 | 0 | 5 | 14 | 9 |\n", + "\n", + "S-Box 3\n", + "\n", + "| Row/Column | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F |\n", + "|------------|----|----|----|----|---|----|----|----|----|----|----|----|----|----|----|----|\n", + "| 0 | 10 | 0 | 9 | 14 | 6 | 3 | 15 | 5 | 1 | 13 | 12 | 7 | 11 | 4 | 2 | 8 |\n", + "| 1 | 13 | 7 | 0 | 9 | 3 | 4 | 6 | 10 | 2 | 8 | 5 | 14 | 12 | 11 | 15 | 1 |\n", + "| 2 | 13 | 6 | 4 | 9 | 8 | 15 | 3 | 0 | 11 | 1 | 2 | 12 | 5 | 10 | 14 | 7 |\n", + "| 3 | 1 | 10 | 13 | 0 | 6 | 9 | 8 | 7 | 4 | 15 | 14 | 3 | 11 | 5 | 2 | 12 |\n", + "\n", + "S-Box 4\n", + "\n", + "| Row/Column | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F |\n", + "|------------|----|----|----|---|----|----|----|----|----|---|---|----|----|----|----|----|\n", + "| 0 | 7 | 13 | 14 | 3 | 0 | 6 | 9 | 10 | 1 | 2 | 8 | 5 | 11 | 12 | 4 | 15 |\n", + "| 1 | 13 | 8 | 11 | 5 | 6 | 15 | 0 | 3 | 4 | 7 | 2 | 12 | 1 | 10 | 14 | 9 |\n", + "| 2 | 10 | 6 | 9 | 0 | 12 | 11 | 7 | 13 | 15 | 1 | 3 | 14 | 5 | 2 | 8 | 4 |\n", + "| 3 | 3 | 15 | 0 | 6 | 10 | 1 | 13 | 8 | 9 | 4 | 5 | 11 | 12 | 7 | 2 | 14 |\n", + "\n", + "S-Box 5\n", + "\n", + "| Row/Column | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F |\n", + "|------------|----|----|----|----|----|----|----|----|----|----|----|----|----|---|----|----|\n", + "| 0 | 2 | 12 | 4 | 1 | 7 | 10 | 11 | 6 | 8 | 5 | 3 | 15 | 13 | 0 | 14 | 9 |\n", + "| 1 | 14 | 11 | 2 | 12 | 4 | 7 | 13 | 1 | 5 | 0 | 15 | 10 | 3 | 9 | 8 | 6 |\n", + "| 2 | 4 | 2 | 1 | 11 | 10 | 13 | 7 | 8 | 15 | 9 | 12 | 5 | 6 | 3 | 0 | 14 |\n", + "| 3 | 11 | 8 | 12 | 7 | 1 | 14 | 2 | 13 | 6 | 15 | 0 | 9 | 10 | 4 | 5 | 3 |\n", + "\n", + "S-Box 6\n", + "\n", + "| Row/Column | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F |\n", + "|------------|----|----|----|----|---|----|----|----|----|----|----|----|----|----|----|----|\n", + "| 0 | 12 | 1 | 10 | 15 | 9 | 2 | 6 | 8 | 0 | 13 | 3 | 4 | 14 | 7 | 5 | 11 |\n", + "| 1 | 10 | 15 | 4 | 2 | 7 | 12 | 9 | 5 | 6 | 1 | 13 | 14 | 0 | 11 | 3 | 8 |\n", + "| 2 | 9 | 14 | 15 | 5 | 2 | 8 | 12 | 3 | 7 | 0 | 4 | 10 | 1 | 13 | 11 | 6 |\n", + "| 3 | 4 | 3 | 2 | 12 | 9 | 5 | 15 | 10 | 11 | 14 | 1 | 7 | 6 | 0 | 8 | 13 |\n", + "\n", + "S-Box 7\n", + "\n", + "| Row/Column | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F |\n", + "|------------|----|----|----|----|----|---|----|----|----|----|---|----|----|----|---|----|\n", + "| 0 | 4 | 11 | 2 | 14 | 15 | 0 | 8 | 13 | 3 | 12 | 9 | 7 | 5 | 10 | 6 | 1 |\n", + "| 1 | 13 | 0 | 11 | 7 | 4 | 9 | 1 | 10 | 14 | 3 | 5 | 12 | 2 | 15 | 8 | 6 |\n", + "| 2 | 1 | 4 | 11 | 13 | 12 | 3 | 7 | 14 | 10 | 15 | 6 | 8 | 0 | 5 | 9 | 2 |\n", + "| 3 | 6 | 11 | 13 | 8 | 1 | 4 | 10 | 7 | 9 | 5 | 0 | 15 | 14 | 2 | 3 | 12 |\n", + "\n", + "S-Box 8\n", + "\n", + "| Row/Column | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F |\n", + "|------------|----|----|----|---|----|----|----|----|----|----|----|----|----|----|----|----|\n", + "| 0 | 13 | 2 | 8 | 4 | 6 | 15 | 11 | 1 | 10 | 9 | 3 | 14 | 5 | 0 | 12 | 7 |\n", + "| 1 | 1 | 15 | 13 | 8 | 10 | 3 | 7 | 4 | 12 | 5 | 6 | 11 | 0 | 14 | 9 | 2 |\n", + "| 2 | 7 | 11 | 4 | 1 | 9 | 12 | 14 | 2 | 0 | 6 | 10 | 13 | 15 | 3 | 5 | 8 |\n", + "| 3 | 2 | 1 | 14 | 7 | 4 | 10 | 8 | 13 | 15 | 12 | 9 | 0 | 3 | 5 | 6 | 11 |\n", + "\n", + "
\n", + "\n", + "Following the example, here are the values (in hexadecimal) from each S-Box based on the eight 6-bit slices:\n", + "\n", + "| S-Box | 6-Bit Slice | Row | Column | Value |\n", + "| ----------- | ----------- | ----------- | ----------- |-----------|\n", + "| 1 | 011000 | 0 | C | 5 |\n", + "| 2 | 010001 | 1 | 8 | C |\n", + "| 3 | 011110 | 0 | F | 8|\n", + "| 4 | 111010 | 2 | D | 2 |\n", + "| 5 | 100001 | 3| 0| B|\n", + "| 6 | 100110 | 2 | 3 | 5 |\n", + "| 7 | 010100 | 0 | A | 9 |\n", + "| 8 | 100111 | 3 | 3 | 7 |\n", + "\n", + "The outputs of the S-Boxes are then combined to form a 32-bit value: 5C82B597\n", + "\n", + "
\n", + "\n", + "\n", + "Following the S-Box subsititution, the output is permutated again according to this permutation: ![P](https://github.com/jmack2201/code-a-chip-des/blob/pipeline/img/P.png?raw=true)\n", + "\n", + "Before: 5C82B597\n", + "\n", + "After: 234AA9BB\n", + "\n", + "
\n", + "\n", + "Following the permutation after the S-Box subsitition, the value of the feistel function for round one is found and the output round right value can be found:\n", + "\n", + "CC00CCFF XOR 234AA9BB = EF4A6544\n", + "\n", + "
\n", + "\n", + "After round one, the output left and right values are:\n", + "\n", + "Left: F0AAF0AA\n", + "\n", + "Right: EF4A6544\n", + "\n", + "
\n", + "\n", + "This round computation repeats 15 more times and uses the appropriate sub-keys for each round. The output left and right for each round are located in the table below:\n", + "\n", + "| Round Number | Left | Right |\n", + "| ----------- | ----------- | -----------|\n", + "| 1 | F0AAF0AA |EF4A6544 |\n", + "| 2 | EF4A6544 |CC017709 |\n", + "| 3 | CC017709 |A25C0BF4 |\n", + "| 4 | A25C0BF4 | 77220045|\n", + "| 5 | 77220045 |8A4FA637 |\n", + "| 6 | 8A4FA637 | E967CD69|\n", + "| 7 | E967CD69 | 064ABA10|\n", + "| 8 | 064ABA10 | D5694B90|\n", + "| 9 | D5694B90 |247CC67A |\n", + "| 10 | 247CC67A |B7D5D7B2 |\n", + "| 11 | B7D5D7B2 |C5783C78 |\n", + "| 12 | C5783C78 |75BD1858 |\n", + "| 13 | 75BD1858 |18C3155A |\n", + "| 14 | 18C3155A |C28C960D |\n", + "| 15 | C28C960D |43423234 |\n", + "| 16 | 43423234 | 0A4CD995 |\n", + "\n", + "
\n", + "\n", + "The final step in finishing the encryption is a final permuation which is the inverse of the initial permuation on the combined left and right halves (there is one more swap of left and right after round 16 before the final permutation):\n", + "![invIP](https://github.com/jmack2201/code-a-chip-des/blob/pipeline/img/invIP.png?raw=true)\n", + "\n", + "Before: 0A4CD99543423234\n", + "\n", + "After: 85E813540F0AB405\n", + "\n", + "
\n", + "\n", + "For an input plain text of 0123456789ABCDEF and a key of 133457799BBCDFF1, the cipher text 85E813540F0AB405 is generated.\n", + "\n" + ], + "metadata": { + "id": "C7ho7dhcrhxO" + } + }, + { + "cell_type": "markdown", + "source": [ + "#### Decryption of Cipher Text\n", + "\n", + "\n", + "---\n", + "\n", + "\n", + "To decrypt a given cipher text using a key, the processs is similar to encryption except the cipher text is used as the plain text.\n", + "

\n", + "In key generation, the sub-keys are created in the same process, but the order of the rounds they are applied to is reversed.\n", + "

\n", + "In our example, the sub-key created for round one is 1B02EFFC7072, but the sub-key will be applied for the 16th round.\n", + "

\n", + "This table shows the updated order of keys for our example key of 133457799BBCDFF1:\n", + "\n", + "| Round Number | Sub-Key |\n", + "| ----------- | ----------- |\n", + "| 1 | CB3D8B0E17F5 |\n", + "| 2 | BF918D3D3F0A |\n", + "| 3 | 5F43B7F2E73A |\n", + "| 4 | 97C5D1FABA41 |\n", + "| 5 | 7571F59467E9 |\n", + "| 6 | 215FD3DED386 |\n", + "| 7 | B1F347BA464F |\n", + "| 8 | E0DBEBEDE781 |\n", + "| 9 | F78A3AC13BFB |\n", + "| 10 | EC84B7F618BC |\n", + "| 11 | 63A53E507B2F |\n", + "| 12 | 7CEC07EB53A8 |\n", + "| 13 | 72ADD6DB351D |\n", + "| 14 | 55FC8A42CF99 |\n", + "| 15 | 79AED9DBC9E5 |\n", + "| 16 | 1B02EFFC7072 |\n", + "\n", + "
Decrypting the cipher text generated from the previous encryption example (85E813540F0AB405) using the same key (133457799BBCDFF1) would result in the created cipher text of 0123456789ABCDEF. If the same key is not used during decryption, the plain text is further scrambled which is the basis of [Triple DES](https://en.wikipedia.org/wiki/Triple_DES).\n", + "\n" + ], + "metadata": { + "id": "TSK0VOBrtZA0" + } + }, + { + "cell_type": "markdown", + "source": [ + "### DES Hardware Implementaton\n", + "\n", + "\n", + "---\n", + "\n" + ], + "metadata": { + "id": "hkDHL95TcU31" + } + }, + { + "cell_type": "markdown", + "source": [ + "#### Block Diagram\n", + "\n", + "Shown here is a diagram of the DES implementation in hardware with block names corresponding to the Verilog module names:\n", + "\n", + "![updatedBD](https://github.com/jmack2201/code-a-chip-des/blob/pipeline/img/block_diagram.jpg?raw=true)\n", + "\n", + "
\n" + ], + "metadata": { + "id": "9bq8YXcQcLyW" + } + }, + { + "cell_type": "markdown", + "source": [ + "#### Configuration\n", + "\n", + "To enable configurability of the DES Hardware, a hardware parameter `NUM_ROUNDS_PER_FF` describes the granularity of pipelining within the design. A value of 0 sets no pipelining within the design and a value of 4 divides the round stack into groups of 4 for pipelining. The diagram below illustrates different confirgurations of DES:\n", + "\n", + "![BD_pipe](https://github.com/jmack2201/code-a-chip-des/blob/pipeline/img/bd_pipeline.jpg?raw=true)\n", + "\n", + "\n", + "Depending on the target area and timing specification, `NUM_ROUNDS_PER_FF` can be tuned to meet those requirements." + ], + "metadata": { + "id": "P33c-VlJruf4" + } + }, + { + "cell_type": "markdown", + "source": [ + "## Simulation\n", + "\n", + "\n", + "---\n", + "\n" + ], + "metadata": { + "id": "5EgpZ25ssAYY" + } + }, + { + "cell_type": "code", + "source": [ + "#@title Download Dependencies\n", + "\n", + "#@markdown The main package that will be used to test the Verilog implemention is [Icarus Verilog](https://steveicarus.github.io/iverilog/index.html) (iverilog).\n", + "\n", + "#@markdown iverilog is a free and open-source tool used to compile and to simulate Verilog file(s).\n", + "!apt-get install iverilog\n" + ], + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "L3oXVoYZx6y3", + "outputId": "140b84d4-7c68-46bd-8116-aefc507006b1" + }, + "execution_count": 2, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "Reading package lists... Done\n", + "Building dependency tree... Done\n", + "Reading state information... Done\n", + "Suggested packages:\n", + " gtkwave\n", + "The following NEW packages will be installed:\n", + " iverilog\n", + "0 upgraded, 1 newly installed, 0 to remove and 10 not upgraded.\n", + "Need to get 2,130 kB of archives.\n", + "After this operation, 6,749 kB of additional disk space will be used.\n", + "Get:1 http://archive.ubuntu.com/ubuntu jammy/universe amd64 iverilog amd64 11.0-1.1 [2,130 kB]\n", + "Fetched 2,130 kB in 0s (5,476 kB/s)\n", + "Selecting previously unselected package iverilog.\n", + "(Reading database ... 120880 files and directories currently installed.)\n", + "Preparing to unpack .../iverilog_11.0-1.1_amd64.deb ...\n", + "Unpacking iverilog (11.0-1.1) ...\n", + "Setting up iverilog (11.0-1.1) ...\n", + "Processing triggers for man-db (2.10.2-1) ...\n" + ] + } + ] + }, + { + "cell_type": "code", + "execution_count": 3, + "metadata": { + "id": "gpgkIYB739Ii", + "colab": { + "base_uri": "https://localhost:8080/" + }, + "outputId": "73d84eae-8ed0-43db-f012-62d9973e89f5" + }, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "Cloning into 'code-a-chip-des'...\n", + "remote: Enumerating objects: 337, done.\u001b[K\n", + "remote: Counting objects: 100% (337/337), done.\u001b[K\n", + "remote: Compressing objects: 100% (227/227), done.\u001b[K\n", + "remote: Total 337 (delta 169), reused 266 (delta 101), pack-reused 0\u001b[K\n", + "Receiving objects: 100% (337/337), 50.09 KiB | 2.50 MiB/s, done.\n", + "Resolving deltas: 100% (169/169), done.\n" + ] + } + ], + "source": [ + "#@title Download Verilog and C++ Files\n", + "\n", + "#@markdown The verilog and C++ files are provided by cloning a GitHub repo into a folder \\\"code-a-chip-des\". Each file in the \\\"code-a-chip-des/scripts\", \\\"code-a-chip-des/verilog/src\", and \\\"code-a-chip-des/tb\" sub-directories is described below:\n", + "\n", + "#@markdown * code-a-chip-des/scripts\n", + "#@markdown * `Makefile`: Handles compilation and simulation for both C++ and Verilog implementations of DES.\n", + "#@markdown * `des.cpp`: Describles C++ implemention of DES for both encryption and decryption.\n", + "#@markdown * code-a-chip-des/verilog/src\n", + "#@markdown * `des_config.v`: Configures the amount of rounds per pipeline register.\n", + "#@markdown * `des_top.v`: Serves as the top level module, instantiates `init_perm`, `key_gen`,`round_stack`, and `final_perm`, and creates the input and output flip-flop.\n", + "#@markdown * `feistel_function.v`: Instantiates `p_box_32_48`, `s_box_48_32`, and `p_box_32_32`, and links them together.\n", + "#@markdown * `final_perm.v`: Performs the inverse of the Inital Permuation after applying 16 rounds of the DES algorithm to the plain text.\n", + "#@markdown * `init_perm.v`: Performs the Initial Permutation of the plain text.\n", + "#@markdown * `key_gen.v`: Creates 16 copies of `round_key_gen` to create the 16 total round keys.\n", + "#@markdown * `key_mux.v`: Multiplexes the output of `key_gen` based on operation mode.\n", + "#@markdown * `p_box_32_32.v`: Permutates the output of `s_box_48_32` for the `feistel_function` output.\n", + "#@markdown * `p_box_32_48.v`: Expands the input of `feistel_function` to be XORed with the round key.\n", + "#@markdown * `p_box_56_48.v`: Compresses the output of `round_key_gen` and connects to the `key_mux` of the assigned round.\n", + "#@markdown * `p_box_64_56.v`: Compresses and permutates the input key before starting generation of 16 round keys.\n", + "#@markdown * `round_ff.v`: Implements the round pipeline register.\n", + "#@markdown * `round_key_gen.v`: Creates a single round key and passes round key to latter round key generation stages\n", + "#@markdown * `round_stack.v`: Constructs 16 `round` instances and prepares input to `final_perm`.\n", + "#@markdown * `round.v`: Instantiates an instance of `feistel_function`, prepares the round outputs, and creates a `round_ff` if desired.\n", + "#@markdown * `s_box_6_4.v`: Describes the eight unique S Boxes used in `feistel_function`.\n", + "#@markdown * `s_box_48_32.v`: Creates eight `s_box_6_4` modules and links them together.\n", + "#@markdown * code-a-chip-des/verilog/tb\n", + "#@markdown * `des_top_tasks.v`: Defines the three tasks primarily used for Verilog simulation.\n", + "#@markdown * `tb_des_top.v`: Contains the testbench for the Verilog simulation.\n", + "\n", + "\n", + "\n", + "!rm -rf code-a-chip-des/\n", + "!git clone -b pipeline https://github.com/jmack2201/code-a-chip-des.git" + ] + }, + { + "cell_type": "markdown", + "source": [ + "#### Configure DES" + ], + "metadata": { + "id": "gr8mG6_AsM-c" + } + }, + { + "cell_type": "code", + "source": [ + "#@markdown To configure the DES, type in the amount of rounds per pipeline register desired in the DES:\n", + "#@markdown * NUM_ROUNDS_PER_FF: $\\in [ 0, 16 ]$\n", + "\n", + "NUM_ROUNDS_PER_FF = 4 #@param {type: \"integer\"}\n", + "\n", + "des_config_file = open(\"/content/code-a-chip-des/verilog/src/des_config.v\",\"w\")\n", + "\n", + "des_config_file.write(\"`ifndef des_config\\n\")\n", + "des_config_file.write(\"\\t`define NUM_ROUND_STAGES {}\\n\".format(NUM_ROUNDS_PER_FF))\n", + "des_config_file.write(\"`endif\\n\")\n", + "\n", + "des_config_file.close()" + ], + "metadata": { + "id": "YRTottxj1hnS" + }, + "execution_count": 4, + "outputs": [] + }, + { + "cell_type": "markdown", + "source": [ + "#### Run Simulation" + ], + "metadata": { + "id": "1hQA6xKYu9fs" + } + }, + { + "cell_type": "code", + "source": [ + "#@markdown Configure the DES simulation by filling in the following:\n", + "#@markdown * Operation: Encryption or Decryption\n", + "#@markdown * Plain Text: 16 Character Hexadecimal Number\n", + "#@markdown * Cipher Key: 16 Character Hexadecimal Number\n", + "\n", + "operation = \"Encryption\" #@param [\"Encryption\",\"Decryption\"]\n", + "plain_text = \"0123456789abcdef\" #@param {type:\"string\"}\n", + "cipher_key = \"133457799BBCDFF1\" #@param {type:\"string\"}\n", + "\n", + "#print out current operation\n", + "print(\"============================================\")\n", + "print(\"Operation: {}\\nPlain Text: {}\\nCipher Key: {}\".format(operation,plain_text.upper(),cipher_key))\n", + "print(\"============================================\")\n", + "\n", + "#run golden C++ simulation\n", + "print(\"Running Golden C++ Simulation...\")\n", + "!cd /content/code-a-chip-des/scripts/; make cpp_flow plain_text={plain_text} cipher_key={cipher_key} encrypt_decrypt={operation} > make_cpp.log\n", + "#pull result cipher text from cpp log file\n", + "golden_sim_out = \"\"\n", + "golden_sim_file = open(\"/content/code-a-chip-des/scripts/make_cpp.log\",\"r\")\n", + "golden_sim_file_lines = golden_sim_file.readlines()\n", + "golden_sim_file.close()\n", + "for line in golden_sim_file_lines:\n", + " if \"Cipher Text\" in line:\n", + " golden_sim_out = line.split(\" \")[len(line.split(\" \"))-1].replace(\"\\n\", \"\").upper()\n", + " break\n", + "print(\"Golden C++ Simulation Output Cipher Text: {}\".format(golden_sim_out))\n", + "print(\"Golden C++ Simulation Complete\")\n", + "print(\"============================================\")\n", + "\n", + "#run verilog simulation\n", + "print(\"Running Verilog Simulation...\")\n", + "!cd /content/code-a-chip-des/sim/; make verilog plain_text={plain_text} cipher_key={cipher_key} encrypt_decrypt={operation} > make_verilog.log\n", + "#pull result cipher text from verilog log file\n", + "verilog_sim_out = \"\"\n", + "verilog_sim_file = open(\"/content/code-a-chip-des/sim/make_verilog.log\",\"r\")\n", + "verilog_sim_file_lines = verilog_sim_file.readlines()\n", + "verilog_sim_file.close()\n", + "for line in verilog_sim_file_lines:\n", + " if \"Valid: 1\" in line:\n", + " verilog_sim_out = line.split(\"\\t\")[2].split(\" \")[2].upper()\n", + " break\n", + "print(\"Verilog Simulation Output Cipher Text: {}\".format(verilog_sim_out))\n", + "print(\"Verilog Simulation Complete\")\n", + "print(\"============================================\")\n", + "if (verilog_sim_out == golden_sim_out):\n", + " print(\"The Verilog and C++ Simulation are the same!\")\n", + " print(\"============================================\")\n" + ], + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "KcL3HAXLvYd3", + "outputId": "a8442794-898e-4f02-9d69-1bc651b5ed11" + }, + "execution_count": 8, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "============================================\n", + "Operation: Encryption\n", + "Plain Text: 0123456789ABCDEF\n", + "Cipher Key: 133457799BBCDFF1\n", + "============================================\n", + "Running Golden C++ Simulation...\n", + "Golden C++ Simulation Output Cipher Text: 85E813540F0AB405\n", + "Golden C++ Simulation Complete\n", + "============================================\n", + "Running Verilog Simulation...\n", + "Verilog Simulation Output Cipher Text: 85E813540F0AB405\n", + "Verilog Simulation Complete\n", + "============================================\n", + "The Verilog and C++ Simulation are the same!\n", + "============================================\n" + ] + } + ] + }, + { + "cell_type": "markdown", + "source": [ + "## OpenLane Flow\n", + "\n", + "\n", + "---\n", + "\n" + ], + "metadata": { + "id": "yL7z3TSLudDX" + } + }, + { + "cell_type": "code", + "execution_count": 7, + "metadata": { + "id": "NC__X6Jph4CU", + "colab": { + "base_uri": "https://localhost:8080/" + }, + "outputId": "b6d13d3a-a747-4f3d-b620-d3d23742feaa" + }, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "Empty environment created at prefix: /content/conda-env\n", + "\n", + "Pinned packages:\n", + " - python 3.7*\n", + "\n", + "\n", + "Transaction\n", + "\n", + " Prefix: /content/conda-env\n", + "\n", + " Updating specs:\n", + "\n", + " - openlane=*\n", + " - open_pdks.sky130a=*\n", + "\n", + "\n", + " Package Version Build Channel Size\n", + "──────────────────────────────────────────────────────────────────────────────────────────────────────────────\n", + " Install:\n", + "──────────────────────────────────────────────────────────────────────────────────────────────────────────────\n", + "\n", + " \u001b[32m+ open_pdks.sky130a \u001b[0m 1.0.458_0_g8c68aca 20231104_052339 litex-hub\u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ _libgcc_mutex \u001b[0m 0.1 main main \u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ libstdcxx-ng \u001b[0m 11.2.0 h1234567_1 main \u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ ld_impl_linux-64 \u001b[0m 2.38 h1181459_1 main \u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ ca-certificates \u001b[0m 2023.08.22 h06a4308_0 main \u001b[32m Cached\u001b[0m\n", + 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Cached\u001b[0m\n", + " \u001b[32m+ _sysroot_linux-64_curr_repodata_hack\u001b[0m 3 haa98f57_10 main \u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ flit-core \u001b[0m 3.6.0 pyhd3eb1b0_0 main \u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ kernel-headers_linux-64 \u001b[0m 3.10.0 h57e8cba_10 main \u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ sysroot_linux-64 \u001b[0m 2.17 h57e8cba_10 main \u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ libxml2 \u001b[0m 2.9.9 20220706_155948 litex-hub\u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ netgen \u001b[0m 1.5.263_0_g4250525 20231104_052339 litex-hub\u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ yosys \u001b[0m 0.35_40_g031ad38b5 20231104_052339_py37 litex-hub\u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ tcllib \u001b[0m 1_21_120_gf12e9934f 20231104_052339 litex-hub\u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ typing_extensions \u001b[0m 4.4.0 py37h06a4308_0 main \u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ binutils_impl_linux-64 \u001b[0m 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magic \u001b[0m 8.3.450_0_g2133660 20231104_052339 litex-hub\u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ klayout \u001b[0m 0.28.12_21_gc71896fc5 20231104_052339_py37 litex-hub\u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ openroad \u001b[0m 2.0_10927_g0922eecb9 20231104_052339_py37 litex-hub\u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ verilator \u001b[0m 5.018_57_ga022b672a 20231104_052339 litex-hub\u001b[32m Cached\u001b[0m\n", + " \u001b[32m+ openlane \u001b[0m 2023.11.03_0_gf4f8dad8 20231104_052339_py37 litex-hub\u001b[32m Cached\u001b[0m\n", + "\n", + " Summary:\n", + "\n", + " Install: 76 packages\n", + "\n", + " Total download: 0 B\n", + "\n", + "──────────────────────────────────────────────────────────────────────────────────────────────────────────────\n", + "\n", + "\n", + "\n", + "Transaction starting\n", + "Linking open_pdks.sky130a-1.0.458_0_g8c68aca-20231104_052339\n", + "Linking _libgcc_mutex-0.1-main\n", + "Linking libstdcxx-ng-11.2.0-h1234567_1\n", + "Linking ld_impl_linux-64-2.38-h1181459_1\n", + "Linking ca-certificates-2023.08.22-h06a4308_0\n", + "Linking libstdcxx-devel_linux-64-11.2.0-h1234567_1\n", + "Linking libgcc-devel_linux-64-11.2.0-h1234567_1\n", + "Linking libgomp-11.2.0-h1234567_1\n", + "Linking _openmp_mutex-5.1-1_gnu\n", + "Linking libgcc-ng-11.2.0-h1234567_1\n", + "Linking libuuid-1.41.5-h5eee18b_0\n", + "Linking lz4-c-1.9.4-h6a678d5_0\n", + "Linking gmp-6.2.1-h295c915_3\n", + "Linking fmt-8.1.1-hd09550d_1\n", + "Linking bzip2-1.0.8-h7b6447c_0\n", + "Linking pixman-0.40.0-h7f8727e_1\n", + "Linking xz-5.4.2-h5eee18b_0\n", + "Linking yaml-0.2.5-h7b6447c_0\n", + "Linking libffi-3.4.4-h6a678d5_0\n", + "Linking ncurses-6.4-h6a678d5_0\n", + "Linking openssl-1.1.1w-h7f8727e_0\n", + "Linking libxcb-1.15-h7f8727e_0\n", + "Linking jpeg-9e-h5eee18b_1\n", + "Linking icu-58.2-he6710b0_3\n", + "Linking pcre-8.45-h295c915_0\n", + "Linking expat-2.5.0-h6a678d5_0\n", + "Linking m4-1.4.18-h4e445db_0\n", + "Linking zlib-1.2.13-h5eee18b_0\n", + "Linking spdlog-1.9.2-hd09550d_0\n", + "Linking readline-8.2-h5eee18b_0\n", + "Linking flex-2.6.4-ha10e3a4_1\n", + "Linking zstd-1.5.5-hc292b87_0\n", + "Linking libpng-1.6.39-h5eee18b_0\n", + "Linking glib-2.69.1-he621ea3_2\n", + "Linking tk-8.6.12-h1ccaba5_0\n", + "Linking gdbm-1.18-hd4cb3f1_4\n", + "Linking sqlite-3.41.2-h5eee18b_0\n", + "Linking bison-3.7.5-h2531618_1\n", + "Linking libboost-1.73.0-h28710b8_12\n", + "Linking freetype-2.12.1-h4a9f257_0\n", + "Linking gstreamer-1.14.1-h5eee18b_1\n", + "Linking dbus-1.13.18-hb2f20db_0\n", + "Linking ruby-3.1.2-h006b21b_1\n", + "Linking python-3.7.16-h7a1cb2a_0\n", + "Linking gst-plugins-base-1.14.1-h6a678d5_1\n", + "Linking certifi-2022.12.7-py37h06a4308_0\n", + "Linking wheel-0.38.4-py37h06a4308_0\n", + "Linking setuptools-65.6.3-py37h06a4308_0\n", + "Linking pip-22.3.1-py37h06a4308_0\n", + "Linking pyyaml-6.0-py37h5eee18b_1\n", + "Linking zipp-3.11.0-py37h06a4308_0\n", + "Linking _sysroot_linux-64_curr_repodata_hack-3-haa98f57_10\n", + "Linking flit-core-3.6.0-pyhd3eb1b0_0\n", + "Linking kernel-headers_linux-64-3.10.0-h57e8cba_10\n", + "Linking sysroot_linux-64-2.17-h57e8cba_10\n", + "Linking libxml2-2.9.9-20220706_155948\n", + "Linking netgen-1.5.263_0_g4250525-20231104_052339\n", + "Linking yosys-0.35_40_g031ad38b5-20231104_052339_py37\n", + "Linking tcllib-1_21_120_gf12e9934f-20231104_052339\n", + "Linking typing_extensions-4.4.0-py37h06a4308_0\n", + "Linking binutils_impl_linux-64-2.38-h2a08ee3_1\n", + "\u001b[33m\u001b[1mwarning libmamba\u001b[m [binutils_impl_linux-64-2.38-h2a08ee3_1] The following files were already present in the environment:\n", + " - lib/liblsan.so\n", + " - lib/liblsan.so.0\n", + " - lib/liblsan.so.0.0.0\n", + " - share/info/libgomp.info\n", + " - share/info/libquadmath.info\n", + " - share/licenses/gcc-libs/RUNTIME.LIBRARY.EXCEPTION\n", + " - share/licenses/gcc-libs/RUNTIME.LIBRARY.EXCEPTION.gomp_copy\n", + " - share/licenses/libstdc++/RUNTIME.LIBRARY.EXCEPTION\n", + "Linking fontconfig-2.13.0-h9420a91_0\n", + "Linking importlib-metadata-4.11.3-py37h06a4308_0\n", + "Linking gcc_impl_linux-64-11.2.0-h1234567_1\n", + "Linking binutils_linux-64-2.38.0-hc2dff05_0\n", + "Linking cairo-1.14.12-h8948797_3\n", + "Linking qt-5.9.7-h5867ecd_1\n", + "Linking click-8.0.4-py37h06a4308_0\n", + "Linking gxx_impl_linux-64-11.2.0-h1234567_1\n", + "Linking gcc_linux-64-11.2.0-h5c386dc_0\n", + "Linking gxx_linux-64-11.2.0-hc2dff05_0\n", + "Linking magic-8.3.450_0_g2133660-20231104_052339\n", + "Linking klayout-0.28.12_21_gc71896fc5-20231104_052339_py37\n", + "Linking openroad-2.0_10927_g0922eecb9-20231104_052339_py37\n", + "Linking verilator-5.018_57_ga022b672a-20231104_052339\n", + "Linking openlane-2023.11.03_0_gf4f8dad8-20231104_052339_py37\n", + "\n", + "Transaction finished\n", + "\n", + "To activate this environment, use:\n", + "\n", + " micromamba activate /content/conda-env\n", + "\n", + "Or to execute a single command in this environment, use:\n", + "\n", + " micromamba run -p /content/conda-env mycommand\n", + "\n", + "Collecting gdstk\n", + " Downloading gdstk-0.9.42-cp37-cp37m-manylinux_2_17_x86_64.manylinux2014_x86_64.whl (1.2 MB)\n", + "\u001b[2K \u001b[90m━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━\u001b[0m \u001b[32m1.2/1.2 MB\u001b[0m \u001b[31m11.9 MB/s\u001b[0m eta \u001b[36m0:00:00\u001b[0m\n", + "\u001b[?25hCollecting numpy\n", + " Downloading numpy-1.21.6-cp37-cp37m-manylinux_2_12_x86_64.manylinux2010_x86_64.whl (15.7 MB)\n", + "\u001b[2K \u001b[90m━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━\u001b[0m \u001b[32m15.7/15.7 MB\u001b[0m \u001b[31m48.6 MB/s\u001b[0m eta \u001b[36m0:00:00\u001b[0m\n", + "\u001b[?25hInstalling collected packages: numpy, gdstk\n", + "Successfully installed gdstk-0.9.42 numpy-1.21.6\n", + "\u001b[33mWARNING: Running pip as the 'root' user can result in broken permissions and conflicting behaviour with the system package manager. It is recommended to use a virtual environment instead: https://pip.pypa.io/warnings/venv\u001b[0m\u001b[33m\n", + "\u001b[0mCollecting libparse\n", + " Downloading libparse-0.3.1-cp37-cp37m-manylinux_2_17_x86_64.manylinux2014_x86_64.whl (1.0 MB)\n", + "\u001b[2K \u001b[90m━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━\u001b[0m \u001b[32m1.0/1.0 MB\u001b[0m \u001b[31m12.0 MB/s\u001b[0m eta \u001b[36m0:00:00\u001b[0m\n", + "\u001b[?25hRequirement already satisfied: wheel in ./conda-env/lib/python3.7/site-packages (from libparse) (0.38.4)\n", + "Installing collected packages: libparse\n", + "Successfully installed libparse-0.3.1\n", + "\u001b[33mWARNING: Running pip as the 'root' user can result in broken permissions and conflicting behaviour with the system package manager. It is recommended to use a virtual environment instead: https://pip.pypa.io/warnings/venv\u001b[0m\u001b[33m\n", + "\u001b[0menv: CONDA_PREFIX=/content/conda-env\n", + "env: PATH=/content/conda-env/bin:/content/conda-env/bin:/opt/bin:/usr/local/nvidia/bin:/usr/local/cuda/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/tools/node/bin:/tools/google-cloud-sdk/bin\n" + ] + } + ], + "source": [ + "#@title Install dependencies {display-mode: \"form\"}\n", + "#@markdown - Click the ▷ button to setup the digital design environment based on [conda-eda](https://github.com/hdl/conda-eda).\n", + "\n", + "openlane_version = 'latest' #@param {type:\"string\"}\n", + "open_pdks_version = 'latest' #@param {type:\"string\"}\n", + "\n", + "if openlane_version == 'latest':\n", + " openlane_version = ''\n", + "if open_pdks_version == 'latest':\n", + " open_pdks_version = ''\n", + "\n", + "import os\n", + "import pathlib\n", + "\n", + "!curl -Ls https://micro.mamba.pm/api/micromamba/linux-64/latest | tar -xj bin/micromamba\n", + "conda_prefix_path = pathlib.Path('conda-env')\n", + "CONDA_PREFIX = str(conda_prefix_path.resolve())\n", + "!bin/micromamba create --yes --prefix $CONDA_PREFIX\n", + "!echo 'python ==3.7*' >> {CONDA_PREFIX}/conda-meta/pinned\n", + "!CI=0 bin/micromamba install --yes --prefix $CONDA_PREFIX \\\n", + " --channel litex-hub \\\n", + " --channel main \\\n", + " openlane={openlane_version} \\\n", + " open_pdks.sky130a={open_pdks_version}\n", + "!python -m pip install gdstk gdstk\n", + "!python -m pip install libparse libparse\n", + "PATH = os.environ['PATH']\n", + "%env CONDA_PREFIX={CONDA_PREFIX}\n", + "%env PATH={CONDA_PREFIX}/bin:{PATH}\n" + ] + }, + { + "cell_type": "markdown", + "metadata": { + "id": "hp8h5vH8TUXr" + }, + "source": [ + "### Configure Flow\n", + "\n", + "For the target design, a frequency of 16.667 MHz and an area of 600um x 600um are both specified. These values can be changed based on the user's requirements and the [documentation](https://openlane.readthedocs.io/en/latest/reference/configuration.html) can be referenced for more information." + ] + }, + { + "cell_type": "code", + "source": [ + "%%writefile config.json\n", + "{\n", + " \"DESIGN_NAME\": \"des_top\",\n", + " \"VERILOG_FILES\": \"dir::code-a-chip-des/verilog/src/*.v\",\n", + " \"FP_CORE_UTIL\": \"50\",\n", + " \"CLOCK_PORT\": \"clk\",\n", + " \"CLOCK_PERIOD\": 60,\n", + " \"FP_SIZING\": \"absolute\",\n", + " \"DIE_AREA\": \"0 0 600 600\"\n", + "}" + ], + "metadata": { + "id": "rbT-vP0h0enK", + "colab": { + "base_uri": "https://localhost:8080/" + }, + "outputId": "d72099ec-4bf7-4846-8540-e0bf18fa9a66" + }, + "execution_count": 16, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "Overwriting config.json\n" + ] + } + ] + }, + { + "cell_type": "markdown", + "metadata": { + "id": "Nrt1yS_u1_m4", + "jp-MarkdownHeadingCollapsed": true, + "tags": [] + }, + "source": [ + "### Run Flow\n", + "\n", + "[OpenLane](https://openlane.readthedocs.io/en/latest/) is an automated [RTL](https://en.wikipedia.org/wiki/Register-transfer_level) to [GDSII](https://en.wikipedia.org/wiki/GDSII) flow based on several components including [OpenROAD](https://theopenroadproject.org/), [Yosys](https://yosyshq.net/yosys/), [Magic](http://www.opencircuitdesign.com/magic/), [Netgen](http://opencircuitdesign.com/netgen/) and custom methodology scripts for design exploration and optimization targeting [open source PDKs](https://github.com/google/open-source-pdks).\n", + "\n", + "![img](https://openlane.readthedocs.io/en/latest/_images/flow_v1.png)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "colab": { + "base_uri": "https://localhost:8080/" + }, + "id": "VP60fdObiP15", + "outputId": "e0ba36c3-a1cd-4d9e-c22f-a6038b94f3a1" + }, + "outputs": [ + { + "output_type": "stream", + "name": "stdout", + "text": [ + "env: PDK=sky130A\n", + "OpenLane 2023.11.03_0_gf4f8dad8-conda\n", + "All rights reserved. (c) 2020-2022 Efabless Corporation and contributors.\n", + "Available under the Apache License, version 2.0. See the LICENSE file for more details.\n", + "\n", + "\u001b[36m[INFO]: Using configuration in 'config.json'...\u001b[39m\n", + "\u001b[36m[INFO]: PDK Root: /content/conda-env/share/pdk\u001b[39m\n", + "\u001b[36m[INFO]: Process Design Kit: sky130A\u001b[39m\n", + "\u001b[36m[INFO]: Standard Cell Library: sky130_fd_sc_hd\u001b[39m\n", + "\u001b[36m[INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd\u001b[39m\n", + "\u001b[36m[INFO]: Run Directory: /content/runs/RUN_2023.11.27_06.08.46\u001b[39m\n", + "\u001b[36m[INFO]: Saving runtime environment...\u001b[39m\n", + "\u001b[36m[INFO]: Preparing LEF files for the nom corner...\u001b[39m\n", + "\u001b[36m[INFO]: Preparing LEF files for the min corner...\u001b[39m\n", + "\u001b[36m[INFO]: Preparing LEF files for the max corner...\u001b[39m\n", + "\u001b[33m[WARNING]: PNR_SDC_FILE is not set. It is recommended to write a custom SDC file for the design. Defaulting to BASE_SDC_FILE\u001b[39m\n", + "\u001b[33m[WARNING]: SIGNOFF_SDC_FILE is not set. It is recommended to write a custom SDC file for the design. Defaulting to BASE_SDC_FILE\u001b[39m\n", + "\u001b[36m[INFO]: Running linter (Verilator) (log: runs/RUN_2023.11.27_06.08.46/logs/synthesis/linter.log)...\u001b[39m\n", + "\u001b[36m[INFO]: 0 errors found by linter\u001b[39m\n", + "\u001b[33m[WARNING]: 22 warnings found by linter\u001b[39m\n", + "[STEP 1]\n", + "\u001b[36m[INFO]: Running Synthesis (log: runs/RUN_2023.11.27_06.08.46/logs/synthesis/1-synthesis.log)...\u001b[39m\n", + "[STEP 2]\n", + "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: runs/RUN_2023.11.27_06.08.46/logs/synthesis/2-sta.log)...\u001b[39m\n", + "[STEP 3]\n", + "\u001b[36m[INFO]: Running Initial Floorplanning (log: runs/RUN_2023.11.27_06.08.46/logs/floorplan/3-initial_fp.log)...\u001b[39m\n", + "\u001b[36m[INFO]: Floorplanned with width 588.8 and height 576.64.\u001b[39m\n", + "[STEP 4]\n", + "\u001b[36m[INFO]: Running IO Placement (log: runs/RUN_2023.11.27_06.08.46/logs/floorplan/4-io.log)...\u001b[39m\n", + "[STEP 5]\n", + "\u001b[36m[INFO]: Running Tap/Decap Insertion (log: runs/RUN_2023.11.27_06.08.46/logs/floorplan/5-tap.log)...\u001b[39m\n", + "\u001b[36m[INFO]: Power planning with power {VPWR} and ground {VGND}...\u001b[39m\n", + "[STEP 6]\n", + "\u001b[36m[INFO]: Generating PDN (log: runs/RUN_2023.11.27_06.08.46/logs/floorplan/6-pdn.log)...\u001b[39m\n", + "[STEP 7]\n", + "\u001b[36m[INFO]: Running Global Placement (log: runs/RUN_2023.11.27_06.08.46/logs/placement/7-global_skip_io.log)...\u001b[39m\n", + "[STEP 8]\n", + "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: runs/RUN_2023.11.27_06.08.46/logs/placement/8-gpl_sta.log)...\u001b[39m\n", + "[STEP 9]\n", + "\u001b[36m[INFO]: Running IO Placement (log: runs/RUN_2023.11.27_06.08.46/logs/placement/9-io.log)...\u001b[39m\n", + "[STEP 10]\n", + "\u001b[36m[INFO]: Running Global Placement (log: runs/RUN_2023.11.27_06.08.46/logs/placement/10-global.log)...\u001b[39m\n", + "[STEP 11]\n", + "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: runs/RUN_2023.11.27_06.08.46/logs/placement/11-gpl_sta.log)...\u001b[39m\n", + "[STEP 12]\n", + "\u001b[36m[INFO]: Running Placement Resizer Design Optimizations (log: runs/RUN_2023.11.27_06.08.46/logs/placement/12-resizer.log)...\u001b[39m\n", + "[STEP 13]\n", + "\u001b[36m[INFO]: Running Detailed Placement (log: runs/RUN_2023.11.27_06.08.46/logs/placement/13-detailed.log)...\u001b[39m\n", + "[STEP 14]\n", + "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: runs/RUN_2023.11.27_06.08.46/logs/placement/14-dpl_sta.log)...\u001b[39m\n", + "[STEP 15]\n", + "\u001b[36m[INFO]: Running Clock Tree Synthesis (log: runs/RUN_2023.11.27_06.08.46/logs/cts/15-cts.log)...\u001b[39m\n", + "[STEP 16]\n", + "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: runs/RUN_2023.11.27_06.08.46/logs/cts/16-cts_sta.log)...\u001b[39m\n", + "[STEP 17]\n", + "\u001b[36m[INFO]: Running Placement Resizer Timing Optimizations (log: runs/RUN_2023.11.27_06.08.46/logs/cts/17-resizer.log)...\u001b[39m\n", + "[STEP 18]\n", + "\u001b[36m[INFO]: Running Global Routing Resizer Design Optimizations (log: runs/RUN_2023.11.27_06.08.46/logs/routing/18-resizer_design.log)...\u001b[39m\n", + "[STEP 19]\n", + "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: runs/RUN_2023.11.27_06.08.46/logs/routing/19-rsz_design_sta.log)...\u001b[39m\n", + "[STEP 20]\n", + "\u001b[36m[INFO]: Running Global Routing Resizer Timing Optimizations (log: runs/RUN_2023.11.27_06.08.46/logs/routing/20-resizer_timing.log)...\u001b[39m\n", + "[STEP 21]\n", + "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: runs/RUN_2023.11.27_06.08.46/logs/routing/21-rsz_timing_sta.log)...\u001b[39m\n", + "[STEP 22]\n", + "\u001b[36m[INFO]: Running Global Routing (log: runs/RUN_2023.11.27_06.08.46/logs/routing/22-global.log)...\u001b[39m\n", + "\u001b[36m[INFO]: Starting OpenROAD Antenna Repair Iterations...\u001b[39m\n", + "[STEP 23]\n", + "\u001b[36m[INFO]: Writing Verilog (log: runs/RUN_2023.11.27_06.08.46/logs/routing/22-global_write_netlist.log)...\u001b[39m\n", + "[STEP 24]\n", + "\u001b[36m[INFO]: Running Single-Corner Static Timing Analysis (log: runs/RUN_2023.11.27_06.08.46/logs/routing/24-grt_sta.log)...\u001b[39m\n", + "[STEP 25]\n", + "\u001b[36m[INFO]: Running Fill Insertion (log: runs/RUN_2023.11.27_06.08.46/logs/routing/25-fill.log)...\u001b[39m\n", + "[STEP 26]\n", + "\u001b[36m[INFO]: Running Detailed Routing (log: runs/RUN_2023.11.27_06.08.46/logs/routing/26-detailed.log)...\u001b[39m\n" + ] + } + ], + "source": [ + "%env PDK=sky130A\n", + "!flow.tcl -design ." + ] + }, + { + "cell_type": "markdown", + "metadata": { + "id": "luguFgZ43AeL" + }, + "source": [ + "### Display Layout" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "id": "WOnhdtp3ivRi" + }, + "outputs": [], + "source": [ + "import pathlib\n", + "import gdstk\n", + "import IPython.display\n", + "\n", + "gdss = sorted(pathlib.Path('runs').glob('*/results/final/gds/*.gds'))\n", + "library = gdstk.read_gds(gdss[-1])\n", + "top_cells = library.top_level()\n", + "top_cells[0].write_svg('des.svg')\n", + "IPython.display.SVG('des.svg')" + ] + }, + { + "cell_type": "markdown", + "metadata": { + "id": "NW_7YdgTZYQK" + }, + "source": [ + "### Metrics\n", + "\n", + "[Documentation](https://openlane.readthedocs.io/en/latest/reference/datapoint_definitions.html)\n" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": { + "id": "OWAwQI3fZC4W", + "colab": { + "base_uri": "https://localhost:8080/", + "height": 1000 + }, + "outputId": "f4eb2daa-4cf7-43c3-d04d-26b2b21d85d9" + }, + "outputs": [ + { + "output_type": "execute_result", + "data": { + "text/plain": [ + " 0\n", + "design /content\n", + "design_name des_top\n", + "config RUN_2023.11.15_22.05.38\n", + "flow_status flow completed\n", + "total_runtime 1h50m53s0ms\n", + "routed_runtime 1h9m29s0ms\n", + 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"routing_layer6_pct 1.57\n", + "wires_count 24510\n", + "wire_bits 84659\n", + "public_wires_count 1086\n", + "public_wire_bits 61235\n", + "memories_count 0\n", + "memory_bits 0\n", + "processes_count 0\n", + "cells_pre_abc 23682\n", + "AND 1255\n", + "DFF 0\n", + "NAND 320\n", + "NOR 805\n", + "OR 7096\n", + "XOR 1100\n", + "XNOR 572\n", + "MUX 1280\n", + "inputs 188\n", + "outputs 130\n", + "level 66\n", + "DecapCells 16308\n", + "WelltapCells 4642\n", + "DiodeCells 126\n", + "FillCells 7130\n", + "NonPhysCells 13992\n", + "TotalCells 42198\n", + "CoreArea_um^2 323476.4896\n", + "power_slowest_internal_uW -1\n", + "power_slowest_switching_uW -1\n", + "power_slowest_leakage_uW -1\n", + "power_typical_internal_uW -1\n", + "power_typical_switching_uW -1\n", + "power_typical_leakage_uW -1\n", + "power_fastest_internal_uW -1\n", + "power_fastest_switching_uW -1\n", + "power_fastest_leakage_uW -1\n", + "critical_path_ns -1\n", + "suggested_clock_period 51.0\n", + "suggested_clock_frequency 19.607843\n", + "CLOCK_PERIOD 50\n", + "FP_ASPECT_RATIO 1\n", + "FP_CORE_UTIL 40\n", + "FP_PDN_HPITCH 153.18\n", + "FP_PDN_VPITCH 153.6\n", + "GRT_ADJUSTMENT 0.3\n", + "GRT_REPAIR_ANTENNAS 1\n", + "MAX_FANOUT_CONSTRAINT 10\n", + "PL_TARGET_DENSITY 0.5\n", + "RUN_HEURISTIC_DIODE_INSERTION 0\n", + "STD_CELL_LIBRARY sky130_fd_sc_hd\n", + "SYNTH_STRATEGY AREA 0" + ], + "text/html": [ + "\n", + "
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design/content
design_namedes_top
configRUN_2023.11.15_22.05.38
flow_statusflow completed
total_runtime1h50m53s0ms
routed_runtime1h9m29s0ms
(Cell/mm^2)/Core_Util101979.562837
DIEAREA_mm^20.34301
CellPer_mm^240791.825135
OpenDP_Util41.01
Final_Util-1
Peak_Memory_Usage_MB1183.35
synth_cell_count13526
tritonRoute_violations0
Short_violations0
MetSpc_violations0
OffGrid_violations0
MinHole_violations0
Other_violations0
Magic_violations0
pin_antenna_violations31
net_antenna_violations18
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spef_tns-1
HPWL458671602.0
routing_layer1_pct0.0
routing_layer2_pct45.35
routing_layer3_pct49.99
routing_layer4_pct18.35
routing_layer5_pct35.17
routing_layer6_pct1.57
wires_count24510
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public_wires_count1086
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outputs130
level66
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