Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

VHDL 2008/93/87 simulator

SystemVerilog to Verilog conversion

A simple and naive way to convert chisel code to systemverilog

cocotb: Python-based chip (RTL) verification

Multi-platform nightly builds of open source digital design and verification tools

A modular build system for hardware

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

Standard Cell Library based Memory Compiler using FF/Latch cells

SystemVerilog synthesis tool

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

Containers for FOSS tools

This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.

Public repository for PySysC, (From SC Common Practices Subgroup)

The SRAM timing analysis chip for verifying SRAMs generated by SRAM22

Verilator open-source SystemVerilog simulator and lint system

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

SystemRDL 2.0 language compiler front-end

Generate verilog register file from systemRDL description

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

Determines the modules declared and instantiated in a SystemVerilog file

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Padrick - A Smart Pad-Multiplexer IP Generator for SoCs

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

A simulator for photonic integrated circuits.

Contains a prototype implementation of a transactional verification algorithm that uses protocols to connect functional model and implementation.