A small, light weight, RISC CPU soft core

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Open source FPGA-based NIC and platform for in-network compute

AMBA AXI VIP

4 stage, in-order, compute RISC-V core based on the CV32E40P

Whisk: 16-bit serial processor for TT02

An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components

Send video/audio over HDMI on an FPGA

Must-have verilog systemverilog modules

SERV - The SErial RISC-V CPU

A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S defaults to 8 bits and AXI-MM to 64 bits)

Pinky (8-bit CPU) written in Verilog and an Assembler written in Python 3

Version 2 of my Crazy Small CPU

This is a mirror repository for official CTU CAN FD repository:

OpenXuantie - OpenC910 Core

NVMe Controller featuring Hardware Acceleration

Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossi…

AMBA bus generator including AXI4, AXI3, AHB, and APB

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…

国产VU13P加速卡资料