Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage …

A SystemVerilog source file pickler.

Build Customized FPGA Implementations for Vivado

Installs Vivado on M1/M2/M3 macs

Microsoft Catapult FPGA, Catapult V3, PCIE Test Demo, On-board usb Blaster and OpenCL BSP