diff --git a/ivtest/gold/sv_mixed_assign_error1-iverilog-stderr.gold b/ivtest/gold/sv_mixed_assign_error1-iverilog-stderr.gold new file mode 100644 index 000000000..d045d0131 --- /dev/null +++ b/ivtest/gold/sv_mixed_assign_error1-iverilog-stderr.gold @@ -0,0 +1,2 @@ +ivltests/sv_mixed_assign_error1.v:10: error: Cannot perform procedural assignment to array 'q' because it is also continuously assigned. +Elaboration failed diff --git a/ivtest/gold/sv_mixed_assign_error2-iverilog-stderr.gold b/ivtest/gold/sv_mixed_assign_error2-iverilog-stderr.gold new file mode 100644 index 000000000..922fef66d --- /dev/null +++ b/ivtest/gold/sv_mixed_assign_error2-iverilog-stderr.gold @@ -0,0 +1,5 @@ +ivltests/sv_mixed_assign_error2.v:15: error: Cannot perform procedural assignment to array word 'p['sd1]' because it is also continuously assigned. +ivltests/sv_mixed_assign_error2.v:16: error: Cannot perform procedural assignment to array word 'p[i]' because it is also continuously assigned. +ivltests/sv_mixed_assign_error2.v:17: error: Cannot perform procedural assignment to array word 'q['sd0]' because it is also continuously assigned. +ivltests/sv_mixed_assign_error2.v:18: error: Cannot perform procedural assignment to array word 'q['sd1]' because it is also continuously assigned. +4 error(s) during elaboration. diff --git a/ivtest/gold/sv_mixed_assign_error3-iverilog-stderr.gold b/ivtest/gold/sv_mixed_assign_error3-iverilog-stderr.gold new file mode 100644 index 000000000..dc6c851f3 --- /dev/null +++ b/ivtest/gold/sv_mixed_assign_error3-iverilog-stderr.gold @@ -0,0 +1,2 @@ +ivltests/sv_mixed_assign_error3.v:10: error: Cannot perform procedural assignment to variable 'q' because it is also continuously assigned. +Elaboration failed diff --git a/ivtest/gold/sv_mixed_assign_error4-iverilog-stderr.gold b/ivtest/gold/sv_mixed_assign_error4-iverilog-stderr.gold new file mode 100644 index 000000000..9d7743ad7 --- /dev/null +++ b/ivtest/gold/sv_mixed_assign_error4-iverilog-stderr.gold @@ -0,0 +1,11 @@ +ivltests/sv_mixed_assign_error4.v:13: error: Cannot perform procedural assignment to part select 'v['sd3:'sd2]' because it is also continuously assigned. +ivltests/sv_mixed_assign_error4.v:14: error: Cannot perform procedural assignment to part select 'v['sd5:'sd4]' because it is also continuously assigned. +ivltests/sv_mixed_assign_error4.v:18: error: Cannot perform procedural assignment to part select 'v['sd2+:'sd2]' because it is also continuously assigned. +ivltests/sv_mixed_assign_error4.v:19: error: Cannot perform procedural assignment to part select 'v['sd5-:'sd2]' because it is also continuously assigned. +ivltests/sv_mixed_assign_error4.v:22: error: Cannot perform procedural assignment to part select 'v[lsb+:'sd2]' because it is also continuously assigned. +ivltests/sv_mixed_assign_error4.v:23: error: Cannot perform procedural assignment to part select 'v[msb-:'sd2]' because it is also continuously assigned. +ivltests/sv_mixed_assign_error4.v:26: error: Cannot perform procedural assignment to bit select 'v['sd2]' because it is also continuously assigned. +ivltests/sv_mixed_assign_error4.v:27: error: Cannot perform procedural assignment to bit select 'v['sd4]' because it is also continuously assigned. +ivltests/sv_mixed_assign_error4.v:30: error: Cannot perform procedural assignment to bit select 'v[lsb]' because it is also continuously assigned. +ivltests/sv_mixed_assign_error4.v:31: error: Cannot perform procedural assignment to bit select 'v[msb]' because it is also continuously assigned. +10 error(s) during elaboration. diff --git a/ivtest/ivltests/sv_mixed_assign1.v b/ivtest/ivltests/sv_mixed_assign1.v new file mode 100644 index 000000000..8d234c17a --- /dev/null +++ b/ivtest/ivltests/sv_mixed_assign1.v @@ -0,0 +1,40 @@ +// Check different words in an array word can be procedurally and continuously assigned. +module test(); + +logic [7:0] a[2:0]; + +assign a[0] = 8'd1; + +reg failed = 0; + +initial begin + a[1] = 8'd2; + #0 $display("%b %b %b", a[0], a[1], a[2]); + if (a[0] !== 8'd1 || a[1] !== 8'd2 || a[2] !== 8'bx) failed = 1; +/* + * IEEE 1800-2017 states that "A force or release statement shall not be + * applied to a variable that is being assigned by a mixture of continuous + * and procedural assignments.", but some other compilers allow this. It + * looks to be more work to detect and report it as an error than to allow + * it. + */ + force a[0] = 8'd3; + #0 $display("%b %b %b", a[0], a[1], a[2]); + if (a[0] !== 8'd3 || a[1] !== 8'd2 || a[2] !== 8'bx) failed = 1; + force a[1] = 8'd4; + #0 $display("%b %b %b", a[0], a[1], a[2]); + if (a[0] !== 8'd3 || a[1] !== 8'd4 || a[2] !== 8'bx) failed = 1; + release a[0]; + #0 $display("%b %b %b", a[0], a[1], a[2]); + if (a[0] !== 8'd1 || a[1] !== 8'd4 || a[2] !== 8'bx) failed = 1; + release a[1]; + #0 $display("%b %b %b", a[0], a[1], a[2]); + if (a[0] !== 8'd1 || a[1] !== 8'd4 || a[2] !== 8'bx) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/sv_mixed_assign2.v b/ivtest/ivltests/sv_mixed_assign2.v new file mode 100644 index 000000000..45fe49377 --- /dev/null +++ b/ivtest/ivltests/sv_mixed_assign2.v @@ -0,0 +1,40 @@ +// Check different parts of a variable can be procedurally and continuously assigned. +module test(); + +logic [11:0] v; + +assign v[7:4] = 4'd1; + +reg failed = 0; + +initial begin + v[11:8] = 4'd2; + #0 $display("%b", v); + if (v !== 12'b00100001xxxx) failed = 1; +/* + * IEEE 1800-2017 states that "A force or release statement shall not be + * applied to a variable that is being assigned by a mixture of continuous + * and procedural assignments.", but some other compilers allow this. It + * looks to be more work to detect and report it as an error than to allow + * it. + */ + force v[7:4] = 8'd3; + #0 $display("%b", v); + if (v !== 12'b00100011xxxx) failed = 1; + force v[11:8] = 8'd4; + #0 $display("%b", v); + if (v !== 12'b01000011xxxx) failed = 1; + release v[7:4]; + #0 $display("%b", v); + if (v !== 12'b01000001xxxx) failed = 1; + release v[11:8]; + #0 $display("%b", v); + if (v !== 12'b01000001xxxx) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/sv_mixed_assign_error1.v b/ivtest/ivltests/sv_mixed_assign_error1.v new file mode 100644 index 000000000..a9781da9c --- /dev/null +++ b/ivtest/ivltests/sv_mixed_assign_error1.v @@ -0,0 +1,13 @@ +// Check entire array cannot be both procedurally and continuously assigned. +module test(); + +logic [7:0] p[1:0]; +logic [7:0] q[1:0]; + +assign q = p; + +initial begin + q = '{ 8'd0, 8'd0 }; +end + +endmodule diff --git a/ivtest/ivltests/sv_mixed_assign_error2.v b/ivtest/ivltests/sv_mixed_assign_error2.v new file mode 100644 index 000000000..36daea639 --- /dev/null +++ b/ivtest/ivltests/sv_mixed_assign_error2.v @@ -0,0 +1,21 @@ +// Check array word cannot be both procedurally and continuously assigned. +module test(); + +logic [7:0] p[1:0]; +logic [7:0] q[1:0]; + +assign p[1] = 8'd2; + +assign q = p; + +integer i; + +initial begin + p[0] = 8'd3; + p[1] = 8'd4; + p[i] = 8'd5; + q[0] = 8'd6; + q[1] = 8'd7; +end + +endmodule diff --git a/ivtest/ivltests/sv_mixed_assign_error3.v b/ivtest/ivltests/sv_mixed_assign_error3.v new file mode 100644 index 000000000..f3588fc86 --- /dev/null +++ b/ivtest/ivltests/sv_mixed_assign_error3.v @@ -0,0 +1,13 @@ +// Check entire vector cannot be both procedurally and continuously assigned. +module test(); + +logic [7:0] p; +logic [7:0] q; + +assign q = p; + +initial begin + q = 8'd0; +end + +endmodule diff --git a/ivtest/ivltests/sv_mixed_assign_error4.v b/ivtest/ivltests/sv_mixed_assign_error4.v new file mode 100644 index 000000000..f973a96cc --- /dev/null +++ b/ivtest/ivltests/sv_mixed_assign_error4.v @@ -0,0 +1,34 @@ +// Check vector part cannot be both procedurally and continuously assigned. +module test(); + +logic [7:0] v; + +assign v[5:2] = 4'd0; + +integer lsb = 0; +integer msb = 7; + +initial begin + v[1:0] = 2'd1; + v[3:2] = 2'd1; + v[5:4] = 2'd1; + v[7:6] = 2'd1; + + v[0 +: 2] = 2'd2; + v[2 +: 2] = 2'd2; + v[5 -: 2] = 2'd2; + v[7 -: 2] = 2'd2; + + v[lsb +: 2] = 2'd3; + v[msb -: 2] = 2'd3; + + v[0] = 1'b1; + v[2] = 1'b1; + v[4] = 1'b1; + v[6] = 1'b1; + + v[lsb] = 1'b1; + v[msb] = 1'b1; +end + +endmodule diff --git a/ivtest/regress-vvp.list b/ivtest/regress-vvp.list index 33e09d425..4037559c9 100644 --- a/ivtest/regress-vvp.list +++ b/ivtest/regress-vvp.list @@ -204,6 +204,12 @@ sv_foreach9 vvp_tests/sv_foreach9.json sv_foreach10 vvp_tests/sv_foreach10.json sv_interface vvp_tests/sv_interface.json sv_literals vvp_tests/sv_literals.json +sv_mixed_assign1 vvp_tests/sv_mixed_assign1.json +sv_mixed_assign2 vvp_tests/sv_mixed_assign2.json +sv_mixed_assign_error1 vvp_tests/sv_mixed_assign_error1.json +sv_mixed_assign_error2 vvp_tests/sv_mixed_assign_error2.json +sv_mixed_assign_error3 vvp_tests/sv_mixed_assign_error3.json +sv_mixed_assign_error4 vvp_tests/sv_mixed_assign_error4.json sv_module_port1 vvp_tests/sv_module_port1.json sv_module_port2 vvp_tests/sv_module_port2.json sv_module_port3 vvp_tests/sv_module_port3.json diff --git a/ivtest/vvp_tests/sv_mixed_assign1.json b/ivtest/vvp_tests/sv_mixed_assign1.json new file mode 100644 index 000000000..207fb7c8c --- /dev/null +++ b/ivtest/vvp_tests/sv_mixed_assign1.json @@ -0,0 +1,5 @@ +{ + "type" : "NI", + "source" : "sv_mixed_assign1.v", + "iverilog-args" : [ "-g2009" ] +} diff --git a/ivtest/vvp_tests/sv_mixed_assign2.json b/ivtest/vvp_tests/sv_mixed_assign2.json new file mode 100644 index 000000000..207fb7c8c --- /dev/null +++ b/ivtest/vvp_tests/sv_mixed_assign2.json @@ -0,0 +1,5 @@ +{ + "type" : "NI", + "source" : "sv_mixed_assign1.v", + "iverilog-args" : [ "-g2009" ] +} diff --git a/ivtest/vvp_tests/sv_mixed_assign_error1.json b/ivtest/vvp_tests/sv_mixed_assign_error1.json new file mode 100644 index 000000000..967b059f5 --- /dev/null +++ b/ivtest/vvp_tests/sv_mixed_assign_error1.json @@ -0,0 +1,6 @@ +{ + "type" : "CE", + "source" : "sv_mixed_assign_error1.v", + "gold" : "sv_mixed_assign_error1", + "iverilog-args" : [ "-g2009" ] +} diff --git a/ivtest/vvp_tests/sv_mixed_assign_error2.json b/ivtest/vvp_tests/sv_mixed_assign_error2.json new file mode 100644 index 000000000..967b059f5 --- /dev/null +++ b/ivtest/vvp_tests/sv_mixed_assign_error2.json @@ -0,0 +1,6 @@ +{ + "type" : "CE", + "source" : "sv_mixed_assign_error1.v", + "gold" : "sv_mixed_assign_error1", + "iverilog-args" : [ "-g2009" ] +} diff --git a/ivtest/vvp_tests/sv_mixed_assign_error3.json b/ivtest/vvp_tests/sv_mixed_assign_error3.json new file mode 100644 index 000000000..967b059f5 --- /dev/null +++ b/ivtest/vvp_tests/sv_mixed_assign_error3.json @@ -0,0 +1,6 @@ +{ + "type" : "CE", + "source" : "sv_mixed_assign_error1.v", + "gold" : "sv_mixed_assign_error1", + "iverilog-args" : [ "-g2009" ] +} diff --git a/ivtest/vvp_tests/sv_mixed_assign_error4.json b/ivtest/vvp_tests/sv_mixed_assign_error4.json new file mode 100644 index 000000000..967b059f5 --- /dev/null +++ b/ivtest/vvp_tests/sv_mixed_assign_error4.json @@ -0,0 +1,6 @@ +{ + "type" : "CE", + "source" : "sv_mixed_assign_error1.v", + "gold" : "sv_mixed_assign_error1", + "iverilog-args" : [ "-g2009" ] +}