From cfcda71bc723690855bad3ea8db965e26aa305eb Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 2 Sep 2024 19:05:02 +0200 Subject: [PATCH] ivtest: Add regression test to check that shift rhs is always unsigned Add a regression test to check that the right-hand side of a shift operation is always treated as unsigned, even if it is a signed registers or a variation thereof. Signed-off-by: Lars-Peter Clausen --- ivtest/ivltests/shift6.v | 51 ++++++++++++++++++++++++++++++++++++ ivtest/regress-vvp.list | 1 + ivtest/vvp_tests/shift6.json | 5 ++++ 3 files changed, 57 insertions(+) create mode 100644 ivtest/ivltests/shift6.v create mode 100644 ivtest/vvp_tests/shift6.json diff --git a/ivtest/ivltests/shift6.v b/ivtest/ivltests/shift6.v new file mode 100644 index 000000000..7dd09a75c --- /dev/null +++ b/ivtest/ivltests/shift6.v @@ -0,0 +1,51 @@ +module test; + +// Check that the right hand side for a shift instruction is always treated as +// unsigned. Even if its a signed register, or a transformation thereof. + + reg failed = 1'b0; + + `define check(val, exp) \ + if ((val) !== (exp)) begin \ + $display("FAILED(%0d): `%s`, expected `%0d`, got `%0d`.", `__LINE__, \ + `"val`", (exp), (val), 4); \ + failed = 1'b1; \ + end + + reg signed [1:0] shift = 2'b10; + + initial begin + `check(1 << shift, 4) + `check(1 << shift[1:0], 4) + `check(2 << shift[1], 4) + `check(1 << $unsigned(shift), 4) + `check(1 << $signed(shift), 4) + `check(1 << {shift}, 4) + + `check(1 <<< shift, 4) + `check(1 <<< shift[1:0], 4) + `check(2 <<< shift[1], 4) + `check(1 <<< $unsigned(shift), 4) + `check(1 <<< $signed(shift), 4) + `check(1 <<< {shift}, 4) + + `check(16 >> shift, 4) + `check(16 >> shift[1:0], 4) + `check(8 >> shift[1], 4) + `check(16 >> $unsigned(shift), 4) + `check(16 >> $signed(shift), 4) + `check(16 >> {shift}, 4) + + `check(16 >>> shift, 4) + `check(16 >>> shift[1:0], 4) + `check(8 >>> shift[1], 4) + `check(16 >>> $unsigned(shift), 4) + `check(16 >>> $signed(shift), 4) + `check(16 >>> {shift}, 4) + + if (!failed) begin + $display("PASSED"); + end + end + +endmodule diff --git a/ivtest/regress-vvp.list b/ivtest/regress-vvp.list index 6f3d6da74..0d9dcbe91 100644 --- a/ivtest/regress-vvp.list +++ b/ivtest/regress-vvp.list @@ -185,6 +185,7 @@ sf_countones_fail vvp_tests/sf_countones_fail.json sf_isunknown_fail vvp_tests/sf_isunknown_fail.json sf_onehot_fail vvp_tests/sf_onehot_fail.json sf_onehot0_fail vvp_tests/sf_onehot0_fail.json +shift6 vvp_tests/shift6.json single_element_array vvp_tests/single_element_array.json struct_enum_partsel vvp_tests/struct_enum_partsel.json struct_field_left_right vvp_tests/struct_field_left_right.json diff --git a/ivtest/vvp_tests/shift6.json b/ivtest/vvp_tests/shift6.json new file mode 100644 index 000000000..b88acf95c --- /dev/null +++ b/ivtest/vvp_tests/shift6.json @@ -0,0 +1,5 @@ + +{ + "type" : "normal", + "source" : "shift6.v" +}