How to build and use target 'fpga'?

[Butylochnik]

Hello, boys and girls! ;-)
It seems like last sources don't build necessary files for synthesis for fpga target.
I found the strings in the Makefile:

UBDIRS = ivlpp vhdlpp vvp vpi libveriuser cadpli tgt-null tgt-stub tgt-vvp \
          tgt-vhdl tgt-vlog95 tgt-pcb tgt-blif tgt-sizer tgt-fpga driver
# Only run distclean for these directories.
NOTUSED = tgt-pal tgt-verilog

moved "tgt-fpga" from NOTUSED to UBDIRS, run make and got a lot of warnings and errors.
It seems like tgt-fpga was "abandoned" and did not updated for a long time.
Why?
Do anyone here tried to correct all the errors and get correct build so that get fpga target?
Was it successful?

[martinwhitaker]

It seems like tgt-fpga was "abandoned" and did not updated for a long time. Why?

Writing a good synthesis tool is a lot of work. And you have to use the vendors' tools for place & route, so there's really not much to be gained from not using them for the initial synthesis.

[Butylochnik]

Thank you, for your reply.
Actually I would simply use Xilinx’s Vivado tool for whole design, from A to Z. But Vivado is huge for my PC. The idea was to use relatively small iVerilog for design and primary synthesis verification. Then make Place & Route and bit file generation at other PC with Vivado. For the moment I use option -S to verify synthesizability. But want to see synthesis results for real device.
But what happened with tgt-fpga? How many versions ago it was abandoned? Is it possible to run it for some Xilinx device? I hope for some old devices it had to work.

[steveicarus]

What Icarus Verilog determines to be synthesizeable, while similar to Vivado, is probably different enough that this will not really be a useful test. In any case, you don't need to use the fpga target for that task.

The fpga target is pretty much abandoned, since it never really got good results or traction in the first place. it's just to much of a specialized task, and the vendors commonly have free synthesizers for their devices anyhow. No one thought it worthwhile to continue with the fpga target.

[Butylochnik]

I analyzed content of the net-list iVerilog generates with option -S. It contains logic elements, ffs, adders, comparators. This looks similar to a net-list for bare silicon design. For fpga net-list should be different. Schematic should be fit in CLBs, and net-list should contain cnfigration information for CLBs and connections between CLBs. And this is a quite complex task.
Am I right?

[steveicarus]

You are right, it is an intensely complex task. In fact, there is no real solution in the mathematical sense and most vendor tools for place-and-route use stochastic methods. (Synthesis in the generic sense is not all that hard, but in the part specific sense, it's almost as challenging as P&R.) That, and the vendors tend to have free tools for their parts, led us to leave that bit to the vendors.

[Butylochnik]

Well, I see.
Thanks/