The example code of document cannot work

[Freed-Wu]

https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/getting_started.rst?plain=1#L64-L120:

For
example, the counter model in counter.v

.. code-block:: verilog

module counter(output, clk, reset);

parameter WIDTH = 8;

output [WIDTH-1 : 0] output;
input 	       clk, reset;

reg [WIDTH-1 : 0]   out;
wire 	       clk, reset;

always @(posedge clk or posedge reset)
  if (reset)
    output <= 0;
  else
    output <= output + 1;

endmodule // counter

and the test bench in counter_tb.v

.. code-block:: verilog

module test;

/* Make a reset that pulses once. */
reg reset = 0;
initial begin
   # 17 reset = 1;
   # 11 reset = 0;
   # 29 reset = 1;
   # 11 reset = 0;
   # 100 $stop;
end

/* Make a regular pulsing clock. */
reg clk = 0;
always #5 clk = !clk;

wire [7:0] value;
counter c1 (value, clk, reset);

initial
   $monitor("At time %t, value = %h (%0d)",
            $time, value, value);

endmodule // test

are written into different files.

The "iverilog" command supports multi-file designs by two methods. The
simplest is to list the files on the command line::

% iverilog -o my_design counter_tb.v counter.v
% vvp my_design

I try but get

$ iverilog -o my_design  counter_tb.v counter.v
counter.v:1: syntax error
counter.v:1: Errors in port declarations.
counter.v:5: syntax error
counter.v:5: error: Invalid variable list in port declaration.
counter.v:13: syntax error
counter.v:13: Syntax in assignment statement l-value.
counter.v:15: syntax error
counter.v:15: error: Malformed statement

[caryr]

"output" is a keyword. Try using "out" for the port name

[martinwhitaker]

It seems the example code was changed (and broken) when it was copied from the Wiki. I've just pushed a fix to the master branch.