diff --git a/projects/ice-v/CPUs/ice-v-swirl.si b/projects/ice-v/CPUs/ice-v-swirl.si
index bde2fb6f..0d5e24e1 100644
--- a/projects/ice-v/CPUs/ice-v-swirl.si
+++ b/projects/ice-v/CPUs/ice-v-swirl.si
@@ -194,7 +194,7 @@ $$end
     { // ==== stage 1 ==========================================================
 $$if DEBUG_swirl then
 if (debug_on) {
-      __display("[1] cycle:%d stall_cpu:%b refetch:%b refetch_addr:%x refetching:%b pc:%x",cycle,stall_cpu,refetch,refetch_addr<<2,refetching,pc<<2);
+      __display("[1] cycle:%d reset:%b stall_cpu:%b refetch:%b refetch_addr:%x refetching:%b pc:%x",cycle,reset,stall_cpu,refetch,refetch_addr<<2,refetching,pc<<2);
       __display("[1] cycle:%d imem.addr:%x imem.rdata:%x dmem.addr:%x dmem.rdata:%x",cycle,imem.addr<<2,imem.rdata,dmem.addr<<2,dmem.rdata);
 }
 $$end
@@ -227,8 +227,8 @@ $$end
 $$if DEBUG_swirl then
 if (debug_on) {
       if (~stall_cpu | on_stall) {
-        __display("[1] instr: %x @%x (bubble:%b reset:%b refetch:%b hold:%b stall_cpu:%b alu_busy:%b rs1 %d rs2 %d)",
-          instr,pc<<2,bubble,reset,refetch,hold,stall_cpu,exec.working,xregsA.addr0,xregsB.addr0);
+        __display("[1] cycle:%d instr: %x @%x (bubble:%b reset:%b refetch:%b hold:%b stall_cpu:%b alu_busy:%b rs1 %d rs2 %d)",
+          cycle,instr,pc<<2,bubble,reset,refetch,hold,stall_cpu,exec.working,xregsA.addr0,xregsB.addr0);
         if (bpred) {
           __display("[1] pc @%x following branch to @%x",pc<<2,imem.addr<<2);
         }
@@ -509,7 +509,7 @@ $$if TRACE_swirl then
 $$end
 
       // signal a jump if needed (flushes pipeline and jumps)
-      refetch          = stall_cpu             // on a stall trigger (and hold) a refetch
+      refetch          = ~reset & stall_cpu             // on a stall trigger (and hold) a refetch
                        | ( ( jump ^ bpred )    // jump prediction failed
                          & ~refetch & ~bubble );
       //                 ^^^^^^ reset refetch if done at prev cycle
@@ -594,11 +594,12 @@ $$end
 $$if DEBUG_swirl then
 if (debug_on) {
     if (~stall_cpu) {
+      __display("-- cycle %d --",cycle);
       __display("exec.xa = %x exec.xb = %x mem.wdata = %x",exec.xa,exec.xb,dmem.wdata);
       __display("exec.jump = %b exec.n = %x  xb_store = %x",exec.jump,exec.n,xb_store);
       __display("xa_keep %b xa_regR %b xa_regW %b xa_regW_prev %b",xa_keep,xa_regR,xa_regW,xa_regW_prev);
       __display("xb_keep %b xb_regR %b xb_regW %b xb_regW_prev %b",xb_keep,xb_regR,xb_regW,xb_regW_prev);
-      __display("imem.addr @%x, dmem.addr @%x\n",imem.addr<<2,dmem.addr<<2);
+      __display("imem.addr @%x, dmem.addr @%x\n",{2b00,imem.addr}<<2,dmem.addr<<2);
     }
 }
 $$end
diff --git a/projects/ice-v/SOCs/swirl-cache.si b/projects/ice-v/SOCs/swirl-cache.si
index bb33e379..cf6d6f6c 100644
--- a/projects/ice-v/SOCs/swirl-cache.si
+++ b/projects/ice-v/SOCs/swirl-cache.si
@@ -285,16 +285,20 @@ $$end
     // main loop
 
     while (1) {
-      if (update_lines_todo) {
+      if (update_lines_todo
+$$if cache_has_spiflash then
+        & ~rom.busy
+$$end
+      ) {
         // there is a pending cache miss
 $$if SIMULATION then
-        if (debug_on) {
-          __display("[%d] => cache miss %b|%b %x|%x (%x_%d|%x_%d)",cycle,
-            ~cache0_hit,~cache1_hit,
-            {qaddr0,2b00},{qaddr1,2b00},
-            cache0_lines.rdata[0,$cache_addr_w$],cache0_lines.addr,
-            cache1_lines.rdata[0,$cache_addr_w$],cache1_lines.addr);
-        }
+        //if (debug_on) {
+        //  __display("[%d] => cache miss %b|%b %x|%x (%x_%d|%x_%d)",cycle,
+        //    ~cache0_hit,~cache1_hit,
+        //    {qaddr0,2b00},{qaddr1,2b00},
+        //    cache0_lines.rdata[0,$cache_addr_w$],cache0_lines.addr,
+        //    cache1_lines.rdata[0,$cache_addr_w$],cache1_lines.addr);
+        //}
 $$end
         // if line is dirty, store back
         //                  vvvvv start by cache0, then cache1
@@ -383,12 +387,12 @@ $$else
             uint16 wdata   = reg_ram_rdata << {n[0,1],3b0};
 $$end
             $$if SIMULATION then
-            //uint32 full = ram.addr + n;
             //if (debug_on) {
+            //  uint32 full = ram.addr + n;
             //  __display("[cache|%d] load @%x = %x (cache %b, line %d, cycle %d, n %d, ram:%b rom:%b)",
             //            cycle,full,reg_ram_rdata,cache0_hit,~cache0_hit ? qline0_id : qline1_id,cycle,n,reg_ram_datanext,rom.rdata_available);
             //}
-            // __write("%x,", reg_ram_rdata);
+            // __write("%x,", (ram.in_ready ? reg_ram_rdata : rom.rdata));
             $$end
             // cache 0
             spram0.addr    = {qline0_id,n[2,$cache_line_w$]};