From a707676329f7c304a3311c764512b5c6cf06eaae Mon Sep 17 00:00:00 2001 From: Sylvain Lefebvre Date: Tue, 14 Nov 2023 19:44:54 +0100 Subject: [PATCH] ice-v swirl, cleanup, comments --- projects/ice-v/CPUs/ice-v-swirl.si | 4 ++-- projects/ice-v/SOCs/ice-v-soc-swirl-cache.si | 2 +- projects/ice-v/src/test_pip.s | 15 +++++++++++++++ 3 files changed, 18 insertions(+), 3 deletions(-) create mode 100644 projects/ice-v/src/test_pip.s diff --git a/projects/ice-v/CPUs/ice-v-swirl.si b/projects/ice-v/CPUs/ice-v-swirl.si index 15b306e1..dd191b2a 100644 --- a/projects/ice-v/CPUs/ice-v-swirl.si +++ b/projects/ice-v/CPUs/ice-v-swirl.si @@ -97,9 +97,9 @@ $$print("====== ice-v swirl (pipeline, data bypass, rdcycle) ======") // - the register written by stage 4 at this cycle [case b] // - none of the above: we have to wait and hold the pipeline [case c] // -// case a) input register value incorrect +// case a) input register value incorrect due to write at i-1 // due to [write at i-1] => mux -// case b) setup register value incorrect, ALU and store +// case b) setup register value incorrect due to write at i // due to [write at i ] => mux // case c) instruction in stage 3 /will/ invalidate a setup register // due to [write at i+1] => hold diff --git a/projects/ice-v/SOCs/ice-v-soc-swirl-cache.si b/projects/ice-v/SOCs/ice-v-soc-swirl-cache.si index f7b2720e..153ea64f 100644 --- a/projects/ice-v/SOCs/ice-v-soc-swirl-cache.si +++ b/projects/ice-v/SOCs/ice-v-soc-swirl-cache.si @@ -255,7 +255,7 @@ $$end algorithm { $$if SIMULATION and not BARE then //while (1) { } - while (cycle < 4000) { } + while (cycle < 250) { } __display("stopping at cycle %d",cycle); $$else while (1) { } diff --git a/projects/ice-v/src/test_pip.s b/projects/ice-v/src/test_pip.s new file mode 100644 index 00000000..35bf43d2 --- /dev/null +++ b/projects/ice-v/src/test_pip.s @@ -0,0 +1,15 @@ +.globl _start + +_start: + +addi t0,zero,0 + +addi t1,t0,1 +addi t2,t1,1 +addi t3,t2,1 +addi t4,t3,1 +addi t5,t4,1 +addi t6,t5,1 + +_end: +jal _end