diff --git a/frameworks/boards/ulx3s/ulx3s.lpf b/frameworks/boards/ulx3s/ulx3s.lpf
index bdbe5338..0af352a1 100644
--- a/frameworks/boards/ulx3s/ulx3s.lpf
+++ b/frameworks/boards/ulx3s/ulx3s.lpf
@@ -27,6 +27,11 @@ IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33;
 IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33;
 IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33;
 
+LOCATE COMP "uart_tx" SITE "L4"; # FPGA transmits to ftdi
+LOCATE COMP "uart_rx" SITE "M1"; # FPGA receives from ftdi
+IOBUF PORT "uart_tx" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "uart_rx" PULLMODE=UP IO_TYPE=LVCMOS33;
+
 ## LED indicators "blinkey" and "gpio" sheet
 LOCATE COMP "leds[7]" SITE "H3";
 LOCATE COMP "leds[6]" SITE "E1";
diff --git a/frameworks/boards/ulx3s/ulx3s.v b/frameworks/boards/ulx3s/ulx3s.v
index 7c2e1f97..a83949f6 100644
--- a/frameworks/boards/ulx3s/ulx3s.v
+++ b/frameworks/boards/ulx3s/ulx3s.v
@@ -80,6 +80,8 @@ $$pin.usb_fpga_pu_dp = 1
 $$pin.usb_fpga_pu_dn = 1
 $$pin.ftdi_rxd   = 1
 $$pin.ftdi_txd   = 1
+$$pin.uart_rx    = 1
+$$pin.uart_tx    = 1
 $$pin.flash_csn  = 1
 $$pin.flash_mosi = 1
 $$pin.flash_miso = 1
@@ -99,6 +101,7 @@ $$pin.qqspi_bank1= 1
 module top(
   %TOP_SIGNATURE%
   output wifi_gpio0,
+  input  [6:0] btns, //// FIXME TODO: issue with reset making btns mandatory (hotfix)
   input  clk_25mhz
   );
 
@@ -106,7 +109,8 @@ module top(
 // ------------------- TODO: 'fake' pin declaration in MAIN_GLUE
 wire flash_clk; // ECP5 specific, see https://github.com/mattvenn/basic-ecp5-pcb/issues/3
 
-wire ready = 0;
+// wire ready = 0;
+wire ready = btns[0];
 reg [15:0] RST_d;
 reg [15:0] RST_q;
 
@@ -118,7 +122,7 @@ always @(posedge clk_25mhz) begin
   if (ready) begin
     RST_q <= RST_d;
   end else begin
-    ready <= 1;
+    // ready <= 1;
     RST_q <= 16'b111111111111111;
   end
 end
diff --git a/projects/neopixel_uart/main_x4.si b/projects/neopixel_uart/main_x4.si
index 2f9c5067..447d2a59 100644
--- a/projects/neopixel_uart/main_x4.si
+++ b/projects/neopixel_uart/main_x4.si
@@ -42,7 +42,7 @@ $$ print('res_cycles = ' .. res_cycles)
 
 // UART
 $$uart_in_clock_freq_mhz = 100
-$$uart_bauds             = 1152000 -- 921600 -- 576000
+$$uart_bauds             = 1152000 -- 1152000 -- 921600 -- 576000
 $include('../common/uart.si')
 
 algorithm sender(input uint24 send_clr,output uint1 ctrl)
@@ -80,9 +80,9 @@ algorithm sender(input uint24 send_clr,output uint1 ctrl)
 
 // The hardware implements the LED driver
 algorithm main(
-  output uint8 leds = 0,
-  output uint1 uart_tx,
-  input  uint1 uart_rx,
+  output uint8  leds = 0,
+  output uint1  uart_tx,
+  input  uint1  uart_rx,
   output uint28 gp,
   input  uint28 gn,
 ) <@fast_clock> {
@@ -90,8 +90,8 @@ algorithm main(
   // clock
   uint1 fast_clock  = uninitialized;
   pll clk_gen (
-    clock_in  <: clock,
-    clock_out :> fast_clock
+    clkin   <: clock,
+    clkout0 :> fast_clock
   );
 
   // UART receiver
@@ -129,9 +129,9 @@ algorithm main(
     colors1.addr1    = id;
     colors2.addr1    = id;
     colors3.addr1    = id;
-    leds             = seg; //receive_step;
+    // leds             = seg; //receive_step;
     if (ui.data_out_ready) {
-      // leds = ui.data_out; // for debugging
+      leds = ui.data_out; // for debugging
       // data is ready on uart
       if (ui.data_out == 8hff) { // FF reset the sequence
         receive_step = 3b1;
diff --git a/projects/neopixel_uart/send.py b/projects/neopixel_uart/send.py
index 79ccdb05..a95ea2fd 100644
--- a/projects/neopixel_uart/send.py
+++ b/projects/neopixel_uart/send.py
@@ -5,8 +5,8 @@
 import glob
 import sys
 
-if len(sys.argv) < 3:
-  print("send.py <port> <led map (optional)")
+if len(sys.argv) < 2:
+  print("send.py <port> <led map (optional)>")
   sys.exit()
 
 map = []
@@ -42,8 +42,9 @@
     line = f.readline()
   f.close()
 
-
-ser = serial.Serial(sys.argv[1],115200)
+speed = 1152000 # 115200
+print("****** UART speed: ",speed)
+ser = serial.Serial(sys.argv[1],speed)
 
 def send_byte(b):
   packet = bytearray()