From deab439c4022abda34e61cde1aac7422f1486ec3 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:49:20 -0700 Subject: [PATCH 01/35] Silicon/Ampere: Add PcdFirmwareVersionNumber for capsule updates Add a new PCD, PcdFirmwareVersionNumber, which is used to hold a decimal value for use in capsule builds. Signed-off-by: Rebecca Cran --- Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec b/Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec index 28c1c1905e7..c11c490f3b8 100644 --- a/Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec +++ b/Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec @@ -90,6 +90,8 @@ gAmpereTokenSpaceGuid.PcdSmbiosTables0MajorVersion|0xFF|UINT8|0x00000005 gAmpereTokenSpaceGuid.PcdSmbiosTables0MinorVersion|0xFF|UINT8|0x00000006 + gAmpereTokenSpaceGuid.PcdFirmwareVersionNumber|0x00000000|UINT32|0x00000012 + # # I2C PCDs for SMBUS # From e51677d484e6de0b040424f408800e5692bde2d2 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:49:26 -0700 Subject: [PATCH 02/35] Silicon/Ampere: Enable FMP capsule updates in AmpereAltraPkg.dsc.inc Signed-off-by: Rebecca Cran --- .../AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 47 ++++++++++++++----- 1 file changed, 36 insertions(+), 11 deletions(-) diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc index 8a17249cc9d..8b4e6aba50a 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -118,6 +118,12 @@ PlatformBootManagerLib|Silicon/Ampere/AmpereSiliconPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf +!if $(CAPSULE_ENABLE) == TRUE + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf +!else + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf +!endif + # # UEFI Shell libraries # @@ -140,26 +146,31 @@ SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisionLib.inf PlatformPKProtectionLib|SecurityPkg/Library/PlatformPKProtectionLibVarPolicy/PlatformPKProtectionLibVarPolicy.inf + # + # re-use the UserPhysicalPresent() dummy implementation from the ovmf tree + # + PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf +!endif + # # Capsule Update requirements # BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf DisplayUpdateProgressLib|MdeModulePkg/Library/DisplayUpdateProgressLibGraphics/DisplayUpdateProgressLibGraphics.inf - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf EdkiiSystemCapsuleLib|SignedCapsulePkg/Library/EdkiiSystemCapsuleLib/EdkiiSystemCapsuleLib.inf - FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf + FmpAuthenticationLib|MdeModulePkg/Library/FmpAuthenticationLibNull/FmpAuthenticationLibNull.inf + FmpDependencyLib|FmpDevicePkg/Library/FmpDependencyLib/FmpDependencyLib.inf + FmpDependencyCheckLib|FmpDevicePkg/Library/FmpDependencyCheckLibNull/FmpDependencyCheckLibNull.inf + FmpDependencyDeviceLib|FmpDevicePkg/Library/FmpDependencyDeviceLibNull/FmpDependencyDeviceLibNull.inf + FmpPayloadHeaderLib|FmpDevicePkg/Library/FmpPayloadHeaderLibV1/FmpPayloadHeaderLibV1.inf + CapsuleUpdatePolicyLib|FmpDevicePkg/Library/CapsuleUpdatePolicyLibNull/CapsuleUpdatePolicyLibNull.inf IniParsingLib|SignedCapsulePkg/Library/IniParsingLib/IniParsingLib.inf PlatformFlashAccessLib|Silicon/Ampere/AmpereAltraPkg/Library/PlatformFlashAccessLib/PlatformFlashAccessLib.inf ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf - # - # re-use the UserPhysicalPresent() dummy implementation from the ovmf tree - # - PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf -!else - TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf - AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf -!endif VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf @@ -268,7 +279,11 @@ [LibraryClasses.common.DXE_RUNTIME_DRIVER] MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +!if $(CAPSULE_ENABLE) == TRUE CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf +!else + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf +!endif ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf !if $(SECURE_BOOT_ENABLE) == TRUE BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf @@ -647,6 +662,8 @@ SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf !endif MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/CapsuleOnDiskLoadPei/CapsuleOnDiskLoadPei.inf + MdeModulePkg/Universal/CapsulePei/CapsulePei.inf MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf @@ -771,7 +788,15 @@ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf - MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf { + +!if $(CAPSULE_ENABLE) == TRUE + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf +!else + FmpAuthenticationLib|MdeModulePkg/Library/FmpAuthenticationLibNull/FmpAuthenticationLibNull.inf +!endif + } + MdeModulePkg/Application/UiApp/UiApp.inf { NULL|MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.inf From 8fa320daa89a03b554d6b47d91941b64f6a01a0b Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:49:28 -0700 Subject: [PATCH 03/35] Silicon/Ampere: Increase max auth variable sizes Increase the maximum size of auth variables. This is needed to work with Secure Boot where variables can be up to around 10KB. Signed-off-by: Rebecca Cran --- Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc index 8b4e6aba50a..b17b7d4e33e 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -407,8 +407,8 @@ gArmTokenSpaceGuid.PcdArmPrimaryCore|0x0 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x5000 gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x91100000 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x20000 From a1f2a894b9d079007418a9ea72b83f7f2b61a454 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:49:30 -0700 Subject: [PATCH 04/35] Platform/Ampere: Change BMC config file to bmc.conf Name the BMC configuration file bmc.conf instead of bmc.sh, since that makes more sense. Signed-off-by: Rebecca Cran --- Platform/Ampere/Tools/fwflash.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Ampere/Tools/fwflash.sh b/Platform/Ampere/Tools/fwflash.sh index 5c666de3a75..91568f8d140 100755 --- a/Platform/Ampere/Tools/fwflash.sh +++ b/Platform/Ampere/Tools/fwflash.sh @@ -5,7 +5,7 @@ set -e -BMC_ENV_FILE=bmc.sh +BMC_ENV_FILE=bmc.conf usage () { echo "Copies firmware to the BMC (running OpenBMC) and runs ampere_flash_bios.sh to flash the host." From 2f2fdd4a145846e69bc6fc6cd40b28c011dd52ed Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:49:32 -0700 Subject: [PATCH 05/35] Silicon/Ampere: Check that flash size is greater than NV storage size Instead of checking that the flash size is greater than *twice* the size of the NV storage, we only need to check that it's larger than it. Signed-off-by: Rebecca Cran --- Silicon/Ampere/AmpereAltraPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c index c9161f30bbe..94ed9a0993e 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c @@ -495,7 +495,7 @@ FlashFvbDxeInitialize ( return EFI_DEVICE_ERROR; } - if (mNvFlashSize >= (mNvStorageSize * 2)) { + if (mNvFlashSize > mNvStorageSize) { DEBUG ((DEBUG_INFO, "%a: NV store on Flash is valid\n", __func__)); } else { DEBUG ((DEBUG_ERROR, "%a: NV store on Flash is invalid\n", __func__)); From 3e01ac6f33dfb7db442c04cdab48d792a9278cb9 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:49:34 -0700 Subject: [PATCH 06/35] Ampere: Add SHELL_ENABLE define (TRUE by default) Add a define, SHELL_ENABLE, which allows building the firmware without the shell, as recommended in https://lvfs.readthedocs.io/en/latest/claims.html#uefi-shell. To maintain existing behavior, it defaults to TRUE. Also, move the setting of PcdShellLibAutoInitialize to FALSE into the PCDs used when building just the shell and dynamic commands as the instructions in ShellPkg/ShellPkg.dec say to do. Signed-off-by: Rebecca Cran --- Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc | 8 +++++++- Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf | 2 ++ Platform/Ampere/JadePkg/Jade.dsc | 1 + Platform/Ampere/JadePkg/Jade.fdf | 2 ++ .../Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 14 ++++++-------- 5 files changed, 18 insertions(+), 9 deletions(-) diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc index 11ab759d2cb..62a16ac9d28 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc @@ -58,6 +58,7 @@ DEFINE FIRMWARE_VER = 2024.01.01-01 DEFINE SECURE_BOOT_ENABLE = TRUE DEFINE TPM2_ENABLE = TRUE + DEFINE SHELL_ENABLE = TRUE DEFINE INCLUDE_TFTP_COMMAND = TRUE DEFINE PLATFORM_CONFIG_UUID = 0690C53C-01B5-40AD-A65B-5399AC0B1E9B @@ -416,7 +417,12 @@ !if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf - ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf +!if $(SHELL_ENABLE) == TRUE + ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } +!endif !endif # diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf index 7bc9e78ef95..78dde178e06 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf @@ -367,6 +367,7 @@ APRIORI DXE { # # UEFI application (Shell Embedded Boot Loader) # +!if $(SHELL_ENABLE) == TRUE INF ShellPkg/Application/Shell/Shell.inf !if $(INCLUDE_TFTP_COMMAND) == TRUE INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf @@ -374,6 +375,7 @@ APRIORI DXE { !if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE INF ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf !endif +!endif !if $(TPM2_ENABLE) == TRUE INF Silicon/Ampere/AmpereAltraPkg/Drivers/Tcg2Dxe/Tcg2Dxe.inf diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc index 8c6a72baa74..6bc8fd2d475 100644 --- a/Platform/Ampere/JadePkg/Jade.dsc +++ b/Platform/Ampere/JadePkg/Jade.dsc @@ -55,6 +55,7 @@ DEFINE FIRMWARE_VER = 0.01.001 DEFINE SECURE_BOOT_ENABLE = TRUE DEFINE TPM2_ENABLE = TRUE + DEFINE SHELL_ENABLE = TRUE DEFINE INCLUDE_TFTP_COMMAND = TRUE DEFINE PLATFORM_CONFIG_UUID = 84BC921F-9D4A-4D1D-A1A1-1AE13EDD07E5 diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf index 95dd0d35525..4fe703fc7a5 100644 --- a/Platform/Ampere/JadePkg/Jade.fdf +++ b/Platform/Ampere/JadePkg/Jade.fdf @@ -340,10 +340,12 @@ APRIORI DXE { # # UEFI application (Shell Embedded Boot Loader) # +!if $(SHELL_ENABLE) == TRUE INF ShellPkg/Application/Shell/Shell.inf !if $(INCLUDE_TFTP_COMMAND) == TRUE INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf !endif +!endif !if $(TPM2_ENABLE) == TRUE INF Silicon/Ampere/AmpereAltraPkg/Drivers/Tcg2Dxe/Tcg2Dxe.inf diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc index b17b7d4e33e..026084bebd5 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -452,13 +452,6 @@ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x100002620000 gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|115200 - # - # We want to use the Shell Libraries but don't want it to initialise - # automatically. We initialise the libraries when the command is called by the - # Shell. - # - gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE # @@ -825,6 +818,7 @@ MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf !endif +!if $(SHELL_ENABLE) == TRUE # # UEFI application (Shell Embedded Boot Loader) # @@ -848,8 +842,12 @@ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 } !ifdef $(INCLUDE_TFTP_COMMAND) - ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } !endif #$(INCLUDE_TFTP_COMMAND) +!endif #$(EDK2_SHELL_ENABLE) EmbeddedPkg/Drivers/MemoryAttributeManagerDxe/MemoryAttributeManagerDxe.inf Silicon/Ampere/AmpereSiliconPkg/Drivers/PlatformBootManagerDxe/PlatformBootManagerDxe.inf From 62012069cb2cef61f00bcbd2481d292a078052fa Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:49:36 -0700 Subject: [PATCH 07/35] Silicon/Ampere: Set PcdFdSize to 32MB Fix the SMBIOS BIOS Size field by setting gArmTokenSpaceGuid.PcdFdSize to 32MB. Signed-off-by: Rebecca Cran --- Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc index 026084bebd5..46232209f0c 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -525,6 +525,7 @@ gArmTokenSpaceGuid.PcdProcessorManufacturer|L"Ampere(R)" gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"Ampere(R)" gArmTokenSpaceGuid.PcdProcessorAssetTag|L"Not Set" + gArmTokenSpaceGuid.PcdFdSize|0x2000000 # # Increasing the maximum size of capsule is to cover ARM Trusted Firmware binaries From f5fe911c4176fd86f8da24f8d744b4c41712c9a9 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:49:37 -0700 Subject: [PATCH 08/35] Silicon/Ampere: Reduce PcdPlatformBootTimeOut to 5s Waiting 10 seconds for the user to press a key to interrupt boot seems excessive. Reduce it to 5 seconds. Signed-off-by: Rebecca Cran --- Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc index 46232209f0c..61fe784ae46 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -533,7 +533,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0xE00000 [PcdsDynamicHii.common.DEFAULT] - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10 + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Possible values are: # 0: Connect Minimal Devices # 1: Connect Network Devices From 7d02fc3fa2147a38c3b1979f14191c57737fa27c Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:49:39 -0700 Subject: [PATCH 09/35] Silicon/Ampere: Add the BGRT driver Add the BootGraphicsResourceTableDxe driver to allow the OS to display a splash screen if the build includes one. Signed-off-by: Rebecca Cran --- Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc index 61fe784ae46..d6b6603b50b 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -626,6 +626,7 @@ } MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressDxe/BootProgressDxe.inf + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf # # PCD From b4c155fce7a448fd7356687cd5d42724848f8ccc Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:49:43 -0700 Subject: [PATCH 10/35] Platform/ADLINK: Update SMBIOS Type17 to use JedecJep106Lib Update the SMBIOS Type17 code to use JedecJep106Lib instead of custom code to determine the manufacturer. Signed-off-by: Rebecca Cran --- Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc | 1 + .../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 1 + .../Type17/PlatformMemoryDeviceFunction.c | 483 +++++++----------- 3 files changed, 184 insertions(+), 301 deletions(-) diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc index 62a16ac9d28..06c62e2ff59 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc @@ -113,6 +113,7 @@ [LibraryClasses] OemMiscLib|Platform/ADLINK/ComHpcAltPkg/Library/OemMiscLib/OemMiscLib.inf + JedecJep106Lib|MdePkg/Library/JedecJep106Lib/JedecJep106Lib.inf # # ACPI Libraries diff --git a/Platform/ADLINK/ComHpcAltPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf b/Platform/ADLINK/ComHpcAltPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf index 96e678477ae..e66ff74d81a 100644 --- a/Platform/ADLINK/ComHpcAltPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf +++ b/Platform/ADLINK/ComHpcAltPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf @@ -51,6 +51,7 @@ BaseMemoryLib DebugLib HiiLib + JedecJep106Lib MemoryAllocationLib NVParamLib UefiBootServicesTableLib diff --git a/Platform/ADLINK/ComHpcAltPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDeviceFunction.c b/Platform/ADLINK/ComHpcAltPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDeviceFunction.c index eaf418bd2c3..eb3ab747d44 100644 --- a/Platform/ADLINK/ComHpcAltPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDeviceFunction.c +++ b/Platform/ADLINK/ComHpcAltPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDeviceFunction.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -25,18 +26,6 @@ #define SPD_MEMORY_TYPE_OFFSET 0x02 #define SPD_CONTINUATION_CHARACTER 0x7F -#define DDR2_SPD_MANUFACTURER_MEMORY_TYPE 0x08 -#define DDR2_SPD_MANUFACTURER_ID_CODE_LENGTH 8 -#define DDR2_SPD_MANUFACTURER_ID_CODE_OFFSET 64 -#define DDR2_SPD_MANUFACTURER_PART_NUMBER_OFFSET 73 -#define DDR2_SPD_MANUFACTURER_SERIAL_NUMBER_OFFSET 95 - -#define DDR3_SPD_MANUFACTURER_MEMORY_TYPE 0x0B -#define DDR3_SPD_MANUFACTURER_ID_BANK_OFFSET 117 -#define DDR3_SPD_MANUFACTURER_ID_CODE_OFFSET 118 -#define DDR3_SPD_MANUFACTURER_PART_NUMBER_OFFSET 128 -#define DDR3_SPD_MANUFACTURER_SERIAL_NUMBER_OFFSET 122 - #define DDR4_SPD_MANUFACTURER_MEMORY_TYPE 0x0C #define DDR4_SPD_MANUFACTURER_ID_BANK_OFFSET 320 #define DDR4_SPD_MANUFACTURER_ID_CODE_OFFSET 321 @@ -56,183 +45,68 @@ typedef enum { PART_NUMBER_TOKEN_INDEX } MEMORY_DEVICE_TOKEN_INDEX; -#pragma pack(1) -typedef struct { - UINT8 VendorId; - CHAR16 *ManufacturerString; -} JEDEC_MF_ID; -#pragma pack() - -JEDEC_MF_ID Bank0Table[] = { - { 0x01, L"AMD\0" }, - { 0x04, L"Fujitsu\0" }, - { 0x07, L"Hitachi\0" }, - { 0x89, L"Intel\0" }, - { 0x10, L"NEC\0" }, - { 0x97, L"Texas Instrument\0" }, - { 0x98, L"Toshiba\0" }, - { 0x1C, L"Mitsubishi\0" }, - { 0x1F, L"Atmel\0" }, - { 0x20, L"STMicroelectronics\0" }, - { 0xA4, L"IBM\0" }, - { 0x2C, L"Micron Technology\0" }, - { 0xAD, L"SK Hynix\0" }, - { 0xB0, L"Sharp\0" }, - { 0xB3, L"IDT\0" }, - { 0x3E, L"Oracle\0" }, - { 0xBF, L"SST\0" }, - { 0x40, L"ProMos/Mosel\0" }, - { 0xC1, L"Infineon\0" }, - { 0xC2, L"Macronix\0" }, - { 0x45, L"SanDisk\0" }, - { 0xCE, L"Samsung\0" }, - { 0xDA, L"Winbond\0" }, - { 0xE0, L"LG Semi\0" }, - { 0x62, L"Sanyo\0" }, - { NULL_TERMINATED_ID, L"Undefined\0" } -}; - -JEDEC_MF_ID Bank1Table[] = { - { 0x98, L"Kingston\0" }, - { 0xBA, L"PNY\0" }, - { 0x4F, L"Transcend\0" }, - { 0x7A, L"Apacer\0" }, - { NULL_TERMINATED_ID, L"Undefined\0" } -}; - -JEDEC_MF_ID Bank2Table[] = { - { 0x9E, L"Corsair\0" }, - { 0xFE, L"Elpida\0" }, - { NULL_TERMINATED_ID, L"Undefined\0" } -}; - -JEDEC_MF_ID Bank3Table[] = { - { 0x0B, L"Nanya\0" }, - { 0x94, L"Mushkin\0" }, - { 0x25, L"Kingmax\0" }, - { NULL_TERMINATED_ID, L"Undefined\0" } -}; - -JEDEC_MF_ID Bank4Table[] = { - { 0xB0, L"OCZ\0" }, - { 0xCB, L"A-DATA\0" }, - { 0xCD, L"G Skill\0" }, - { 0xEF, L"Team\0" }, - { NULL_TERMINATED_ID, L"Undefined\0" } -}; - -JEDEC_MF_ID Bank5Table[] = { - { 0x02, L"Patriot\0" }, - { 0x9B, L"Crucial\0" }, - { 0x51, L"Qimonda\0" }, - { 0x57, L"AENEON\0" }, - { 0xF7, L"Avant\0" }, - { NULL_TERMINATED_ID, L"Undefined\0" } -}; - -JEDEC_MF_ID Bank6Table[] = { - { 0x34, L"Super Talent\0" }, - { 0xD3, L"Silicon Power\0" }, - { NULL_TERMINATED_ID, L"Undefined\0" } -}; - -JEDEC_MF_ID Bank7Table[] = { - { NULL_TERMINATED_ID, L"Undefined\0" } -}; - -JEDEC_MF_ID *ManufacturerJedecIdBankTable[] = { - Bank0Table, - Bank1Table, - Bank2Table, - Bank3Table, - Bank4Table, - Bank5Table, - Bank6Table, - Bank7Table -}; - VOID UpdateManufacturer ( - IN UINT8 *SpdData, - IN UINT16 ManufacturerToken + IN UINT8 *SpdData, + IN UINT16 ManufacturerToken ) { - UINTN Index; - UINT8 VendorId; - UINT8 MemType; - UINT8 NumberOfJedecIdBankTables; - JEDEC_MF_ID *IdTblPtr = NULL; + UINTN Index; + UINT8 VendorId; + UINT8 MemType; + CONST CHAR8 *ManufacturerString; + CHAR16 *UnicodeManufacturerString; + UINTN Length; MemType = SpdData[SPD_MEMORY_TYPE_OFFSET]; switch (MemType) { - case DDR2_SPD_MANUFACTURER_MEMORY_TYPE: - for (Index = 0; Index < DDR2_SPD_MANUFACTURER_ID_CODE_LENGTH; Index++) { - VendorId = SpdData[DDR2_SPD_MANUFACTURER_ID_CODE_OFFSET + Index]; - if (VendorId != SPD_CONTINUATION_CHARACTER) { - break; - } - } - - break; - - case DDR3_SPD_MANUFACTURER_MEMORY_TYPE: - Index = SpdData[DDR3_SPD_MANUFACTURER_ID_BANK_OFFSET] & (~SPD_PARITY_BIT_MASK); // Remove parity bit - VendorId = SpdData[DDR4_SPD_MANUFACTURER_ID_CODE_OFFSET]; - break; - - case DDR4_SPD_MANUFACTURER_MEMORY_TYPE: - Index = SpdData[DDR4_SPD_MANUFACTURER_ID_BANK_OFFSET] & (~SPD_PARITY_BIT_MASK); // Remove parity bit - VendorId = SpdData[DDR4_SPD_MANUFACTURER_ID_CODE_OFFSET]; - break; - - default: // Not supported - return; + case DDR4_SPD_MANUFACTURER_MEMORY_TYPE: + Index = SpdData[DDR4_SPD_MANUFACTURER_ID_BANK_OFFSET] & (~SPD_PARITY_BIT_MASK); // Remove parity bit + VendorId = SpdData[DDR4_SPD_MANUFACTURER_ID_CODE_OFFSET]; + break; + + default: // Not supported + DEBUG ((DEBUG_ERROR, "Unsupported/unknown DDR memory type encountered: %d\n", MemType)); + return; } - NumberOfJedecIdBankTables = ARRAY_SIZE (ManufacturerJedecIdBankTable) - 1; // Exclude NULL-terminated table - if (Index > NumberOfJedecIdBankTables) { - Index = NumberOfJedecIdBankTables; + ManufacturerString = Jep106GetManufacturerName (VendorId, Index); + if (ManufacturerString == NULL) { + DEBUG ((DEBUG_WARN, "Failed to get JEDEC JEP107 manufacturer from VendorID %d, Index %d\n", VendorId, Index)); + return; } - IdTblPtr = ManufacturerJedecIdBankTable[Index]; - - // Search in Manufacturer table and update vendor name accordingly in HII Database - while (IdTblPtr->VendorId != NULL_TERMINATED_ID) { - if (IdTblPtr->VendorId == VendorId) { - HiiSetString (mSmbiosPlatformDxeHiiHandle, ManufacturerToken, IdTblPtr->ManufacturerString, NULL); - break; - } - - IdTblPtr++; + Length = AsciiStrSize (ManufacturerString); + UnicodeManufacturerString = AllocateZeroPool (Length * sizeof (CHAR16)); + if (UnicodeManufacturerString == NULL) { + DEBUG ((DEBUG_WARN, "Failed to allocate memory for DDR manufacturer string.\n")); + return; } + + AsciiStrToUnicodeStrS (ManufacturerString, UnicodeManufacturerString, Length); + HiiSetString (mSmbiosPlatformDxeHiiHandle, ManufacturerToken, UnicodeManufacturerString, NULL); + FreePool (UnicodeManufacturerString); } VOID UpdateSerialNumber ( - IN UINT8 *SpdData, - IN UINT16 SerialNumberToken + IN UINT8 *SpdData, + IN UINT16 SerialNumberToken ) { - UINT8 MemType; - UINTN Offset; - CHAR16 SerialNumberStr[SMBIOS_UNICODE_STRING_MAX_LENGTH]; + UINT8 MemType; + UINTN Offset; + CHAR16 SerialNumberStr[SMBIOS_UNICODE_STRING_MAX_LENGTH]; MemType = SpdData[SPD_MEMORY_TYPE_OFFSET]; switch (MemType) { - case DDR2_SPD_MANUFACTURER_MEMORY_TYPE: - Offset = DDR2_SPD_MANUFACTURER_SERIAL_NUMBER_OFFSET; - break; - - case DDR3_SPD_MANUFACTURER_MEMORY_TYPE: - Offset = DDR3_SPD_MANUFACTURER_SERIAL_NUMBER_OFFSET; - break; - - case DDR4_SPD_MANUFACTURER_MEMORY_TYPE: - Offset = DDR4_SPD_MANUFACTURER_SERIAL_NUMBER_OFFSET; - break; + case DDR4_SPD_MANUFACTURER_MEMORY_TYPE: + Offset = DDR4_SPD_MANUFACTURER_SERIAL_NUMBER_OFFSET; + break; - default: // Not supported - return; + default: // Not supported + DEBUG ((DEBUG_ERROR, "Unsupported/unknown DDR memory type encountered: %d\n", MemType)); + return; } UnicodeSPrint ( @@ -249,30 +123,23 @@ UpdateSerialNumber ( VOID UpdatePartNumber ( - IN UINT8 *SpdData, - IN UINT16 PartNumberToken + IN UINT8 *SpdData, + IN UINT16 PartNumberToken ) { - UINT8 MemType; - UINTN Offset; - CHAR16 PartNumberStr[SMBIOS_UNICODE_STRING_MAX_LENGTH]; + UINT8 MemType; + UINTN Offset; + CHAR16 PartNumberStr[SMBIOS_UNICODE_STRING_MAX_LENGTH]; MemType = SpdData[SPD_MEMORY_TYPE_OFFSET]; switch (MemType) { - case DDR2_SPD_MANUFACTURER_MEMORY_TYPE: - Offset = DDR2_SPD_MANUFACTURER_PART_NUMBER_OFFSET; - break; - - case DDR3_SPD_MANUFACTURER_MEMORY_TYPE: - Offset = DDR3_SPD_MANUFACTURER_PART_NUMBER_OFFSET; - break; + case DDR4_SPD_MANUFACTURER_MEMORY_TYPE: + Offset = DDR4_SPD_MANUFACTURER_PART_NUMBER_OFFSET; + break; - case DDR4_SPD_MANUFACTURER_MEMORY_TYPE: - Offset = DDR4_SPD_MANUFACTURER_PART_NUMBER_OFFSET; - break; - - default: // Not supported - return; + default: // Not supported + DEBUG ((DEBUG_ERROR, "Unsupported/unknown DDR memory type encountered: %d\n", MemType)); + return; } UnicodeSPrint ( @@ -312,20 +179,20 @@ UpdatePartNumber ( **/ SMBIOS_PLATFORM_DXE_TABLE_FUNCTION (PlatformMemoryDevice) { - UINT8 Index; - UINT8 SlotIndex; - UINTN HandleCount; - UINTN MemorySize; - UINT16 *HandleArray; - CHAR16 UnicodeStr[SMBIOS_UNICODE_STRING_MAX_LENGTH]; - EFI_STATUS Status; - SMBIOS_HANDLE MemoryArrayHandle; - PLATFORM_DIMM *Dimm; - STR_TOKEN_INFO *InputStrToken; - PLATFORM_DIMM_LIST *DimmList; - PLATFORM_DRAM_INFO *DramInfo; - SMBIOS_TABLE_TYPE17 *InputData; - SMBIOS_TABLE_TYPE17 *Type17Record; + UINTN Index; + UINTN SlotIndex; + UINTN HandleCount; + UINTN MemorySize; + UINT16 *HandleArray; + CHAR16 UnicodeStr[SMBIOS_UNICODE_STRING_MAX_LENGTH]; + EFI_STATUS Status; + SMBIOS_HANDLE MemoryArrayHandle; + PLATFORM_DIMM *Dimm; + STR_TOKEN_INFO *InputStrToken; + PLATFORM_DIMM_LIST *DimmList; + PLATFORM_DRAM_INFO *DramInfo; + SMBIOS_TABLE_TYPE17 *InputData; + SMBIOS_TABLE_TYPE17 *Type17Record; HandleCount = 0; HandleArray = NULL; @@ -361,7 +228,7 @@ SMBIOS_PLATFORM_DXE_TABLE_FUNCTION (PlatformMemoryDevice) { return EFI_OUT_OF_RESOURCES; } - if (HandleCount != GetNumberOfSupportedSockets ()) { + if (HandleCount < 1) { DEBUG (( DEBUG_ERROR, "[%a]:[%dL] Failed to get Memory Array Handle\n", @@ -372,110 +239,124 @@ SMBIOS_PLATFORM_DXE_TABLE_FUNCTION (PlatformMemoryDevice) { return EFI_NOT_FOUND; } - for (Index = 0; Index < GetNumberOfSupportedSockets (); Index++) { - InputData = (SMBIOS_TABLE_TYPE17 *)RecordData; - InputStrToken = (STR_TOKEN_INFO *)StrToken; - MemoryArrayHandle = HandleArray[Index]; - - while (InputData->Hdr.Type != NULL_TERMINATED_TYPE) { - for (SlotIndex = 0; SlotIndex < DimmList->BoardDimmSlots; SlotIndex++) { - // - // Prepare additional strings for SMBIOS Table. - // - Dimm = &DimmList->Dimm[SlotIndex]; - if (Dimm->NodeId != Index) { - continue; - } - - Status = SmbiosPlatformDxeSaveHiiDefaultString (InputStrToken); - if (EFI_ERROR (Status)) { - FreePool (HandleArray); - return Status; - } - - if (Dimm->Info.DimmStatus == DIMM_INSTALLED_OPERATIONAL) { - UpdateManufacturer (Dimm->SpdData.Data, InputStrToken->TokenArray[MANUFACTURER_TOKEN_INDEX]); - UpdateSerialNumber (Dimm->SpdData.Data, InputStrToken->TokenArray[SERIAL_NUMBER_TOKEN_INDEX]); - UpdatePartNumber (Dimm->SpdData.Data, InputStrToken->TokenArray[PART_NUMBER_TOKEN_INDEX]); - } - - UnicodeSPrint (UnicodeStr, sizeof (UnicodeStr), L"Socket %d DIMM %d", Index, SlotIndex); - HiiSetString (mSmbiosPlatformDxeHiiHandle, InputStrToken->TokenArray[DEVICE_LOCATOR_TOKEN_INDEX], UnicodeStr, NULL); - UnicodeSPrint (UnicodeStr, sizeof (UnicodeStr), L"Bank %d", SlotIndex); - HiiSetString (mSmbiosPlatformDxeHiiHandle, InputStrToken->TokenArray[BANK_LOCATOR_TOKEN_INDEX], UnicodeStr, NULL); - UnicodeSPrint (UnicodeStr, sizeof (UnicodeStr), L"Array %d Asset Tag %d", Index, SlotIndex); - HiiSetString (mSmbiosPlatformDxeHiiHandle, InputStrToken->TokenArray[ASSET_TAG_TOKEN_INDEX], UnicodeStr, NULL); - - // - // Create Table and fill up information. - // - SmbiosPlatformDxeCreateTable ( - (VOID *)&Type17Record, - (VOID *)&InputData, - sizeof (SMBIOS_TABLE_TYPE17), - InputStrToken - ); - if (Type17Record == NULL) { - FreePool (HandleArray); - return EFI_OUT_OF_RESOURCES; - } - - if (Dimm->Info.DimmStatus == DIMM_INSTALLED_OPERATIONAL) { - MemorySize = Dimm->Info.DimmSize * 1024; - if (MemorySize >= 0x7FFF) { - Type17Record->Size = 0x7FFF; - Type17Record->ExtendedSize = MemorySize; - } else { - Type17Record->Size = (UINT16)MemorySize; - Type17Record->ExtendedSize = 0; - } - - Type17Record->MemoryType = 0x1A; // DDR4 - Type17Record->Speed = (UINT16)DramInfo->MaxSpeed; - Type17Record->ConfiguredMemoryClockSpeed = (UINT16)DramInfo->MaxSpeed; - Type17Record->Attributes = Dimm->Info.DimmNrRank & 0x0F; - Type17Record->ConfiguredVoltage = 1200; - Type17Record->MinimumVoltage = 1140; - Type17Record->MaximumVoltage = 1260; - Type17Record->DeviceSet = 0; // None - - if ((Dimm->Info.DimmType == UDIMM) || (Dimm->Info.DimmType == SODIMM)) { - Type17Record->TypeDetail.Unbuffered = 1; // BIT 14: unregistered - } else if ( (Dimm->Info.DimmType == RDIMM) - || (Dimm->Info.DimmType == LRDIMM) - || (Dimm->Info.DimmType == RSODIMM)) - { - Type17Record->TypeDetail.Registered = 1; // BIT 13: registered - } - - /* FIXME: Determine if need to set technology to NVDIMM-* when supported */ - Type17Record->MemoryTechnology = 0x3; // DRAM - } - - // Update Type 16 handle - Type17Record->MemoryArrayHandle = MemoryArrayHandle; - - // - // Add Table record and free pool. - // - Status = SmbiosPlatformDxeAddRecord ((UINT8 *)Type17Record, NULL); - if (EFI_ERROR (Status)) { - FreePool (HandleArray); - FreePool (Type17Record); - return Status; - } - - FreePool (Type17Record); - Status = SmbiosPlatformDxeRestoreHiiDefaultString (InputStrToken); - if (EFI_ERROR (Status)) { - FreePool (HandleArray); - return Status; - } + InputData = (SMBIOS_TABLE_TYPE17 *)RecordData; + InputStrToken = (STR_TOKEN_INFO *)StrToken; + MemoryArrayHandle = HandleArray[0]; + + SlotIndex = 0; + + // Divide the PLATFORM_DIMM_INFO_MAX_SLOT by 2 since we only have + // 1 socket on this platform. + for (Index = 0; Index < (PLATFORM_DIMM_INFO_MAX_SLOT / 2); Index++) { + + if (SlotIndex > 5) { + break; + } + + if ((Index == 6) || (Index == 7) || (Index >= 14) || (((Index + 1) % 2) == 0)) { + continue; + } + + // + // Prepare additional strings for SMBIOS Table. + // + Dimm = &DimmList->Dimm[Index]; + if (Dimm->NodeId != 0) { + continue; + } + + Status = SmbiosPlatformDxeSaveHiiDefaultString (InputStrToken); + if (EFI_ERROR (Status)) { + FreePool (HandleArray); + return Status; + } + if (Dimm->Info.DimmStatus == DIMM_INSTALLED_OPERATIONAL) { + UpdateManufacturer (Dimm->SpdData.Data, InputStrToken->TokenArray[MANUFACTURER_TOKEN_INDEX]); + UpdateSerialNumber (Dimm->SpdData.Data, InputStrToken->TokenArray[SERIAL_NUMBER_TOKEN_INDEX]); + UpdatePartNumber (Dimm->SpdData.Data, InputStrToken->TokenArray[PART_NUMBER_TOKEN_INDEX]); + } + UnicodeSPrint (UnicodeStr, sizeof (UnicodeStr), L"DIMM %d", SlotIndex + 1); + HiiSetString (mSmbiosPlatformDxeHiiHandle, InputStrToken->TokenArray[DEVICE_LOCATOR_TOKEN_INDEX], UnicodeStr, NULL); + + // + // Create Table and fill up information. + // + SmbiosPlatformDxeCreateTable ( + (VOID *)&Type17Record, + (VOID *)&InputData, + sizeof (SMBIOS_TABLE_TYPE17), + InputStrToken + ); + if (Type17Record == NULL) { + FreePool (HandleArray); + return EFI_OUT_OF_RESOURCES; + } + + if (Dimm->Info.DimmStatus != DIMM_NOT_INSTALLED) { + DEBUG ((DEBUG_INFO, "DIMM %d (Memory Controller %d Channel %d): \n", SlotIndex, Index / 2, (Index % 2))); + DEBUG ((DEBUG_INFO, "\tStatus (1=Installed-Operational, 2=Installed-NonOperational, 3=Installed-Failed): %d\n", Dimm->Info.DimmStatus)); + DEBUG ((DEBUG_INFO, "\tPart Number: %a\n", Dimm->Info.PartNumber)); + DEBUG ((DEBUG_INFO, "\tDimmSize: %llu\n", Dimm->Info.DimmSize)); + DEBUG ((DEBUG_INFO, "\tDimmMfcId: %d\n", Dimm->Info.DimmMfcId)); + DEBUG ((DEBUG_INFO, "\tDimmNrRank: %d\n", Dimm->Info.DimmNrRank)); + DEBUG ((DEBUG_INFO, "\tDimmType: %d\n", Dimm->Info.DimmType)); + DEBUG ((DEBUG_INFO, "\tDimmDevType: %d\n", Dimm->Info.DimmDevType)); + } else { + DEBUG ((DEBUG_INFO, "DIMM %d (Memory Controller %d Channel %d): not installed\n", SlotIndex, Index / 2, (Index % 2))); + } + + if (Dimm->Info.DimmStatus == DIMM_INSTALLED_OPERATIONAL) { + MemorySize = Dimm->Info.DimmSize * 1024; + + if (MemorySize >= 0x7FFF) { + Type17Record->Size = 0x7FFF; + Type17Record->ExtendedSize = MemorySize; + } else { + Type17Record->Size = (UINT16)MemorySize; + Type17Record->ExtendedSize = 0; + } + + Type17Record->MemoryType = MemoryTypeDdr4; + Type17Record->Speed = (UINT16)DramInfo->MaxSpeed; + Type17Record->ConfiguredMemoryClockSpeed = (UINT16)DramInfo->MaxSpeed; + Type17Record->Attributes = Dimm->Info.DimmNrRank & 0x0F; + Type17Record->ConfiguredVoltage = 1200; + Type17Record->MinimumVoltage = 1140; + Type17Record->MaximumVoltage = 1260; + Type17Record->DeviceSet = 0; // None + + if (Dimm->Info.DimmType == UDIMM || Dimm->Info.DimmType == SODIMM) { + Type17Record->TypeDetail.Unbuffered = 1; // BIT 14: unregistered + } else if (Dimm->Info.DimmType == RDIMM || + Dimm->Info.DimmType == LRDIMM || + Dimm->Info.DimmType == RSODIMM) + { + Type17Record->TypeDetail.Registered = 1; // BIT 13: registered } + /* FIXME: Determine if need to set technology to NVDIMM-* when supported */ + Type17Record->MemoryTechnology = MemoryTechnologyDram; + } + // Update Type 16 handle + Type17Record->MemoryArrayHandle = MemoryArrayHandle; + + // + // Add Table record and free pool. + // + Status = SmbiosPlatformDxeAddRecord ((UINT8 *)Type17Record, NULL); + if (EFI_ERROR (Status)) { + FreePool (HandleArray); + FreePool (Type17Record); + return Status; + } - InputData++; - InputStrToken++; + FreePool (Type17Record); + Status = SmbiosPlatformDxeRestoreHiiDefaultString (InputStrToken); + if (EFI_ERROR (Status)) { + FreePool (HandleArray); + return Status; } + + SlotIndex++; } FreePool (HandleArray); From 4ae043a5e660531109da7647a6bbee4fe9abe6c3 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:49:45 -0700 Subject: [PATCH 11/35] Platform/{ADLINK,Ampere}: Rework capsule updates Rework capsule update support so that the capsules contain correct, up-to-date version information and can be applied from Linux using fwupmgr. Since there can only be a single FMP descriptor, drop support for SCP upgrades: those can still be done via the BMC. Signed-off-by: Rebecca Cran --- .../SystemFirmwareDescriptor.aslc | 20 ++-- .../SystemFirmwareDescriptor.inf | 2 - ...ig.ini => TfaUefiFirmwareUpdateConfig.ini} | 8 +- ...onfig.ini => UefiFirmwareUpdateConfig.ini} | 8 +- Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc | 86 ++++++++------ Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf | 22 ++-- .../ADLINK/ComHpcAltPkg/ComHpcAltCapsule.dsc | 5 +- .../ADLINK/ComHpcAltPkg/ComHpcAltCapsule.fdf | 106 +++++------------- .../ADLINK/ComHpcAltPkg/firmware.metainfo.xml | 48 ++++++++ .../SystemFirmwareDescriptor.aslc | 16 +-- .../SystemFirmwareDescriptor.inf | 2 - .../SCPFirmwareUpdateConfig.ini | 20 ---- .../SystemFirmwareUpdateConfig.ini | 2 +- Platform/Ampere/JadePkg/Jade.dsc | 45 +++++++- Platform/Ampere/JadePkg/Jade.fdf | 25 ++--- Platform/Ampere/JadePkg/JadeCapsule.dsc | 6 +- Platform/Ampere/JadePkg/JadeCapsule.fdf | 85 +++----------- Platform/Ampere/Tools/fw_ver.sh | 8 +- Platform/Ampere/Tools/tools_def.txt.patch | 10 ++ Platform/Ampere/buildfw.sh | 16 ++- .../AmpereAltraLinuxBootPkg.dsc.inc | 4 +- .../AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 2 +- 22 files changed, 276 insertions(+), 270 deletions(-) rename Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/{SystemFirmwareUpdateConfig.ini => TfaUefiFirmwareUpdateConfig.ini} (70%) rename Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/{SCPFirmwareUpdateConfig.ini => UefiFirmwareUpdateConfig.ini} (77%) create mode 100644 Platform/ADLINK/ComHpcAltPkg/firmware.metainfo.xml delete mode 100644 Platform/Ampere/JadePkg/Capsule/SystemFirmwareUpdateConfig/SCPFirmwareUpdateConfig.ini create mode 100644 Platform/Ampere/Tools/tools_def.txt.patch diff --git a/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc index eb3ed7470b3..b40f6f3d177 100644 --- a/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc +++ b/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc @@ -14,15 +14,13 @@ #include #include +#include "HostFwInfo.h" + #define PACKAGE_VERSION 0xFFFFFFFF #define PACKAGE_VERSION_STRING L"Unknown" -#define CURRENT_FIRMWARE_VERSION 0x7E841A00 // YearMonthDayBuild (0xYYYMDDBB) -#define CURRENT_FIRMWARE_VERSION_STRING L"2024.04.26.00" -#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x0204640C - #define IMAGE_ID SIGNATURE_64('A', 'A', 'D', 'P', '_', 'F', 'W', ' ') -#define IMAGE_ID_STRING L"ADLINK AADP System Firmware" +#define IMAGE_ID_STRING L"ADLINK AADP Host Firmware" // PcdSystemFmpCapsuleImageTypeIdGuid #define IMAGE_TYPE_ID_GUID { 0xcdcdd0b7, 0x8afb, 0x4883, { 0x85, 0x3a, 0xae, 0x93, 0x98, 0x07, 0x7a, 0x0e } } @@ -35,7 +33,7 @@ typedef struct { CHAR16 PackageVersionNameStr[sizeof(PACKAGE_VERSION_STRING)/sizeof(CHAR16)]; } IMAGE_DESCRIPTOR; -STATIC IMAGE_DESCRIPTOR mImageDescriptor = +STATIC IMAGE_DESCRIPTOR mHostImageDescriptor = { { EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE, @@ -51,15 +49,17 @@ STATIC IMAGE_DESCRIPTOR mImageDescriptor = CURRENT_FIRMWARE_VERSION, // Version; OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName; {0x0}, // Reserved2 - 0, // Size; + 0xA00000, // Size; IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | IMAGE_ATTRIBUTE_RESET_REQUIRED | IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | - IMAGE_ATTRIBUTE_IN_USE, // AttributesSupported; + IMAGE_ATTRIBUTE_IN_USE | + IMAGE_ATTRIBUTE_UEFI_IMAGE, // AttributesSupported; IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | IMAGE_ATTRIBUTE_RESET_REQUIRED | IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | - IMAGE_ATTRIBUTE_IN_USE, // AttributesSetting; + IMAGE_ATTRIBUTE_IN_USE | + IMAGE_ATTRIBUTE_UEFI_IMAGE, // AttributesSetting; 0x0, // Compatibilities; LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion; 0x00000000, // LastAttemptVersion; @@ -73,4 +73,4 @@ STATIC IMAGE_DESCRIPTOR mImageDescriptor = PACKAGE_VERSION_STRING, }; -VOID* CONST ReferenceAcpiTable = &mImageDescriptor; +VOID* CONST ReferenceAcpiTable = &mHostImageDescriptor; diff --git a/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf index 792a28aaff6..22faf63ba2a 100644 --- a/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf +++ b/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf @@ -32,8 +32,6 @@ PeiServicesLib PeimEntryPoint -[FixedPcd] - [Pcd] gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor diff --git a/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini b/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/TfaUefiFirmwareUpdateConfig.ini similarity index 70% rename from Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini rename to Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/TfaUefiFirmwareUpdateConfig.ini index 721fbff4552..1471fa729a1 100644 --- a/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini +++ b/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/TfaUefiFirmwareUpdateConfig.ini @@ -10,12 +10,12 @@ [Head] NumOfUpdate = 1 NumOfRecovery = 0 -Update0 = AADP_UEFI_TFA +Update0 = AADP_TFA_UEFI -[AADP_UEFI_TFA] -FirmwareType = 2147483650 # SystemFirmware: 0x80000002 - OEM UEFI and ARM Trusted Firmware +[AADP_TFA_UEFI] +FirmwareType = 2147483650 # SystemFirmware: 0x80000002 - ARM Trusted Firmware and OEM UEFI AddressType = 1 # 0 - relative address, 1 - absolute address. BaseAddress = 0x00000000 # Base address offset on flash Length = 0x00D10000 # Length ImageOffset = 0x00000000 # Image offset of this SystemFirmware image -FileGuid = c07b0079-b3a2-448d-8c9c-46ba3c42b33e # PcdEdkiiSystemFirmwareFileGuid +FileGuid = 074c21e5-7d17-48e9-808d-f0c85e52a7db # PcdEdkiiSystemFirmwareFileGuid diff --git a/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/SCPFirmwareUpdateConfig.ini b/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/UefiFirmwareUpdateConfig.ini similarity index 77% rename from Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/SCPFirmwareUpdateConfig.ini rename to Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/UefiFirmwareUpdateConfig.ini index eeccd5be0de..0ff55feb4f3 100644 --- a/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/SCPFirmwareUpdateConfig.ini +++ b/Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/UefiFirmwareUpdateConfig.ini @@ -10,12 +10,12 @@ [Head] NumOfUpdate = 1 NumOfRecovery = 0 -Update0 = AltraSCP +Update0 = AADP_UEFI -[AltraSCP] -FirmwareType = 2147483649 # 0x80000001: SMpro/PMpro Firmware +[AADP_UEFI] +FirmwareType = 2147483651 # SystemFirmware: 0x80000003 - OEM UEFI AddressType = 1 # 0 - relative address, 1 - absolute address. BaseAddress = 0x00000000 # Base address offset on flash -Length = 0x00050000 # Length +Length = 0x00A10000 # Length ImageOffset = 0x00000000 # Image offset of this SystemFirmware image FileGuid = c07b0079-b3a2-448d-8c9c-46ba3c42b33e # PcdEdkiiSystemFirmwareFileGuid diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc index 06c62e2ff59..e089b693d1b 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc @@ -55,7 +55,10 @@ DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x8000004F !endif - DEFINE FIRMWARE_VER = 2024.01.01-01 + DEFINE FIRMWARE_VER = 00.01.01-00 + DEFINE FIRMWARE_VER_HEX = 0x00010100 + DEFINE CAPSULE_ENABLE = TRUE + DEFINE INCLUDE_TFA_FW = TRUE DEFINE SECURE_BOOT_ENABLE = TRUE DEFINE TPM2_ENABLE = TRUE DEFINE SHELL_ENABLE = TRUE @@ -74,31 +77,10 @@ DEFINE PERFORMANCE_MEASUREMENT_ENABLE = FALSE DEFINE HEAP_GUARD_ENABLE = FALSE -# How to enable Secure Boot support -# From https://github.com/edk2-porting/edk2-rk3588/issues/69 - -# In case you haven't seen how we do it on the Pi, this is relatively -# easy to add during the EDK2 build process. -# -# Basically you want to first get all the needed Secure Boot certificates -# and dbx, most of which can be downloaded directly: -# https://github.com/pftf/RPi4/blob/master/.github/workflows/linux_edk2.yml#L50-L58 -# -# Note that, because we sure don't want any third party (including -# ourselves) to have control over somebody else's machine when it comes -# to Secure Boot, we always generate a new PK as part of the build process and then discard the private key altogether. -# -# Then, at EDK2 build time, you just need to feed the -# -D SECURE_BOOT_ENABLE=TRUE option along with something like -# -D DEFAULT_KEYS=TRUE -D PK_DEFAULT_FILE=$WORKSPACE/keys/pk.cer -# -D KEK_DEFAULT_FILE1=$WORKSPACE/keys/ms_kek.cer -# -D DB_DEFAULT_FILE1=$WORKSPACE/keys/ms_db1.cer -# -D DB_DEFAULT_FILE2=$WORKSPACE/keys/ms_db2.cer -# -D DBX_DEFAULT_FILE1=$WORKSPACE/keys/arm64_dbx.bin: -# https://github.com/pftf/RPi4/blob/master/.github/workflows/linux_edk2.yml#L64-L65 -# -# And with this, you should have a UEFI firmware that both Windows and -# Linux are happy with when it comes to Secure Boot. +!if $(CAPSULE_ENABLE) == TRUE + DEFINE UEFI_IMAGE = Build/ComHpcAlt/comhpcalt_uefi.bin + DEFINE TFA_UEFI_IMAGE = Build/ComHpcAlt/comhpcalt_tfa_uefi.bin +!endif !include MdePkg/MdeLibs.dsc.inc @@ -171,6 +153,8 @@ # gAmpereTokenSpaceGuid.PcdPcieHotPlugPortMapTable.UseDefaultConfig|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE + [PcdsFixedAtBuild] gAmpereTokenSpaceGuid.PcdPcieHotPlugGpioResetMap|0x3F @@ -200,6 +184,17 @@ gAmpereTokenSpaceGuid.PcdSmbusI2cBusSpeed|100000 + # We should support CoD in future, since it provides a nicer + # upgrade experience (e.g. a progress bar). + gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleOnDiskSupport|FALSE + +!if $(SECURE_BOOT_ENABLE) == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdRsa2048Sha256PublicKeyBuffer|{0} + !include Platform/ADLINK/ComHpcAltPkg/root.cer.gEfiSecurityPkgTokenSpaceGuid.PcdPkcs7CertBuffer.inc +!endif + + gAmpereTokenSpaceGuid.PcdFirmwareVersionNumber|$(FIRMWARE_VER_HEX) + gPostCodeDebugFeaturePkgTokenSpaceGuid.PcdStatusCodeUsePostCode|TRUE [PcdsFixedAtBuild.common] @@ -291,8 +286,8 @@ [PcdsDynamicExDefault.common.DEFAULT] gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100 - gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0xf6, 0xc8, 0x4a, 0x70, 0x39, 0xcb, 0xb7, 0x47, 0x8f, 0x26, 0x39, 0x6c, 0xe9, 0xdb, 0x69, 0x71} - gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{0x79, 0x00, 0x7b, 0xc0, 0xa2, 0xb3, 0x8d, 0x44, 0x8c, 0x9c, 0x46, 0xba, 0x3c, 0x42, 0xb3, 0x3e} + gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{GUID("cdcdd0b7-8afb-4883-853a-ae9398077a0e")}|VOID*|0x10 + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{GUID("074c21e5-7d17-48e9-808d-f0c85e52a7db")}|VOID*|0x10 [PcdsPatchableInModule] # @@ -359,15 +354,6 @@ ManageabilityPkg/Universal/IpmiBlobTransferDxe/IpmiBlobTransferDxe.inf Features/ManageabilityPkg/Universal/IpmiProtocol/Dxe/IpmiProtocolDxe.inf - # - # Firmware Capsule Update - # - Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf - MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf - SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf - SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf - MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf - # # HII # @@ -379,6 +365,32 @@ Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.inf Silicon/Ampere/AmpereSiliconPkg/Drivers/BmcConfigDxe/BmcConfigDxe.inf + # + # Firmware Capsule Update + # +!if $(CAPSULE_ENABLE) == TRUE + Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf + MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf + MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf { + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf + } + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf + } + MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + + # + # System Firmware Update + # + Silicon/Ampere/AmpereAltraPkg/Drivers/SystemFirmwareUpdateDxe/SystemFirmwareUpdateDxe.inf +!endif + # Redfish # !if $(NETWORK_ENABLE) == TRUE diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf index 78dde178e06..28f75475ac7 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf @@ -160,6 +160,10 @@ APRIORI PEI { INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf } +!if $(CAPSULE_ENABLE) == TRUE + INF RuleOverride = FMP_IMAGE_DESC Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf +!endif + INF ArmPlatformPkg/Sec/Sec.inf INF MdeModulePkg/Core/Pei/PeiMain.inf INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf @@ -175,6 +179,8 @@ APRIORI PEI { INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Universal/CapsuleOnDiskLoadPei/CapsuleOnDiskLoadPei.inf + INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf INF Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.inf @@ -192,8 +198,6 @@ APRIORI PEI { INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf - INF RuleOverride = FMP_IMAGE_DESC Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf - FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { SECTION FV_IMAGE = FVMAIN @@ -414,21 +418,19 @@ APRIORI DXE { # SMBIOS # INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf - INF ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf INF ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + INF ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf INF Platform/ADLINK/ComHpcAltPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf INF ManageabilityPkg/Universal/IpmiBlobTransferDxe/IpmiBlobTransferDxe.inf # # Firmware Capsule Update # - INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf - INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf - - FILE FREEFORM = PCD(gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiPkcs7TestPublicKeyFileGuid) { - SECTION RAW = BaseTools/Source/Python/Pkcs7Sign/TestRoot.cer - SECTION UI = "Pkcs7TestRoot" - } +!if $(CAPSULE_ENABLE) == TRUE + INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf + INF MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf + INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf +!endif # # HII diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAltCapsule.dsc b/Platform/ADLINK/ComHpcAltPkg/ComHpcAltCapsule.dsc index 6520c1e4320..ea9d49f9eb5 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAltCapsule.dsc +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAltCapsule.dsc @@ -26,5 +26,6 @@ # Defines for default states. These can be changed on the command line. # -D FLAG=VALUE # - DEFINE UEFI_TFA_IMAGE = Build/ComHpcAlt/comhpcalt_tfa_uefi.bin - DEFINE SCP_IMAGE = altra_scp_signed_2.10.20230517.slim + DEFINE INCLUDE_TFA_FW = TRUE + DEFINE UEFI_IMAGE = Build/ComHpcAlt/comhpcalt_uefi.bin + DEFINE TFA_UEFI_IMAGE = Build/ComHpcAlt/comhpcalt_tfa_uefi.bin diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAltCapsule.fdf b/Platform/ADLINK/ComHpcAltPkg/ComHpcAltCapsule.fdf index 39ed2b55832..b076034c9eb 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAltCapsule.fdf +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAltCapsule.fdf @@ -20,27 +20,25 @@ # ################################################################################ -[FD.ALTRA_SCP_FIRMWARE_CAPSULE] +[FD.COMHPCALT_HOST_FIRMWARE_CAPSULE] BaseAddress = 0x00000000 # The base address of the Firmware in NOR Flash. -Size = 0x00050000 # The size in bytes of the FLASH Device +!if $(INCLUDE_TFA_FW) == TRUE + Size = 0x00C10000 # The size in bytes of the FLASH Device +!else + Size = 0x00A10000 +!endif ErasePolarity = 1 0x00000000|0x00010000 FILE = $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/SYSTEMFIRMWAREDESCRIPTOR.Fv -0x00010000|0x00040000 -FILE = $(SCP_IMAGE) - -[FD.COMHPCALT_UEFI_TFA_FIRMWARE_CAPSULE] -BaseAddress = 0x00000000 # The base address of the Firmware in NOR Flash. -Size = 0x00D10000 # The size in bytes of the FLASH Device -ErasePolarity = 1 - -0x00000000|0x00010000 -FILE = $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/SYSTEMFIRMWAREDESCRIPTOR.Fv - -0x00010000|0x00D00000 -FILE = $(UEFI_TFA_IMAGE) +!if $(INCLUDE_TFA_FW) == TRUE + 0x00010000|0x00C00000 + FILE = $(TFA_UEFI_IMAGE) +!else + 0x00010000|0x00A00000 + FILE = $(UEFI_IMAGE) +!endif ################################################################################ # @@ -53,7 +51,7 @@ FILE = $(UEFI_TFA_IMAGE) # ################################################################################ -[FV.SystemScpFirmwareUpdateCargo] +[FV.HostFirmwareUpdateCargo] FvAlignment = 16 ERASE_POLARITY = 1 MEMORY_MAPPED = TRUE @@ -71,78 +69,36 @@ READ_STATUS = TRUE READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE -FILE RAW = c07b0079-b3a2-448d-8c9c-46ba3c42b33e { # PcdEdkiiSystemFirmwareFileGuid - FD = ALTRA_SCP_FIRMWARE_CAPSULE - } +FILE RAW = 074c21e5-7d17-48e9-808d-f0c85e52a7db { # PcdEdkiiSystemFirmwareFileGuid + FD = COMHPCALT_HOST_FIRMWARE_CAPSULE +} FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid - $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/CAPSULEDISPATCHFV.Fv - } + $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/CAPSULEDISPATCHFV.Fv +} FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid - Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/SCPFirmwareUpdateConfig.ini - } - -[FmpPayload.FmpPayloadScpSystemFirmwarePkcs7] -IMAGE_HEADER_INIT_VERSION = 0x02 +!if $(INCLUDE_TFA_FW) + Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/TfaUefiFirmwareUpdateConfig.ini +!else + Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/UefiFirmwareUpdateConfig.ini +!endif +} + +[FmpPayload.FmpPayloadHostFirmwarePkcs7] +IMAGE_HEADER_INIT_VERSION = 0x03 IMAGE_TYPE_ID = cdcdd0b7-8afb-4883-853a-ae9398077a0e # PcdSystemFmpCapsuleImageTypeIdGuid IMAGE_INDEX = 0x1 HARDWARE_INSTANCE = 0x0 MONOTONIC_COUNT = 0x1 CERTIFICATE_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7 -FV = SystemScpFirmwareUpdateCargo +FV = HostFirmwareUpdateCargo -[Capsule.ComHpcAltScpFirmwareUpdateCapsuleFmpPkcs7] +[Capsule.ComHpcAltHostFirmware] CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid CAPSULE_HEADER_SIZE = 0x20 CAPSULE_HEADER_INIT_VERSION = 0x1 -FMP_PAYLOAD = FmpPayloadScpSystemFirmwarePkcs7 - -[FV.SystemFirmwareUpdateCargo] -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - -FILE RAW = c07b0079-b3a2-448d-8c9c-46ba3c42b33e { # PcdEdkiiSystemFirmwareFileGuid - FD = COMHPCALT_UEFI_TFA_FIRMWARE_CAPSULE - } - -FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid - $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/CAPSULEDISPATCHFV.Fv - } - -FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid - Platform/ADLINK/ComHpcAltPkg/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini - } - -[FmpPayload.FmpPayloadSystemFirmwarePkcs7] -IMAGE_HEADER_INIT_VERSION = 0x02 -IMAGE_TYPE_ID = cdcdd0b7-8afb-4883-853a-ae9398077a0e # PcdSystemFmpCapsuleImageTypeIdGuid -IMAGE_INDEX = 0x1 -HARDWARE_INSTANCE = 0x0 -MONOTONIC_COUNT = 0x1 -CERTIFICATE_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7 - -FV = SystemFirmwareUpdateCargo - -[Capsule.ComHpcAltUefiAtfFirmwareUpdateCapsuleFmpPkcs7] -CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid -CAPSULE_HEADER_SIZE = 0x20 -CAPSULE_HEADER_INIT_VERSION = 0x1 +FMP_PAYLOAD = FmpPayloadHostFirmwarePkcs7 -FMP_PAYLOAD = FmpPayloadSystemFirmwarePkcs7 diff --git a/Platform/ADLINK/ComHpcAltPkg/firmware.metainfo.xml b/Platform/ADLINK/ComHpcAltPkg/firmware.metainfo.xml new file mode 100644 index 00000000000..cb66feb6fc8 --- /dev/null +++ b/Platform/ADLINK/ComHpcAltPkg/firmware.metainfo.xml @@ -0,0 +1,48 @@ + + + com.adlinktech.ComHpcAlt.firmware + + X-System + + COM-HPC-ALT + Ampere Altra Developer Platform/Dev Kit/AVA Developer Platform/Developer Rugged + Firmware for ADLINK Ampere Altra Boards + +

+ Updating the firmware on your Ampere Altra Developer Platform + improves performance and adds new features. +

+ + + cdcdd0b7-8afb-4883-853a-ae9398077a0e + + https://www.adlinktech.com + BSD-2-Clause-Patent + BSD-2-Clause-Patent + + + + https://github.com/tianocore/edk2-platforms + + {RELEASE_NOTES} + + + + + + + + org.freedesktop.fwupd + + + + number + org.uefi.capsule + signed + + + + bios + + diff --git a/Platform/Ampere/JadePkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Ampere/JadePkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc index eb3a3c731bc..c80bc31438b 100644 --- a/Platform/Ampere/JadePkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc +++ b/Platform/Ampere/JadePkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc @@ -12,15 +12,13 @@ #include #include +#include "HostFwInfo.h" + #define PACKAGE_VERSION 0xFFFFFFFF #define PACKAGE_VERSION_STRING L"Unknown" -#define CURRENT_FIRMWARE_VERSION 0x00000001 -#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000001" -#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001 - #define IMAGE_ID SIGNATURE_64('J', 'A', 'D', 'E', '_', 'F', 'W', ' ') -#define IMAGE_ID_STRING L"Jade System Firmware" +#define IMAGE_ID_STRING L"Jade Host Firmware" // PcdSystemFmpCapsuleImageTypeIdGuid #define IMAGE_TYPE_ID_GUID { 0xf08bca31, 0x542e, 0x4cea, { 0x8b, 0x48, 0x8e, 0x54, 0xf9, 0x42, 0x25, 0x94 } } @@ -49,15 +47,17 @@ STATIC IMAGE_DESCRIPTOR mImageDescriptor = CURRENT_FIRMWARE_VERSION, // Version; OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName; {0x0}, // Reserved2 - 0, // Size; + 0xA00000, // Size; IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | IMAGE_ATTRIBUTE_RESET_REQUIRED | IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | - IMAGE_ATTRIBUTE_IN_USE, // AttributesSupported; + IMAGE_ATTRIBUTE_IN_USE | + IMAGE_ATTRIBUTE_UEFI_IMAGE, // AttributesSupported; IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | IMAGE_ATTRIBUTE_RESET_REQUIRED | IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | - IMAGE_ATTRIBUTE_IN_USE, // AttributesSetting; + IMAGE_ATTRIBUTE_IN_USE | + IMAGE_ATTRIBUTE_UEFI_IMAGE, // AttributesSetting; 0x0, // Compatibilities; LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion; 0x00000000, // LastAttemptVersion; diff --git a/Platform/Ampere/JadePkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Ampere/JadePkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf index 8d77cf4e264..4fa129da224 100644 --- a/Platform/Ampere/JadePkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf +++ b/Platform/Ampere/JadePkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf @@ -31,8 +31,6 @@ PeiServicesLib PeimEntryPoint -[FixedPcd] - [Pcd] gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor diff --git a/Platform/Ampere/JadePkg/Capsule/SystemFirmwareUpdateConfig/SCPFirmwareUpdateConfig.ini b/Platform/Ampere/JadePkg/Capsule/SystemFirmwareUpdateConfig/SCPFirmwareUpdateConfig.ini deleted file mode 100644 index 050463a46f6..00000000000 --- a/Platform/Ampere/JadePkg/Capsule/SystemFirmwareUpdateConfig/SCPFirmwareUpdateConfig.ini +++ /dev/null @@ -1,20 +0,0 @@ -## @file -# -# Copyright (c) 2024, Ampere Computing LLC. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Head] -NumOfUpdate = 1 -NumOfRecovery = 0 -Update0 = JadeSCP - -[JadeSCP] -FirmwareType = 2147483649 # 0x80000001: SMpro/PMpro Firmware -AddressType = 1 # 0 - relative address, 1 - absolute address. -BaseAddress = 0x00000000 # Base address offset on flash -Length = 0x00050000 # Length -ImageOffset = 0x00000000 # Image offset of this SystemFirmware image -FileGuid = 431c06ed-4fe2-438f-98a3-a9b1fd923019 # PcdEdkiiSystemFirmwareFileGuid diff --git a/Platform/Ampere/JadePkg/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini b/Platform/Ampere/JadePkg/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini index 253005d1b71..0972b5937cb 100644 --- a/Platform/Ampere/JadePkg/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini +++ b/Platform/Ampere/JadePkg/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini @@ -15,6 +15,6 @@ Update0 = JadeUEFIATF FirmwareType = 2147483650 # SystemFirmware: 0x80000002 - OEM UEFI and ARM Trusted Firmware AddressType = 1 # 0 - relative address, 1 - absolute address. BaseAddress = 0x00000000 # Base address offset on flash -Length = 0x00D10000 # Length +Length = 0x00A10000 # Length ImageOffset = 0x00000000 # Image offset of this SystemFirmware image FileGuid = 431c06ed-4fe2-438f-98a3-a9b1fd923019 # PcdEdkiiSystemFirmwareFileGuid diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc index 6bc8fd2d475..2c4fd5c3dfb 100644 --- a/Platform/Ampere/JadePkg/Jade.dsc +++ b/Platform/Ampere/JadePkg/Jade.dsc @@ -52,7 +52,10 @@ !else DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x8000000F !endif - DEFINE FIRMWARE_VER = 0.01.001 + DEFINE FIRMWARE_VER = 00.01.01-01 + DEFINE FIRMWARE_VER_HEX = 0x00010100 + DEFINE CAPSULE_ENABLE = TRUE + DEFINE INCLUDE_TFA_FW = TRUE DEFINE SECURE_BOOT_ENABLE = TRUE DEFINE TPM2_ENABLE = TRUE DEFINE SHELL_ENABLE = TRUE @@ -68,6 +71,11 @@ DEFINE NETWORK_TLS_ENABLE = TRUE DEFINE REDFISH_ENABLE = TRUE +!if $(CAPSULE_ENABLE) == TRUE + DEFINE UEFI_IMAGE = Build/Jade/jade_uefi.bin + DEFINE TFA_UEFI_IMAGE = BUild/Jade/jade_tfa_uefi.bin +!endif + !include MdePkg/MdeLibs.dsc.inc # Include default Ampere Platform DSC file @@ -124,6 +132,8 @@ # gAmpereTokenSpaceGuid.PcdPcieHotPlugPortMapTable.UseDefaultConfig|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE + [PcdsFixedAtBuild] gAmpereTokenSpaceGuid.PcdPcieHotPlugGpioResetMap|0x3F @@ -186,6 +196,17 @@ gAmpereTokenSpaceGuid.PcdPcieHotPlugPortMapTable.PortMap[35]|{ 35, 1, 7, 6, 0, 0x24, 0x70, 0x4, 0, 11, 8 } # S1 RCB3.6 - SSD8 gAmpereTokenSpaceGuid.PcdPcieHotPlugPortMapTable.PortMap[36]|{ 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xFF } # Require if no fully structure used + # We should support CoD in future, since it provides a nicer + # upgrade experience (e.g. a progress bar). + gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleOnDiskSupport|FALSE + +!if $(SECURE_BOOT_ENABLE) == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdRsa2048Sha256PublicKeyBuffer|{0} + !include Platform/Ampere/JadePkg/root.cer.gEfiSecurityPkgTokenSpaceGuid.PcdPkcs7CertBuffer.inc +!endif + + gAmpereTokenSpaceGuid.PcdFirmwareVersionNumber|$(FIRMWARE_VER_HEX) + [PcdsFixedAtBuild.common] # # Platform config UUID @@ -212,8 +233,8 @@ [PcdsDynamicExDefault.common.DEFAULT] gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100 - gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x31, 0xca, 0x8b, 0xf0, 0x2e, 0x54, 0xea, 0x4c, 0x8b, 0x48, 0x8e, 0x54, 0xf9, 0x42, 0x25, 0x94} - gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{0xed, 0x06, 0x1c, 0x43, 0xe2, 0x4f, 0x8f, 0x43, 0x98, 0xa3, 0xa9, 0xb1, 0xfd, 0x92, 0x30, 0x19} + gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{GUID("f08bca31-542e-4cea-8b48-8e54f9422594")}|VOID*|0x10 + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{GUID("431c06ed-4fe2-438f-98a3-a9b1fd923019")}|VOID*|0x10 [PcdsPatchableInModule] # @@ -275,16 +296,28 @@ # # Firmware Capsule Update # +!if $(CAPSULE_ENABLE) == TRUE Platform/Ampere/JadePkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf - SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf - SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf - MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf + MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf { + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf + } + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf + } + MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } # # System Firmware Update # Silicon/Ampere/AmpereAltraPkg/Drivers/SystemFirmwareUpdateDxe/SystemFirmwareUpdateDxe.inf +!endif # # In-band NVPARAM Access diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf index 4fe703fc7a5..66091defe97 100644 --- a/Platform/Ampere/JadePkg/Jade.fdf +++ b/Platform/Ampere/JadePkg/Jade.fdf @@ -153,6 +153,10 @@ APRIORI PEI { INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf } +!if $(CAPSULE_ENABLE) == TRUE + INF RuleOverride = FMP_IMAGE_DESC Platform/Ampere/JadePkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf +!endif + INF ArmPlatformPkg/Sec/Sec.inf INF MdeModulePkg/Core/Pei/PeiMain.inf INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf @@ -165,6 +169,8 @@ APRIORI PEI { INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Universal/CapsuleOnDiskLoadPei/CapsuleOnDiskLoadPei.inf + INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf INF Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.inf @@ -182,8 +188,6 @@ APRIORI PEI { INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf - INF RuleOverride = FMP_IMAGE_DESC Platform/Ampere/JadePkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf - FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { SECTION FV_IMAGE = FVMAIN @@ -404,18 +408,11 @@ APRIORI DXE { # # Firmware Capsule Update # - INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf - INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf - - FILE FREEFORM = PCD(gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiPkcs7TestPublicKeyFileGuid) { - SECTION RAW = BaseTools/Source/Python/Pkcs7Sign/TestRoot.cer - SECTION UI = "Pkcs7TestRoot" - } - - # - # System Firmware Update - # - INF Silicon/Ampere/AmpereAltraPkg/Drivers/SystemFirmwareUpdateDxe/SystemFirmwareUpdateDxe.inf +!if $(CAPSULE_ENABLE) == TRUE + INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf + INF MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf + INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf +!endif # # In-band NVPARAM Access diff --git a/Platform/Ampere/JadePkg/JadeCapsule.dsc b/Platform/Ampere/JadePkg/JadeCapsule.dsc index c79581c9e5a..4e850010fb4 100755 --- a/Platform/Ampere/JadePkg/JadeCapsule.dsc +++ b/Platform/Ampere/JadePkg/JadeCapsule.dsc @@ -26,5 +26,7 @@ # Defines for default states. These can be changed on the command line. # -D FLAG=VALUE # - DEFINE UEFI_ATF_IMAGE = Build/Jade/jade_tfa_uefi.bin - DEFINE SCP_IMAGE = Build/Jade/altra_scp.slim + DEFINE INCLUDE_TFA_FW = TRUE + DEFINE UEFI_IMAGE = Build/Jade/jade_uefi.bin + DEFINE TFA_UEFI_IMAGE = Build/Jade/jade_tfa_uefi.bin + diff --git a/Platform/Ampere/JadePkg/JadeCapsule.fdf b/Platform/Ampere/JadePkg/JadeCapsule.fdf index b9536b171bf..6c26ef3ca4d 100755 --- a/Platform/Ampere/JadePkg/JadeCapsule.fdf +++ b/Platform/Ampere/JadePkg/JadeCapsule.fdf @@ -20,27 +20,25 @@ # ################################################################################ -[FD.JADE_SCP_FIRMWARE_CAPSULE] +[FD.JADE_HOST_FIRMWARE_CAPSULE] BaseAddress = 0x00000000 # The base address of the Firmware in NOR Flash. -Size = 0x00050000 # The size in bytes of the FLASH Device +!if $(INCLUDE_TFA_FW) == TRUE + Size = 0x00C10000 +!else + Size = 0x00A10000 +!endif ErasePolarity = 1 0x00000000|0x00010000 FILE = $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/SYSTEMFIRMWAREDESCRIPTOR.Fv -0x00010000|0x00040000 -FILE = $(SCP_IMAGE) - -[FD.JADE_UEFI_ATF_FIRMWARE_CAPSULE] -BaseAddress = 0x00000000 # The base address of the Firmware in NOR Flash. -Size = 0x00D10000 # The size in bytes of the FLASH Device -ErasePolarity = 1 - -0x00000000|0x00010000 -FILE = $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/SYSTEMFIRMWAREDESCRIPTOR.Fv - -0x00010000|0x00D00000 -FILE = $(UEFI_ATF_IMAGE) +!if $(INCLUDE_TFA_FW) == TRUE + 0x00010000|0x00C00000 + FILE = $(TFA_UEFI_IMAGE) +!else + 0x00010000|0x00A00000 + FILE = $(UEFI_IMAGE) +!endif ################################################################################ # @@ -53,53 +51,6 @@ FILE = $(UEFI_ATF_IMAGE) # ################################################################################ -[FV.SystemScpFirmwareUpdateCargo] -FvAlignment = 16 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - -FILE RAW = 431C06ED-4FE2-438F-98A3-A9B1FD923019 { # PcdEdkiiSystemFirmwareFileGuid - FD = JADE_SCP_FIRMWARE_CAPSULE - } - -FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid - $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/CAPSULEDISPATCHFV.Fv - } - -FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid - Platform/Ampere/JadePkg/Capsule/SystemFirmwareUpdateConfig/SCPFirmwareUpdateConfig.ini - } - -[FmpPayload.FmpPayloadScpSystemFirmwarePkcs7] -IMAGE_HEADER_INIT_VERSION = 0x02 -IMAGE_TYPE_ID = f08bca31-542e-4cea-8b48-8e54f9422594 # PcdSystemFmpCapsuleImageTypeIdGuid -IMAGE_INDEX = 0x1 -HARDWARE_INSTANCE = 0x0 -MONOTONIC_COUNT = 0x1 -CERTIFICATE_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7 - -FV = SystemScpFirmwareUpdateCargo - -[Capsule.JadeScpFirmwareUpdateCapsuleFmpPkcs7] -CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid -CAPSULE_HEADER_SIZE = 0x20 -CAPSULE_HEADER_INIT_VERSION = 0x1 - -FMP_PAYLOAD = FmpPayloadScpSystemFirmwarePkcs7 - [FV.SystemFirmwareUpdateCargo] FvAlignment = 16 ERASE_POLARITY = 1 @@ -119,7 +70,7 @@ READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE FILE RAW = 431C06ED-4FE2-438F-98A3-A9B1FD923019 { # PcdEdkiiSystemFirmwareFileGuid - FD = JADE_UEFI_ATF_FIRMWARE_CAPSULE + FD = JADE_HOST_FIRMWARE_CAPSULE } FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid @@ -130,8 +81,8 @@ FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfig Platform/Ampere/JadePkg/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini } -[FmpPayload.FmpPayloadSystemFirmwarePkcs7] -IMAGE_HEADER_INIT_VERSION = 0x02 +[FmpPayload.FmpPayloadHostFirmwarePkcs7] +IMAGE_HEADER_INIT_VERSION = 0x03 IMAGE_TYPE_ID = f08bca31-542e-4cea-8b48-8e54f9422594 # PcdSystemFmpCapsuleImageTypeIdGuid IMAGE_INDEX = 0x1 HARDWARE_INSTANCE = 0x0 @@ -140,9 +91,9 @@ CERTIFICATE_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7 FV = SystemFirmwareUpdateCargo -[Capsule.JadeUefiAtfFirmwareUpdateCapsuleFmpPkcs7] +[Capsule.JadeHostFirmware] CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid CAPSULE_HEADER_SIZE = 0x20 CAPSULE_HEADER_INIT_VERSION = 0x1 -FMP_PAYLOAD = FmpPayloadSystemFirmwarePkcs7 +FMP_PAYLOAD = FmpPayloadHostFirmwarePkcs7 diff --git a/Platform/Ampere/Tools/fw_ver.sh b/Platform/Ampere/Tools/fw_ver.sh index caf5dcbea56..1b09a56565a 100644 --- a/Platform/Ampere/Tools/fw_ver.sh +++ b/Platform/Ampere/Tools/fw_ver.sh @@ -11,4 +11,10 @@ fi MAJOR_VER="$(date +%y)" MINOR_VER="$(date +%m)" -VER="$(date +%Y.%m.%d)" +MICRO_VER="$(date +%d)" +VER="${MAJOR_VER}.${MINOR_VER}.${MICRO_VER}-$(printf '%02d' ${BUILD})" +YHEX=$(printf '%03x' $(date +%y)) +MHEX=$(printf '%01x' $(date +%m)) +DHEX=$(printf '%02x' $(date +%e)) +BHEX=$(printf '%02x' ${BUILD}) +VER_HEX=0x${YHEX}${MHEX}${DHEX}${BHEX} diff --git a/Platform/Ampere/Tools/tools_def.txt.patch b/Platform/Ampere/Tools/tools_def.txt.patch new file mode 100644 index 00000000000..d4e77030b4f --- /dev/null +++ b/Platform/Ampere/Tools/tools_def.txt.patch @@ -0,0 +1,10 @@ +--- BaseTools/Conf/tools_def.template 2024-11-26 08:55:42.209038055 -0700 ++++ Conf/tools_def.txt 2024-11-26 08:56:30.666355277 -0700 +@@ -2414,6 +2414,7 @@ + ################## + *_*_*_PKCS7SIGN_PATH = Pkcs7Sign + *_*_*_PKCS7SIGN_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 ++*_*_*_PKCS7SIGN_FLAGS = --signer-private-cert ENV(SECUREBOOT_DIR)/certs/user.pem --other-public-cert ENV(SECUREBOOT_DIR)/certs/intermediate.pub.pem --trusted-public-cert ENV(SECUREBOOT_DIR)/certs/root.pub.pem + + ################## + # NASM tool definitions diff --git a/Platform/Ampere/buildfw.sh b/Platform/Ampere/buildfw.sh index 21eb8641198..02495bba00f 100755 --- a/Platform/Ampere/buildfw.sh +++ b/Platform/Ampere/buildfw.sh @@ -258,8 +258,20 @@ if [ -z "${LINUXBOOT}" ] && [ -f "${TFA_SLIM}" ] && [ -f "${SCP_SLIM}" ]; then -D SECURE_BOOT_ENABLE \ -p Platform/${MANUFACTURER}/${BOARD_NAME}Pkg/${BOARD_NAME}Capsule.dsc - cp -vf "Build/${BOARD_NAME}/${BLDTYPE}_${TOOLCHAIN}/FV/${BOARD_NAME^^}UEFIATFFIRMWAREUPDATECAPSULEFMPPKCS7.Cap" "${OUTPUT_BASENAME}.cap" - cp -vf "Build/${BOARD_NAME}/${BLDTYPE}_${TOOLCHAIN}/FV/${BOARD_NAME^^}SCPFIRMWAREUPDATECAPSULEFMPPKCS7.Cap" "${OUTPUT_BIN_DIR}/${BOARD_NAME,,}_scp_${SCP_VERSION}.cap" + cp -vf "Build/${BOARD_NAME}/${BLDTYPE}_${TOOLCHAIN}/FV/${BOARD_NAME^^}HOSTFIRMWARE.Cap" "Build/${BOARD_NAME}/${BOARD_NAME,,}_host_${BLDTYPE,,}_${VER}.cap" + cp -vf "Build/${BOARD_NAME}/${BLDTYPE}_${TOOLCHAIN}/AARCH64/CapsuleApp.efi" "Build/${BOARD_NAME}/" + mkdir Build/${BOARD_NAME}/Cab || true + rm -f Build/${BOARD_NAME}/Cab/* + METAINFO_FILE="Build/${BOARD_NAME}/Cab/firmware.metainfo.xml" + cp -vf "${WORKSPACE}/edk2-platforms/Platform/${MANUFACTURER}/${BOARD_NAME}Pkg/firmware.metainfo.xml" "${METAINFO_FILE}" + cp -vf "Build/${BOARD_NAME}/${BOARD_NAME,,}_host_${BLDTYPE,,}_${VER}.cap" "Build/${BOARD_NAME}/Cab/firmware.bin" + sed -i "s/{URGENCY}/high/g" "${METAINFO_FILE}" + sed -i "s/{FW_VERSION}/$(printf '%d' ${VER_HEX})/g" "${METAINFO_FILE}" + sed -i "s/{FW_DATE}/$(date +%Y-%m-%d)/g" "${METAINFO_FILE}" + sed -i "s/{RELEASE_NOTES}//g" "${METAINFO_FILE}" + pushd "Build/${BOARD_NAME}/Cab" + lcab -q ./* "../${BOARD_NAME,,}_host_${BLDTYPE,,}_${VER}.cab" + popd fi if [ "${BOARD_NAME}" = "ComHpcAlt" ] && [ ! -e "${WORKSPACE}/${UPD720202_ROM_FILE}" ]; then diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc index 39ebdce91f6..016bf652b30 100755 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc @@ -241,7 +241,7 @@ [PcdsFixedAtBuild.common] !ifdef $(FIRMWARE_VER) - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER_FULL)" !endif gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 @@ -428,7 +428,7 @@ # # SMBIOS PCDs # - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER_FULL)" gAmpereTokenSpaceGuid.PcdSmbiosTables0MajorVersion|$(MAJOR_VER) gAmpereTokenSpaceGuid.PcdSmbiosTables0MinorVersion|$(MINOR_VER) gArmTokenSpaceGuid.PcdProcessorManufacturer|L"Ampere(R)" diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc index d6b6603b50b..65f265d4925 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -519,7 +519,7 @@ # # SMBIOS PCDs # - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER_FULL)" gAmpereTokenSpaceGuid.PcdSmbiosTables0MajorVersion|$(MAJOR_VER) gAmpereTokenSpaceGuid.PcdSmbiosTables0MinorVersion|$(MINOR_VER) gArmTokenSpaceGuid.PcdProcessorManufacturer|L"Ampere(R)" From 6dfd03809ea7fcbff60f7863480ad3a068ae8cf0 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:49:49 -0700 Subject: [PATCH 12/35] Platform/Ampere: Rework buildfw.sh to support capsules and secure boot Signed-off-by: Rebecca Cran --- Platform/Ampere/buildfw.sh | 125 +++++++++++++++++++++++++++++++------ 1 file changed, 107 insertions(+), 18 deletions(-) diff --git a/Platform/Ampere/buildfw.sh b/Platform/Ampere/buildfw.sh index 02495bba00f..96de8a67b34 100755 --- a/Platform/Ampere/buildfw.sh +++ b/Platform/Ampere/buildfw.sh @@ -1,5 +1,15 @@ #!/usr/bin/env bash +## +# @file +# Build script for platforms with an Altra(R) CPU from Ampere(R). +# +# Copyright (c) 2024, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + set -o errexit tfa_usage () { @@ -41,7 +51,15 @@ usage () { echo " Available platforms:" echo " ADLINK -> ComHpcAlt" echo " Ampere -> Jade" - echo " ASRockRack -> Altrad8ud2" + echo " ASRockRack -> Altra1L2Q" + echo " ASRockRack -> Altra1L2T" + echo "" + echo "Environment Variables:" + echo " SECUREBOOT_DIR - directory to store SecureBoot keys, certs etc." + echo " USE_EXISTING_SB_KEYS - use existing Secure Boot Platform and Update keys" + echo " DOWNLOAD_MS_SB_KEYS - force re-download of Microsoft Secure Boot KEK and DB certificates" + echo " CERT_PASSWORD - password to use when generating Platform and Update Keys and certificates" + echo " defaults to \"password\" if not specified." exit 1 } @@ -173,6 +191,27 @@ ${MAKE_COMMAND} -C edk2/BaseTools -j ${BUILD_THREADS} . "${WORKSPACE}/edk2-platforms/Platform/Ampere/Tools/fw_ver.sh" UPDATE . edk2/edksetup.sh +if [ -e "${WORKSPACE}/build.conf" ]; then + . "${WORKSPACE}/build.conf" +fi + +pushd edk2 +cp -vf BaseTools/Conf/tools_def.template Conf/tools_def.txt +patch -p0 < "${WORKSPACE}/edk2-platforms/Platform/Ampere/Tools/tools_def.txt.patch" +popd + +if [ -z "${SECUREBOOT_DIR}" ]; then + SECUREBOOT_DIR="${WORKSPACE}/secureboot_objects/" + export SECUREBOOT_DIR +fi + +if [ -n "${USE_EXISTING_SB_KEYS}" ]; then + export USE_EXISTING_SB_KEYS +fi +if [ -n "${CERT_PASSWORD}" ]; then + export CERT_PASSWORD +fi + EDK2_SECURE_BOOT_ENABLE=${EDK2_SECURE_BOOT_ENABLE:-TRUE} EDK2_NETWORK_ENABLE=${EDK2_NETWORK_ENABLE:-TRUE} EDK2_INCLUDE_TFTP_COMMAND=${EDK2_INCLUDE_TFTP_COMMAND:-TRUE} @@ -180,13 +219,38 @@ EDK2_NETWORK_IP6_ENABLE=${EDK2_NETWORK_IP6_ENABLE:-TRUE} EDK2_NETWORK_ALLOW_HTTP_CONNECTIONS=${EDK2_NETWORK_ALLOW_HTTP_CONNECTIONS:-TRUE} EDK2_NETWORK_TLS_ENABLE=${EDK2_NETWORK_TLS_ENABLE:-TRUE} EDK2_REDFISH_ENABLE=${EDK2_REDFISH_ENABLE:-TRUE} -EDK2_PERFORMANCE_MEASUREMENT_ENABLE=${EDK2_PERFORMANCE_MEASUREMENT_ENABLE:-TRUE} +EDK2_PERFORMANCE_MEASUREMENT_ENABLE=${EDK2_PERFORMANCE_MEASUREMENT_ENABLE:-FALSE} EDK2_TPM2_ENABLE=${EDK2_TPM2_ENABLE:-TRUE} +EDK2_HEAP_GUARD_ENABLE=${EDK2_HEAP_GUARD_ENABLE:-FALSE} +EDK2_X86_EMULATOR_ENABLE=${EDK2_X86_EMULATOR_ENABLE:-TRUE} +EDK2_SHELL_ENABLE=${EDK2_SHELL_ENABLE:-TRUE} if [ "${BLDTYPE}" = "RELEASE" ]; then - EDK2_HEAP_GUARD_ENABLE=FALSE + EDK2_SHELL_ENABLE=${EDK2_SHELL_ENABLE:-FALSE} else - EDK2_HEAP_GUARD_ENABLE=TRUE + EDK2_SHELL_ENABLE=${EDK2_SHELL_ENABLE:-TRUE} +fi + +if [ "${EDK2_HEAP_GUARD_ENABLE}" = "TRUE" ] && [ "${EDK2_X86_EMULATOR_ENABLE}" = "TRUE" ]; then + echo "Error: HeapGuard and X86 emulator are incompatible. Only one may be enabled at a time." + exit 1 +fi + +if [ "${EDK2_SECURE_BOOT_ENABLE}" = "TRUE" ]; then + export MANUFACTURER + export BOARD_NAME + "${WORKSPACE}/edk2-platforms/Platform/Ampere/Tools/GenerateSecureBootKeys.sh" + + EXTRA_BUILD_FLAGS+=" -D DEFAULT_KEYS=TRUE" + EXTRA_BUILD_FLAGS+=" -D PK_DEFAULT_FILE=${SECUREBOOT_DIR}/certs/platform_key.der" + EXTRA_BUILD_FLAGS+=" -D KEK_DEFAULT_FILE1=${SECUREBOOT_DIR}/certs/ms_kek1.der" + EXTRA_BUILD_FLAGS+=" -D KEK_DEFAULT_FILE2=${SECUREBOOT_DIR}/certs/ms_kek2.der" + EXTRA_BUILD_FLAGS+=" -D DB_DEFAULT_FILE1=${SECUREBOOT_DIR}/certs/ms_db1.der" + EXTRA_BUILD_FLAGS+=" -D DB_DEFAULT_FILE2=${SECUREBOOT_DIR}/certs/ms_db2.der" + EXTRA_BUILD_FLAGS+=" -D DB_DEFAULT_FILE3=${SECUREBOOT_DIR}/certs/ms_db3.der" + EXTRA_BUILD_FLAGS+=" -D DB_DEFAULT_FILE4=${SECUREBOOT_DIR}/certs/ms_db4.der" + EXTRA_BUILD_FLAGS+=" -D DB_DEFAULT_FILE5=${SECUREBOOT_DIR}/certs/ms_db5.der" + EXTRA_BUILD_FLAGS+=" -D DBX_DEFAULT_FILE1=${SECUREBOOT_DIR}/certs/dummy_dbx.der" fi UPD720202_ROM_FILE="K2026090.mem" @@ -198,9 +262,25 @@ if [ -e "${WORKSPACE}/IntelUndiBin/Release/AARCH64/GigUndiDxe.efi" ]; then EXTRA_BUILD_FLAGS+=" -D INTEL_UNDI_BIN=TRUE" fi +echo "EXTRA_BUILD_FLAGS=${EXTRA_BUILD_FLAGS}" + +# YearMonthDayBuild (0xYYMMDDBB) +echo "#define CURRENT_FIRMWARE_VERSION ${VER_HEX}" > "${WORKSPACE}/edk2-platforms/Platform/${MANUFACTURER}/${BOARD_NAME}Pkg/Capsule/SystemFirmwareDescriptor/HostFwInfo.h" +echo "#define CURRENT_FIRMWARE_VERSION_STRING L\"${FW_STR}\"" >> "${WORKSPACE}/edk2-platforms/Platform/${MANUFACTURER}/${BOARD_NAME}Pkg/Capsule/SystemFirmwareDescriptor/HostFwInfo.h" +echo "#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000000" >> "${WORKSPACE}/edk2-platforms/Platform/${MANUFACTURER}/${BOARD_NAME}Pkg/Capsule/SystemFirmwareDescriptor/HostFwInfo.h" + +if [ -f "${SCP_SLIM}" ]; then + cp -vf "${SCP_SLIM}" "Build/${BOARD_NAME}/altra_scp.slim" +fi +if [ -f "${TFA_SLIM}" ]; then + cp -vf "${TFA_SLIM}" "Build/${BOARD_NAME}/altra_atf.slim" +fi + build -a AARCH64 -t ${TOOLCHAIN} -b ${BLDTYPE} -n ${BUILD_THREADS} \ - -D FIRMWARE_VER="${VER}-${BUILD} TF-A ${TFA_VERSION}" \ - -D MAJOR_VER=${MAJOR_VER} -D MINOR_VER=${MINOR_VER} \ + -D FIRMWARE_VER_FULL="${VER} TF-A ${TFA_VERSION}" \ + -D FIRMWARE_VER="${VER}" \ + -D FIRMWARE_VER_HEX="${VER_HEX}" \ + -D MAJOR_VER=${MAJOR_VER} -D MINOR_VER=${MINOR_VER} \ -D SECURE_BOOT_ENABLE=${EDK2_SECURE_BOOT_ENABLE} \ -D NETWORK_ENABLE=${EDK2_NETWORK_ENABLE} \ -D INCLUDE_TFTP_COMMAND=${EDK2_INCLUDE_TFTP_COMMAND} \ @@ -211,17 +291,20 @@ build -a AARCH64 -t ${TOOLCHAIN} -b ${BLDTYPE} -n ${BUILD_THREADS} \ -D PERFORMANCE_MEASUREMENT_ENABLE=${EDK2_PERFORMANCE_MEASUREMENT_ENABLE} \ -D TPM2_ENABLE=${EDK2_TPM2_ENABLE} \ -D HEAP_GUARD_ENABLE=${EDK2_HEAP_GUARD_ENABLE} \ - -Y COMPILE_INFO -y BuildReport.log \ + -D X86_EMULATOR_ENABLE=${EDK2_X86_EMULATOR_ENABLE} \ + -D SHELL_ENABLE=${EDK2_SHELL_ENABLE} \ + -Y COMPILE_INFO -y BuildReport.log \ -p Platform/${MANUFACTURER}/${BOARD_NAME}Pkg/${BOARD_NAME}${LINUXBOOT}.dsc \ ${EXTRA_BUILD_FLAGS} -OUTPUT_BASENAME=${OUTPUT_BIN_DIR}/${BOARD_NAME,,}_tfa_uefi_${BLDTYPE,,}_${VER}-${BUILD} +OUTPUT_BASENAME=${OUTPUT_BIN_DIR}/${BOARD_NAME,,}_tfa_uefi_${BLDTYPE,,}_${VER} -OUTPUT_UEFI_IMAGE=Build/${BOARD_NAME}/${BOARD_NAME,,}_uefi_${BLDTYPE,,}_${VER}-${BUILD}.bin -OUTPUT_TFA_UEFI_IMAGE=Build/${BOARD_NAME}/${BOARD_NAME,,}_tfa_uefi_${BLDTYPE,,}_${VER}-${BUILD}.bin -OUTPUT_SPINOR_IMAGE=Build/${BOARD_NAME}/${BOARD_NAME,,}_rom_${BLDTYPE,,}_${VER}-${BUILD}.bin +OUTPUT_UEFI_IMAGE=Build/${BOARD_NAME}/${BOARD_NAME,,}_uefi_${BLDTYPE,,}_${VER}.bin +OUTPUT_TFA_UEFI_IMAGE=Build/${BOARD_NAME}/${BOARD_NAME,,}_tfa_uefi_${BLDTYPE,,}_${VER}.bin +OUTPUT_SPINOR_IMAGE=Build/${BOARD_NAME}/${BOARD_NAME,,}_rom_${BLDTYPE,,}_${VER}.bin cp -v "Build/${BOARD_NAME}/${BLDTYPE}_${TOOLCHAIN}/FV/BL33_${BOARD_NAME^^}_UEFI.fd" "${OUTPUT_UEFI_IMAGE}" +cp -vf "${OUTPUT_UEFI_IMAGE}" "Build/${BOARD_NAME}/${BOARD_NAME,,}_uefi.bin" if [ -f "${TFA_SLIM}" ]; then # Create a 2MB file with 0xff @@ -245,18 +328,24 @@ if [ -f "${TFA_SLIM}" ]; then cp -vf "${OUTPUT_TFA_UEFI_IMAGE}" "Build/${BOARD_NAME}/${BOARD_NAME,,}_tfa_uefi.bin" fi +if [ -f "${TFA_SLIM}" ]; then + INCLUDE_TFA_FW=TRUE +else + INCLUDE_TFA_FW=FALSE +fi + # LinuxBoot doesn't support capsule updates if [ -z "${LINUXBOOT}" ] && [ -f "${TFA_SLIM}" ] && [ -f "${SCP_SLIM}" ]; then - cp -vf "${SCP_SLIM}" "Build/${BOARD_NAME}/altra_scp.slim" - cp -vf "${TFA_SLIM}" "Build/${BOARD_NAME}/altra_atf.slim" # Build the capsule (for upgrading from the UEFI Shell or Linux) build -a AARCH64 -t ${TOOLCHAIN} -b ${BLDTYPE} -n ${BUILD_THREADS} \ - -D FIRMWARE_VER="${VER}-${BUILD} TF-A ${TFA_VERSION}" \ - -D MAJOR_VER=${MAJOR_VER} \ - -D MINOR_VER=${MINOR_VER} \ - -D SECURE_BOOT_ENABLE \ - -p Platform/${MANUFACTURER}/${BOARD_NAME}Pkg/${BOARD_NAME}Capsule.dsc + -D FIRMWARE_VER_FULL="${VER} TF-A ${TFA_VERSION}" \ + -D FIRMWARE_VER="${VER}" \ + -D FIRMWARE_VER_HEX="${VER_HEX}" \ + -D MAJOR_VER=${MAJOR_VER} \ + -D MINOR_VER=${MINOR_VER} \ + -D INCLUDE_TFA_FW=${INCLUDE_TFA_FW} \ + -p Platform/${MANUFACTURER}/${BOARD_NAME}Pkg/${BOARD_NAME}Capsule.dsc cp -vf "Build/${BOARD_NAME}/${BLDTYPE}_${TOOLCHAIN}/FV/${BOARD_NAME^^}HOSTFIRMWARE.Cap" "Build/${BOARD_NAME}/${BOARD_NAME,,}_host_${BLDTYPE,,}_${VER}.cap" cp -vf "Build/${BOARD_NAME}/${BLDTYPE}_${TOOLCHAIN}/AARCH64/CapsuleApp.efi" "Build/${BOARD_NAME}/" From c25841c253986d02d76e74775c9c76e20b59d271 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:47:11 -0700 Subject: [PATCH 13/35] Platform/Ampere: Use full space allocated for NVRAM Use the full space allocated in the flash layout map for NVRAM. Move the storage of the UUID to the end of that region. Signed-off-by: Rebecca Cran --- Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf | 39 +++++++++---------- Platform/Ampere/JadePkg/Jade.fdf | 32 +++++++-------- .../Drivers/FlashPei/FlashPei.c | 29 +++++++------- 3 files changed, 50 insertions(+), 50 deletions(-) diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf index 28f75475ac7..561c3f0f152 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf @@ -20,12 +20,15 @@ # ################################################################################ -# Note: We actually have 26MB (0x01A0'0000 bytes) for UEFI. -# A smaller size of 8MB is used to reduce time for flashing etc. +# Note: We have 10MB (0x00A0'0000 bytes) for UEFI. +# +# If this 10MB is ever changed, ComHpcAltCapsule.fdf and +# Capsule/HostFirmwareDescriptor/HostFirmwareDescriptor.aslc need +# updated too. [FD.BL33_COMHPCALT_UEFI] BaseAddress = 0x92000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. -Size = 0x00A00000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +Size = 0x00A00000 # The size in bytes of the FLASH Device ErasePolarity = 1 # This one is tricky, it must be: BlockSize * NumBlocks = Size @@ -51,18 +54,18 @@ NumBlocks = 0xA0 # # FV MAIN # Offset: 0x00000000 -# Size: 0x00970000 +# Size: 0x00900000 # -0x00000000|0x00970000 +0x00000000|0x00900000 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize FV = FVMAIN_COMPACT # # NV Variables -# Offset: 0x00970000 -# Size: 0x00030000 +# Offset: 0x00900000 +# Size: 0x00100000 # -0x00970000|0x00030000 +0x00900000|0x00070000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize DATA = { ## This is the EFI_FIRMWARE_VOLUME_HEADER @@ -80,8 +83,8 @@ DATA = { 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision 0x48, 0x00, 0x2D, 0x09, 0x00, 0x00, 0x00, 0x02, - # Blockmap[0]: 0x3 Blocks * 0x10000 Bytes / Block - 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + # Blockmap[0]: 0x7 Blocks * 0x10000 Bytes / Block + 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, # Blockmap[1]: End 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ## This is the VARIABLE_STORE_HEADER @@ -91,15 +94,15 @@ DATA = { # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, - # Size: 0x30000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - - # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x2FFB8 + # Size: 0xB0000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xAFFB8 # This can speed up the Variable Dispatch a bit. - 0xB8, 0xFF, 0x02, 0x00, + 0xB8, 0xFF, 0x06, 0x00, # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } -0x009A0000|0x00010000 +0x00970000|0x00020000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize DATA = { # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = @@ -109,16 +112,12 @@ DATA = { # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF, # WriteQueueSize: UINT64 Size: 0x10000 - 0x20 (FTW_WORKING_HEADER) = 0xFFE0 - 0xE0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + 0xE0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 } -0x009B0000|0x00040000 +0x00990000|0x00070000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize -# Leave 0x10000 (64KB) at the end for VPD data -# 0x009F0000|0x00010000 -# Absolute SPI-NOR flash address: 0xFF0000 - ################################################################################ # # FV Section diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf index 66091defe97..f9c794a467a 100644 --- a/Platform/Ampere/JadePkg/Jade.fdf +++ b/Platform/Ampere/JadePkg/Jade.fdf @@ -22,12 +22,12 @@ [FD.BL33_JADE_UEFI] BaseAddress = 0x92000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. -Size = 0x007C0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +Size = 0x00A00000 # The size in bytes of the FLASH Device ErasePolarity = 1 # This one is tricky, it must be: BlockSize * NumBlocks = Size BlockSize = 0x10000|gAmpereTokenSpaceGuid.PcdFvBlockSize -NumBlocks = 0x7C +NumBlocks = 0xA0 ################################################################################ # @@ -48,18 +48,18 @@ NumBlocks = 0x7C # # FV MAIN # Offset: 0x00000000 -# Size: 0x00740000 +# Size: 0x00900000 # -0x00000000|0x00740000 +0x00000000|0x00900000 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize FV = FVMAIN_COMPACT # # NV Variables -# Offset: 0x00740000 -# Size: 0x00080000 +# Offset: 0x00900000 +# Size: 0x00100000 # -0x00740000|0x00030000 +0x00900000|0x00070000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize DATA = { ## This is the EFI_FIRMWARE_VOLUME_HEADER @@ -76,9 +76,9 @@ DATA = { # Signature "_FVH" # Attributes 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision - 0x48, 0x00, 0x2A, 0x09, 0x00, 0x00, 0x00, 0x02, - # Blockmap[0]: 0x8 Blocks * 0x10000 Bytes / Block - 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + 0x48, 0x00, 0x2D, 0x09, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x7 Blocks * 0x10000 Bytes / Block + 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, # Blockmap[1]: End 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ## This is the VARIABLE_STORE_HEADER @@ -88,15 +88,15 @@ DATA = { # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, - # Size: 0x30000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - - # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x2FFB8 + # Size: 0xB0000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xAFFB8 # This can speed up the Variable Dispatch a bit. - 0xB8, 0xFF, 0x02, 0x00, + 0xB8, 0xFF, 0x06, 0x00, # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } -0x00770000|0x00010000 +0x00970000|0x00020000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize DATA = { # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = @@ -106,10 +106,10 @@ DATA = { # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF, # WriteQueueSize: UINT64 Size: 0x10000 - 0x20 (FTW_WORKING_HEADER) = 0xFFE0 - 0xE0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + 0xE0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 } -0x00780000|0x00040000 +0x00990000|0x00070000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ################################################################################ diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.c index f96958bfc20..2a733c6193e 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.c @@ -111,6 +111,7 @@ FlashPeiEntryPoint ( UINT32 FWNvRamSize; UINTN NvRamAddress; UINT32 NvRamSize; + UINT32 UuidOffset; BOOLEAN ClearUserConfig; CopyMem ((VOID *)BuildUuid, PcdGetPtr (PcdPlatformConfigUuid), sizeof (BuildUuid)); @@ -134,35 +135,31 @@ FlashPeiEntryPoint ( return Status; } - if (FWNvRamSize < (NvRamSize * 2 + sizeof (BuildUuid))) { - // - // NVRAM size provided by FW is not enough - // - return EFI_INVALID_PARAMETER; - } - // - // We stored BUILD UUID build at the offset NVRAM_SIZE * 2 + // We stored BUILD UUID build just after the NVRAM // + UuidOffset = FWNvRamStartOffset + NvRamSize; Status = FlashReadCommand ( - FWNvRamStartOffset + NvRamSize * 2, + UuidOffset, (UINT8 *)StoredUuid, sizeof (StoredUuid) ); if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to read UUID from flash: %r\n", __func__, Status)); return Status; } ClearUserConfig = IsIpmiClearCmosSet (); if (CompareMem ((VOID *)StoredUuid, (VOID *)BuildUuid, sizeof (BuildUuid)) != 0) { - DEBUG ((DEBUG_INFO, "BUILD UUID Changed, Update Storage with NVRAM FV\n")); + DEBUG ((DEBUG_INFO, "BUILD UUID changed: resetting NVRAM region.\n")); ClearUserConfig = TRUE; } if (ClearUserConfig) { - Status = FlashEraseCommand (FWNvRamStartOffset, NvRamSize * 2 + sizeof (BuildUuid)); + Status = FlashEraseCommand (FWNvRamStartOffset, NvRamSize); if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to erase NVRAM area: %r\n", __func__, Status)); return Status; } @@ -172,23 +169,26 @@ FlashPeiEntryPoint ( NvRamSize ); if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to write NVRAM area: %r\n", __func__, Status)); return Status; } // // Write new BUILD UUID to the Flash // - Status = FlashEraseCommand (FWNvRamStartOffset + (NvRamSize * 2), sizeof (BuildUuid)); + Status = FlashEraseCommand (UuidOffset, sizeof (BuildUuid)); if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to erase UUID area: %r\n", __func__, Status)); return Status; } Status = FlashWriteCommand ( - FWNvRamStartOffset + NvRamSize * 2, + UuidOffset, (UINT8 *)BuildUuid, sizeof (BuildUuid) ); if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to write UUID: %r\n", __func__, Status)); return Status; } @@ -200,7 +200,7 @@ FlashPeiEntryPoint ( ResetCold (); } } else { - DEBUG ((DEBUG_INFO, "Identical UUID, copy stored NVRAM to RAM\n")); + DEBUG ((DEBUG_INFO, "Identical UUID: copying stored NVRAM to RAM\n")); Status = FlashReadCommand ( FWNvRamStartOffset, @@ -208,6 +208,7 @@ FlashPeiEntryPoint ( NvRamSize ); if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to read NVRAM from flash: %r\n", __func__, Status)); return Status; } } From 3abeb17a16dec5a94a16523b1706a283077054ee Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:47:27 -0700 Subject: [PATCH 14/35] Platform/ADLINK: Minor cleanups of ComHpcAltBoardSetting.cfg - Improve comments in the file header. - Change NV_SI_RO_BOARD_S0_DIMM_AVAIL to 0xffff since the code which reads DIMM information shouldn't get a different array based on the platform. - Remove the notes of where changes from the default were made. - Add missing fields at the bottom. Signed-off-by: Rebecca Cran --- .../ComHpcAltPkg/ComHpcAltBoardSetting.cfg | 53 +++++++------------ 1 file changed, 18 insertions(+), 35 deletions(-) diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAltBoardSetting.cfg b/Platform/ADLINK/ComHpcAltPkg/ComHpcAltBoardSetting.cfg index 676beaf7eb5..bb061cccc69 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAltBoardSetting.cfg +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAltBoardSetting.cfg @@ -1,27 +1,30 @@ +## +# @file # COM-HPC-ALT board setting # -# Settings between #(, #) are provided by EE team, -# DO NOT change without consault EE while upgrade to -# Ampere Altra reference design. +# BOARD_VENDOR 0x5F13 (24339) refers to "ADLINK TECHNOLOGY INC." in +# https://www.iana.org/assignments/enterprise-numbers/enterprise-numbers # -# BOARD_VENDOR 0x5F13()=24339) is refer to "ADLINK TECHNOLOGY INC." of https://www.iana.org/assignments/enterprise-numbers/enterprise-numbers # BOARD_TYPE is COM=1 # BOARD_REV=1 will go with HW. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + # # Name, offset (hex), value # value can be hex or decimal # -#( NV_SI_RO_BOARD_VENDOR, 0x0000, 0x00005F13 NV_SI_RO_BOARD_TYPE, 0x0008, 0x00000001 NV_SI_RO_BOARD_REV, 0x0010, 0x00000001 NV_SI_RO_BOARD_CFG, 0x0018, 0x00000000 -NV_SI_RO_BOARD_S0_DIMM_AVAIL, 0x0020, 0x00001515 +NV_SI_RO_BOARD_S0_DIMM_AVAIL, 0x0020, 0x0000ffff NV_SI_RO_BOARD_S1_DIMM_AVAIL, 0x0028, 0x00000000 NV_SI_RO_BOARD_SPI0CS0_FREQ_KHZ, 0x0030, 0x00004E20 NV_SI_RO_BOARD_SPI0CS1_FREQ_KHZ, 0x0038, 0x00004E20 -#) NV_SI_RO_BOARD_SPI1CS0_FREQ_KHZ, 0x0040, 0x00002710 NV_SI_RO_BOARD_SPI1CS1_FREQ_KHZ, 0x0048, 0x00002710 NV_SI_RO_BOARD_TPM_LOC, 0x0050, 0x00000000 @@ -30,24 +33,17 @@ NV_SI_RO_BOARD_I2C1_FREQ_KHZ, 0x0060, 0x00000190 NV_SI_RO_BOARD_I2C2_10_FREQ_KHZ, 0x0068, 0x00000190 NV_SI_RO_BOARD_I2C3_FREQ_KHZ, 0x0070, 0x00000190 NV_SI_RO_BOARD_I2C9_FREQ_KHZ, 0x0078, 0x00000190 -#( NV_SI_RO_BOARD_2P_CFG, 0x0080, 0xFFFFFF00 NV_SI_RO_BOARD_S0_RCA0_CFG, 0x0088, 0x00000004 NV_SI_RO_BOARD_S0_RCA1_CFG, 0x0090, 0x00000004 NV_SI_RO_BOARD_S0_RCA2_CFG, 0x0098, 0x00000000 -#) NV_SI_RO_BOARD_S0_RCA3_CFG, 0x00A0, 0x00000004 -#( -#x8 BCM575 = 0x00000003 +# x8 BCM575 = 0x00000003 NV_SI_RO_BOARD_S0_RCB0_LO_CFG, 0x00A8, 0x00000003 NV_SI_RO_BOARD_S0_RCB0_HI_CFG, 0x00B0, 0x00000003 -#) -#( NV_SI_RO_BOARD_S0_RCB1_LO_CFG, 0x00B8, 0x00000000 NV_SI_RO_BOARD_S0_RCB1_HI_CFG, 0x00C0, 0x00000000 -#) -#( -#x1:USB3 x1:VGA = 0x00020002 +# x1:USB3 x1:VGA = 0x00020002 NV_SI_RO_BOARD_S0_RCB2_LO_CFG, 0x00C8, 0x00020002 # x0:NULL x1:i210 = 0x00000002 NV_SI_RO_BOARD_S0_RCB2_HI_CFG, 0x00D0, 0x00000002 @@ -55,10 +51,8 @@ NV_SI_RO_BOARD_S0_RCB2_HI_CFG, 0x00D0, 0x00000002 NV_SI_RO_BOARD_S0_RCB3_LO_CFG, 0x00D8, 0x00020002 # x4:M2.1 x4:M2.2 = 0x00020002 NV_SI_RO_BOARD_S0_RCB3_HI_CFG, 0x00E0, 0x00020002 -#) NV_SI_RO_BOARD_S1_RCA0_CFG, 0x00E8, 0x00000000 NV_SI_RO_BOARD_S1_RCA1_CFG, 0x00F0, 0x00000000 -#( NV_SI_RO_BOARD_S1_RCA2_CFG, 0x00F8, 0x00000000 NV_SI_RO_BOARD_S1_RCA3_CFG, 0x0100, 0x00000000 NV_SI_RO_BOARD_S1_RCB0_LO_CFG, 0x0108, 0x00000000 @@ -69,7 +63,6 @@ NV_SI_RO_BOARD_S1_RCB2_LO_CFG, 0x0128, 0x00000000 NV_SI_RO_BOARD_S1_RCB2_HI_CFG, 0x0130, 0x00000000 NV_SI_RO_BOARD_S1_RCB3_LO_CFG, 0x0138, 0x00000000 NV_SI_RO_BOARD_S1_RCB3_HI_CFG, 0x0140, 0x00000000 -#) NV_SI_RO_BOARD_T_LTLM_DELTA_P0, 0x0148, 0x00000001 NV_SI_RO_BOARD_T_LTLM_DELTA_P1, 0x0150, 0x00000002 NV_SI_RO_BOARD_T_LTLM_DELTA_P2, 0x0158, 0x00000003 @@ -86,17 +79,11 @@ NV_SI_RO_BOARD_P_LM_EXP_SMOOTH_CONST, 0x01A8, 0x00000000 NV_SI_RO_BOARD_TPM_ALG_ID, 0x01B0, 0x00000002 NV_SI_RO_BOARD_DDR_SPEED_GRADE, 0x01B8, 0x00000C80 NV_SI_RO_BOARD_DDR_S0_RTT_WR, 0x01C0, 0x20020000 -#( NV_SI_RO_BOARD_DDR_S1_RTT_WR, 0x01C8, 0x00000000 -#) NV_SI_RO_BOARD_DDR_S0_RTT_NOM, 0x01D0, 0x31060177 -#( NV_SI_RO_BOARD_DDR_S1_RTT_NOM, 0x01D8, 0x00000000 -#) NV_SI_RO_BOARD_DDR_S0_RTT_PARK, 0x01E0, 0x30060070 -#( NV_SI_RO_BOARD_DDR_S1_RTT_PARK, 0x01E8, 0x00000000 -#) NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_1DPC, 0x01F0, 0x00000000 NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_1DPC, 0x01F8, 0x00000000 NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_1DPC, 0x0200, 0x00000000 @@ -135,22 +122,16 @@ NV_SI_RO_BOARD_DDR_PHY_VREF_ADJ, 0x0300, 0x00000000 NV_SI_RO_BOARD_DDR_DRAM_VREF_ADJ, 0x0308, 0x00000000 NV_SI_RO_BOARD_DDR_WR_PREAMBLE_CYCLE, 0x0310, 0x02010201 NV_SI_RO_BOARD_DDR_ADCMD_2T_MODE, 0x0318, 0x00000000 -#( NV_SI_RO_BOARD_I2C_VRD_CONFIG_INFO, 0x0320, 0x6A685860 -#) NV_SI_RO_BOARD_DDR_PHY_FEATURE_CTRL, 0x0328, 0x00000000 NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_ACCESS, 0x0330, 0x01050106 NV_SI_RO_BOARD_DIMM_TEMP_THRESHOLD, 0x0338, 0x000005F4 NV_SI_RO_BOARD_DIMM_SPD_COMPARE_DISABLE, 0x0340, 0x00000000 NV_SI_RO_BOARD_S0_PCIE_CLK_CFG, 0x0348, 0x00000000 -#( NV_SI_RO_BOARD_S0_RCA4_CFG, 0x0350, 0x00030003 NV_SI_RO_BOARD_S0_RCA5_CFG, 0x0358, 0x00000000 -#) NV_SI_RO_BOARD_S0_RCA6_CFG, 0x0360, 0x02020202 -#( NV_SI_RO_BOARD_S0_RCA7_CFG, 0x0368, 0x02020202 -#) NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET, 0x0370, 0x00000000 NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET, 0x0378, 0x00000000 NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET, 0x0380, 0x00000000 @@ -184,12 +165,10 @@ NV_SI_RO_BOARD_S0_RCA5_TXRX_G4PRESET, 0x0458, 0x57575757 NV_SI_RO_BOARD_S0_RCA6_TXRX_G4PRESET, 0x0460, 0x57575757 NV_SI_RO_BOARD_S0_RCA7_TXRX_G4PRESET, 0x0468, 0x57575757 NV_SI_RO_BOARD_S1_PCIE_CLK_CFG, 0x0470, 0x00000000 -#( NV_SI_RO_BOARD_S1_RCA4_CFG, 0x0478, 0x00000000 NV_SI_RO_BOARD_S1_RCA5_CFG, 0x0480, 0x00000000 NV_SI_RO_BOARD_S1_RCA6_CFG, 0x0488, 0x00000000 NV_SI_RO_BOARD_S1_RCA7_CFG, 0x0490, 0x00000000 -#) NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET, 0x0498, 0x00000000 NV_SI_RO_BOARD_S1_RCA3_TXRX_G3PRESET, 0x04A0, 0x00000000 NV_SI_RO_BOARD_S1_RCB0A_TXRX_G3PRESET, 0x04A8, 0x00000000 @@ -243,9 +222,7 @@ NV_SI_RO_BOARD_TPM_DISABLE, 0x0620, 0x00000000 NV_SI_RO_BOARD_MESH_S0_CXG_RC_STRONG_ORDERING_EN, 0x0628, 0x00000000 NV_SI_RO_BOARD_MESH_S1_CXG_RC_STRONG_ORDERING_EN, 0x0630, 0x00000000 NV_SI_RO_BOARD_GPIO_SW_WATCHDOG_EN, 0x0638, 0x00000000 -#( NV_SI_RO_BOARD_PCIE_HP_DISABLE, 0x0640, 0x00000001 -#) NV_SI_RO_BOARD_I2C_VRD_VOUT_FORMAT, 0x0648, 0x00000000 NV_SI_RO_BOARD_I2C_VRD_SMBUS_CMD_FLAGS, 0x0650, 0x00000000 NV_SI_RO_BOARD_CUST_SPM_LOCATION, 0x0658, 0x00000000 @@ -295,3 +272,9 @@ NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_TO1, 0x7B0, 0x00000000 NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_TO2, 0x7B8, 0x00000000 NV_SI_RO_BOARD_PCIE_AER_CE_THRESHOLD, 0x7C0, 0x00000001 NV_SI_RO_BOARD_PCIE_AER_CE_INTERVAL, 0x7C8, 0x00000000 +NV_SI_RO_BOARD_I2C_RCA_VRD_VOUT_FORMAT,0x7D0, 0x00000000 +NV_SI_RO_BOARD_CCIX_MODE_OVERWRITE, 0x7D8, 0x00000000 +NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_MARGIN_MV, 0x07E0, 0x00000000 +NV_SI_RO_BOARD_2P_DPLL, 0x7E8, 0x00000000 +NV_SI_RO_BOARD_RC_DOMAIN_CTRL, 0x7F0, 0x00000000 +NV_SI_RO_BOARD_PCIE_SRIS_MODE, 0x7F8, 0x00000000 From 07a417d741ad58a5097bd5e1d77b2b909b2b3b1b Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:47:30 -0700 Subject: [PATCH 15/35] Silicon/Ampere: Don't use yoda conditions Update PlatformFlashAccessLib.c to avoid use of yoda conditions. Signed-off-by: Rebecca Cran --- .../Library/PlatformFlashAccessLib/PlatformFlashAccessLib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PlatformFlashAccessLib/PlatformFlashAccessLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/PlatformFlashAccessLib/PlatformFlashAccessLib.c index d279637be37..8e9ba695238 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/PlatformFlashAccessLib/PlatformFlashAccessLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/PlatformFlashAccessLib/PlatformFlashAccessLib.c @@ -177,7 +177,7 @@ MmFlashUpdate ( // Return data in the first double word of payload MmFwuStatus = (EFI_MM_COMMUNICATE_FWU_RES *)mEfiMmSysFwuReq.PayLoad.Data; if (MmFwuStatus->Status == FWU_MM_RES_IN_PROGRESS) { - if (NULL != Progress) { + if (Progress != NULL) { Progress (ProgressUpdate); } From 4c2805357e2933b084356a0ab0ca3382ccafe209 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:47:32 -0700 Subject: [PATCH 16/35] Platform/ADLINK: Improve MmcLib I2C brd config Improve the error checking code when fetching the I2C board config info. Change the DEBUG print on success from DEBUG_ERROR to DEBUG_INFO and on error print a message and return A2. Signed-off-by: Rebecca Cran --- Platform/ADLINK/ComHpcAltPkg/Library/MmcLib/MmcLib.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Platform/ADLINK/ComHpcAltPkg/Library/MmcLib/MmcLib.c b/Platform/ADLINK/ComHpcAltPkg/Library/MmcLib/MmcLib.c index 8e0694c61c0..ad944ed4d68 100644 --- a/Platform/ADLINK/ComHpcAltPkg/Library/MmcLib/MmcLib.c +++ b/Platform/ADLINK/ComHpcAltPkg/Library/MmcLib/MmcLib.c @@ -74,7 +74,10 @@ GetFirmwareMajorVersion ( Status = NVParamGet (NV_SI_RO_BOARD_I2C_VRD_CONFIG_INFO, ACLRd, &Val); if (!EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, " I2C brd config info 0x%X (%d)\n", Val, Val)); + DEBUG ((DEBUG_INFO, " I2C brd config info %r 0x%X (%d)\n", Status, Val, Val)); + } else { + DEBUG ((DEBUG_ERROR, "Failed to fetch I2C board config info. Defaulting to A2\n")); + return 0xA2; } if (Val == 0x6A685860) { From dc90d931d116f6639ad289097e9a2307e09dabd9 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:47:35 -0700 Subject: [PATCH 17/35] Platform/ADLINK: Enable building with or without X86 emulator To provide flexibility, allow users to build with or without the X86 emulator. Signed-off-by: Rebecca Cran --- Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc | 2 ++ Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf | 2 ++ 2 files changed, 4 insertions(+) diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc index e089b693d1b..4c1ad4352f7 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc @@ -441,4 +441,6 @@ # # OpRom emulator # +!if $(X86_EMULATOR_ENABLE) == TRUE Emulator/X86EmulatorDxe/X86EmulatorDxe.inf +!endif diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf index 561c3f0f152..5a771c4fd14 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf @@ -445,7 +445,9 @@ APRIORI DXE { # # Emulator for x64 OpRoms, etc. # +!if $(X86_EMULATOR_ENABLE) == TRUE INF Emulator/X86EmulatorDxe/X86EmulatorDxe.inf +!endif # # set MMC power off type From 46c06e3e60ed84f81e2aefe7ab17c18f07b5e26a Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:47:37 -0700 Subject: [PATCH 18/35] Silicon/Ampere: Add LogoDxe to display logo during boot The LogoDxe allows OEMs to display their logo while waiting for the user to press a key to interrupt the boot. Add it to AmpereAltraPkg.dsc.inc and ComHpcAlt.fdf. Signed-off-by: Rebecca Cran --- Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf | 2 ++ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 1 + 2 files changed, 3 insertions(+) diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf index 5a771c4fd14..256f555e95e 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf @@ -442,6 +442,8 @@ APRIORI DXE { INF Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.inf INF Silicon/Ampere/AmpereSiliconPkg/Drivers/BmcConfigDxe/BmcConfigDxe.inf + INF MdeModulePkg/Logo/LogoDxe.inf + # # Emulator for x64 OpRoms, etc. # diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc index 65f265d4925..8e9b8cde854 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -626,6 +626,7 @@ } MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressDxe/BootProgressDxe.inf + MdeModulePkg/Logo/LogoDxe.inf MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf # From 42686f026825e5103f625697687fbd896ebae21f Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:47:39 -0700 Subject: [PATCH 19/35] Silicon/Ampere: Add RemoveStaleFvFileOptions from OVMF Add RemoveStaleFvFileOptions from OVMF to PlatformBootManagerDxe. This removes stale boot options such as the UEFI Shell if the firmware has been built without it. Signed-off-by: Rebecca Cran --- .../PlatformBootManagerDxe.c | 150 ++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/Silicon/Ampere/AmpereSiliconPkg/Drivers/PlatformBootManagerDxe/PlatformBootManagerDxe.c b/Silicon/Ampere/AmpereSiliconPkg/Drivers/PlatformBootManagerDxe/PlatformBootManagerDxe.c index 01abd52b0e9..cf2a393b48e 100644 --- a/Silicon/Ampere/AmpereSiliconPkg/Drivers/PlatformBootManagerDxe/PlatformBootManagerDxe.c +++ b/Silicon/Ampere/AmpereSiliconPkg/Drivers/PlatformBootManagerDxe/PlatformBootManagerDxe.c @@ -20,6 +20,7 @@ #include #include +#include #include #include #include @@ -79,6 +80,153 @@ CONST UINT16 UsbEnglishLang = 0x0409; extern EFI_GUID mBmAutoCreateBootOptionGuid; +/** + Remove all MemoryMapped(...)/FvFile(...) and Fv(...)/FvFile(...) boot options + whose device paths do not resolve exactly to an FvFile in the system. + + This removes any boot options that point to binaries built into the firmware + and have become stale due to any of the following: + - FvMain's base address or size changed (historical), + - FvMain's FvNameGuid changed, + - the FILE_GUID of the pointed-to binary changed, + - the referenced binary is no longer built into the firmware. + + EfiBootManagerFindLoadOption() used in PlatformRegisterFvBootOption() only + avoids exact duplicates. + + Copied from OvmfPkg/Library/PlatformBootManagerLibLight/PlatformBm.c +**/ +static +VOID +RemoveStaleFvFileOptions ( + VOID + ) +{ + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + UINTN BootOptionCount; + UINTN Index; + + BootOptions = EfiBootManagerGetLoadOptions ( + &BootOptionCount, + LoadOptionTypeBoot + ); + + for (Index = 0; Index < BootOptionCount; ++Index) { + EFI_DEVICE_PATH_PROTOCOL *Node1, *Node2, *SearchNode; + EFI_STATUS Status; + EFI_HANDLE FvHandle; + + // + // If the device path starts with neither MemoryMapped(...) nor Fv(...), + // then keep the boot option. + // + Node1 = BootOptions[Index].FilePath; + if (!((DevicePathType (Node1) == HARDWARE_DEVICE_PATH) && + (DevicePathSubType (Node1) == HW_MEMMAP_DP)) && + !((DevicePathType (Node1) == MEDIA_DEVICE_PATH) && + (DevicePathSubType (Node1) == MEDIA_PIWG_FW_VOL_DP))) + { + continue; + } + + // + // If the second device path node is not FvFile(...), then keep the boot + // option. + // + Node2 = NextDevicePathNode (Node1); + if ((DevicePathType (Node2) != MEDIA_DEVICE_PATH) || + (DevicePathSubType (Node2) != MEDIA_PIWG_FW_FILE_DP)) + { + continue; + } + + // + // Locate the Firmware Volume2 protocol instance that is denoted by the + // boot option. If this lookup fails (i.e., the boot option references a + // firmware volume that doesn't exist), then we'll proceed to delete the + // boot option. + // + SearchNode = Node1; + Status = gBS->LocateDevicePath ( + &gEfiFirmwareVolume2ProtocolGuid, + &SearchNode, + &FvHandle + ); + + if (!EFI_ERROR (Status)) { + // + // The firmware volume was found; now let's see if it contains the FvFile + // identified by GUID. + // + EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvFileNode; + UINTN BufferSize; + EFI_FV_FILETYPE FoundType; + EFI_FV_FILE_ATTRIBUTES FileAttributes; + UINT32 AuthenticationStatus; + + Status = gBS->HandleProtocol ( + FvHandle, + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **)&FvProtocol + ); + ASSERT_EFI_ERROR (Status); + + FvFileNode = (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *)Node2; + // + // Buffer==NULL means we request metadata only: BufferSize, FoundType, + // FileAttributes. + // + Status = FvProtocol->ReadFile ( + FvProtocol, + &FvFileNode->FvFileName, // NameGuid + NULL, // Buffer + &BufferSize, + &FoundType, + &FileAttributes, + &AuthenticationStatus + ); + if (!EFI_ERROR (Status)) { + // + // The FvFile was found. Keep the boot option. + // + continue; + } + } + + // + // Delete the boot option. + // + Status = EfiBootManagerDeleteLoadOptionVariable ( + BootOptions[Index].OptionNumber, + LoadOptionTypeBoot + ); + DEBUG_CODE_BEGIN (); + CHAR16 *DevicePathString; + + DevicePathString = ConvertDevicePathToText ( + BootOptions[Index].FilePath, + FALSE, + FALSE + ); + DEBUG (( + EFI_ERROR (Status) ? DEBUG_WARN : DEBUG_VERBOSE, + "%a: removing stale Boot#%04x %s: %r\n", + __func__, + (UINT32)BootOptions[Index].OptionNumber, + DevicePathString == NULL ? L"" : DevicePathString, + Status + )); + if (DevicePathString != NULL) { + FreePool (DevicePathString); + } + + DEBUG_CODE_END (); + } + + EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount); +} + /** Append a Boot Option to a Boot Options list. If the description and the device path are null, this function will copy data from @@ -894,6 +1042,8 @@ RefreshAllBootOptions ( BootOptionTemp[Index].OptionalDataSize = sizeof (EFI_GUID); } + RemoveStaleFvFileOptions (); + return Status; } From 064149f9505fd2199b0938cc4290ba6569b4bb65 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:47:41 -0700 Subject: [PATCH 20/35] Silicon/Ampere: Add checks around PerformanceLib Add checks around adding non-NULL PerformanceLib instances, only adding them if PERFORMANCE_MEASUREMENT_ENABLE is TRUE. Signed-off-by: Rebecca Cran --- .../AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc | 14 ++++++++++++++ .../Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 14 ++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc index 016bf652b30..288811bbb07 100755 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc @@ -126,7 +126,9 @@ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf +!endif ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf [LibraryClasses.common.PEI_CORE] @@ -134,7 +136,9 @@ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf +!endif ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf @@ -149,7 +153,9 @@ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf +!endif ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf @@ -172,23 +178,31 @@ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf +!endif [LibraryClasses.common.DXE_DRIVER] DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf +!endif MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf [LibraryClasses.common.UEFI_APPLICATION] UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiTianoCustomDecompressLib.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf +!endif MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf [LibraryClasses.common.UEFI_DRIVER] ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf +!endif DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc index 8e9b8cde854..72fc200d0e4 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -203,14 +203,18 @@ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf +!endif [LibraryClasses.common.PEI_CORE] HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf +!endif ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf @@ -225,7 +229,9 @@ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf +!endif ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf @@ -252,26 +258,34 @@ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf +!endif [LibraryClasses.common.DXE_DRIVER] DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf +!endif MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf PciHostBridgeLib|Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf PciSegmentLib|Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLibPci.inf [LibraryClasses.common.UEFI_APPLICATION] UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiTianoCustomDecompressLib.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf +!endif MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf [LibraryClasses.common.UEFI_DRIVER] ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf +!endif DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf From 9c2af497a17edb23d590811fd11614907267bd1c Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:47:43 -0700 Subject: [PATCH 21/35] Silicon/Ampere: Add extra 3MB for FPDT boot records Since we set PcdPerformanceLibraryPropertyMask to 1, extra memory is needed to hold the FPDT boot records. Through testing, increase it from the default of 192KB to 3MB. Signed-off-by: Rebecca Cran --- Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc index 72fc200d0e4..94adb1b63e9 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -354,6 +354,10 @@ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + # With PcdPerformanceLibraryPropertyMask set to 1, we need to + # increase the memory allocated for the FPDT boot records. + gEfiMdeModulePkgTokenSpaceGuid.PcdExtFpdtBootRecordPadSize|0x300000 + # DEBUG_ASSERT_ENABLED 0x01 # DEBUG_PRINT_ENABLED 0x02 # DEBUG_CODE_ENABLED 0x04 From dce0531a4fd76d92313018c9f5b3e91e524b89c0 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:47:54 -0700 Subject: [PATCH 22/35] Platform/ADLINK: Add BGRT driver Add the BGRT driver to ComHpcAlt.fdf to allow the OS to display the OEM logo while booting. Signed-off-by: Rebecca Cran --- Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf | 1 + 1 file changed, 1 insertion(+) diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf index 256f555e95e..19b173f59b8 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf @@ -409,6 +409,7 @@ APRIORI DXE { # INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf INF Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf INF RuleOverride=ACPITABLE Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf INF RuleOverride=ACPITABLE Platform/ADLINK/ComHpcAltPkg/Ac01AcpiTables/Ac01AcpiTables.inf INF RuleOverride=ACPITABLE Platform/ADLINK/ComHpcAltPkg/Ac02AcpiTables/Ac02AcpiTables.inf From de7fcaab856465c4cc541ea6e03c8f3c2d33eab3 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:47:56 -0700 Subject: [PATCH 23/35] Platform/ADLINK: Move FirmwarePerformancePei earlier Move the FirmwarePerformancePei driver earlier in the boot process. Signed-off-by: Rebecca Cran --- Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf index 19b173f59b8..f8012f8b9f5 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf @@ -166,13 +166,13 @@ APRIORI PEI { INF ArmPlatformPkg/Sec/Sec.inf INF MdeModulePkg/Core/Pei/PeiMain.inf INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf +!endif INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf INF Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf INF Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.inf -!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE - INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf -!endif INF Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressPeim/BootProgressPeim.inf INF ArmPkg/Drivers/CpuPei/CpuPei.inf INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf From ababe4ed1494e456423a37ab252b4b6d7c1dbe01 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:47:58 -0700 Subject: [PATCH 24/35] Platform/ADLINK: Add SecureBoot keys Include the file which sets the Secure Boot keys. Signed-off-by: Rebecca Cran --- Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf index f8012f8b9f5..a0f3be3beac 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf @@ -253,6 +253,8 @@ APRIORI DXE { !if $(SECURE_BOOT_ENABLE) == TRUE INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf + + !include ArmPlatformPkg/SecureBootDefaultKeys.fdf.inc !endif INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf From 5e964f4ac8676814331c4d76e280dec0024c06ae Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:48:00 -0700 Subject: [PATCH 25/35] Platform/ADLINK: Add boot manager drivers Add boot manager drivers which were missing. Signed-off-by: Rebecca Cran --- Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf index a0f3be3beac..c1749e7cfd1 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.fdf @@ -398,6 +398,9 @@ APRIORI DXE { INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf INF MdeModulePkg/Application/UiApp/UiApp.inf + INF MdeModulePkg/Universal/BootManagerPolicyDxe/BootManagerPolicyDxe.inf + INF Silicon/Ampere/AmpereSiliconPkg/Drivers/PlatformBootManagerDxe/PlatformBootManagerDxe.inf + INF Silicon/Ampere/AmpereSiliconPkg/Drivers/IpmiBootDxe/IpmiBootDxe.inf # # Networking stack From f90ffd537508300f00ef49cadb78cf87b5eec730 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:48:02 -0700 Subject: [PATCH 26/35] Platform/ADLINK: configure video resolution to max Override the video configuration PCDs to use the maximum available resolution. Copied from Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc Signed-off-by: Rebecca Cran --- Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc index 4c1ad4352f7..82485e277b6 100644 --- a/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc +++ b/Platform/ADLINK/ComHpcAltPkg/ComHpcAlt.dsc @@ -289,6 +289,17 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{GUID("cdcdd0b7-8afb-4883-853a-ae9398077a0e")}|VOID*|0x10 gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{GUID("074c21e5-7d17-48e9-808d-f0c85e52a7db")}|VOID*|0x10 + # Default Video Resolution + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0 # 0 - Maximum + # Setup Video Resolution + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|0 # 0 - Maximum + [PcdsPatchableInModule] # # Console Resolution (HD mode) From 99e10f518378e3c455fa18e1e31f36570f5f061c Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 11:48:05 -0700 Subject: [PATCH 27/35] Platform/Ampere: Add SecureBoot tools Add a script to generate Secure Boot keys and certificates. Also, add a default openssl.cnf file which will be copied to the secureboot_objects directory where users can customize it. Signed-off-by: Rebecca Cran --- .../Ampere/Tools/GenerateSecureBootKeys.sh | 120 ++++++++++++++++ Platform/Ampere/Tools/openssl.cnf | 130 ++++++++++++++++++ 2 files changed, 250 insertions(+) create mode 100755 Platform/Ampere/Tools/GenerateSecureBootKeys.sh create mode 100644 Platform/Ampere/Tools/openssl.cnf diff --git a/Platform/Ampere/Tools/GenerateSecureBootKeys.sh b/Platform/Ampere/Tools/GenerateSecureBootKeys.sh new file mode 100755 index 00000000000..27013658447 --- /dev/null +++ b/Platform/Ampere/Tools/GenerateSecureBootKeys.sh @@ -0,0 +1,120 @@ +#!/usr/bin/env bash + +## +# @file +# Script to download and generate keys/certificates/information +# for Secure Boot. +# +# Copyright (c) 2024, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +set -o errexit + +cleanup () { + rm keys/dbx.priv >/dev/null 2>&1 || true + rm keys/intermediate.priv >/dev/null 2>&1 || true + rm keys/user.priv >/dev/null 2>&1 || true + rm certs/??.pem >/dev/null 2>&1 || true + rm certs/user.pfx >/dev/null 2>&1 || true + rm certs/root.crt >/dev/null 2>&1 || true + rm certs/intermediate.csr >/dev/null 2>&1 || true + rm certs/intermediate.crt >/dev/null 2>&1 || true + rm certs/user.csr >/dev/null 2>&1 || true + rm certs/user.crt >/dev/null 2>&1 || true + rm serial serial.* index.* >/dev/null 2>&1 || true +} + +if [ -z "${CERT_PASSWORD}" ]; then + CERT_PASSWORD=password +fi + +if [ -z "${SECUREBOOT_DIR}" ]; then + SECUREBOOT_DIR="${PWD}/secureboot_objects/" +fi + +if [ ! -d "${SECUREBOOT_DIR}" ]; then + mkdir "${SECUREBOOT_DIR}" +fi + +pushd "${SECUREBOOT_DIR}" || exit 1 + +if [ -z "${USE_EXISTING_SB_KEYS}" ]; then + mkdir keys || true + mkdir certs || true + cleanup + + if [ ! -f "openssl.cnf" ]; then + cp -vf "${WORKSPACE}/edk2-platforms/Platform/Ampere/Tools/openssl.cnf" . + fi + + echo "unique_subject = no" > index.txt.attr + openssl req -config openssl.cnf -new -x509 -newkey rsa:2048 -subj "/CN=${BOARD_NAME} Platform Key/" -keyout keys/platform_key.priv -outform DER -out certs/platform_key.der -days 7300 -nodes -sha256 + openssl x509 -inform DER -in certs/platform_key.der -outform PEM -out certs/platform_key.pem + openssl req -config openssl.cnf -new -x509 -newkey rsa:2048 -subj "/CN=${BOARD_NAME} Update Key/" -keyout keys/update_key.priv -outform DER -out certs/update_key.der -days 7300 -nodes -sha256 + openssl x509 -inform DER -in certs/update_key.der -outform PEM -out certs/update_key.pem + + # Root Certificate + openssl req -config openssl.cnf -batch -new -x509 -days 3650 -key keys/update_key.priv -out certs/root.crt + openssl x509 -in certs/root.crt -out certs/root.der -outform DER + openssl x509 -inform DER -in certs/root.der -outform PEM -out certs/root.pub.pem + + # Intermediate Certificate + openssl genrsa -aes256 -out keys/intermediate.priv -passout pass:"${CERT_PASSWORD}" 2048 + openssl req -config openssl.cnf -batch -new -key keys/intermediate.priv -out certs/intermediate.csr -passin pass:"${CERT_PASSWORD}" -passout pass:"${CERT_PASSWORD}" + + truncate -s0 index.txt + echo 01 > serial + + openssl ca -config openssl.cnf -batch -extensions v3_ca -in certs/intermediate.csr -days 3650 -out certs/intermediate.crt -cert certs/root.crt -keyfile keys/update_key.priv + openssl x509 -in certs/intermediate.crt -out certs/intermediate.der -outform DER + openssl x509 -inform DER -in certs/intermediate.der -outform PEM -out certs/intermediate.pub.pem + + # User Certificate + openssl genrsa -aes256 -out keys/user.priv -passout pass:"${CERT_PASSWORD}" 2048 + openssl req -config openssl.cnf -batch -new -key keys/user.priv -out certs/user.csr -passin pass:"${CERT_PASSWORD}" -passout pass:"${CERT_PASSWORD}" + openssl ca -config openssl.cnf -batch -in certs/user.csr -days 3650 -out certs/user.crt -cert certs/intermediate.crt -keyfile keys/intermediate.priv -passin pass:"${CERT_PASSWORD}" + openssl x509 -in certs/user.crt -out certs/user.der -outform DER + openssl x509 -inform DER -in certs/user.der -outform PEM -out certs/user.pub.pem + + openssl pkcs12 -export -out certs/user.pfx -inkey keys/user.priv -in certs/user.crt -passin pass:"${CERT_PASSWORD}" -passout pass:"${CERT_PASSWORD}" + openssl pkcs12 -in certs/user.pfx -nodes -out certs/user.pem -passin pass:"${CERT_PASSWORD}" +fi + +python3 ${WORKSPACE}/edk2/BaseTools/Scripts/BinToPcd.py -i certs/root.der -p gEfiSecurityPkgTokenSpaceGuid.PcdPkcs7CertBuffer -o ${WORKSPACE}/edk2-platforms/Platform/${MANUFACTURER}/${BOARD_NAME}Pkg/root.cer.gEfiSecurityPkgTokenSpaceGuid.PcdPkcs7CertBuffer.inc + +pushd certs +if [ ! -f "ms_kek1.der" ] || [ -n "${DOWNLOAD_MS_SB_KEYS}" ]; then + curl -L "https://go.microsoft.com/fwlink/?LinkId=321185" -o ms_kek1.der +fi +if [ ! -f "ms_kek2.der" ] || [ -n "${DOWNLOAD_MS_SB_KEYS}" ]; then + curl -L "https://go.microsoft.com/fwlink/?linkid=2239775" -o ms_kek2.der +fi +if [ ! -f "ms_db1.der" ] || [ -n "${DOWNLOAD_MS_SB_KEYS}" ]; then + curl -L "https://go.microsoft.com/fwlink/?linkid=321192" -o ms_db1.der +fi +if [ ! -f "ms_db2.der" ] || [ -n "${DOWNLOAD_MS_SB_KEYS}" ]; then + curl -L "https://go.microsoft.com/fwlink/?linkid=321194" -o ms_db2.der +fi +if [ ! -f "ms_db3.der" ] || [ -n "${DOWNLOAD_MS_SB_KEYS}" ]; then + curl -L "https://go.microsoft.com/fwlink/?linkid=2239776" -o ms_db3.der +fi +if [ ! -f "ms_db4.der" ] || [ -n "${DOWNLOAD_MS_SB_KEYS}" ]; then + curl -L "https://go.microsoft.com/fwlink/?linkid=2239872" -o ms_db4.der +fi +if [ ! -f "ms_db5.der" ] || [ -n "${DOWNLOAD_MS_SB_KEYS}" ]; then + curl -L "https://go.microsoft.com/fwlink/?linkid=2284009" -o ms_db5.der +fi +popd || exit 1 + +if [ ! -f "certs/dummy_dbx.der" ]; then + # Generate a random certificate to place in the DBX. Otherwise, Linux won't try and update + # the dbx variable when running `fwupgmgr`. + openssl req -config openssl.cnf -new -x509 -newkey rsa:2048 -subj "/CN=Dummy DBX/" -keyout keys/dbx.priv -outform DER -out certs/dummy_dbx.der -days 7300 -nodes -sha256 +fi + +cleanup + +popd || exit 1 diff --git a/Platform/Ampere/Tools/openssl.cnf b/Platform/Ampere/Tools/openssl.cnf new file mode 100644 index 00000000000..92e2a7aa810 --- /dev/null +++ b/Platform/Ampere/Tools/openssl.cnf @@ -0,0 +1,130 @@ +HOME = . +openssl_conf = openssl_init +config_diagnostics = 1 +oid_section = new_oids + +[ new_oids ] +tsa_policy1 = 1.2.3.4.1 +tsa_policy2 = 1.2.3.4.5.6 +tsa_policy3 = 1.2.3.4.5.7 + +[openssl_init] +providers = provider_sect +ssl_conf = ssl_module + +[ evp_properties ] +[provider_sect] +default = default_sect + +[default_sect] +activate = 1 + +[ ssl_module ] +system_default = crypto_policy + +[ crypto_policy ] +.include = /etc/crypto-policies/back-ends/opensslcnf.config + +[ ca ] +default_ca = CA_default # The default ca section + +[ CA_default ] + +dir = . # Where everything is kept +certs = $dir/certs # Where the issued certs are kept +crl_dir = $dir/crl # Where the issued crl are kept +database = $dir/index.txt # database index file. +unique_subject = no # Set to 'no' to allow creation of + # several certs with same subject. +new_certs_dir = $dir/certs # default place for new certs. + +certificate = $dir/cacert.pem # The CA certificate +serial = $dir/serial # The current serial number +crlnumber = $dir/crlnumber # the current crl number + # must be commented out to leave a V1 CRL +crl = $dir/crl.pem # The current CRL +private_key = $dir/private/cakey.pem # The private key + +x509_extensions = codesign_reqext # The extensions to add to the cert + +name_opt = ca_default # Subject Name options +cert_opt = ca_default # Certificate field options + +default_days = 365 # how long to certify for +default_crl_days= 30 # how long before next CRL +default_md = default # use public key default MD +preserve = no # keep passed DN ordering + +policy = policy_match + +[ policy_match ] +countryName = match +stateOrProvinceName = match +organizationName = match +organizationalUnitName = optional +commonName = supplied +emailAddress = optional + +[ policy_anything ] +countryName = optional +stateOrProvinceName = optional +localityName = optional +organizationName = optional +organizationalUnitName = optional +commonName = supplied +emailAddress = optional + +[ req ] +default_bits = 2048 +default_md = sha256 +utf8 = yes +string_mask = utf8only +default_keyfile = privkey.pem +distinguished_name = codesign_dn +x509_extensions = v3_ca # The extensions to add to the self signed cert +req_extensions = codesign_reqext +attributes = req_attributes + +# Passwords for private keys if not present they will be prompted for +input_password = secret +output_password = secret + +[ codesign_dn ] +countryName = Country Name (2 letter code) +countryName_default = US +countryName_min = 2 +countryName_max = 2 + +stateOrProvinceName = State or Province Name (full name) +stateOrProvinceName_default = California + +localityName = San Jose + +0.organizationName = Organization Name (eg, company) +0.organizationName_default = Example Corp + +organizationalUnitName = Organizational Unit Name (eg, section) + +commonName = Common Name (e.g. server FQDN or YOUR name) +commonName_default = example.com +commonName_max = 64 + +emailAddress = Email Address +emailAddress_max = 64 + +[ req_attributes ] +challengePassword = A challenge password +challengePassword_min = 4 +challengePassword_max = 20 + +unstructuredName = An optional company name + +[ codesign_reqext ] +keyUsage = critical,digitalSignature +extendedKeyUsage = critical,codeSigning +subjectKeyIdentifier = hash + +[ v3_ca ] +subjectKeyIdentifier=hash +authorityKeyIdentifier=keyid:always,issuer +basicConstraints = critical,CA:true From 52910ccd093477d93113b73efd72cb702810af75 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Mon, 16 Dec 2024 20:09:01 -0700 Subject: [PATCH 28/35] Silicon/Ampere: Use DxeRuntimeDebugLibSerialPort in RELEASE builds Use the DxeRuntimeDebugLibSerialPort driver in RELEASE builds to avoid a crash if a driver tries to output text at Runtime. Signed-off-by: Rebecca Cran --- Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 2 -- 1 file changed, 2 deletions(-) diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc index 94adb1b63e9..a80b63403bc 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -302,9 +302,7 @@ !if $(SECURE_BOOT_ENABLE) == TRUE BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf !endif -!if $(TARGET) != RELEASE DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf -!endif VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf From 0a32973e9af33bb7646ffb5f6c1d0c9f75c85899 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Tue, 11 Feb 2025 09:03:40 -0700 Subject: [PATCH 29/35] Platform/Ampere: Add macOS support to buildfw.sh buildfw.sh depends on features of the GNU getopt implementation such as long options. Require users to install the gnu-getopt homebrew package on macOS. Signed-off-by: Rebecca Cran --- Platform/Ampere/buildfw.sh | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Platform/Ampere/buildfw.sh b/Platform/Ampere/buildfw.sh index 96de8a67b34..0ba80d942e4 100755 --- a/Platform/Ampere/buildfw.sh +++ b/Platform/Ampere/buildfw.sh @@ -107,6 +107,13 @@ if [ "$(uname -o)" = "FreeBSD" ]; then mkdir bin || true ln -sfv /usr/local/bin/gmake bin/make export PATH=$PWD/bin:$PATH +elif [ "$(uname -o)" = "Darwin" ]; then + MAKE_COMMAND=gmake + GETOPT_COMMAND=/opt/homebrew/opt/gnu-getopt/bin/getopt + if ! command -v ${GETOPT_COMMAND} >/dev/null 2>&1; then + echo "GNU getopt is required. Please install the gnu-getopt homebrew package." + exit 1 + fi else MAKE_COMMAND=make GETOPT_COMMAND=getopt From 67bd322c5b19b14fac7c25e1e13fbcfc9a779f55 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Tue, 11 Feb 2025 09:03:57 -0700 Subject: [PATCH 30/35] Platform/ASRockRack: Add ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q platforms Signed-off-by: Rebecca Cran --- .../ASRockRack/Altra1L2QPkg/Altra1L2Q.dsc | 421 ++ .../ASRockRack/Altra1L2QPkg/Altra1L2Q.fdf | 520 ++ .../Altra1L2QPkg/Altra1L2QBoardSetting.cfg | 275 + .../Altra1L2QPkg/Altra1L2QCapsule.dsc | 31 + .../Altra1L2QPkg/Altra1L2QCapsule.fdf | 105 + .../Altra1L2QPkg/Altra1L2QLinuxBoot.dsc | 132 + .../Altra1L2QPkg/Altra1L2QLinuxBoot.fdf | 224 + .../SystemFirmwareDescriptor.aslc | 76 + .../SystemFirmwareDescriptor.inf | 39 + .../SystemFirmwareDescriptorPei.c | 73 + .../TfaUefiFirmwareUpdateConfig.ini | 21 + .../UefiFirmwareUpdateConfig.ini | 21 + Platform/ASRockRack/Altra1L2QPkg/Readme.md | 36 + .../Altra1L2QPkg/firmware.metainfo.xml | 47 + .../ASRockRack/Altra1L2TPkg/Altra1L2T.dsc | 421 ++ .../ASRockRack/Altra1L2TPkg/Altra1L2T.fdf | 520 ++ .../Altra1L2TPkg/Altra1L2TBoardSetting.cfg | 275 + .../Altra1L2TPkg/Altra1L2TCapsule.dsc | 31 + .../Altra1L2TPkg/Altra1L2TCapsule.fdf | 104 + .../Altra1L2TPkg/Altra1L2TLinuxBoot.dsc | 132 + .../Altra1L2TPkg/Altra1L2TLinuxBoot.fdf | 224 + .../SystemFirmwareDescriptor.aslc | 76 + .../SystemFirmwareDescriptor.inf | 39 + .../SystemFirmwareDescriptorPei.c | 73 + .../TfaUefiFirmwareUpdateConfig.ini | 21 + .../UefiFirmwareUpdateConfig.ini | 21 + Platform/ASRockRack/Altra1L2TPkg/Readme.md | 38 + .../Altra1L2TPkg/firmware.metainfo.xml | 47 + .../Ac01AcpiTables/Ac01AcpiTables.inf | 20 + .../AltraBoardPkg/Ac01AcpiTables/CPU-S0.asi | 6345 +++++++++++++++++ .../AltraBoardPkg/Ac01AcpiTables/CPU.asi | 151 + .../AltraBoardPkg/Ac01AcpiTables/Dsdt.asl | 950 +++ .../AltraBoardPkg/Ac01AcpiTables/PCI-PDRC.asi | 134 + .../AltraBoardPkg/Ac01AcpiTables/PCI-S0.asi | 2928 ++++++++ .../AltraBoardPkg/Ac01AcpiTables/PMU-S0.asi | 905 +++ .../AltraBoardPkg/Ac01AcpiTables/PMU.asi | 9 + .../Ac02AcpiTables/Ac02AcpiTables.inf | 20 + .../AltraBoardPkg/Ac02AcpiTables/CPU-S0.asi | 6345 +++++++++++++++++ .../AltraBoardPkg/Ac02AcpiTables/CPU.asi | 151 + .../Ac02AcpiTables/CommonDevices.asi | 923 +++ .../AltraBoardPkg/Ac02AcpiTables/Dsdt.asl | 37 + .../AltraBoardPkg/Ac02AcpiTables/PCI-PDRC.asi | 134 + .../AltraBoardPkg/Ac02AcpiTables/PCI-S0.asi | 2890 ++++++++ .../AltraBoardPkg/Ac02AcpiTables/PMU-S0.asi | 1292 ++++ .../AltraBoardPkg/Ac02AcpiTables/PMU.asi | 9 + .../Drivers/PciPlatformDxe/PciPlatformDxe.c | 258 + .../Drivers/PciPlatformDxe/PciPlatformDxe.inf | 41 + .../SmbiosPlatformDxe/SmbiosPlatformDxe.c | 486 ++ .../SmbiosPlatformDxe/SmbiosPlatformDxe.h | 201 + .../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 70 + .../SmbiosPlatformDxeDataTable.c | 96 + .../SmbiosPlatformDxeStrings.uni | 23 + .../Type07/PlatformCache.uni | 11 + .../Type07/PlatformCacheData.c | 53 + .../Type07/PlatformCacheFunction.c | 168 + .../Type08/PlatformPortConnector.uni | 30 + .../Type08/PlatformPortConnectorData.c | 237 + .../Type08/PlatformPortConnectorFunction.c | 57 + .../Type09/PlatformSystemSlot.uni | 21 + .../Type09/PlatformSystemSlotData.c | 292 + .../Type09/PlatformSystemSlotFunction.c | 313 + .../Type11/PlatformOemString.uni | 11 + .../Type11/PlatformOemStringData.c | 42 + .../Type11/PlatformOemStringFunction.c | 57 + .../Type12/PlatformJumperStringData.c | 42 + .../Type12/PlatformJumperStringFunction.c | 57 + .../Type12/PlatformJumperStrings.uni | 11 + .../Type12/PlatformOemString.uni | 11 + .../Type16/PlatformPhysicalMemoryArrayData.c | 48 + .../PlatformPhysicalMemoryArrayFunction.c | 41 + .../Type17/PlatformMemoryDevice.uni | 16 + .../Type17/PlatformMemoryDeviceData.c | 63 + .../Type17/PlatformMemoryDeviceFunction.c | 367 + .../PlatformMemoryArrayMappedAddressData.c | 47 + ...PlatformMemoryArrayMappedAddressFunction.c | 153 + .../Type38/PlatformIpmiDeviceData.c | 46 + .../Type38/PlatformIpmiDeviceFunction.c | 39 + .../Type41/PlatformOnboardDevicesExtended.uni | 13 + .../PlatformOnboardDevicesExtendedData.c | 104 + .../PlatformOnboardDevicesExtendedFunction.c | 57 + .../Library/BoardPcieLib/BoardPcieLib.c | 183 + .../Library/BoardPcieLib/BoardPcieLib.inf | 27 + .../Library/IOExpanderLib/IOExpanderLib.c | 402 ++ .../Library/IOExpanderLib/IOExpanderLib.inf | 28 + .../Library/ISL1208RealTimeClockLib/ISL1208.c | 313 + .../Library/ISL1208RealTimeClockLib/ISL1208.h | 91 + .../ISL1208RealTimeClockLib.c | 265 + .../ISL1208RealTimeClockLib.inf | 46 + .../Library/OemMiscLib/IpmiFruInfo.c | 523 ++ .../Library/OemMiscLib/IpmiFruInfo.h | 48 + .../Library/OemMiscLib/OemMiscLib.c | 821 +++ .../Library/OemMiscLib/OemMiscLib.inf | 49 + .../PlatformBmcReadyLib/PlatformBmcReadyLib.c | 26 + .../PlatformBmcReadyLib.inf | 18 + 94 files changed, 33708 insertions(+) create mode 100644 Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.dsc create mode 100644 Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.fdf create mode 100644 Platform/ASRockRack/Altra1L2QPkg/Altra1L2QBoardSetting.cfg create mode 100644 Platform/ASRockRack/Altra1L2QPkg/Altra1L2QCapsule.dsc create mode 100644 Platform/ASRockRack/Altra1L2QPkg/Altra1L2QCapsule.fdf create mode 100644 Platform/ASRockRack/Altra1L2QPkg/Altra1L2QLinuxBoot.dsc create mode 100644 Platform/ASRockRack/Altra1L2QPkg/Altra1L2QLinuxBoot.fdf create mode 100644 Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc create mode 100644 Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf create mode 100644 Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c create mode 100644 Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareUpdateConfig/TfaUefiFirmwareUpdateConfig.ini create mode 100644 Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareUpdateConfig/UefiFirmwareUpdateConfig.ini create mode 100644 Platform/ASRockRack/Altra1L2QPkg/Readme.md create mode 100644 Platform/ASRockRack/Altra1L2QPkg/firmware.metainfo.xml create mode 100644 Platform/ASRockRack/Altra1L2TPkg/Altra1L2T.dsc create mode 100644 Platform/ASRockRack/Altra1L2TPkg/Altra1L2T.fdf create mode 100644 Platform/ASRockRack/Altra1L2TPkg/Altra1L2TBoardSetting.cfg create mode 100644 Platform/ASRockRack/Altra1L2TPkg/Altra1L2TCapsule.dsc create mode 100644 Platform/ASRockRack/Altra1L2TPkg/Altra1L2TCapsule.fdf create mode 100644 Platform/ASRockRack/Altra1L2TPkg/Altra1L2TLinuxBoot.dsc create mode 100644 Platform/ASRockRack/Altra1L2TPkg/Altra1L2TLinuxBoot.fdf create mode 100644 Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc create mode 100644 Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf create mode 100644 Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c create mode 100644 Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareUpdateConfig/TfaUefiFirmwareUpdateConfig.ini create mode 100644 Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareUpdateConfig/UefiFirmwareUpdateConfig.ini create mode 100644 Platform/ASRockRack/Altra1L2TPkg/Readme.md create mode 100644 Platform/ASRockRack/Altra1L2TPkg/firmware.metainfo.xml create mode 100644 Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/Ac01AcpiTables.inf create mode 100755 Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/CPU-S0.asi create mode 100755 Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/CPU.asi create mode 100755 Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/Dsdt.asl create mode 100644 Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PCI-PDRC.asi create mode 100755 Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PCI-S0.asi create mode 100755 Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PMU-S0.asi create mode 100644 Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PMU.asi create mode 100644 Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/Ac02AcpiTables.inf create mode 100644 Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/CPU-S0.asi create mode 100644 Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/CPU.asi create mode 100644 Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/CommonDevices.asi create mode 100644 Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/Dsdt.asl create mode 100644 Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PCI-PDRC.asi create mode 100644 Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PCI-S0.asi create mode 100644 Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PMU-S0.asi create mode 100644 Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PMU.asi create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/PciPlatformDxe/PciPlatformDxe.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.h create mode 100755 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxeDataTable.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxeStrings.uni create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type07/PlatformCache.uni create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type07/PlatformCacheData.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type07/PlatformCacheFunction.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type08/PlatformPortConnector.uni create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type08/PlatformPortConnectorData.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type08/PlatformPortConnectorFunction.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type09/PlatformSystemSlot.uni create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type09/PlatformSystemSlotData.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type09/PlatformSystemSlotFunction.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type11/PlatformOemString.uni create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type11/PlatformOemStringData.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type11/PlatformOemStringFunction.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformJumperStringData.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformJumperStringFunction.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformJumperStrings.uni create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformOemString.uni create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type16/PlatformPhysicalMemoryArrayData.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type16/PlatformPhysicalMemoryArrayFunction.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDevice.uni create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDeviceData.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDeviceFunction.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type19/PlatformMemoryArrayMappedAddressData.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type19/PlatformMemoryArrayMappedAddressFunction.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type38/PlatformIpmiDeviceData.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type38/PlatformIpmiDeviceFunction.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type41/PlatformOnboardDevicesExtended.uni create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type41/PlatformOnboardDevicesExtendedData.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type41/PlatformOnboardDevicesExtendedFunction.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Library/BoardPcieLib/BoardPcieLib.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Library/BoardPcieLib/BoardPcieLib.inf create mode 100644 Platform/ASRockRack/AltraBoardPkg/Library/IOExpanderLib/IOExpanderLib.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Library/IOExpanderLib/IOExpanderLib.inf create mode 100644 Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208.h create mode 100644 Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208RealTimeClockLib.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208RealTimeClockLib.inf create mode 100644 Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/IpmiFruInfo.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/IpmiFruInfo.h create mode 100644 Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/OemMiscLib.c create mode 100644 Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/OemMiscLib.inf create mode 100644 Platform/ASRockRack/AltraBoardPkg/Library/PlatformBmcReadyLib/PlatformBmcReadyLib.c create mode 100755 Platform/ASRockRack/AltraBoardPkg/Library/PlatformBmcReadyLib/PlatformBmcReadyLib.inf diff --git a/Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.dsc b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.dsc new file mode 100644 index 00000000000..ef01771e1be --- /dev/null +++ b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.dsc @@ -0,0 +1,421 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = Altra1L2Q + PLATFORM_GUID = 57ce30d1-ad4d-41a0-a611-41ed20d33e50 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001E + OUTPUT_DIRECTORY = Build/Altra1L2Q + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.fdf + + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=VALUE + # + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNP Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_MANAGEABILITY 0x00800000 // Detailed debug and payload manageability messages + # // related to modules such as Redfish, IPMI, MCTP etc. + # DEBUG_ERROR 0x80000000 // Error +!if $(TARGET) == RELEASE + DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x80000002 +!else + DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x8000004F +!endif + + DEFINE FIRMWARE_VER = 00.01.01-00 + DEFINE FIRMWARE_VER_HEX = 0x00010100 + DEFINE CAPSULE_ENABLE = TRUE + DEFINE INCLUDE_TFA_FW = TRUE + DEFINE SECURE_BOOT_ENABLE = TRUE + DEFINE TPM2_ENABLE = TRUE + DEFINE SHELL_ENABLE = TRUE + DEFINE INCLUDE_TFTP_COMMAND = TRUE + DEFINE PLATFORM_CONFIG_UUID = 281f70a7-2333-401c-a4c8-f794775a5cd4 + + # + # Network definition + # + DEFINE NETWORK_ENABLE = TRUE + DEFINE NETWORK_IP6_ENABLE = TRUE + DEFINE NETWORK_HTTP_BOOT_ENABLE = TRUE + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE + DEFINE NETWORK_TLS_ENABLE = TRUE + DEFINE REDFISH_ENABLE = TRUE + DEFINE PERFORMANCE_MEASUREMENT_ENABLE = FALSE + DEFINE HEAP_GUARD_ENABLE = FALSE + +!if $(CAPSULE_ENABLE) == TRUE + DEFINE UEFI_IMAGE = Build/Altra1L2Q/altra1l2q_uefi.bin + DEFINE TFA_UEFI_IMAGE = Build/Altra1L2Q/altra1l2q_tfa_uefi.bin +!endif + +!include MdePkg/MdeLibs.dsc.inc + +# Include default Ampere Platform DSC file +!include Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc + +################################################################################ +# +# Specific Platform Library +# +################################################################################ +[LibraryClasses] + + OemMiscLib|Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/OemMiscLib.inf + JedecJep106Lib|MdePkg/Library/JedecJep106Lib/JedecJep106Lib.inf + + # + # ACPI Libraries + # + AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf + + # + # EFI Redfish drivers + # +!if $(NETWORK_ENABLE) == TRUE +!if $(REDFISH_ENABLE) == TRUE + RedfishContentCodingLib|RedfishPkg/Library/RedfishContentCodingLibNull/RedfishContentCodingLibNull.inf + RedfishPlatformHostInterfaceLib|RedfishPkg/Library/PlatformHostInterfaceLibNull/PlatformHostInterfaceLibNull.inf +!endif +!endif + + # + # Pcie Board + # + BoardPcieLib|Platform/ASRockRack/AltraBoardPkg/Library/BoardPcieLib/BoardPcieLib.inf + + IOExpanderLib|Platform/Ampere/JadePkg/Library/IOExpanderLib/IOExpanderLib.inf + + PlatformBmcReadyLib|Platform/Ampere/JadePkg/Library/PlatformBmcReadyLib/PlatformBmcReadyLib.inf + LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf + + # + # RTC Library: Common RTC + # + RealTimeClockLib|Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208RealTimeClockLib.inf + + # + # EFI Redfish drivers + # +!if $(REDFISH_ENABLE) == TRUE + RedfishContentCodingLib|RedfishPkg/Library/RedfishContentCodingLibNull/RedfishContentCodingLibNull.inf + RedfishPlatformHostInterfaceLib|RedfishPkg/Library/PlatformHostInterfaceBmcUsbNicLib/PlatformHostInterfaceBmcUsbNicLib.inf +!endif + +################################################################################ +# +# Specific Platform Pcds +# +################################################################################ +[PcdsFeatureFlag.common] + # + # Activate AcpiSdtProtocol + # + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + # + # Flag to indicate option of using default or specific platform Port Map table + # + gAmpereTokenSpaceGuid.PcdPcieHotPlugPortMapTable.UseDefaultConfig|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE + +[PcdsFixedAtBuild] + + gAmpereTokenSpaceGuid.PcdPcieHotPlugGpioResetMap|0x3F + + # + # Setting Portmap table + # + # * Elements of array: + # - 0: Index of Portmap entry in Portmap table structure (Vport). + # - 1: Socket number (Socket). + # - 2: Root complex port for each Portmap entry (RcaPort). + # - 3: Root complex sub-port for each Portmap entry (RcaSubPort). + # - 4: Select output port of IO expander (PinPort). + # - 5: I2C address of IO expander that CPLD backplane simulates (I2cAddress). + # - 6: Address of I2C switch between CPU and CPLD backplane (MuxAddress). + # - 7: Channel of I2C switch (MuxChannel). + # - 8: It is set from PcieHotPlugSetGPIOMapCmd () function to select GPIO[16:21] (PcdPcieHotPlugGpioResetMap) or I2C for PCIe reset purpose. + # - 9: Segment of root complex (Segment). + # - 10: SSD slot index on the front panel of backplane (DriveIndex). + # + # * Caution: + # - The last array ({ 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xFF }) require if no fully structured used. + # - Size of Portmap table: PortMap[MAX_PORTMAP_ENTRY][sizeof(PCIE_HOTPLUG_PORTMAP_ENTRY)] <=> PortMap[96][11]. + # * Example: Bellow configuration is the configuration for Portmap table of Mt. Jade 2U platform. + # + gAmpereTokenSpaceGuid.PcdPcieHotPlugPortMapTable.PortMap[0]|{ 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xFF } # Require if no fully structure used + + gAmpereTokenSpaceGuid.PcdSmbusI2cBusSpeed|100000 + + # We should support CoD in future, since it provides a nicer + # upgrade experience (e.g. a progress bar). + gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleOnDiskSupport|FALSE + +!if $(SECURE_BOOT_ENABLE) == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdRsa2048Sha256PublicKeyBuffer|{0} + !include Platform/ASRockRack/Altra1L2QPkg/root.cer.gEfiSecurityPkgTokenSpaceGuid.PcdPkcs7CertBuffer.inc +!endif + + gAmpereTokenSpaceGuid.PcdFirmwareVersionNumber|$(FIRMWARE_VER_HEX) + +[PcdsFixedAtBuild.common] + # + # Platform config UUID + # + gAmpereTokenSpaceGuid.PcdPlatformConfigUuid|"$(PLATFORM_CONFIG_UUID)" + + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x307 + + # Clearing BIT0 in this PCD prevents installing a 32-bit SMBIOS entry point, + # if the entry point version is >= 3.0. AARCH64 OSes cannot assume the + # presence of the 32-bit entry point anyway (because many AARCH64 systems + # don't have 32-bit addressable physical RAM), and the additional allocations + # below 4 GB needlessly fragment the memory map. So expose the 64-bit entry + # point only, for entry point versions >= 3.0. + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 + +!if $(SECURE_BOOT_ENABLE) == TRUE + # Override the default values from SecurityPkg to ensure images + # from all sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04 +!endif + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragments for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 +!if $(SECURE_BOOT_ENABLE) == TRUE + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|600 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1500 +!else + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|300 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|150 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1000 +!endif + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|12000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + # + # Enable strict image permissions for all images. (This applies + # only to images that were built with >= 4 KB section alignment.) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3 + + # + # Enable NX memory protection for all non-code regions, including OEM and OS + # reserved ones, with the exception of LoaderData regions, of which OS loaders + # (e.g., GRUB) may assume that its contents are executable. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD5 + + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard|TRUE + +!if $(HEAP_GUARD_ENABLE) == TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPageType|0xC000000000007B9E + gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPoolType|0xC000000000007B9E + gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask|0x0F +!endif + +[PcdsDynamicDefault.common.DEFAULT] + # SMBIOS Type 0 - BIOS Information + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"ASRock Rack Inc." + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString|L"MM/DD/YYYY" + +[PcdsDynamicExDefault.common.DEFAULT] + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100 + gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{GUID("f42e6f13-a7a6-4912-9962-ad2734b45c3a")}|VOID*|0x10 + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{GUID("1e9a10da-e398-4045-810f-4ade92e6cdee")}|VOID*|0x10 + + # Default Video Resolution + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0 # 0 - Maximum + # Setup Video Resolution + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|0 # 0 - Maximum + +[PcdsPatchableInModule] + # + # Console Resolution (HD mode) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|768 + +################################################################################ +# +# Specific Platform Component +# +################################################################################ +[Components.common] + # + # ACPI + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2B + } + Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf + Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/Ac01AcpiTables.inf + Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/Ac02AcpiTables.inf + + # + # PCIe + # + Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf + + !if $(NETWORK_ENABLE) == TRUE + # Intel I210 + !if $(INTEL_UNDI_BIN) == TRUE + IntelUndiBin/GigUndiBinRelease.inf + !endif + # For the Redfish USB CDC connection to the BMC + MdeModulePkg/Bus/Usb/UsbNetwork/NetworkCommon/NetworkCommon.inf + MdeModulePkg/Bus/Usb/UsbNetwork/UsbCdcEcm/UsbCdcEcm.inf + !endif + + # + # Renesas PD720202 XHCI firmware uploader + # +!ifdef $(USB_UPD720202_ROM_FILE) + Drivers/OptionRomPkg/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf { + + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + } +!endif + + # + # VGA Aspeed + # + Drivers/ASpeed/ASpeedGopBinPkg/ASpeedAst2500GopDxe.inf + + # + # SMBIOS + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + ManageabilityPkg/Universal/IpmiBlobTransferDxe/IpmiBlobTransferDxe.inf + Features/ManageabilityPkg/Universal/IpmiProtocol/Dxe/IpmiProtocolDxe.inf + + # + # HII + # + Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf + Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf + Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf + Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.inf + Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.inf + Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.inf + Silicon/Ampere/AmpereSiliconPkg/Drivers/BmcConfigDxe/BmcConfigDxe.inf + + # + # Firmware Capsule Update + # +!if $(CAPSULE_ENABLE) == TRUE + Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf + MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf + MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf { + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf + } + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf + } + MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + + # + # System Firmware Update + # + Silicon/Ampere/AmpereAltraPkg/Drivers/SystemFirmwareUpdateDxe/SystemFirmwareUpdateDxe.inf +!endif + + # Redfish + # +!if $(NETWORK_ENABLE) == TRUE + SecurityPkg/Hash2DxeCrypto/Hash2DxeCrypto.inf + !if $(REDFISH_ENABLE) == TRUE + !include RedfishPkg/Redfish.dsc.inc + !endif +!endif + + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + + # Multi-Processor Support + ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.inf + +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf +!if $(SHELL_ENABLE) == TRUE + ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } +!endif +!endif + + # + # OpRom emulator + # +!if $(X86_EMULATOR_ENABLE) == TRUE + Emulator/X86EmulatorDxe/X86EmulatorDxe.inf +!endif diff --git a/Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.fdf b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.fdf new file mode 100644 index 00000000000..cf0968119ea --- /dev/null +++ b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.fdf @@ -0,0 +1,520 @@ +## @file +# +# Copyright (c) 2020 - 2022, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +# Note: We have 10MB (0x00A0'0000 bytes) for UEFI. +# +# If this 10MB is ever changed, Altra1L2QCapsule.fdf and +# Capsule/HostFirmwareDescriptor/HostFirmwareDescriptor.aslc need +# updated too. + +[FD.BL33_ALTRA1L2Q_UEFI] +BaseAddress = 0x92000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x00A00000 # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x10000|gAmpereTokenSpaceGuid.PcdFvBlockSize +NumBlocks = 0xA0 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +# +# FV MAIN +# Offset: 0x00000000 +# Size: 0x00900000 +# +0x00000000|0x00900000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + +# +# NV Variables +# Offset: 0x00900000 +# Size: 0x00100000 +# +0x00900000|0x00070000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x80000 + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x2D, 0x09, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x7 Blocks * 0x10000 Bytes / Block + 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + # It is compatible with SECURE_BOOT_ENABLE == FALSE as well. + # Signature: gEfiAuthenticatedVariableGuid = + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, + # Size: 0xB0000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xAFFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xFF, 0x06, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x00970000|0x00020000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 Size: 0x10000 - 0x20 (FTW_WORKING_HEADER) = 0xFFE0 + 0xE0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x00990000|0x00070000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 61C0F511-A691-4F54-974F-B9A42172CE53 + +APRIORI PEI { + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/SmbusHc/SmbusHcPei.inf + INF ManageabilityPkg/Universal/IpmiProtocol/Pei/IpmiPpiPei.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf +} + +!if $(CAPSULE_ENABLE) == TRUE + INF RuleOverride = FMP_IMAGE_DESC Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf +!endif + + INF ArmPlatformPkg/Sec/Sec.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf +!endif + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressPeim/BootProgressPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Universal/CapsuleOnDiskLoadPei/CapsuleOnDiskLoadPei.inf + INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.inf + + # + # IPMI SSIF + # + INF Silicon/Ampere/AmpereAltraPkg/Drivers/SmbusHc/SmbusHcPei.inf + INF ManageabilityPkg/Universal/IpmiProtocol/Pei/IpmiPpiPei.inf + + # + # Print platform information before passing control into the Driver Execution Environment (DXE) phase + # + INF Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.inf + + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + +!if $(TPM2_ENABLE) == TRUE + INF MdeModulePkg/Universal/ResetSystemPei/ResetSystemPei.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/Tcg2Pei/Tcg2Pei.inf +!endif + +[FV.FvMain] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 5C60F367-A505-419A-859E-2A4FF6CA6FE5 + +APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf +} + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressDxe/BootProgressDxe.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) == TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf + INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf + + !include ArmPlatformPkg/SecureBootDefaultKeys.fdf.inc +!endif + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf + INF ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.inf + +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf +!endif + + # + # Environment Variables Protocol + # + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # + # Timer + # + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + # + # Watchdog Timer + # + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + + # + # ARM GIC Dxe + # + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # SCSI Bus and Disk Driver + # + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + + # + # SATA Support + # + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + + # + # NVME Support + # + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # + # USB Support + # + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # PCIe Support + # + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf + + !if $(NETWORK_ENABLE) == TRUE + INF SecurityPkg/Hash2DxeCrypto/Hash2DxeCrypto.inf + # Intel I210 + !if $(INTEL_UNDI_BIN) == TRUE + INF IntelUndiBin/GigUndiBinRelease.inf + !endif + INF MdeModulePkg/Bus/Usb/UsbNetwork/NetworkCommon/NetworkCommon.inf + INF MdeModulePkg/Bus/Usb/UsbNetwork/UsbCdcEcm/UsbCdcEcm.inf + !endif + + # + # VGA Aspeed + # + INF Drivers/ASpeed/ASpeedGopBinPkg/ASpeedAst2500GopDxe.inf + + # + # Random Number Generator Support + # + INF Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.inf + + # + # IPMI SSIF + # + INF Silicon/Ampere/AmpereAltraPkg/Drivers/SmbusHc/SmbusHcDxe.inf + INF ManageabilityPkg/Universal/IpmiProtocol/Dxe/IpmiProtocolDxe.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # +!if $(SHELL_ENABLE) == TRUE + INF ShellPkg/Application/Shell/Shell.inf +!if $(INCLUDE_TFTP_COMMAND) == TRUE + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +!endif +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE + INF ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf +!endif +!endif + +!if $(TPM2_ENABLE) == TRUE + INF Silicon/Ampere/AmpereAltraPkg/Drivers/Tcg2Dxe/Tcg2Dxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/Tcg2Config/Tcg2ConfigDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/Tcg2AcpiDxe/Tcg2AcpiDxe.inf + INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf +!endif + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + INF MdeModulePkg/Universal/BootManagerPolicyDxe/BootManagerPolicyDxe.inf + INF Silicon/Ampere/AmpereSiliconPkg/Drivers/PlatformBootManagerDxe/PlatformBootManagerDxe.inf + INF Silicon/Ampere/AmpereSiliconPkg/Drivers/IpmiBootDxe/IpmiBootDxe.inf + + # + # Networking stack + # +!if $(NETWORK_ENABLE) == TRUE + !include NetworkPkg/Network.fdf.inc +!endif + + # + # ACPI + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf + INF RuleOverride=ACPITABLE Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf + INF RuleOverride=ACPITABLE Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/Ac01AcpiTables.inf + INF RuleOverride=ACPITABLE Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/Ac02AcpiTables.inf + + # + # SMBIOS + # + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + INF ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + INF Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + INF ManageabilityPkg/Universal/IpmiBlobTransferDxe/IpmiBlobTransferDxe.inf + + # + # Firmware Capsule Update + # +!if $(CAPSULE_ENABLE) == TRUE + INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf + INF MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf + INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf +!endif + + # + # HII + # + INF Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.inf + INF Silicon/Ampere/AmpereSiliconPkg/Drivers/BmcConfigDxe/BmcConfigDxe.inf + + INF MdeModulePkg/Logo/LogoDxe.inf + + # + # Emulator for x64 OpRoms, etc. + # +!if $(X86_EMULATOR_ENABLE) == TRUE + INF Emulator/X86EmulatorDxe/X86EmulatorDxe.inf +!endif + + # + # EFI Redfish drivers + # +!if $(NETWORK_ENABLE) == TRUE + !if $(REDFISH_ENABLE) == TRUE + !include RedfishPkg/Redfish.fdf.inc + !endif +!endif + + # + # Renesas PD720202 XHCI firmware uploader, requires firmware image + # in directory $(WORKSPACE) + # +!ifdef $(USB_UPD720202_ROM_FILE) + INF Drivers/OptionRomPkg/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf + FILE FREEFORM = A059EBC4-D73D-4279-81BF-E4A89308B923 { + SECTION RAW = $(WORKSPACE)/K2026090.mem + } +!endif + +[FV.SystemFirmwareDescriptor] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF RuleOverride = FMP_IMAGE_DESC Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf + +[FV.CapsuleDispatchFv] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf + +!include Silicon/Ampere/AmpereSiliconPkg/FvRules.fdf.inc diff --git a/Platform/ASRockRack/Altra1L2QPkg/Altra1L2QBoardSetting.cfg b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2QBoardSetting.cfg new file mode 100644 index 00000000000..9a1ac32a756 --- /dev/null +++ b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2QBoardSetting.cfg @@ -0,0 +1,275 @@ +## +# ALTRAD8UD2-1L2Q Board Setting +# +# This is a collection of board and hardware configurations +# for an Altra-based ARM64 platform. It is stored in the persistent storage. +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# Name, offset (hex), value +# value can be hex or decimal +# + +NV_SI_RO_BOARD_VENDOR, 0x0000, 0x0000CD3A +NV_SI_RO_BOARD_TYPE, 0x0008, 0x00000000 +NV_SI_RO_BOARD_REV, 0x0010, 0x00000000 +NV_SI_RO_BOARD_CFG, 0x0018, 0x00000000 +NV_SI_RO_BOARD_S0_DIMM_AVAIL, 0x0020, 0x0000FFFF +NV_SI_RO_BOARD_S1_DIMM_AVAIL, 0x0028, 0x0000FFFF +NV_SI_RO_BOARD_SPI0CS0_FREQ_KHZ, 0x0030, 0x000080E8 +NV_SI_RO_BOARD_SPI0CS1_FREQ_KHZ, 0x0038, 0x000080E8 +NV_SI_RO_BOARD_SPI1CS0_FREQ_KHZ, 0x0040, 0x00002710 +NV_SI_RO_BOARD_SPI1CS1_FREQ_KHZ, 0x0048, 0x00002710 +NV_SI_RO_BOARD_TPM_LOC, 0x0050, 0x00000000 +NV_SI_RO_BOARD_I2C0_FREQ_KHZ, 0x0058, 0x00000190 +NV_SI_RO_BOARD_I2C1_FREQ_KHZ, 0x0060, 0x00000190 +NV_SI_RO_BOARD_I2C2_10_FREQ_KHZ, 0x0068, 0x00000190 +NV_SI_RO_BOARD_I2C3_FREQ_KHZ, 0x0070, 0x00000190 +NV_SI_RO_BOARD_I2C9_FREQ_KHZ, 0x0078, 0x00000190 +NV_SI_RO_BOARD_2P_CFG, 0x0080, 0xFFFFFFFF +# TODO +NV_SI_RO_BOARD_S0_RCA0_CFG, 0x0088, 0x00000004 +# TODO +NV_SI_RO_BOARD_S0_RCA1_CFG, 0x0090, 0x00000004 +NV_SI_RO_BOARD_S0_RCA2_CFG, 0x0098, 0x00000004 +NV_SI_RO_BOARD_S0_RCA3_CFG, 0x00A0, 0x00000004 +NV_SI_RO_BOARD_S0_RCB0_LO_CFG, 0x00A8, 0x00020002 +NV_SI_RO_BOARD_S0_RCB0_HI_CFG, 0x00B0, 0x00020002 +NV_SI_RO_BOARD_S0_RCB1_LO_CFG, 0x00B8, 0x00020002 +NV_SI_RO_BOARD_S0_RCB1_HI_CFG, 0x00C0, 0x00020002 +NV_SI_RO_BOARD_S0_RCB2_LO_CFG, 0x00C8, 0x00020002 +NV_SI_RO_BOARD_S0_RCB2_HI_CFG, 0x00D0, 0x00000003 +NV_SI_RO_BOARD_S0_RCB3_LO_CFG, 0x00D8, 0x00000003 +NV_SI_RO_BOARD_S0_RCB3_HI_CFG, 0x00E0, 0x00020002 +NV_SI_RO_BOARD_S1_RCA0_CFG, 0x00E8, 0x00000000 +NV_SI_RO_BOARD_S1_RCA1_CFG, 0x00F0, 0x00000000 +NV_SI_RO_BOARD_S1_RCA2_CFG, 0x00F8, 0x02020202 +NV_SI_RO_BOARD_S1_RCA3_CFG, 0x0100, 0x00030003 +NV_SI_RO_BOARD_S1_RCB0_LO_CFG, 0x0108, 0x00000003 +NV_SI_RO_BOARD_S1_RCB0_HI_CFG, 0x0110, 0x00020002 +NV_SI_RO_BOARD_S1_RCB1_LO_CFG, 0x0118, 0x00020002 +NV_SI_RO_BOARD_S1_RCB1_HI_CFG, 0x0120, 0x00000003 +NV_SI_RO_BOARD_S1_RCB2_LO_CFG, 0x0128, 0x00020002 +NV_SI_RO_BOARD_S1_RCB2_HI_CFG, 0x0130, 0x00020002 +NV_SI_RO_BOARD_S1_RCB3_LO_CFG, 0x0138, 0x00020002 +NV_SI_RO_BOARD_S1_RCB3_HI_CFG, 0x0140, 0x00020002 +NV_SI_RO_BOARD_T_LTLM_DELTA_P0, 0x0148, 0x00000001 +NV_SI_RO_BOARD_T_LTLM_DELTA_P1, 0x0150, 0x00000002 +NV_SI_RO_BOARD_T_LTLM_DELTA_P2, 0x0158, 0x00000003 +NV_SI_RO_BOARD_T_LTLM_DELTA_P3, 0x0160, 0x00000004 +NV_SI_RO_BOARD_T_LTLM_DELTA_M1, 0x0168, 0xFFFFFFFF +NV_SI_RO_BOARD_T_LTLM_DELTA_M2, 0x0170, 0xFFFFFFFE +NV_SI_RO_BOARD_T_LTLM_DELTA_M3, 0x0178, 0xFFFFFFFD +NV_SI_RO_BOARD_P_LM_PID_P, 0x0180, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_I, 0x0188, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_I_L_THOLD, 0x0190, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_I_H_THOLD, 0x0198, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_D, 0x01A0, 0x00000000 +NV_SI_RO_BOARD_P_LM_EXP_SMOOTH_CONST, 0x01A8, 0x00000000 +NV_SI_RO_BOARD_TPM_ALG_ID, 0x01B0, 0x00000002 +NV_SI_RO_BOARD_DDR_SPEED_GRADE, 0x01B8, 0x00000C80 +NV_SI_RO_BOARD_DDR_S0_RTT_WR, 0x01C0, 0x20020000 +NV_SI_RO_BOARD_DDR_S1_RTT_WR, 0x01C8, 0x20020000 +NV_SI_RO_BOARD_DDR_S0_RTT_NOM, 0x01D0, 0x31060177 +NV_SI_RO_BOARD_DDR_S1_RTT_NOM, 0x01D8, 0x31060177 +NV_SI_RO_BOARD_DDR_S0_RTT_PARK, 0x01E0, 0x30060070 +NV_SI_RO_BOARD_DDR_S1_RTT_PARK, 0x01E8, 0x30060070 +NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_1DPC, 0x01F0, 0x00000000 +NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_1DPC, 0x01F8, 0x00000000 +NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_1DPC, 0x0200, 0x00000000 +NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_1DPC, 0x0208, 0x00000000 +NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_2DPC, 0x0210, 0x044C0CCC +NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_2DPC, 0x0218, 0x084C0CCC +NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_2DPC, 0x0220, 0x04130333 +NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_2DPC, 0x0228, 0x08130333 +NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_1DPC, 0x0230, 0x01130333 +NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_1DPC, 0x0238, 0x02230333 +NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_1DPC, 0x0240, 0x01430333 +NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_1DPC, 0x0248, 0x02830333 +NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_2DPC, 0x0250, 0x055EDEED +NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_2DPC, 0x0258, 0x0A5DEDDE +NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_2DPC, 0x0260, 0x055B7BB7 +NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_2DPC, 0x0268, 0x0A57B77B +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_1DPC, 0x0270, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_1DPC, 0x0278, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_1DPC, 0x0280, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_1DPC, 0x0288, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_2DPC, 0x0290, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_2DPC, 0x0298, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_2DPC, 0x02A0, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_2DPC, 0x02A8, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_1DPC, 0x02B0, 0x00000024 +NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_1DPC, 0x02B8, 0x001A001A +NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_2DPC, 0x02C0, 0x00000050 +NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_2DPC, 0x02C8, 0x00240020 +NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_DEFAULT, 0x02D0, 0x02800280 +NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_DEFAULT, 0x02D8, 0x90909090 +NV_SI_RO_BOARD_DDR_WRDQS_SHIFT_DEFAULT, 0x02E0, 0x00000000 +NV_SI_RO_BOARD_DDR_ADCMD_DLY_DEFAULT, 0x02E8, 0x00C000C0 +NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_ADJ, 0x02F0, 0x00000000 +NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_ADJ, 0x02F8, 0x00000000 +NV_SI_RO_BOARD_DDR_PHY_VREF_ADJ, 0x0300, 0x00000000 +NV_SI_RO_BOARD_DDR_DRAM_VREF_ADJ, 0x0308, 0x00000000 +NV_SI_RO_BOARD_DDR_WR_PREAMBLE_CYCLE, 0x0310, 0x02010201 +NV_SI_RO_BOARD_DDR_ADCMD_2T_MODE, 0x0318, 0x00000000 +NV_SI_RO_BOARD_I2C_VRD_CONFIG_INFO, 0x0320, 0x00000000 +NV_SI_RO_BOARD_DDR_PHY_FEATURE_CTRL, 0x0328, 0x00000000 +NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_ACCESS, 0x0330, 0x01050106 +NV_SI_RO_BOARD_DIMM_TEMP_THRESHOLD, 0x0338, 0x000005F4 +NV_SI_RO_BOARD_DIMM_SPD_COMPARE_DISABLE, 0x0340, 0x00000000 +NV_SI_RO_BOARD_S0_PCIE_CLK_CFG, 0x0348, 0x00000000 +NV_SI_RO_BOARD_S0_RCA4_CFG, 0x0350, 0x02020202 +NV_SI_RO_BOARD_S0_RCA5_CFG, 0x0358, 0x02020202 +NV_SI_RO_BOARD_S0_RCA6_CFG, 0x0360, 0x02020202 +NV_SI_RO_BOARD_S0_RCA7_CFG, 0x0368, 0x00030003 +NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET, 0x0370, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET, 0x0378, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET, 0x0380, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET, 0x0388, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCB0A_TXRX_G3PRESET, 0x0390, 0x00000000 +NV_SI_RO_BOARD_S0_RCB0B_TXRX_G3PRESET, 0x0398, 0x00000000 +NV_SI_RO_BOARD_S0_RCB1A_TXRX_G3PRESET, 0x03A0, 0x00000000 +NV_SI_RO_BOARD_S0_RCB1B_TXRX_G3PRESET, 0x03A8, 0x00000000 +NV_SI_RO_BOARD_S0_RCB2A_TXRX_G3PRESET, 0x03B0, 0x00000000 +NV_SI_RO_BOARD_S0_RCB2B_TXRX_G3PRESET, 0x03B8, 0x00000000 +NV_SI_RO_BOARD_S0_RCB3A_TXRX_G3PRESET, 0x03C0, 0x00000000 +NV_SI_RO_BOARD_S0_RCB3B_TXRX_G3PRESET, 0x03C8, 0x00000000 +NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET, 0x03D0, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET, 0x03D8, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET, 0x03E0, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET, 0x03E8, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET, 0x03F0, 0x57575757 +NV_SI_RO_BOARD_S0_RCA1_TXRX_G4PRESET, 0x03F8, 0x57575757 +NV_SI_RO_BOARD_S0_RCA2_TXRX_G4PRESET, 0x0400, 0x57575757 +NV_SI_RO_BOARD_S0_RCA3_TXRX_G4PRESET, 0x0408, 0x57575757 +NV_SI_RO_BOARD_S0_RCB0A_TXRX_G4PRESET, 0x0410, 0x57575757 +NV_SI_RO_BOARD_S0_RCB0B_TXRX_G4PRESET, 0x0418, 0x57575757 +NV_SI_RO_BOARD_S0_RCB1A_TXRX_G4PRESET, 0x0420, 0x57575757 +NV_SI_RO_BOARD_S0_RCB1B_TXRX_G4PRESET, 0x0428, 0x57575757 +NV_SI_RO_BOARD_S0_RCB2A_TXRX_G4PRESET, 0x0430, 0x57575757 +NV_SI_RO_BOARD_S0_RCB2B_TXRX_G4PRESET, 0x0438, 0x57575757 +NV_SI_RO_BOARD_S0_RCB3A_TXRX_G4PRESET, 0x0440, 0x57575757 +NV_SI_RO_BOARD_S0_RCB3B_TXRX_G4PRESET, 0x0448, 0x57575757 +NV_SI_RO_BOARD_S0_RCA4_TXRX_G4PRESET, 0x0450, 0x57575757 +NV_SI_RO_BOARD_S0_RCA5_TXRX_G4PRESET, 0x0458, 0x57575757 +NV_SI_RO_BOARD_S0_RCA6_TXRX_G4PRESET, 0x0460, 0x57575757 +NV_SI_RO_BOARD_S0_RCA7_TXRX_G4PRESET, 0x0468, 0x57575757 +NV_SI_RO_BOARD_S1_PCIE_CLK_CFG, 0x0470, 0x00000000 +NV_SI_RO_BOARD_S1_RCA4_CFG, 0x0478, 0x00030003 +NV_SI_RO_BOARD_S1_RCA5_CFG, 0x0480, 0x02020202 +NV_SI_RO_BOARD_S1_RCA6_CFG, 0x0488, 0x02020202 +NV_SI_RO_BOARD_S1_RCA7_CFG, 0x0490, 0x02020202 +NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET, 0x0498, 0xFFFFFFFF +NV_SI_RO_BOARD_S1_RCA3_TXRX_G3PRESET, 0x04A0, 0xFFFFFFFF +NV_SI_RO_BOARD_S1_RCB0A_TXRX_G3PRESET, 0x04A8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB0B_TXRX_G3PRESET, 0x04B0, 0x00000000 +NV_SI_RO_BOARD_S1_RCB1A_TXRX_G3PRESET, 0x04B8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB1B_TXRX_G3PRESET, 0x04C0, 0x00000000 +NV_SI_RO_BOARD_S1_RCB2A_TXRX_G3PRESET, 0x04C8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB2B_TXRX_G3PRESET, 0x04D0, 0x00000000 +NV_SI_RO_BOARD_S1_RCB3A_TXRX_G3PRESET, 0x04D8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB3B_TXRX_G3PRESET, 0x04E0, 0x00000000 +NV_SI_RO_BOARD_S1_RCA4_TXRX_G3PRESET, 0x04E8, 0xFFFFFFFF +NV_SI_RO_BOARD_S1_RCA5_TXRX_G3PRESET, 0x04F0, 0xFFFFFFFF +NV_SI_RO_BOARD_S1_RCA6_TXRX_G3PRESET, 0x04F8, 0xFFFFFFFF +NV_SI_RO_BOARD_S1_RCA7_TXRX_G3PRESET, 0x0500, 0xFFFFFFFF +NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET, 0x0508, 0x57575757 +NV_SI_RO_BOARD_S1_RCA3_TXRX_G4PRESET, 0x0510, 0x57575757 +NV_SI_RO_BOARD_S1_RCB0A_TXRX_G4PRESET, 0x0518, 0x57575757 +NV_SI_RO_BOARD_S1_RCB0B_TXRX_G4PRESET, 0x0520, 0x57575757 +NV_SI_RO_BOARD_S1_RCB1A_TXRX_G4PRESET, 0x0528, 0x57575757 +NV_SI_RO_BOARD_S1_RCB1B_TXRX_G4PRESET, 0x0530, 0x57575757 +NV_SI_RO_BOARD_S1_RCB2A_TXRX_G4PRESET, 0x0538, 0x57575757 +NV_SI_RO_BOARD_S1_RCB2B_TXRX_G4PRESET, 0x0540, 0x57575757 +NV_SI_RO_BOARD_S1_RCB3A_TXRX_G4PRESET, 0x0548, 0x57575757 +NV_SI_RO_BOARD_S1_RCB3B_TXRX_G4PRESET, 0x0550, 0x57575757 +NV_SI_RO_BOARD_S1_RCA4_TXRX_G4PRESET, 0x0558, 0x57575757 +NV_SI_RO_BOARD_S1_RCA5_TXRX_G4PRESET, 0x0560, 0x57575757 +NV_SI_RO_BOARD_S1_RCA6_TXRX_G4PRESET, 0x0568, 0x57575757 +NV_SI_RO_BOARD_S1_RCA7_TXRX_G4PRESET, 0x0570, 0x57575757 +NV_SI_RO_BOARD_2P_CE_MASK_THRESHOLD, 0x0578, 0x00000003 +NV_SI_RO_BOARD_2P_CE_MASK_INTERVAL, 0x0580, 0x000001A4 +NV_SI_RO_BOARD_SX_PHY_CFG_SETTING, 0x0588, 0x00000000 +NV_SI_RO_BOARD_DDR_PHY_DC_CLK, 0x0590, 0x00018000 +NV_SI_RO_BOARD_DDR_PHY_DC_DATA, 0x0598, 0x80018000 +NV_SI_RO_BOARD_SX_RCA0_TXRX_20GPRESET, 0x05A0, 0x00000000 +NV_SI_RO_BOARD_SX_RCA1_TXRX_20GPRESET, 0x05A8, 0x00000000 +NV_SI_RO_BOARD_SX_RCA2_TXRX_20GPRESET, 0x05B0, 0x00000000 +NV_SI_RO_BOARD_SX_RCA3_TXRX_20GPRESET, 0x05B8, 0x00000000 +NV_SI_RO_BOARD_SX_RCA0_TXRX_25GPRESET, 0x05C0, 0x00000000 +NV_SI_RO_BOARD_SX_RCA1_TXRX_25GPRESET, 0x05C8, 0x00000000 +NV_SI_RO_BOARD_SX_RCA2_TXRX_25GPRESET, 0x05D0, 0x00000000 +NV_SI_RO_BOARD_SX_RCA3_TXRX_25GPRESET, 0x05D8, 0x00000000 +NV_SI_RO_BOARD_DDR_2X_REFRESH_TEMP_THRESHOLD, 0x05E0, 0x00550055 +NV_SI_RO_BOARD_PCP_VRD_VOUT_WAIT_US, 0x05E8, 0x00000064 +NV_SI_RO_BOARD_PCP_VRD_VOUT_RESOLUTION_MV, 0x05F0, 0x00000005 +NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_EN, 0x05F8, 0x00000001 +NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_TIME, 0x0600, 0x00000002 +NV_SI_RO_BOARD_DVFS_VOUT_20MV_RAMP_TIME_US, 0x0608, 0x00000005 +NV_SI_RO_BOARD_PCIE_AER_FW_FIRST, 0x0610, 0x00000000 +NV_SI_RO_BOARD_RTC_GPI_LOCK_BYPASS, 0x0618, 0x00000000 +NV_SI_RO_BOARD_TPM_DISABLE, 0x0620, 0x00000000 +NV_SI_RO_BOARD_MESH_S0_CXG_RC_STRONG_ORDERING_EN, 0x0628, 0x00000000 +NV_SI_RO_BOARD_MESH_S1_CXG_RC_STRONG_ORDERING_EN, 0x0630, 0x00000000 +NV_SI_RO_BOARD_GPIO_SW_WATCHDOG_EN, 0x0638, 0x00000000 +NV_SI_RO_BOARD_PCIE_HP_DISABLE, 0x0640, 0x00000000 +NV_SI_RO_BOARD_I2C_VRD_VOUT_FORMAT, 0x0648, 0x00000000 +NV_SI_RO_BOARD_I2C_VRD_SMBUS_CMD_FLAGS, 0x0650, 0x00000000 +NV_SI_RO_BOARD_CUST_SPM_LOCATION, 0x0658, 0x00000000 +NV_SI_RO_BOARD_RAS_DDR_CE_WINDOW, 0x0660, 0x00000000 +NV_SI_RO_BOARD_RAS_DDR_CE_TH1, 0x0668, 0x000001F4 +NV_SI_RO_BOARD_RAS_DDR_CE_TH2, 0x0670, 0x00001388 +NV_SI_RO_BOARD_RAS_DDR_CE_THC, 0x0678, 0x00000000 +NV_SI_RO_BOARD_MQ_SX_RCA0_TXRX_20GPRESET, 0x0680, 0x00000000 +NV_SI_RO_BOARD_MQ_SX_RCA1_TXRX_20GPRESET, 0x0688, 0x00000000 +NV_SI_RO_BOARD_MQ_SX_RCA0_TXRX_25GPRESET, 0x0690, 0x00000000 +NV_SI_RO_BOARD_MQ_SX_RCA1_TXRX_25GPRESET, 0x0698, 0x00000000 +NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G3PRESET, 0x06A0, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA1_TXRX_G3PRESET, 0x06A8, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA2_TXRX_G3PRESET, 0x06B0, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA3_TXRX_G3PRESET, 0x06B8, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA4_TXRX_G3PRESET, 0x06C0, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA5_TXRX_G3PRESET, 0x06C8, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA6_TXRX_G3PRESET, 0x06D0, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA7_TXRX_G3PRESET, 0x06D8, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G3PRESET, 0x06E0, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S1_RCA3_TXRX_G3PRESET, 0x06E8, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S1_RCA4_TXRX_G3PRESET, 0x06F0, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S1_RCA5_TXRX_G3PRESET, 0x06F8, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S1_RCA6_TXRX_G3PRESET, 0x0700, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S1_RCA7_TXRX_G3PRESET, 0x0708, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G4PRESET, 0x0710, 0x57575757 +NV_SI_RO_BOARD_MQ_S0_RCA1_TXRX_G4PRESET, 0x0718, 0x57575757 +NV_SI_RO_BOARD_MQ_S0_RCA2_TXRX_G4PRESET, 0x0720, 0x57575757 +NV_SI_RO_BOARD_MQ_S0_RCA3_TXRX_G4PRESET, 0x0728, 0x57575757 +NV_SI_RO_BOARD_MQ_S0_RCA4_TXRX_G4PRESET, 0x0730, 0x57575757 +NV_SI_RO_BOARD_MQ_S0_RCA5_TXRX_G4PRESET, 0x0738, 0x57575757 +NV_SI_RO_BOARD_MQ_S0_RCA6_TXRX_G4PRESET, 0x0740, 0x57575757 +NV_SI_RO_BOARD_MQ_S0_RCA7_TXRX_G4PRESET, 0x0748, 0x57575757 +NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G4PRESET, 0x0750, 0x57575757 +NV_SI_RO_BOARD_MQ_S1_RCA3_TXRX_G4PRESET, 0x0758, 0x57575757 +NV_SI_RO_BOARD_MQ_S1_RCA4_TXRX_G4PRESET, 0x0760, 0x57575757 +NV_SI_RO_BOARD_MQ_S1_RCA5_TXRX_G4PRESET, 0x0768, 0x57575757 +NV_SI_RO_BOARD_MQ_S1_RCA6_TXRX_G4PRESET, 0x0770, 0x57575757 +NV_SI_RO_BOARD_MQ_S1_RCA7_TXRX_G4PRESET, 0x0778, 0x57575757 +NV_SI_RO_BOARD_RAS_FLAGS, 0x0780, 0x00000000 +NV_SI_RO_BOARD_DDR_PROGRESS_LOG_CTRL, 0x0788, 0x00000000 +NV_SI_RO_BOARD_2P_ALI_CE_MASK_THRESHOLD, 0x0790, 0x00000001 +NV_SI_RO_BOARD_2P_ALI_CE_MASK_INTERVAL, 0x0798, 0x00000000 +NV_SI_RO_BOARD_RAS_2P_CE_FILTER, 0x07A0, 0x00000000 +NV_SI_RO_BOARD_PCIE_AER_CE_THRESHOLD_EN, 0x07A8, 0x00000000 +NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_TO1, 0x07B0, 0x00000000 +NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_TO2, 0x07B8, 0x00000000 +NV_SI_RO_BOARD_PCIE_AER_CE_THRESHOLD, 0x07C0, 0x00000001 +NV_SI_RO_BOARD_PCIE_AER_CE_INTERVAL, 0x07C8, 0x00000000 +NV_SI_RO_BOARD_I2C_RCA_VRD_VOUT_FORMAT, 0x07D0, 0x00000000 +NV_SI_RO_BOARD_CCIX_MODE_OVERWRITE, 0x07D8, 0x00000000 +NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_MARGIN_MV, 0x07E0, 0x00000000 +NV_SI_RO_BOARD_2P_DPLL, 0x07E8, 0x00000000 +NV_SI_RO_BOARD_RC_DOMAIN_CTRL, 0x07F0, 0x00000000 +NV_SI_RO_BOARD_PCIE_SRIS_MODE, 0x07F8, 0x00000000 diff --git a/Platform/ASRockRack/Altra1L2QPkg/Altra1L2QCapsule.dsc b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2QCapsule.dsc new file mode 100644 index 00000000000..3805103f4b7 --- /dev/null +++ b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2QCapsule.dsc @@ -0,0 +1,31 @@ +## @file +# +# Copyright (c) 2020 - 2024, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = Altra1L2Q + PLATFORM_GUID = 57ce30d1-ad4d-41a0-a611-41ed20d33e50 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001B + OUTPUT_DIRECTORY = Build/Altra1L2Q + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/ASRockRack/Altra1L2QPkg/Altra1L2QCapsule.fdf + + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=VALUE + # + DEFINE INCLUDE_TFA_FW = TRUE + DEFINE UEFI_IMAGE = Build/Altra1L2Q/altra1l2q_uefi.bin + DEFINE TFA_UEFI_IMAGE = Build/Altra1L2Q/altra1l2q_tfa_uefi.bin diff --git a/Platform/ASRockRack/Altra1L2QPkg/Altra1L2QCapsule.fdf b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2QCapsule.fdf new file mode 100644 index 00000000000..2b75fbd10fc --- /dev/null +++ b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2QCapsule.fdf @@ -0,0 +1,105 @@ +## @file +# +# Copyright (c) 2020 - 2024, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.ALTRA1L2Q_HOST_FIRMWARE_CAPSULE] +BaseAddress = 0x00000000 # The base address of the Firmware in NOR Flash. +!if $(INCLUDE_TFA_FW) == TRUE + Size = 0x00C10000 # The size in bytes of the FLASH Device +!else + Size = 0x00A10000 +!endif +ErasePolarity = 1 + +0x00000000|0x00010000 +FILE = $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/SYSTEMFIRMWAREDESCRIPTOR.Fv + +!if $(INCLUDE_TFA_FW) == TRUE + 0x00010000|0x00C00000 + FILE = $(TFA_UEFI_IMAGE) +!else + 0x00010000|0x00A00000 + FILE = $(UEFI_IMAGE) +!endif + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.HostFirmwareUpdateCargo] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +FILE RAW = 1e9a10da-e398-4045-810f-4ade92e6cdee { # PcdEdkiiSystemFirmwareFileGuid + FD = ALTRA1L2Q_HOST_FIRMWARE_CAPSULE +} + +FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid + $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/CAPSULEDISPATCHFV.Fv +} + +FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid +!if $(INCLUDE_TFA_FW) + Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareUpdateConfig/TfaUefiFirmwareUpdateConfig.ini +!else + Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareUpdateConfig/UefiFirmwareUpdateConfig.ini +!endif + + } + +[FmpPayload.FmpPayloadHostFirmwarePkcs7] +IMAGE_HEADER_INIT_VERSION = 0x03 +IMAGE_TYPE_ID = f42e6f13-a7a6-4912-9962-ad2734b45c3a # PcdSystemFmpCapsuleImageTypeIdGuid +IMAGE_INDEX = 0x1 +HARDWARE_INSTANCE = 0x0 +MONOTONIC_COUNT = 0x1 +CERTIFICATE_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7 + +FV = HostFirmwareUpdateCargo + +[Capsule.Altra1L2QHostFirmware] +CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid +CAPSULE_HEADER_SIZE = 0x20 +CAPSULE_HEADER_INIT_VERSION = 0x1 + +FMP_PAYLOAD = FmpPayloadHostFirmwarePkcs7 + diff --git a/Platform/ASRockRack/Altra1L2QPkg/Altra1L2QLinuxBoot.dsc b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2QLinuxBoot.dsc new file mode 100644 index 00000000000..8facc052517 --- /dev/null +++ b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2QLinuxBoot.dsc @@ -0,0 +1,132 @@ +## @file +# +# Copyright (c) 2020 - 2022, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = Altra1L2Q + PLATFORM_GUID = 57ce30d1-ad4d-41a0-a611-41ed20d33e50 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001B + OUTPUT_DIRECTORY = Build/Altra1L2Q + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/ASRockRack/Altra1L2QPkg/Altra1L2QLinuxBoot.fdf + + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=VALUE + # + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // Network Io Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_MANAGEABILITY 0x00800000 // Detailed debug and payload manageability messages + # // related to modules such as Redfish, IPMI, MCTP etc. + # DEBUG_ERROR 0x80000000 // Error + DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x8000004F + DEFINE FIRMWARE_VER = 0.01.001 + DEFINE EDK2_SKIP_PEICORE = TRUE + +!include MdePkg/MdeLibs.dsc.inc + +# Include default Ampere Platform DSC file +!include Silicon/Ampere/AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc + +# +# Specific Platform Library +# +[LibraryClasses.common] + # + # ACPI Libraries + # + AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf + AcpiHelperLib|Platform/Ampere/AmperePlatformPkg/Library/AcpiHelperLib/AcpiHelperLib.inf + + # + # Pcie Board + # + BoardPcieLib|Platform/ASRockRack/Altra1L2QPkg/Library/BoardPcieLib/BoardPcieLib.inf + + IOExpanderLib|Platform/ASRockRack/Altra1L2QPkg/Library/IOExpanderLib/IOExpanderLib.inf + + PlatformBmcReadyLib|Platform/ASRockRack/Altra1L2QPkg/Library/PlatformBmcReadyLib/PlatformBmcReadyLib.inf + OemMiscLib|Platform/ASRockRack/Altra1L2QPkg/Library/OemMiscLib/OemMiscLib.inf + +[LibraryClasses.common.PEIM] + SmbusLib|MdePkg/Library/PeiSmbusLibSmbus2Ppi/PeiSmbusLibSmbus2Ppi.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + # + # RTC Library: Common RTC + # + RealTimeClockLib|Platform/ASRockRack/Altra1L2QPkg/Library/PCF85063RealTimeClockLib/PCF85063RealTimeClockLib.inf + +[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER] + SmbusLib|MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf + +[PcdsFixedAtBuild.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0307 + + gAmpereTokenSpaceGuid.PcdSmbiosTables0MajorVersion|$(MAJOR_VER) + gAmpereTokenSpaceGuid.PcdSmbiosTables0MinorVersion|$(MINOR_VER) +!ifdef $(FIRMWARE_VER) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" +!endif + + # Clearing BIT0 in this PCD prevents installing a 32-bit SMBIOS entry point, + # if the entry point version is >= 3.0. AARCH64 OSes cannot assume the + # presence of the 32-bit entry point anyway (because many AARCH64 systems + # don't have 32-bit addressable physical RAM), and the additional allocations + # below 4 GB needlessly fragment the memory map. So expose the 64-bit entry + # point only, for entry point versions >= 3.0. + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 + +# +# Specific Platform Component +# +[Components.common] + + # + # ACPI + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + Platform/ASRockRack/Altra1L2QPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf + Platform/ASRockRack/Altra1L2QPkg/AcpiTables/AcpiTables.inf + Platform/ASRockRack/Altra1L2QPkg/Ac02AcpiTables/Ac02AcpiTables.inf + + # + # SMBIOS + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + Platform/ASRockRack/Altra1L2QPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + + MdeModulePkg/Application/HelloWorld/HelloWorld.inf diff --git a/Platform/ASRockRack/Altra1L2QPkg/Altra1L2QLinuxBoot.fdf b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2QLinuxBoot.fdf new file mode 100644 index 00000000000..8abeb484185 --- /dev/null +++ b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2QLinuxBoot.fdf @@ -0,0 +1,224 @@ +## @file +# +# Copyright (c) 2020 - 2022, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.BL33_ALTRA1L2Q_UEFI] +BaseAddress = 0x92000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x00AC0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x10000 +NumBlocks = 0xAC + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +0x00000000|0x00AC0000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x10000 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 16 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 5C60F367-A505-419A-859E-2A4FF6CA6FE5 + +APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInitDxe/PlatformInitDxe.inf +} + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf + + # + # Environment Variables Protocol + # + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + + # + # Timer + # + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + # + # Initialize works at Dxe phase + # + INF Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInitDxe/PlatformInitDxe.inf + + # + # Watchdog Timer + # + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + + # + # ARM GIC Dxe + # + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + # + # SMBus + # +# INF Silicon/Ampere/AmpereAltraPkg/Drivers/SmbusHcDxe/SmbusHcDxe.inf + + # + # IPMI + # +# INF Silicon/Ampere/AmpereSiliconPkg/Drivers/IpmiSsif/IpmiSsifDxe.inf + + # + # Linuxboot in Flash Support + # + INF Platform/Ampere/LinuxBootPkg/LinuxBoot.inf + + # + # Bds + # + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + + # + # ACPI + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF Platform/ASRockRack/Altra1L2QPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF RuleOverride=ACPITABLE Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf + INF RuleOverride=ACPITABLE Platform/ASRockRack/Altra1L2QPkg/AcpiTables/AcpiTables.inf + INF RuleOverride=ACPITABLE Platform/ASRockRack/Altra1L2QPkg/Ac02AcpiTables/Ac02AcpiTables.inf + + # + # SMBIOS + # + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + INF ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + INF Platform/ASRockRack/Altra1L2QPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + + INF MdeModulePkg/Application/HelloWorld/HelloWorld.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +APRIORI PEI { + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf +} + + INF ArmPlatformPkg/Sec/Sec.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf +# INF Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf +# INF Silicon/Ampere/AmpereAltraPkg/Drivers/SmbusHcPei/SmbusHcPei.inf + + # + # IPMI + # +# INF Silicon/Ampere/AmpereSiliconPkg/Drivers/IpmiSsif/IpmiSsifPeim.inf + + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + +!include Silicon/Ampere/AmpereSiliconPkg/FvRules.fdf.inc diff --git a/Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc new file mode 100644 index 00000000000..64582d19155 --- /dev/null +++ b/Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc @@ -0,0 +1,76 @@ +/** @file + System Firmware descriptor. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include + +#include "HostFwInfo.h" + +#define PACKAGE_VERSION 0xFFFFFFFF +#define PACKAGE_VERSION_STRING L"Unknown" + +#define IMAGE_ID SIGNATURE_64('A', 'S', 'R', 'R', '2', 'Q', 'F', 'W') +#define IMAGE_ID_STRING L"ALTRAD8UD2-1L2Q Host Firmware" + +// PcdSystemFmpCapsuleImageTypeIdGuid +#define IMAGE_TYPE_ID_GUID { 0xf42e6f13, 0xa7a6, 0x4912, { 0x99, 0x62, 0xad, 0x27, 0x34, 0xb4, 0x5c, 0x3a } } + +typedef struct { + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor; + // real string data + CHAR16 ImageIdNameStr[sizeof(IMAGE_ID_STRING)/sizeof(CHAR16)]; + CHAR16 VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING)/sizeof(CHAR16)]; + CHAR16 PackageVersionNameStr[sizeof(PACKAGE_VERSION_STRING)/sizeof(CHAR16)]; +} IMAGE_DESCRIPTOR; + +STATIC IMAGE_DESCRIPTOR mImageDescriptor = +{ + { + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE, + sizeof(EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR), + sizeof(IMAGE_DESCRIPTOR), + PACKAGE_VERSION, // PackageVersion + OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersionName + 1, // ImageIndex; + {0x0}, // Reserved + IMAGE_TYPE_ID_GUID, // ImageTypeId; + IMAGE_ID, // ImageId; + OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName; + CURRENT_FIRMWARE_VERSION, // Version; + OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName; + {0x0}, // Reserved2 + 0xA00000, // Size; + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | + IMAGE_ATTRIBUTE_RESET_REQUIRED | + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | + IMAGE_ATTRIBUTE_IN_USE | + IMAGE_ATTRIBUTE_UEFI_IMAGE, // AttributesSupported; + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | + IMAGE_ATTRIBUTE_RESET_REQUIRED | + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | + IMAGE_ATTRIBUTE_IN_USE | + IMAGE_ATTRIBUTE_UEFI_IMAGE, // AttributesSetting; + 0x0, // Compatibilities; + LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion; + 0x00000000, // LastAttemptVersion; + 0, // LastAttemptStatus; + {0x0}, // Reserved3 + 0, // HardwareInstance; + }, + // real string data + IMAGE_ID_STRING, + CURRENT_FIRMWARE_VERSION_STRING, + PACKAGE_VERSION_STRING, +}; + +VOID* CONST ReferenceAcpiTable = &mImageDescriptor; diff --git a/Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf new file mode 100644 index 00000000000..861a02989a3 --- /dev/null +++ b/Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf @@ -0,0 +1,39 @@ +## @file +# System Firmware descriptor. +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = SystemFirmwareDescriptor + FILE_GUID = 396f4af1-76fb-4745-bfb9-004ecf0b936b + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = SystemFirmwareDescriptorPeimEntry + +[Sources] + SystemFirmwareDescriptor.aslc + SystemFirmwareDescriptorPei.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + SignedCapsulePkg/SignedCapsulePkg.dec + +[LibraryClasses] + DebugLib + PcdLib + PeiServicesLib + PeimEntryPoint + +[Pcd] + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor + +[Depex] + TRUE diff --git a/Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c b/Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c new file mode 100644 index 00000000000..7857606686e --- /dev/null +++ b/Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c @@ -0,0 +1,73 @@ +/** @file + System Firmware descriptor producer. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include + +/** + Entrypoint for SystemFirmwareDescriptor PEIM. + + @param[in] FileHandle Handle of the file being invoked. + @param[in] PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS PPI successfully installed. +**/ +EFI_STATUS +EFIAPI +SystemFirmwareDescriptorPeimEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR *Descriptor; + UINTN Size; + UINTN Index; + UINT32 AuthenticationStatus; + + // + // Search RAW section. + // + Index = 0; + while (TRUE) { + Status = PeiServicesFfsFindSectionData3 ( + EFI_SECTION_RAW, + Index, + FileHandle, + (VOID **)&Descriptor, + &AuthenticationStatus + ); + if (EFI_ERROR (Status)) { + // Should not happen, must something wrong in FDF. + ASSERT (FALSE); + return EFI_NOT_FOUND; + } + if (Descriptor->Signature == EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE) { + break; + } + Index++; + } + + DEBUG (( + DEBUG_INFO, + "EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR size - 0x%x\n", + Descriptor->Length + )); + + Size = Descriptor->Length; + PcdSetPtrS (PcdEdkiiSystemFirmwareImageDescriptor, &Size, Descriptor); + + return EFI_SUCCESS; +} diff --git a/Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareUpdateConfig/TfaUefiFirmwareUpdateConfig.ini b/Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareUpdateConfig/TfaUefiFirmwareUpdateConfig.ini new file mode 100644 index 00000000000..ecdcd9ff3bf --- /dev/null +++ b/Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareUpdateConfig/TfaUefiFirmwareUpdateConfig.ini @@ -0,0 +1,21 @@ +## @file +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Head] +NumOfUpdate = 1 +NumOfRecovery = 0 +Update0 = TFA_UEFI + +[TFA_UEFI] +FirmwareType = 2147483650 # SystemFirmware: 0x80000002 - ARM Trusted Firmware and OEM UEFI +AddressType = 1 # 0 - relative address, 1 - absolute address. +BaseAddress = 0x00000000 # Base address offset on flash +Length = 0x00D10000 # Length +ImageOffset = 0x00000000 # Image offset of this SystemFirmware image +FileGuid = 1e9a10da-e398-4045-810f-4ade92e6cdee # PcdEdkiiSystemFirmwareFileGuid diff --git a/Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareUpdateConfig/UefiFirmwareUpdateConfig.ini b/Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareUpdateConfig/UefiFirmwareUpdateConfig.ini new file mode 100644 index 00000000000..a53abfa2c50 --- /dev/null +++ b/Platform/ASRockRack/Altra1L2QPkg/Capsule/SystemFirmwareUpdateConfig/UefiFirmwareUpdateConfig.ini @@ -0,0 +1,21 @@ +## @file +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Head] +NumOfUpdate = 1 +NumOfRecovery = 0 +Update0 = UEFI + +[UEFI] +FirmwareType = 2147483651 # SystemFirmware: 0x80000003 - OEM UEFI +AddressType = 1 # 0 - relative address, 1 - absolute address. +BaseAddress = 0x00000000 # Base address offset on flash +Length = 0x00A10000 # Length +ImageOffset = 0x00000000 # Image offset of this SystemFirmware image +FileGuid = 1e9a10da-e398-4045-810f-4ade92e6cdee # PcdEdkiiSystemFirmwareFileGuid diff --git a/Platform/ASRockRack/Altra1L2QPkg/Readme.md b/Platform/ASRockRack/Altra1L2QPkg/Readme.md new file mode 100644 index 00000000000..a33bca0e681 --- /dev/null +++ b/Platform/ASRockRack/Altra1L2QPkg/Readme.md @@ -0,0 +1,36 @@ +Introduction +============ + +This directory holds the EDK2 and LinuxBoot firmware for the ASRock Rack +AltraD8UD2-1L2Q board. This is a workstation board with an LGA 4926 socket +and supports an Ampere Altra or Altra Max CPU from 32 to 128 cores. + +Building the firmare +-------------------- + +To build EDK2, run the `bld.sh` script. You need a copy of the Ampere +TF-A (ATF) and SCP binaries which are available from Customer Connect +after signing the Ampere NDA. + +Usage: + ./Platform/Ampere/bld.sh [options] + +Options: + -b , --build Specify the build type: DEBUG or RELEASE + -t , --toolchain Specify the toolchain to use: GCC or CLANG + -m , --manufacturer Specify platform manufacturer (e.g. Ampere) + -p , --platform Specify platform to build (e.g. Jade) + -l , --linuxboot Build LinuxBoot firmware instead of full EDK2 with UEFI Shell, specifying path to flashkernel + -f, --flash Copy firmware to BMC and flash firmware (keeping EFI variables and NVPARAMs) after building + -F, --full-flash Copy firmware to BMC and flash full EEPROM (resetting EFI variables and NVPARAMs) after building + + Note: flash options require bmc.sh file with env vars BMC_HOST, BMC_USER and BMC_PASS defined + + Available manufacturers: + Ampere + ASRockRack + + Available platforms: + Ampere -> Jade + ASRockRack -> Altra1L2Q + diff --git a/Platform/ASRockRack/Altra1L2QPkg/firmware.metainfo.xml b/Platform/ASRockRack/Altra1L2QPkg/firmware.metainfo.xml new file mode 100644 index 00000000000..68b9271cfac --- /dev/null +++ b/Platform/ASRockRack/Altra1L2QPkg/firmware.metainfo.xml @@ -0,0 +1,47 @@ + + + com.asrockrack.altrad8ud2-1l2q.firmware + + X-System + + ALTRAD8UD2-1L2Q + Firmware for ASRock Rack ALTRAD8UD2-1L2Q + +

+ Updating the firmware on your ALTRAD8UD2-1L2Q + improves performance and adds new features. +

+ + + f42e6f13-a7a6-4912-9962-ad2734b45c3a + + https://www.asrockrack.com + BSD-2-Clause-Patent + BSD-2-Clause-Patent + + + + https://github.com/tianocore/edk2-platforms + + {RELEASE_NOTES} + + + + + + + + org.freedesktop.fwupd + + + + number + org.uefi.capsule + signed + + + + bios + + diff --git a/Platform/ASRockRack/Altra1L2TPkg/Altra1L2T.dsc b/Platform/ASRockRack/Altra1L2TPkg/Altra1L2T.dsc new file mode 100644 index 00000000000..b775766774f --- /dev/null +++ b/Platform/ASRockRack/Altra1L2TPkg/Altra1L2T.dsc @@ -0,0 +1,421 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = Altra1L2T + PLATFORM_GUID = edc65dea-a173-496a-8ad0-5c96e3fd2079 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001E + OUTPUT_DIRECTORY = Build/Altra1L2T + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/ASRockRack/Altra1L2TPkg/Altra1L2T.fdf + + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=VALUE + # + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNP Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_MANAGEABILITY 0x00800000 // Detailed debug and payload manageability messages + # // related to modules such as Redfish, IPMI, MCTP etc. + # DEBUG_ERROR 0x80000000 // Error +!if $(TARGET) == RELEASE + DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x80000002 +!else + DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x8000004F +!endif + + DEFINE FIRMWARE_VER = 00.01.01-00 + DEFINE FIRMWARE_VER_HEX = 0x00010100 + DEFINE CAPSULE_ENABLE = TRUE + DEFINE INCLUDE_TFA_FW = TRUE + DEFINE SECURE_BOOT_ENABLE = TRUE + DEFINE TPM2_ENABLE = TRUE + DEFINE SHELL_ENABLE = TRUE + DEFINE INCLUDE_TFTP_COMMAND = TRUE + DEFINE PLATFORM_CONFIG_UUID = e268c8df-2676-444d-be6c-7dbd660d72c1 + + # + # Network definition + # + DEFINE NETWORK_ENABLE = TRUE + DEFINE NETWORK_IP6_ENABLE = TRUE + DEFINE NETWORK_HTTP_BOOT_ENABLE = TRUE + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE + DEFINE NETWORK_TLS_ENABLE = TRUE + DEFINE REDFISH_ENABLE = TRUE + DEFINE PERFORMANCE_MEASUREMENT_ENABLE = FALSE + DEFINE HEAP_GUARD_ENABLE = FALSE + +!if $(CAPSULE_ENABLE) == TRUE + DEFINE UEFI_IMAGE = Build/Altra1L2T/altra1l2q_uefi.bin + DEFINE TFA_UEFI_IMAGE = Build/Altra1L2T/altra1l2q_tfa_uefi.bin +!endif + +!include MdePkg/MdeLibs.dsc.inc + +# Include default Ampere Platform DSC file +!include Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc + +################################################################################ +# +# Specific Platform Library +# +################################################################################ +[LibraryClasses] + + OemMiscLib|Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/OemMiscLib.inf + JedecJep106Lib|MdePkg/Library/JedecJep106Lib/JedecJep106Lib.inf + + # + # ACPI Libraries + # + AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf + + # + # EFI Redfish drivers + # +!if $(NETWORK_ENABLE) == TRUE +!if $(REDFISH_ENABLE) == TRUE + RedfishContentCodingLib|RedfishPkg/Library/RedfishContentCodingLibNull/RedfishContentCodingLibNull.inf + RedfishPlatformHostInterfaceLib|RedfishPkg/Library/PlatformHostInterfaceLibNull/PlatformHostInterfaceLibNull.inf +!endif +!endif + + # + # Pcie Board + # + BoardPcieLib|Platform/ASRockRack/AltraBoardPkg/Library/BoardPcieLib/BoardPcieLib.inf + + IOExpanderLib|Platform/Ampere/JadePkg/Library/IOExpanderLib/IOExpanderLib.inf + + PlatformBmcReadyLib|Platform/Ampere/JadePkg/Library/PlatformBmcReadyLib/PlatformBmcReadyLib.inf + LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf + + # + # RTC Library: Common RTC + # + RealTimeClockLib|Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208RealTimeClockLib.inf + + # + # EFI Redfish drivers + # +!if $(REDFISH_ENABLE) == TRUE + RedfishContentCodingLib|RedfishPkg/Library/RedfishContentCodingLibNull/RedfishContentCodingLibNull.inf + RedfishPlatformHostInterfaceLib|RedfishPkg/Library/PlatformHostInterfaceBmcUsbNicLib/PlatformHostInterfaceBmcUsbNicLib.inf +!endif + +################################################################################ +# +# Specific Platform Pcds +# +################################################################################ +[PcdsFeatureFlag.common] + # + # Activate AcpiSdtProtocol + # + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + # + # Flag to indicate option of using default or specific platform Port Map table + # + gAmpereTokenSpaceGuid.PcdPcieHotPlugPortMapTable.UseDefaultConfig|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE + +[PcdsFixedAtBuild] + + gAmpereTokenSpaceGuid.PcdPcieHotPlugGpioResetMap|0x3F + + # + # Setting Portmap table + # + # * Elements of array: + # - 0: Index of Portmap entry in Portmap table structure (Vport). + # - 1: Socket number (Socket). + # - 2: Root complex port for each Portmap entry (RcaPort). + # - 3: Root complex sub-port for each Portmap entry (RcaSubPort). + # - 4: Select output port of IO expander (PinPort). + # - 5: I2C address of IO expander that CPLD backplane simulates (I2cAddress). + # - 6: Address of I2C switch between CPU and CPLD backplane (MuxAddress). + # - 7: Channel of I2C switch (MuxChannel). + # - 8: It is set from PcieHotPlugSetGPIOMapCmd () function to select GPIO[16:21] (PcdPcieHotPlugGpioResetMap) or I2C for PCIe reset purpose. + # - 9: Segment of root complex (Segment). + # - 10: SSD slot index on the front panel of backplane (DriveIndex). + # + # * Caution: + # - The last array ({ 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xFF }) require if no fully structured used. + # - Size of Portmap table: PortMap[MAX_PORTMAP_ENTRY][sizeof(PCIE_HOTPLUG_PORTMAP_ENTRY)] <=> PortMap[96][11]. + # * Example: Bellow configuration is the configuration for Portmap table of Mt. Jade 2U platform. + # + gAmpereTokenSpaceGuid.PcdPcieHotPlugPortMapTable.PortMap[0]|{ 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xFF } # Require if no fully structure used + + gAmpereTokenSpaceGuid.PcdSmbusI2cBusSpeed|100000 + + # We should support CoD in future, since it provides a nicer + # upgrade experience (e.g. a progress bar). + gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleOnDiskSupport|FALSE + +!if $(SECURE_BOOT_ENABLE) == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdRsa2048Sha256PublicKeyBuffer|{0} + !include Platform/ASRockRack/Altra1L2TPkg/root.cer.gEfiSecurityPkgTokenSpaceGuid.PcdPkcs7CertBuffer.inc +!endif + + gAmpereTokenSpaceGuid.PcdFirmwareVersionNumber|$(FIRMWARE_VER_HEX) + +[PcdsFixedAtBuild.common] + # + # Platform config UUID + # + gAmpereTokenSpaceGuid.PcdPlatformConfigUuid|"$(PLATFORM_CONFIG_UUID)" + + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x307 + + # Clearing BIT0 in this PCD prevents installing a 32-bit SMBIOS entry point, + # if the entry point version is >= 3.0. AARCH64 OSes cannot assume the + # presence of the 32-bit entry point anyway (because many AARCH64 systems + # don't have 32-bit addressable physical RAM), and the additional allocations + # below 4 GB needlessly fragment the memory map. So expose the 64-bit entry + # point only, for entry point versions >= 3.0. + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 + +!if $(SECURE_BOOT_ENABLE) == TRUE + # Override the default values from SecurityPkg to ensure images + # from all sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04 +!endif + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragments for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 +!if $(SECURE_BOOT_ENABLE) == TRUE + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|600 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1500 +!else + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|300 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|150 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1000 +!endif + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|12000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + # + # Enable strict image permissions for all images. (This applies + # only to images that were built with >= 4 KB section alignment.) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3 + + # + # Enable NX memory protection for all non-code regions, including OEM and OS + # reserved ones, with the exception of LoaderData regions, of which OS loaders + # (e.g., GRUB) may assume that its contents are executable. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD5 + + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard|TRUE + +!if $(HEAP_GUARD_ENABLE) == TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPageType|0xC000000000007B9E + gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPoolType|0xC000000000007B9E + gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask|0x0F +!endif + +[PcdsDynamicDefault.common.DEFAULT] + # SMBIOS Type 0 - BIOS Information + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"ASRock Rack Inc." + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString|L"MM/DD/YYYY" + +[PcdsDynamicExDefault.common.DEFAULT] + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100 + gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{GUID("731cbc77-cce1-4ec2-b79a-265470b332f1")}|VOID*|0x10 + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{GUID("a4c7d17d-491f-4be6-a261-ed5d9d36de42")}|VOID*|0x10 + + # Default Video Resolution + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0 # 0 - Maximum + # Setup Video Resolution + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|0 # 0 - Maximum + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|0 # 0 - Maximum + +[PcdsPatchableInModule] + # + # Console Resolution (HD mode) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|768 + +################################################################################ +# +# Specific Platform Component +# +################################################################################ +[Components.common] + # + # ACPI + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2B + } + Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf + Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/Ac01AcpiTables.inf + Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/Ac02AcpiTables.inf + + # + # PCIe + # + Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf + + !if $(NETWORK_ENABLE) == TRUE + # Intel I210 + !if $(INTEL_UNDI_BIN) == TRUE + IntelUndiBin/GigUndiBinRelease.inf + !endif + # For the Redfish USB CDC connection to the BMC + MdeModulePkg/Bus/Usb/UsbNetwork/NetworkCommon/NetworkCommon.inf + MdeModulePkg/Bus/Usb/UsbNetwork/UsbCdcEcm/UsbCdcEcm.inf + !endif + + # + # Renesas PD720202 XHCI firmware uploader + # +!ifdef $(USB_UPD720202_ROM_FILE) + Drivers/OptionRomPkg/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf { + + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + } +!endif + + # + # VGA Aspeed + # + Drivers/ASpeed/ASpeedGopBinPkg/ASpeedAst2500GopDxe.inf + + # + # SMBIOS + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + ManageabilityPkg/Universal/IpmiBlobTransferDxe/IpmiBlobTransferDxe.inf + Features/ManageabilityPkg/Universal/IpmiProtocol/Dxe/IpmiProtocolDxe.inf + + # + # HII + # + Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf + Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf + Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf + Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.inf + Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.inf + Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.inf + Silicon/Ampere/AmpereSiliconPkg/Drivers/BmcConfigDxe/BmcConfigDxe.inf + + # + # Firmware Capsule Update + # +!if $(CAPSULE_ENABLE) == TRUE + Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf + MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf + MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf { + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf + } + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf + } + MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + + # + # System Firmware Update + # + Silicon/Ampere/AmpereAltraPkg/Drivers/SystemFirmwareUpdateDxe/SystemFirmwareUpdateDxe.inf +!endif + + # Redfish + # +!if $(NETWORK_ENABLE) == TRUE + SecurityPkg/Hash2DxeCrypto/Hash2DxeCrypto.inf + !if $(REDFISH_ENABLE) == TRUE + !include RedfishPkg/Redfish.dsc.inc + !endif +!endif + + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + + # Multi-Processor Support + ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.inf + +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf +!if $(SHELL_ENABLE) == TRUE + ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } +!endif +!endif + + # + # OpRom emulator + # +!if $(X86_EMULATOR_ENABLE) == TRUE + Emulator/X86EmulatorDxe/X86EmulatorDxe.inf +!endif diff --git a/Platform/ASRockRack/Altra1L2TPkg/Altra1L2T.fdf b/Platform/ASRockRack/Altra1L2TPkg/Altra1L2T.fdf new file mode 100644 index 00000000000..fca4453be26 --- /dev/null +++ b/Platform/ASRockRack/Altra1L2TPkg/Altra1L2T.fdf @@ -0,0 +1,520 @@ +## @file +# +# Copyright (c) 2020 - 2022, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +# Note: We have 10MB (0x00A0'0000 bytes) for UEFI. +# +# If this 10MB is ever changed, Altra1L2TCapsule.fdf and +# Capsule/HostFirmwareDescriptor/HostFirmwareDescriptor.aslc need +# updated too. + +[FD.BL33_ALTRA1L2T_UEFI] +BaseAddress = 0x92000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x00A00000 # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x10000|gAmpereTokenSpaceGuid.PcdFvBlockSize +NumBlocks = 0xA0 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +# +# FV MAIN +# Offset: 0x00000000 +# Size: 0x00900000 +# +0x00000000|0x00900000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + +# +# NV Variables +# Offset: 0x00900000 +# Size: 0x00100000 +# +0x00900000|0x00070000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x80000 + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x2D, 0x09, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x7 Blocks * 0x10000 Bytes / Block + 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + # It is compatible with SECURE_BOOT_ENABLE == FALSE as well. + # Signature: gEfiAuthenticatedVariableGuid = + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, + # Size: 0xB0000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xAFFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xFF, 0x06, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x00970000|0x00020000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 Size: 0x10000 - 0x20 (FTW_WORKING_HEADER) = 0xFFE0 + 0xE0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x00990000|0x00070000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 61C0F511-A691-4F54-974F-B9A42172CE53 + +APRIORI PEI { + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/SmbusHc/SmbusHcPei.inf + INF ManageabilityPkg/Universal/IpmiProtocol/Pei/IpmiPpiPei.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf +} + +!if $(CAPSULE_ENABLE) == TRUE + INF RuleOverride = FMP_IMAGE_DESC Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf +!endif + + INF ArmPlatformPkg/Sec/Sec.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf +!endif + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressPeim/BootProgressPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Universal/CapsuleOnDiskLoadPei/CapsuleOnDiskLoadPei.inf + INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.inf + + # + # IPMI SSIF + # + INF Silicon/Ampere/AmpereAltraPkg/Drivers/SmbusHc/SmbusHcPei.inf + INF ManageabilityPkg/Universal/IpmiProtocol/Pei/IpmiPpiPei.inf + + # + # Print platform information before passing control into the Driver Execution Environment (DXE) phase + # + INF Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.inf + + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + +!if $(TPM2_ENABLE) == TRUE + INF MdeModulePkg/Universal/ResetSystemPei/ResetSystemPei.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/Tcg2Pei/Tcg2Pei.inf +!endif + +[FV.FvMain] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 5C60F367-A505-419A-859E-2A4FF6CA6FE5 + +APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf +} + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressDxe/BootProgressDxe.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) == TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf + INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf + + !include ArmPlatformPkg/SecureBootDefaultKeys.fdf.inc +!endif + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf + INF ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.inf + +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf +!endif + + # + # Environment Variables Protocol + # + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # + # Timer + # + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + # + # Watchdog Timer + # + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + + # + # ARM GIC Dxe + # + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # SCSI Bus and Disk Driver + # + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + + # + # SATA Support + # + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + + # + # NVME Support + # + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # + # USB Support + # + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # PCIe Support + # + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf + + !if $(NETWORK_ENABLE) == TRUE + INF SecurityPkg/Hash2DxeCrypto/Hash2DxeCrypto.inf + # Intel I210 + !if $(INTEL_UNDI_BIN) == TRUE + INF IntelUndiBin/GigUndiBinRelease.inf + !endif + INF MdeModulePkg/Bus/Usb/UsbNetwork/NetworkCommon/NetworkCommon.inf + INF MdeModulePkg/Bus/Usb/UsbNetwork/UsbCdcEcm/UsbCdcEcm.inf + !endif + + # + # VGA Aspeed + # + INF Drivers/ASpeed/ASpeedGopBinPkg/ASpeedAst2500GopDxe.inf + + # + # Random Number Generator Support + # + INF Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.inf + + # + # IPMI SSIF + # + INF Silicon/Ampere/AmpereAltraPkg/Drivers/SmbusHc/SmbusHcDxe.inf + INF ManageabilityPkg/Universal/IpmiProtocol/Dxe/IpmiProtocolDxe.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # +!if $(SHELL_ENABLE) == TRUE + INF ShellPkg/Application/Shell/Shell.inf +!if $(INCLUDE_TFTP_COMMAND) == TRUE + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +!endif +!if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE + INF ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf +!endif +!endif + +!if $(TPM2_ENABLE) == TRUE + INF Silicon/Ampere/AmpereAltraPkg/Drivers/Tcg2Dxe/Tcg2Dxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/Tcg2Config/Tcg2ConfigDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/Tcg2AcpiDxe/Tcg2AcpiDxe.inf + INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf +!endif + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + INF MdeModulePkg/Universal/BootManagerPolicyDxe/BootManagerPolicyDxe.inf + INF Silicon/Ampere/AmpereSiliconPkg/Drivers/PlatformBootManagerDxe/PlatformBootManagerDxe.inf + INF Silicon/Ampere/AmpereSiliconPkg/Drivers/IpmiBootDxe/IpmiBootDxe.inf + + # + # Networking stack + # +!if $(NETWORK_ENABLE) == TRUE + !include NetworkPkg/Network.fdf.inc +!endif + + # + # ACPI + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf + INF RuleOverride=ACPITABLE Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf + INF RuleOverride=ACPITABLE Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/Ac01AcpiTables.inf + INF RuleOverride=ACPITABLE Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/Ac02AcpiTables.inf + + # + # SMBIOS + # + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + INF ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + INF Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + INF ManageabilityPkg/Universal/IpmiBlobTransferDxe/IpmiBlobTransferDxe.inf + + # + # Firmware Capsule Update + # +!if $(CAPSULE_ENABLE) == TRUE + INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf + INF MdeModulePkg/Universal/EsrtFmpDxe/EsrtFmpDxe.inf + INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf +!endif + + # + # HII + # + INF Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.inf + INF Silicon/Ampere/AmpereSiliconPkg/Drivers/BmcConfigDxe/BmcConfigDxe.inf + + INF MdeModulePkg/Logo/LogoDxe.inf + + # + # Emulator for x64 OpRoms, etc. + # +!if $(X86_EMULATOR_ENABLE) == TRUE + INF Emulator/X86EmulatorDxe/X86EmulatorDxe.inf +!endif + + # + # EFI Redfish drivers + # +!if $(NETWORK_ENABLE) == TRUE + !if $(REDFISH_ENABLE) == TRUE + !include RedfishPkg/Redfish.fdf.inc + !endif +!endif + + # + # Renesas PD720202 XHCI firmware uploader, requires firmware image + # in directory $(WORKSPACE) + # +!ifdef $(USB_UPD720202_ROM_FILE) + INF Drivers/OptionRomPkg/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf + FILE FREEFORM = A059EBC4-D73D-4279-81BF-E4A89308B923 { + SECTION RAW = $(WORKSPACE)/K2026090.mem + } +!endif + +[FV.SystemFirmwareDescriptor] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF RuleOverride = FMP_IMAGE_DESC Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf + +[FV.CapsuleDispatchFv] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf + +!include Silicon/Ampere/AmpereSiliconPkg/FvRules.fdf.inc diff --git a/Platform/ASRockRack/Altra1L2TPkg/Altra1L2TBoardSetting.cfg b/Platform/ASRockRack/Altra1L2TPkg/Altra1L2TBoardSetting.cfg new file mode 100644 index 00000000000..b3c3665eb86 --- /dev/null +++ b/Platform/ASRockRack/Altra1L2TPkg/Altra1L2TBoardSetting.cfg @@ -0,0 +1,275 @@ +## +# ALTRAD8UD-1L2T Board Setting +# +# This is a collection of board and hardware configurations +# for an Altra-based ARM64 platform. It is stored in the persistent storage. +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# Name, offset (hex), value +# value can be hex or decimal +# + +NV_SI_RO_BOARD_VENDOR, 0x0000, 0x0000CD3A +NV_SI_RO_BOARD_TYPE, 0x0008, 0x00000000 +NV_SI_RO_BOARD_REV, 0x0010, 0x00000000 +NV_SI_RO_BOARD_CFG, 0x0018, 0x00000000 +NV_SI_RO_BOARD_S0_DIMM_AVAIL, 0x0020, 0x0000FFFF +NV_SI_RO_BOARD_S1_DIMM_AVAIL, 0x0028, 0x0000FFFF +NV_SI_RO_BOARD_SPI0CS0_FREQ_KHZ, 0x0030, 0x000080E8 +NV_SI_RO_BOARD_SPI0CS1_FREQ_KHZ, 0x0038, 0x000080E8 +NV_SI_RO_BOARD_SPI1CS0_FREQ_KHZ, 0x0040, 0x00002710 +NV_SI_RO_BOARD_SPI1CS1_FREQ_KHZ, 0x0048, 0x00002710 +NV_SI_RO_BOARD_TPM_LOC, 0x0050, 0x00000000 +NV_SI_RO_BOARD_I2C0_FREQ_KHZ, 0x0058, 0x00000190 +NV_SI_RO_BOARD_I2C1_FREQ_KHZ, 0x0060, 0x00000190 +NV_SI_RO_BOARD_I2C2_10_FREQ_KHZ, 0x0068, 0x00000190 +NV_SI_RO_BOARD_I2C3_FREQ_KHZ, 0x0070, 0x00000190 +NV_SI_RO_BOARD_I2C9_FREQ_KHZ, 0x0078, 0x00000190 +NV_SI_RO_BOARD_2P_CFG, 0x0080, 0xFFFFFFFF +# TODO +NV_SI_RO_BOARD_S0_RCA0_CFG, 0x0088, 0x00000004 +# TODO +NV_SI_RO_BOARD_S0_RCA1_CFG, 0x0090, 0x00000004 +NV_SI_RO_BOARD_S0_RCA2_CFG, 0x0098, 0x00000004 +NV_SI_RO_BOARD_S0_RCA3_CFG, 0x00A0, 0x00000004 +NV_SI_RO_BOARD_S0_RCB0_LO_CFG, 0x00A8, 0x00020002 +NV_SI_RO_BOARD_S0_RCB0_HI_CFG, 0x00B0, 0x00020002 +NV_SI_RO_BOARD_S0_RCB1_LO_CFG, 0x00B8, 0x00020002 +NV_SI_RO_BOARD_S0_RCB1_HI_CFG, 0x00C0, 0x00020002 +NV_SI_RO_BOARD_S0_RCB2_LO_CFG, 0x00C8, 0x00020002 +NV_SI_RO_BOARD_S0_RCB2_HI_CFG, 0x00D0, 0x00000003 +NV_SI_RO_BOARD_S0_RCB3_LO_CFG, 0x00D8, 0x00000003 +NV_SI_RO_BOARD_S0_RCB3_HI_CFG, 0x00E0, 0x00020002 +NV_SI_RO_BOARD_S1_RCA0_CFG, 0x00E8, 0x00000000 +NV_SI_RO_BOARD_S1_RCA1_CFG, 0x00F0, 0x00000000 +NV_SI_RO_BOARD_S1_RCA2_CFG, 0x00F8, 0x02020202 +NV_SI_RO_BOARD_S1_RCA3_CFG, 0x0100, 0x00030003 +NV_SI_RO_BOARD_S1_RCB0_LO_CFG, 0x0108, 0x00000003 +NV_SI_RO_BOARD_S1_RCB0_HI_CFG, 0x0110, 0x00020002 +NV_SI_RO_BOARD_S1_RCB1_LO_CFG, 0x0118, 0x00020002 +NV_SI_RO_BOARD_S1_RCB1_HI_CFG, 0x0120, 0x00000003 +NV_SI_RO_BOARD_S1_RCB2_LO_CFG, 0x0128, 0x00020002 +NV_SI_RO_BOARD_S1_RCB2_HI_CFG, 0x0130, 0x00020002 +NV_SI_RO_BOARD_S1_RCB3_LO_CFG, 0x0138, 0x00020002 +NV_SI_RO_BOARD_S1_RCB3_HI_CFG, 0x0140, 0x00020002 +NV_SI_RO_BOARD_T_LTLM_DELTA_P0, 0x0148, 0x00000001 +NV_SI_RO_BOARD_T_LTLM_DELTA_P1, 0x0150, 0x00000002 +NV_SI_RO_BOARD_T_LTLM_DELTA_P2, 0x0158, 0x00000003 +NV_SI_RO_BOARD_T_LTLM_DELTA_P3, 0x0160, 0x00000004 +NV_SI_RO_BOARD_T_LTLM_DELTA_M1, 0x0168, 0xFFFFFFFF +NV_SI_RO_BOARD_T_LTLM_DELTA_M2, 0x0170, 0xFFFFFFFE +NV_SI_RO_BOARD_T_LTLM_DELTA_M3, 0x0178, 0xFFFFFFFD +NV_SI_RO_BOARD_P_LM_PID_P, 0x0180, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_I, 0x0188, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_I_L_THOLD, 0x0190, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_I_H_THOLD, 0x0198, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_D, 0x01A0, 0x00000000 +NV_SI_RO_BOARD_P_LM_EXP_SMOOTH_CONST, 0x01A8, 0x00000000 +NV_SI_RO_BOARD_TPM_ALG_ID, 0x01B0, 0x00000002 +NV_SI_RO_BOARD_DDR_SPEED_GRADE, 0x01B8, 0x00000C80 +NV_SI_RO_BOARD_DDR_S0_RTT_WR, 0x01C0, 0x20020000 +NV_SI_RO_BOARD_DDR_S1_RTT_WR, 0x01C8, 0x20020000 +NV_SI_RO_BOARD_DDR_S0_RTT_NOM, 0x01D0, 0x31060177 +NV_SI_RO_BOARD_DDR_S1_RTT_NOM, 0x01D8, 0x31060177 +NV_SI_RO_BOARD_DDR_S0_RTT_PARK, 0x01E0, 0x30060070 +NV_SI_RO_BOARD_DDR_S1_RTT_PARK, 0x01E8, 0x30060070 +NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_1DPC, 0x01F0, 0x00000000 +NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_1DPC, 0x01F8, 0x00000000 +NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_1DPC, 0x0200, 0x00000000 +NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_1DPC, 0x0208, 0x00000000 +NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_2DPC, 0x0210, 0x044C0CCC +NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_2DPC, 0x0218, 0x084C0CCC +NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_2DPC, 0x0220, 0x04130333 +NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_2DPC, 0x0228, 0x08130333 +NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_1DPC, 0x0230, 0x01130333 +NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_1DPC, 0x0238, 0x02230333 +NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_1DPC, 0x0240, 0x01430333 +NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_1DPC, 0x0248, 0x02830333 +NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_2DPC, 0x0250, 0x055EDEED +NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_2DPC, 0x0258, 0x0A5DEDDE +NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_2DPC, 0x0260, 0x055B7BB7 +NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_2DPC, 0x0268, 0x0A57B77B +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_1DPC, 0x0270, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_1DPC, 0x0278, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_1DPC, 0x0280, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_1DPC, 0x0288, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_2DPC, 0x0290, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_2DPC, 0x0298, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_2DPC, 0x02A0, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_2DPC, 0x02A8, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_1DPC, 0x02B0, 0x00000024 +NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_1DPC, 0x02B8, 0x001A001A +NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_2DPC, 0x02C0, 0x00000050 +NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_2DPC, 0x02C8, 0x00240020 +NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_DEFAULT, 0x02D0, 0x02800280 +NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_DEFAULT, 0x02D8, 0x90909090 +NV_SI_RO_BOARD_DDR_WRDQS_SHIFT_DEFAULT, 0x02E0, 0x00000000 +NV_SI_RO_BOARD_DDR_ADCMD_DLY_DEFAULT, 0x02E8, 0x00C000C0 +NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_ADJ, 0x02F0, 0x00000000 +NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_ADJ, 0x02F8, 0x00000000 +NV_SI_RO_BOARD_DDR_PHY_VREF_ADJ, 0x0300, 0x00000000 +NV_SI_RO_BOARD_DDR_DRAM_VREF_ADJ, 0x0308, 0x00000000 +NV_SI_RO_BOARD_DDR_WR_PREAMBLE_CYCLE, 0x0310, 0x02010201 +NV_SI_RO_BOARD_DDR_ADCMD_2T_MODE, 0x0318, 0x00000000 +NV_SI_RO_BOARD_I2C_VRD_CONFIG_INFO, 0x0320, 0x00000000 +NV_SI_RO_BOARD_DDR_PHY_FEATURE_CTRL, 0x0328, 0x00000000 +NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_ACCESS, 0x0330, 0x01050106 +NV_SI_RO_BOARD_DIMM_TEMP_THRESHOLD, 0x0338, 0x000005F4 +NV_SI_RO_BOARD_DIMM_SPD_COMPARE_DISABLE, 0x0340, 0x00000000 +NV_SI_RO_BOARD_S0_PCIE_CLK_CFG, 0x0348, 0x00000000 +NV_SI_RO_BOARD_S0_RCA4_CFG, 0x0350, 0x02020202 +NV_SI_RO_BOARD_S0_RCA5_CFG, 0x0358, 0x02020202 +NV_SI_RO_BOARD_S0_RCA6_CFG, 0x0360, 0x02020202 +NV_SI_RO_BOARD_S0_RCA7_CFG, 0x0368, 0x00030003 +NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET, 0x0370, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET, 0x0378, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET, 0x0380, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET, 0x0388, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCB0A_TXRX_G3PRESET, 0x0390, 0x00000000 +NV_SI_RO_BOARD_S0_RCB0B_TXRX_G3PRESET, 0x0398, 0x00000000 +NV_SI_RO_BOARD_S0_RCB1A_TXRX_G3PRESET, 0x03A0, 0x00000000 +NV_SI_RO_BOARD_S0_RCB1B_TXRX_G3PRESET, 0x03A8, 0x00000000 +NV_SI_RO_BOARD_S0_RCB2A_TXRX_G3PRESET, 0x03B0, 0x00000000 +NV_SI_RO_BOARD_S0_RCB2B_TXRX_G3PRESET, 0x03B8, 0x00000000 +NV_SI_RO_BOARD_S0_RCB3A_TXRX_G3PRESET, 0x03C0, 0x00000000 +NV_SI_RO_BOARD_S0_RCB3B_TXRX_G3PRESET, 0x03C8, 0x00000000 +NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET, 0x03D0, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET, 0x03D8, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET, 0x03E0, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET, 0x03E8, 0xFFFFFFFF +NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET, 0x03F0, 0x57575757 +NV_SI_RO_BOARD_S0_RCA1_TXRX_G4PRESET, 0x03F8, 0x57575757 +NV_SI_RO_BOARD_S0_RCA2_TXRX_G4PRESET, 0x0400, 0x57575757 +NV_SI_RO_BOARD_S0_RCA3_TXRX_G4PRESET, 0x0408, 0x57575757 +NV_SI_RO_BOARD_S0_RCB0A_TXRX_G4PRESET, 0x0410, 0x57575757 +NV_SI_RO_BOARD_S0_RCB0B_TXRX_G4PRESET, 0x0418, 0x57575757 +NV_SI_RO_BOARD_S0_RCB1A_TXRX_G4PRESET, 0x0420, 0x57575757 +NV_SI_RO_BOARD_S0_RCB1B_TXRX_G4PRESET, 0x0428, 0x57575757 +NV_SI_RO_BOARD_S0_RCB2A_TXRX_G4PRESET, 0x0430, 0x57575757 +NV_SI_RO_BOARD_S0_RCB2B_TXRX_G4PRESET, 0x0438, 0x57575757 +NV_SI_RO_BOARD_S0_RCB3A_TXRX_G4PRESET, 0x0440, 0x57575757 +NV_SI_RO_BOARD_S0_RCB3B_TXRX_G4PRESET, 0x0448, 0x57575757 +NV_SI_RO_BOARD_S0_RCA4_TXRX_G4PRESET, 0x0450, 0x57575757 +NV_SI_RO_BOARD_S0_RCA5_TXRX_G4PRESET, 0x0458, 0x57575757 +NV_SI_RO_BOARD_S0_RCA6_TXRX_G4PRESET, 0x0460, 0x57575757 +NV_SI_RO_BOARD_S0_RCA7_TXRX_G4PRESET, 0x0468, 0x57575757 +NV_SI_RO_BOARD_S1_PCIE_CLK_CFG, 0x0470, 0x00000000 +NV_SI_RO_BOARD_S1_RCA4_CFG, 0x0478, 0x00030003 +NV_SI_RO_BOARD_S1_RCA5_CFG, 0x0480, 0x02020202 +NV_SI_RO_BOARD_S1_RCA6_CFG, 0x0488, 0x02020202 +NV_SI_RO_BOARD_S1_RCA7_CFG, 0x0490, 0x02020202 +NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET, 0x0498, 0xFFFFFFFF +NV_SI_RO_BOARD_S1_RCA3_TXRX_G3PRESET, 0x04A0, 0xFFFFFFFF +NV_SI_RO_BOARD_S1_RCB0A_TXRX_G3PRESET, 0x04A8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB0B_TXRX_G3PRESET, 0x04B0, 0x00000000 +NV_SI_RO_BOARD_S1_RCB1A_TXRX_G3PRESET, 0x04B8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB1B_TXRX_G3PRESET, 0x04C0, 0x00000000 +NV_SI_RO_BOARD_S1_RCB2A_TXRX_G3PRESET, 0x04C8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB2B_TXRX_G3PRESET, 0x04D0, 0x00000000 +NV_SI_RO_BOARD_S1_RCB3A_TXRX_G3PRESET, 0x04D8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB3B_TXRX_G3PRESET, 0x04E0, 0x00000000 +NV_SI_RO_BOARD_S1_RCA4_TXRX_G3PRESET, 0x04E8, 0xFFFFFFFF +NV_SI_RO_BOARD_S1_RCA5_TXRX_G3PRESET, 0x04F0, 0xFFFFFFFF +NV_SI_RO_BOARD_S1_RCA6_TXRX_G3PRESET, 0x04F8, 0xFFFFFFFF +NV_SI_RO_BOARD_S1_RCA7_TXRX_G3PRESET, 0x0500, 0xFFFFFFFF +NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET, 0x0508, 0x57575757 +NV_SI_RO_BOARD_S1_RCA3_TXRX_G4PRESET, 0x0510, 0x57575757 +NV_SI_RO_BOARD_S1_RCB0A_TXRX_G4PRESET, 0x0518, 0x57575757 +NV_SI_RO_BOARD_S1_RCB0B_TXRX_G4PRESET, 0x0520, 0x57575757 +NV_SI_RO_BOARD_S1_RCB1A_TXRX_G4PRESET, 0x0528, 0x57575757 +NV_SI_RO_BOARD_S1_RCB1B_TXRX_G4PRESET, 0x0530, 0x57575757 +NV_SI_RO_BOARD_S1_RCB2A_TXRX_G4PRESET, 0x0538, 0x57575757 +NV_SI_RO_BOARD_S1_RCB2B_TXRX_G4PRESET, 0x0540, 0x57575757 +NV_SI_RO_BOARD_S1_RCB3A_TXRX_G4PRESET, 0x0548, 0x57575757 +NV_SI_RO_BOARD_S1_RCB3B_TXRX_G4PRESET, 0x0550, 0x57575757 +NV_SI_RO_BOARD_S1_RCA4_TXRX_G4PRESET, 0x0558, 0x57575757 +NV_SI_RO_BOARD_S1_RCA5_TXRX_G4PRESET, 0x0560, 0x57575757 +NV_SI_RO_BOARD_S1_RCA6_TXRX_G4PRESET, 0x0568, 0x57575757 +NV_SI_RO_BOARD_S1_RCA7_TXRX_G4PRESET, 0x0570, 0x57575757 +NV_SI_RO_BOARD_2P_CE_MASK_THRESHOLD, 0x0578, 0x00000003 +NV_SI_RO_BOARD_2P_CE_MASK_INTERVAL, 0x0580, 0x000001A4 +NV_SI_RO_BOARD_SX_PHY_CFG_SETTING, 0x0588, 0x00000000 +NV_SI_RO_BOARD_DDR_PHY_DC_CLK, 0x0590, 0x00018000 +NV_SI_RO_BOARD_DDR_PHY_DC_DATA, 0x0598, 0x80018000 +NV_SI_RO_BOARD_SX_RCA0_TXRX_20GPRESET, 0x05A0, 0x00000000 +NV_SI_RO_BOARD_SX_RCA1_TXRX_20GPRESET, 0x05A8, 0x00000000 +NV_SI_RO_BOARD_SX_RCA2_TXRX_20GPRESET, 0x05B0, 0x00000000 +NV_SI_RO_BOARD_SX_RCA3_TXRX_20GPRESET, 0x05B8, 0x00000000 +NV_SI_RO_BOARD_SX_RCA0_TXRX_25GPRESET, 0x05C0, 0x00000000 +NV_SI_RO_BOARD_SX_RCA1_TXRX_25GPRESET, 0x05C8, 0x00000000 +NV_SI_RO_BOARD_SX_RCA2_TXRX_25GPRESET, 0x05D0, 0x00000000 +NV_SI_RO_BOARD_SX_RCA3_TXRX_25GPRESET, 0x05D8, 0x00000000 +NV_SI_RO_BOARD_DDR_2X_REFRESH_TEMP_THRESHOLD, 0x05E0, 0x00550055 +NV_SI_RO_BOARD_PCP_VRD_VOUT_WAIT_US, 0x05E8, 0x00000064 +NV_SI_RO_BOARD_PCP_VRD_VOUT_RESOLUTION_MV, 0x05F0, 0x00000005 +NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_EN, 0x05F8, 0x00000001 +NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_TIME, 0x0600, 0x00000002 +NV_SI_RO_BOARD_DVFS_VOUT_20MV_RAMP_TIME_US, 0x0608, 0x00000005 +NV_SI_RO_BOARD_PCIE_AER_FW_FIRST, 0x0610, 0x00000000 +NV_SI_RO_BOARD_RTC_GPI_LOCK_BYPASS, 0x0618, 0x00000000 +NV_SI_RO_BOARD_TPM_DISABLE, 0x0620, 0x00000000 +NV_SI_RO_BOARD_MESH_S0_CXG_RC_STRONG_ORDERING_EN, 0x0628, 0x00000000 +NV_SI_RO_BOARD_MESH_S1_CXG_RC_STRONG_ORDERING_EN, 0x0630, 0x00000000 +NV_SI_RO_BOARD_GPIO_SW_WATCHDOG_EN, 0x0638, 0x00000000 +NV_SI_RO_BOARD_PCIE_HP_DISABLE, 0x0640, 0x00000000 +NV_SI_RO_BOARD_I2C_VRD_VOUT_FORMAT, 0x0648, 0x00000000 +NV_SI_RO_BOARD_I2C_VRD_SMBUS_CMD_FLAGS, 0x0650, 0x00000000 +NV_SI_RO_BOARD_CUST_SPM_LOCATION, 0x0658, 0x00000000 +NV_SI_RO_BOARD_RAS_DDR_CE_WINDOW, 0x0660, 0x00000000 +NV_SI_RO_BOARD_RAS_DDR_CE_TH1, 0x0668, 0x000001F4 +NV_SI_RO_BOARD_RAS_DDR_CE_TH2, 0x0670, 0x00001388 +NV_SI_RO_BOARD_RAS_DDR_CE_THC, 0x0678, 0x00000000 +NV_SI_RO_BOARD_MQ_SX_RCA0_TXRX_20GPRESET, 0x0680, 0x00000000 +NV_SI_RO_BOARD_MQ_SX_RCA1_TXRX_20GPRESET, 0x0688, 0x00000000 +NV_SI_RO_BOARD_MQ_SX_RCA0_TXRX_25GPRESET, 0x0690, 0x00000000 +NV_SI_RO_BOARD_MQ_SX_RCA1_TXRX_25GPRESET, 0x0698, 0x00000000 +NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G3PRESET, 0x06A0, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA1_TXRX_G3PRESET, 0x06A8, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA2_TXRX_G3PRESET, 0x06B0, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA3_TXRX_G3PRESET, 0x06B8, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA4_TXRX_G3PRESET, 0x06C0, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA5_TXRX_G3PRESET, 0x06C8, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA6_TXRX_G3PRESET, 0x06D0, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA7_TXRX_G3PRESET, 0x06D8, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G3PRESET, 0x06E0, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S1_RCA3_TXRX_G3PRESET, 0x06E8, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S1_RCA4_TXRX_G3PRESET, 0x06F0, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S1_RCA5_TXRX_G3PRESET, 0x06F8, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S1_RCA6_TXRX_G3PRESET, 0x0700, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S1_RCA7_TXRX_G3PRESET, 0x0708, 0xFFFFFFFF +NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G4PRESET, 0x0710, 0x57575757 +NV_SI_RO_BOARD_MQ_S0_RCA1_TXRX_G4PRESET, 0x0718, 0x57575757 +NV_SI_RO_BOARD_MQ_S0_RCA2_TXRX_G4PRESET, 0x0720, 0x57575757 +NV_SI_RO_BOARD_MQ_S0_RCA3_TXRX_G4PRESET, 0x0728, 0x57575757 +NV_SI_RO_BOARD_MQ_S0_RCA4_TXRX_G4PRESET, 0x0730, 0x57575757 +NV_SI_RO_BOARD_MQ_S0_RCA5_TXRX_G4PRESET, 0x0738, 0x57575757 +NV_SI_RO_BOARD_MQ_S0_RCA6_TXRX_G4PRESET, 0x0740, 0x57575757 +NV_SI_RO_BOARD_MQ_S0_RCA7_TXRX_G4PRESET, 0x0748, 0x57575757 +NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G4PRESET, 0x0750, 0x57575757 +NV_SI_RO_BOARD_MQ_S1_RCA3_TXRX_G4PRESET, 0x0758, 0x57575757 +NV_SI_RO_BOARD_MQ_S1_RCA4_TXRX_G4PRESET, 0x0760, 0x57575757 +NV_SI_RO_BOARD_MQ_S1_RCA5_TXRX_G4PRESET, 0x0768, 0x57575757 +NV_SI_RO_BOARD_MQ_S1_RCA6_TXRX_G4PRESET, 0x0770, 0x57575757 +NV_SI_RO_BOARD_MQ_S1_RCA7_TXRX_G4PRESET, 0x0778, 0x57575757 +NV_SI_RO_BOARD_RAS_FLAGS, 0x0780, 0x00000000 +NV_SI_RO_BOARD_DDR_PROGRESS_LOG_CTRL, 0x0788, 0x00000000 +NV_SI_RO_BOARD_2P_ALI_CE_MASK_THRESHOLD, 0x0790, 0x00000001 +NV_SI_RO_BOARD_2P_ALI_CE_MASK_INTERVAL, 0x0798, 0x00000000 +NV_SI_RO_BOARD_RAS_2P_CE_FILTER, 0x07A0, 0x00000000 +NV_SI_RO_BOARD_PCIE_AER_CE_THRESHOLD_EN, 0x07A8, 0x00000000 +NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_TO1, 0x07B0, 0x00000000 +NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_TO2, 0x07B8, 0x00000000 +NV_SI_RO_BOARD_PCIE_AER_CE_THRESHOLD, 0x07C0, 0x00000001 +NV_SI_RO_BOARD_PCIE_AER_CE_INTERVAL, 0x07C8, 0x00000000 +NV_SI_RO_BOARD_I2C_RCA_VRD_VOUT_FORMAT, 0x07D0, 0x00000000 +NV_SI_RO_BOARD_CCIX_MODE_OVERWRITE, 0x07D8, 0x00000000 +NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_MARGIN_MV, 0x07E0, 0x00000000 +NV_SI_RO_BOARD_2P_DPLL, 0x07E8, 0x00000000 +NV_SI_RO_BOARD_RC_DOMAIN_CTRL, 0x07F0, 0x00000000 +NV_SI_RO_BOARD_PCIE_SRIS_MODE, 0x07F8, 0x00000000 diff --git a/Platform/ASRockRack/Altra1L2TPkg/Altra1L2TCapsule.dsc b/Platform/ASRockRack/Altra1L2TPkg/Altra1L2TCapsule.dsc new file mode 100644 index 00000000000..9ff8bed18dd --- /dev/null +++ b/Platform/ASRockRack/Altra1L2TPkg/Altra1L2TCapsule.dsc @@ -0,0 +1,31 @@ +## @file +# +# Copyright (c) 2020 - 2024, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = Altra1L2T + PLATFORM_GUID = edc65dea-a173-496a-8ad0-5c96e3fd2079 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001B + OUTPUT_DIRECTORY = Build/Altra1L2T + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/ASRockRack/Altra1L2TPkg/Altra1L2TCapsule.fdf + + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=VALUE + # + DEFINE INCLUDE_TFA_FW = TRUE + DEFINE UEFI_IMAGE = Build/Altra1L2T/altra1l2t_uefi.bin + DEFINE TFA_UEFI_IMAGE = Build/Altra1L2T/altra1l2t_tfa_uefi.bin diff --git a/Platform/ASRockRack/Altra1L2TPkg/Altra1L2TCapsule.fdf b/Platform/ASRockRack/Altra1L2TPkg/Altra1L2TCapsule.fdf new file mode 100644 index 00000000000..44e546844a3 --- /dev/null +++ b/Platform/ASRockRack/Altra1L2TPkg/Altra1L2TCapsule.fdf @@ -0,0 +1,104 @@ +## @file +# +# Copyright (c) 2020 - 2024, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.ALTRA1L2T_HOST_FIRMWARE_CAPSULE] +BaseAddress = 0x00000000 # The base address of the Firmware in NOR Flash. +!if $(INCLUDE_TFA_FW) == TRUE + Size = 0x00C10000 # The size in bytes of the FLASH Device +!else + Size = 0x00A10000 +!endif +ErasePolarity = 1 + +0x00000000|0x00010000 +FILE = $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/SYSTEMFIRMWAREDESCRIPTOR.Fv + +!if $(INCLUDE_TFA_FW) == TRUE + 0x00010000|0x00C00000 + FILE = $(TFA_UEFI_IMAGE) +!else + 0x00010000|0x00A00000 + FILE = $(UEFI_IMAGE) +!endif + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.HostFirmwareUpdateCargo] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +FILE RAW = a4c7d17d-491f-4be6-a261-ed5d9d36de42 { # PcdEdkiiSystemFirmwareFileGuid + FD = ALTRA1L2T_HOST_FIRMWARE_CAPSULE +} + +FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid + $(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/CAPSULEDISPATCHFV.Fv +} + +FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid +!if $(INCLUDE_TFA_FW) + Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareUpdateConfig/TfaUefiFirmwareUpdateConfig.ini +!else + Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareUpdateConfig/UefiFirmwareUpdateConfig.ini +!endif +} + +[FmpPayload.FmpPayloadHostFirmwarePkcs7] +IMAGE_HEADER_INIT_VERSION = 0x03 +IMAGE_TYPE_ID = 731cbc77-cce1-4ec2-b79a-265470b332f1 # PcdSystemFmpCapsuleImageTypeIdGuid +IMAGE_INDEX = 0x1 +HARDWARE_INSTANCE = 0x0 +MONOTONIC_COUNT = 0x1 +CERTIFICATE_GUID = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7 + +FV = HostFirmwareUpdateCargo + +[Capsule.Altra1L2THostFirmware] +CAPSULE_GUID = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid +CAPSULE_HEADER_SIZE = 0x20 +CAPSULE_HEADER_INIT_VERSION = 0x1 + +FMP_PAYLOAD = FmpPayloadHostFirmwarePkcs7 + diff --git a/Platform/ASRockRack/Altra1L2TPkg/Altra1L2TLinuxBoot.dsc b/Platform/ASRockRack/Altra1L2TPkg/Altra1L2TLinuxBoot.dsc new file mode 100644 index 00000000000..83ccbe9a4cf --- /dev/null +++ b/Platform/ASRockRack/Altra1L2TPkg/Altra1L2TLinuxBoot.dsc @@ -0,0 +1,132 @@ +## @file +# +# Copyright (c) 2020 - 2022, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = Altra1L2T + PLATFORM_GUID = edc65dea-a173-496a-8ad0-5c96e3fd2079 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001B + OUTPUT_DIRECTORY = Build/Altra1L2T + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/ASRockRack/Altra1L2TPkg/Altra1L2TLinuxBoot.fdf + + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=VALUE + # + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // Network Io Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_MANAGEABILITY 0x00800000 // Detailed debug and payload manageability messages + # // related to modules such as Redfish, IPMI, MCTP etc. + # DEBUG_ERROR 0x80000000 // Error + DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x8000004F + DEFINE FIRMWARE_VER = 0.01.001 + DEFINE EDK2_SKIP_PEICORE = TRUE + +!include MdePkg/MdeLibs.dsc.inc + +# Include default Ampere Platform DSC file +!include Silicon/Ampere/AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc + +# +# Specific Platform Library +# +[LibraryClasses.common] + # + # ACPI Libraries + # + AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf + AcpiHelperLib|Platform/Ampere/AmperePlatformPkg/Library/AcpiHelperLib/AcpiHelperLib.inf + + # + # Pcie Board + # + BoardPcieLib|Platform/ASRockRack/Altra1L2TPkg/Library/BoardPcieLib/BoardPcieLib.inf + + IOExpanderLib|Platform/ASRockRack/Altra1L2TPkg/Library/IOExpanderLib/IOExpanderLib.inf + + PlatformBmcReadyLib|Platform/ASRockRack/Altra1L2TPkg/Library/PlatformBmcReadyLib/PlatformBmcReadyLib.inf + OemMiscLib|Platform/ASRockRack/Altra1L2TPkg/Library/OemMiscLib/OemMiscLib.inf + +[LibraryClasses.common.PEIM] + SmbusLib|MdePkg/Library/PeiSmbusLibSmbus2Ppi/PeiSmbusLibSmbus2Ppi.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + # + # RTC Library: Common RTC + # + RealTimeClockLib|Platform/ASRockRack/Altra1L2TPkg/Library/PCF85063RealTimeClockLib/PCF85063RealTimeClockLib.inf + +[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER] + SmbusLib|MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf + +[PcdsFixedAtBuild.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0307 + + gAmpereTokenSpaceGuid.PcdSmbiosTables0MajorVersion|$(MAJOR_VER) + gAmpereTokenSpaceGuid.PcdSmbiosTables0MinorVersion|$(MINOR_VER) +!ifdef $(FIRMWARE_VER) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" +!endif + + # Clearing BIT0 in this PCD prevents installing a 32-bit SMBIOS entry point, + # if the entry point version is >= 3.0. AARCH64 OSes cannot assume the + # presence of the 32-bit entry point anyway (because many AARCH64 systems + # don't have 32-bit addressable physical RAM), and the additional allocations + # below 4 GB needlessly fragment the memory map. So expose the 64-bit entry + # point only, for entry point versions >= 3.0. + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 + +# +# Specific Platform Component +# +[Components.common] + + # + # ACPI + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + Platform/ASRockRack/Altra1L2TPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf + Platform/ASRockRack/Altra1L2TPkg/AcpiTables/AcpiTables.inf + Platform/ASRockRack/Altra1L2TPkg/Ac02AcpiTables/Ac02AcpiTables.inf + + # + # SMBIOS + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + Platform/ASRockRack/Altra1L2TPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + + MdeModulePkg/Application/HelloWorld/HelloWorld.inf diff --git a/Platform/ASRockRack/Altra1L2TPkg/Altra1L2TLinuxBoot.fdf b/Platform/ASRockRack/Altra1L2TPkg/Altra1L2TLinuxBoot.fdf new file mode 100644 index 00000000000..3982944f82e --- /dev/null +++ b/Platform/ASRockRack/Altra1L2TPkg/Altra1L2TLinuxBoot.fdf @@ -0,0 +1,224 @@ +## @file +# +# Copyright (c) 2020 - 2022, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.BL33_ALTRA1L2T_UEFI] +BaseAddress = 0x92000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x00AC0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x10000 +NumBlocks = 0xAC + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +0x00000000|0x00AC0000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x10000 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 16 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 5C60F367-A505-419A-859E-2A4FF6CA6FE5 + +APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInitDxe/PlatformInitDxe.inf +} + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf + + # + # Environment Variables Protocol + # + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + + # + # Timer + # + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + # + # Initialize works at Dxe phase + # + INF Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInitDxe/PlatformInitDxe.inf + + # + # Watchdog Timer + # + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + + # + # ARM GIC Dxe + # + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + # + # SMBus + # +# INF Silicon/Ampere/AmpereAltraPkg/Drivers/SmbusHcDxe/SmbusHcDxe.inf + + # + # IPMI + # +# INF Silicon/Ampere/AmpereSiliconPkg/Drivers/IpmiSsif/IpmiSsifDxe.inf + + # + # Linuxboot in Flash Support + # + INF Platform/Ampere/LinuxBootPkg/LinuxBoot.inf + + # + # Bds + # + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + + # + # ACPI + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF Platform/ASRockRack/Altra1L2TPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF RuleOverride=ACPITABLE Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf + INF RuleOverride=ACPITABLE Platform/ASRockRack/Altra1L2TPkg/AcpiTables/AcpiTables.inf + INF RuleOverride=ACPITABLE Platform/ASRockRack/Altra1L2TPkg/Ac02AcpiTables/Ac02AcpiTables.inf + + # + # SMBIOS + # + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + INF ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + INF Platform/ASRockRack/Altra1L2TPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + + INF MdeModulePkg/Application/HelloWorld/HelloWorld.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +APRIORI PEI { + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf +} + + INF ArmPlatformPkg/Sec/Sec.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf +# INF Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf +# INF Silicon/Ampere/AmpereAltraPkg/Drivers/SmbusHcPei/SmbusHcPei.inf + + # + # IPMI + # +# INF Silicon/Ampere/AmpereSiliconPkg/Drivers/IpmiSsif/IpmiSsifPeim.inf + + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + +!include Silicon/Ampere/AmpereSiliconPkg/FvRules.fdf.inc diff --git a/Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc new file mode 100644 index 00000000000..37d91b2cc4d --- /dev/null +++ b/Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc @@ -0,0 +1,76 @@ +/** @file + System Firmware descriptor. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include + +#include "HostFwInfo.h" + +#define PACKAGE_VERSION 0xFFFFFFFF +#define PACKAGE_VERSION_STRING L"Unknown" + +#define IMAGE_ID SIGNATURE_64('A', 'S', 'R', 'R', '2', 'Q', 'F', 'W') +#define IMAGE_ID_STRING L"ALTRAD8UD-1L2T Host Firmware" + +// PcdSystemFmpCapsuleImageTypeIdGuid +#define IMAGE_TYPE_ID_GUID { 0x731cbc77, 0xcce1, 0x4ec2, { 0xb7, 0x9a, 0x26, 0x54, 0x70, 0xb3, 0x32, 0xf1 } } + +typedef struct { + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor; + // real string data + CHAR16 ImageIdNameStr[sizeof(IMAGE_ID_STRING)/sizeof(CHAR16)]; + CHAR16 VersionNameStr[sizeof(CURRENT_FIRMWARE_VERSION_STRING)/sizeof(CHAR16)]; + CHAR16 PackageVersionNameStr[sizeof(PACKAGE_VERSION_STRING)/sizeof(CHAR16)]; +} IMAGE_DESCRIPTOR; + +STATIC IMAGE_DESCRIPTOR mImageDescriptor = +{ + { + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE, + sizeof(EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR), + sizeof(IMAGE_DESCRIPTOR), + PACKAGE_VERSION, // PackageVersion + OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersionName + 1, // ImageIndex; + {0x0}, // Reserved + IMAGE_TYPE_ID_GUID, // ImageTypeId; + IMAGE_ID, // ImageId; + OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName; + CURRENT_FIRMWARE_VERSION, // Version; + OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName; + {0x0}, // Reserved2 + 0xA00000, // Size; + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | + IMAGE_ATTRIBUTE_RESET_REQUIRED | + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | + IMAGE_ATTRIBUTE_IN_USE | + IMAGE_ATTRIBUTE_UEFI_IMAGE, // AttributesSupported; + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | + IMAGE_ATTRIBUTE_RESET_REQUIRED | + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | + IMAGE_ATTRIBUTE_IN_USE | + IMAGE_ATTRIBUTE_UEFI_IMAGE, // AttributesSetting; + 0x0, // Compatibilities; + LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSupportedImageVersion; + 0x00000000, // LastAttemptVersion; + 0, // LastAttemptStatus; + {0x0}, // Reserved3 + 0, // HardwareInstance; + }, + // real string data + IMAGE_ID_STRING, + CURRENT_FIRMWARE_VERSION_STRING, + PACKAGE_VERSION_STRING, +}; + +VOID* CONST ReferenceAcpiTable = &mImageDescriptor; diff --git a/Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf new file mode 100644 index 00000000000..861a02989a3 --- /dev/null +++ b/Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf @@ -0,0 +1,39 @@ +## @file +# System Firmware descriptor. +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = SystemFirmwareDescriptor + FILE_GUID = 396f4af1-76fb-4745-bfb9-004ecf0b936b + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = SystemFirmwareDescriptorPeimEntry + +[Sources] + SystemFirmwareDescriptor.aslc + SystemFirmwareDescriptorPei.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + SignedCapsulePkg/SignedCapsulePkg.dec + +[LibraryClasses] + DebugLib + PcdLib + PeiServicesLib + PeimEntryPoint + +[Pcd] + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor + +[Depex] + TRUE diff --git a/Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c b/Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c new file mode 100644 index 00000000000..7857606686e --- /dev/null +++ b/Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c @@ -0,0 +1,73 @@ +/** @file + System Firmware descriptor producer. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include + +/** + Entrypoint for SystemFirmwareDescriptor PEIM. + + @param[in] FileHandle Handle of the file being invoked. + @param[in] PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS PPI successfully installed. +**/ +EFI_STATUS +EFIAPI +SystemFirmwareDescriptorPeimEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR *Descriptor; + UINTN Size; + UINTN Index; + UINT32 AuthenticationStatus; + + // + // Search RAW section. + // + Index = 0; + while (TRUE) { + Status = PeiServicesFfsFindSectionData3 ( + EFI_SECTION_RAW, + Index, + FileHandle, + (VOID **)&Descriptor, + &AuthenticationStatus + ); + if (EFI_ERROR (Status)) { + // Should not happen, must something wrong in FDF. + ASSERT (FALSE); + return EFI_NOT_FOUND; + } + if (Descriptor->Signature == EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE) { + break; + } + Index++; + } + + DEBUG (( + DEBUG_INFO, + "EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR size - 0x%x\n", + Descriptor->Length + )); + + Size = Descriptor->Length; + PcdSetPtrS (PcdEdkiiSystemFirmwareImageDescriptor, &Size, Descriptor); + + return EFI_SUCCESS; +} diff --git a/Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareUpdateConfig/TfaUefiFirmwareUpdateConfig.ini b/Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareUpdateConfig/TfaUefiFirmwareUpdateConfig.ini new file mode 100644 index 00000000000..f67e5302824 --- /dev/null +++ b/Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareUpdateConfig/TfaUefiFirmwareUpdateConfig.ini @@ -0,0 +1,21 @@ +## @file +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Head] +NumOfUpdate = 1 +NumOfRecovery = 0 +Update0 = TFA_UEFI + +[TFA_UEFI] +FirmwareType = 2147483650 # SystemFirmware: 0x80000002 - ARM Trusted Firmware and OEM UEFI +AddressType = 1 # 0 - relative address, 1 - absolute address. +BaseAddress = 0x00000000 # Base address offset on flash +Length = 0x00D10000 # Length +ImageOffset = 0x00000000 # Image offset of this SystemFirmware image +FileGuid = a4c7d17d-491f-4be6-a261-ed5d9d36de42 # PcdEdkiiSystemFirmwareFileGuid diff --git a/Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareUpdateConfig/UefiFirmwareUpdateConfig.ini b/Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareUpdateConfig/UefiFirmwareUpdateConfig.ini new file mode 100644 index 00000000000..be773e7cdd3 --- /dev/null +++ b/Platform/ASRockRack/Altra1L2TPkg/Capsule/SystemFirmwareUpdateConfig/UefiFirmwareUpdateConfig.ini @@ -0,0 +1,21 @@ +## @file +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Head] +NumOfUpdate = 1 +NumOfRecovery = 0 +Update0 = UEFI + +[UEFI] +FirmwareType = 2147483651 # SystemFirmware: 0x80000003 - OEM UEFI +AddressType = 1 # 0 - relative address, 1 - absolute address. +BaseAddress = 0x00000000 # Base address offset on flash +Length = 0x00A10000 # Length +ImageOffset = 0x00000000 # Image offset of this SystemFirmware image +FileGuid = a4c7d17d-491f-4be6-a261-ed5d9d36de42 # PcdEdkiiSystemFirmwareFileGuid diff --git a/Platform/ASRockRack/Altra1L2TPkg/Readme.md b/Platform/ASRockRack/Altra1L2TPkg/Readme.md new file mode 100644 index 00000000000..d639e9cc590 --- /dev/null +++ b/Platform/ASRockRack/Altra1L2TPkg/Readme.md @@ -0,0 +1,38 @@ +Introduction +============ + +This directory holds the EDK2 and LinuxBoot firmware for the ASRock Rack +AltraD8UD-1L2T board. This is a workstation board with an LGA 4926 socket +and supports an Ampere Altra or Altra Max CPU from 32 to 128 cores. + +Building the firmare +-------------------- + +To build EDK2, run the `bld.sh` script. You need a copy of the Ampere +TF-A (ATF) and SCP binaries which are available from Customer Connect +after signing the Ampere NDA. + +Usage: + ./Platform/Ampere/bld.sh [options] + +Options: + -b , --build Specify the build type: DEBUG or RELEASE + -t , --toolchain Specify the toolchain to use: GCC or CLANG + -m , --manufacturer Specify platform manufacturer (e.g. Ampere) + -p , --platform Specify platform to build (e.g. Jade) + -l , --linuxboot Build LinuxBoot firmware instead of full EDK2 with UEFI Shell, specifying path to flashkernel + -f, --flash Copy firmware to BMC and flash firmware (keeping EFI variables and NVPARAMs) after building + -F, --full-flash Copy firmware to BMC and flash full EEPROM (resetting EFI variables and NVPARAMs) after building + + Note: flash options require bmc.sh file with env vars BMC_HOST, BMC_USER and BMC_PASS defined + + Available manufacturers: + Ampere + ASRockRack + + Available platforms: + ADLINK -> ComHpcAlt + Ampere -> Jade + ASRockRack -> Altra1L2Q + ASRockRack -> Altra1L2T + diff --git a/Platform/ASRockRack/Altra1L2TPkg/firmware.metainfo.xml b/Platform/ASRockRack/Altra1L2TPkg/firmware.metainfo.xml new file mode 100644 index 00000000000..29c4e258aae --- /dev/null +++ b/Platform/ASRockRack/Altra1L2TPkg/firmware.metainfo.xml @@ -0,0 +1,47 @@ + + + com.asrockrack.altrad8ud-1l2t.firmware + + X-System + + ALTRAD8UD-1L2T + Firmware for ASRock Rack ALTRAD8UD-1L2T + +

+ Updating the firmware on your ALTRAD8UD-1L2T + improves performance and adds new features. +

+ + + 731cbc77-cce1-4ec2-b79a-265470b332f1 + + https://www.asrockrack.com + BSD-2-Clause-Patent + BSD-2-Clause-Patent + + + + https://github.com/tianocore/edk2-platforms + + {RELEASE_NOTES} + + + + + + + + org.freedesktop.fwupd + + + + number + org.uefi.capsule + signed + + + + bios + + diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/Ac01AcpiTables.inf b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/Ac01AcpiTables.inf new file mode 100644 index 00000000000..0429a9d0e85 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/Ac01AcpiTables.inf @@ -0,0 +1,20 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = Ac01AcpiTables + FILE_GUID = 5ADDBC13-8634-480C-9B94-671B7855CDB8 + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + Dsdt.asl + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/CPU-S0.asi b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/CPU-S0.asi new file mode 100755 index 00000000000..07555787ca8 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/CPU-S0.asi @@ -0,0 +1,6345 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope (\_SB.SYST) { + Device (CL00) { + Name(_HID, "ACPI0010") + Name(_UID, 0x1) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL01) { + Name(_HID, "ACPI0010") + Name(_UID, 0x2) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL02) { + Name(_HID, "ACPI0010") + Name(_UID, 0x3) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL03) { + Name(_HID, "ACPI0010") + Name(_UID, 0x4) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL04) { + Name(_HID, "ACPI0010") + Name(_UID, 0x5) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL05) { + Name(_HID, "ACPI0010") + Name(_UID, 0x6) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL06) { + Name(_HID, "ACPI0010") + Name(_UID, 0x7) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL07) { + Name(_HID, "ACPI0010") + Name(_UID, 0x8) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL08) { + Name(_HID, "ACPI0010") + Name(_UID, 0x9) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL09) { + Name(_HID, "ACPI0010") + Name(_UID, 0xA) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL0A) { + Name(_HID, "ACPI0010") + Name(_UID, 0xB) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL0B) { + Name(_HID, "ACPI0010") + Name(_UID, 0xC) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL0C) { + Name(_HID, "ACPI0010") + Name(_UID, 0xD) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL0D) { + Name(_HID, "ACPI0010") + Name(_UID, 0xE) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL0E) { + Name(_HID, "ACPI0010") + Name(_UID, 0xF) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL0F) { + Name(_HID, "ACPI0010") + Name(_UID, 0x10) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL10) { + Name(_HID, "ACPI0010") + Name(_UID, 0x11) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL11) { + Name(_HID, "ACPI0010") + Name(_UID, 0x12) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL12) { + Name(_HID, "ACPI0010") + Name(_UID, 0x13) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL13) { + Name(_HID, "ACPI0010") + Name(_UID, 0x14) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL14) { + Name(_HID, "ACPI0010") + Name(_UID, 0x15) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL15) { + Name(_HID, "ACPI0010") + Name(_UID, 0x16) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL16) { + Name(_HID, "ACPI0010") + Name(_UID, 0x17) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL17) { + Name(_HID, "ACPI0010") + Name(_UID, 0x18) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL18) { + Name(_HID, "ACPI0010") + Name(_UID, 0x19) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL19) { + Name(_HID, "ACPI0010") + Name(_UID, 0x1A) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL1A) { + Name(_HID, "ACPI0010") + Name(_UID, 0x1B) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL1B) { + Name(_HID, "ACPI0010") + Name(_UID, 0x1C) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL1C) { + Name(_HID, "ACPI0010") + Name(_UID, 0x1D) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL1D) { + Name(_HID, "ACPI0010") + Name(_UID, 0x1E) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL1E) { + Name(_HID, "ACPI0010") + Name(_UID, 0x1F) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL1F) { + Name(_HID, "ACPI0010") + Name(_UID, 0x20) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL20) { + Name(_HID, "ACPI0010") + Name(_UID, 0x21) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL21) { + Name(_HID, "ACPI0010") + Name(_UID, 0x22) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL22) { + Name(_HID, "ACPI0010") + Name(_UID, 0x23) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL23) { + Name(_HID, "ACPI0010") + Name(_UID, 0x24) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL24) { + Name(_HID, "ACPI0010") + Name(_UID, 0x25) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL25) { + Name(_HID, "ACPI0010") + Name(_UID, 0x26) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL26) { + Name(_HID, "ACPI0010") + Name(_UID, 0x27) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL27) { + Name(_HID, "ACPI0010") + Name(_UID, 0x28) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL28) { + Name(_HID, "ACPI0010") + Name(_UID, 0x29) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL29) { + Name(_HID, "ACPI0010") + Name(_UID, 0x2A) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL2A) { + Name(_HID, "ACPI0010") + Name(_UID, 0x2B) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL2B) { + Name(_HID, "ACPI0010") + Name(_UID, 0x2C) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL2C) { + Name(_HID, "ACPI0010") + Name(_UID, 0x2D) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL2D) { + Name(_HID, "ACPI0010") + Name(_UID, 0x2E) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL2E) { + Name(_HID, "ACPI0010") + Name(_UID, 0x2F) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL2F) { + Name(_HID, "ACPI0010") + Name(_UID, 0x30) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL30) { + Name(_HID, "ACPI0010") + Name(_UID, 0x31) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL31) { + Name(_HID, "ACPI0010") + Name(_UID, 0x32) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL32) { + Name(_HID, "ACPI0010") + Name(_UID, 0x33) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL33) { + Name(_HID, "ACPI0010") + Name(_UID, 0x34) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL34) { + Name(_HID, "ACPI0010") + Name(_UID, 0x35) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL35) { + Name(_HID, "ACPI0010") + Name(_UID, 0x36) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL36) { + Name(_HID, "ACPI0010") + Name(_UID, 0x37) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL37) { + Name(_HID, "ACPI0010") + Name(_UID, 0x38) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL38) { + Name(_HID, "ACPI0010") + Name(_UID, 0x39) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL39) { + Name(_HID, "ACPI0010") + Name(_UID, 0x3A) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL3A) { + Name(_HID, "ACPI0010") + Name(_UID, 0x3B) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL3B) { + Name(_HID, "ACPI0010") + Name(_UID, 0x3C) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL3C) { + Name(_HID, "ACPI0010") + Name(_UID, 0x3D) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL3D) { + Name(_HID, "ACPI0010") + Name(_UID, 0x3E) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL3E) { + Name(_HID, "ACPI0010") + Name(_UID, 0x3F) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL3F) { + Name(_HID, "ACPI0010") + Name(_UID, 0x40) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } +} + +Scope (\_SB.SYST.CL00) { + Device(C000) { + Name(_HID, "ACPI0007") + Name(_UID, 0x0) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x000, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x004, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x008, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x00c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x010, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x014, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x050, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x054, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x058, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 0, 0xFD, 2} + }) // Domain 0 + } + + Device(C001) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x080, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x084, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x088, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x08c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x090, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x094, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x0d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x0d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x0d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 1, 0xFD, 2} + }) // Domain 1 + } +} + +Scope (\_SB.SYST.CL01) { + Device(C002) { + Name(_HID, "ACPI0007") + Name(_UID, 0x100) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x100, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x104, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x108, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x10c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x114, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x12c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x134, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x13c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x150, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x154, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x158, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 2, 0xFD, 2} + }) // Domain 2 + } + + Device(C003) { + Name(_HID, "ACPI0007") + Name(_UID, 0x101) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x180, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x184, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x188, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x18c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x190, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x194, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 3, 0xFD, 2} + }) // Domain 3 + } +} + +Scope (\_SB.SYST.CL02) { + Device(C004) { + Name(_HID, "ACPI0007") + Name(_UID, 0x200) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x200, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x204, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x208, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x20c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x210, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x214, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x22c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x234, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x23c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x250, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x254, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x258, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 4, 0xFD, 2} + }) // Domain 4 + } + + Device(C005) { + Name(_HID, "ACPI0007") + Name(_UID, 0x201) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x280, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x284, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x288, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x28c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x290, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x294, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 5, 0xFD, 2} + }) // Domain 5 + } +} + +Scope (\_SB.SYST.CL03) { + Device(C006) { + Name(_HID, "ACPI0007") + Name(_UID, 0x300) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x300, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x304, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x308, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x30c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x310, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x314, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x32c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x334, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x33c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x350, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x354, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x358, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 6, 0xFD, 2} + }) // Domain 6 + } + + Device(C007) { + Name(_HID, "ACPI0007") + Name(_UID, 0x301) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x380, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x384, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x388, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x38c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x390, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x394, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 7, 0xFD, 2} + }) // Domain 7 + } +} + +Scope (\_SB.SYST.CL04) { + Device(C008) { + Name(_HID, "ACPI0007") + Name(_UID, 0x400) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x400, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x404, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x408, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x40c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x410, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x414, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x42c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x434, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x43c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x450, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x454, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x458, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 8, 0xFD, 2} + }) // Domain 8 + } + + Device(C009) { + Name(_HID, "ACPI0007") + Name(_UID, 0x401) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x480, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x484, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x488, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x48c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x490, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x494, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x4ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x4b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x4bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x4d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x4d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x4d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 9, 0xFD, 2} + }) // Domain 9 + } +} + +Scope (\_SB.SYST.CL05) { + Device(C010) { + Name(_HID, "ACPI0007") + Name(_UID, 0x500) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x500, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x504, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x508, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x50c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x510, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x514, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x52c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x534, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x53c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x550, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x554, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x558, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 10, 0xFD, 2} + }) // Domain 10 + } + + Device(C011) { + Name(_HID, "ACPI0007") + Name(_UID, 0x501) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x580, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x584, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x588, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x58c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x590, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x594, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x5ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x5b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x5bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x5d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x5d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x5d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 11, 0xFD, 2} + }) // Domain 11 + } +} + +Scope (\_SB.SYST.CL06) { + Device(C012) { + Name(_HID, "ACPI0007") + Name(_UID, 0x600) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x600, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x604, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x608, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x60c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x610, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x614, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x62c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x634, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x63c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x650, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x654, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x658, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 12, 0xFD, 2} + }) // Domain 12 + } + + Device(C013) { + Name(_HID, "ACPI0007") + Name(_UID, 0x601) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x680, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x684, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x688, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x68c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x690, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x694, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x6ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x6b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x6bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x6d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x6d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x6d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 13, 0xFD, 2} + }) // Domain 13 + } +} + +Scope (\_SB.SYST.CL07) { + Device(C014) { + Name(_HID, "ACPI0007") + Name(_UID, 0x700) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x700, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x704, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x708, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x70c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x710, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x714, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x72c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x734, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x73c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x750, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x754, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x758, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 14, 0xFD, 2} + }) // Domain 14 + } + + Device(C015) { + Name(_HID, "ACPI0007") + Name(_UID, 0x701) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x780, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x784, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x788, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x78c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x790, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x794, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x7ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x7b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x7bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x7d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x7d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x7d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 15, 0xFD, 2} + }) // Domain 15 + } +} + +Scope (\_SB.SYST.CL08) { + Device(C016) { + Name(_HID, "ACPI0007") + Name(_UID, 0x800) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x800, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x804, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x808, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x80c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x810, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x814, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x82c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x834, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x83c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x850, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x854, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x858, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 16, 0xFD, 2} + }) // Domain 16 + } + + Device(C017) { + Name(_HID, "ACPI0007") + Name(_UID, 0x801) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x880, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x884, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x888, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x88c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x890, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x894, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x8ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x8b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x8bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x8d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x8d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x8d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 17, 0xFD, 2} + }) // Domain 17 + } +} + +Scope (\_SB.SYST.CL09) { + Device(C018) { + Name(_HID, "ACPI0007") + Name(_UID, 0x900) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x900, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x904, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x908, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x90c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x910, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x914, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x92c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x934, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x93c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x950, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x954, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x958, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 18, 0xFD, 2} + }) // Domain 18 + } + + Device(C019) { + Name(_HID, "ACPI0007") + Name(_UID, 0x901) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x980, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x984, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x988, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x98c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x990, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x994, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x9ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x9b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x9bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x9d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x9d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x9d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 19, 0xFD, 2} + }) // Domain 19 + } +} + +Scope (\_SB.SYST.CL0A) { + Device(C020) { + Name(_HID, "ACPI0007") + Name(_UID, 0xa00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xa00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xa14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xa2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xa34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xa3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xa50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xa54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xa58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 20, 0xFD, 2} + }) // Domain 20 + } + + Device(C021) { + Name(_HID, "ACPI0007") + Name(_UID, 0xa01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xa80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xa94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xaac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xab4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xabc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xad0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xad4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xad8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 21, 0xFD, 2} + }) // Domain 21 + } +} + +Scope (\_SB.SYST.CL0B) { + Device(C022) { + Name(_HID, "ACPI0007") + Name(_UID, 0xb00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xb00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xb14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xb2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xb34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xb3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xb50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xb54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xb58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 22, 0xFD, 2} + }) // Domain 22 + } + + Device(C023) { + Name(_HID, "ACPI0007") + Name(_UID, 0xb01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xb80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xb94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xbac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xbb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xbbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xbd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xbd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xbd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 23, 0xFD, 2} + }) // Domain 23 + } +} + +Scope (\_SB.SYST.CL0C) { + Device(C024) { + Name(_HID, "ACPI0007") + Name(_UID, 0xc00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xc00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xc14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xc2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xc34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xc3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xc50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xc54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xc58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 24, 0xFD, 2} + }) // Domain 24 + } + + Device(C025) { + Name(_HID, "ACPI0007") + Name(_UID, 0xc01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xc80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xc94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xcac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xcb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xcbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xcd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xcd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xcd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 25, 0xFD, 2} + }) // Domain 25 + } +} + +Scope (\_SB.SYST.CL0D) { + Device(C026) { + Name(_HID, "ACPI0007") + Name(_UID, 0xd00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xd00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xd14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xd2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xd34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xd3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xd50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xd54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xd58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 26, 0xFD, 2} + }) // Domain 26 + } + + Device(C027) { + Name(_HID, "ACPI0007") + Name(_UID, 0xd01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xd80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xd94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xdac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xdb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xdbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xdd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xdd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xdd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 27, 0xFD, 2} + }) // Domain 27 + } +} + +Scope (\_SB.SYST.CL0E) { + Device(C028) { + Name(_HID, "ACPI0007") + Name(_UID, 0xe00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xe00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xe14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xe2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xe34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xe3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xe50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xe54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xe58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 28, 0xFD, 2} + }) // Domain 28 + } + + Device(C029) { + Name(_HID, "ACPI0007") + Name(_UID, 0xe01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xe80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xe94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xeac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xeb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xebc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xed0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xed4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xed8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 29, 0xFD, 2} + }) // Domain 29 + } +} + +Scope (\_SB.SYST.CL0F) { + Device(C030) { + Name(_HID, "ACPI0007") + Name(_UID, 0xf00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xf00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xf14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xf2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xf34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xf3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xf50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xf54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xf58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 30, 0xFD, 2} + }) // Domain 30 + } + + Device(C031) { + Name(_HID, "ACPI0007") + Name(_UID, 0xf01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xf80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xf94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xfac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xfb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xfbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xfd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xfd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xfd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 31, 0xFD, 2} + }) // Domain 31 + } +} + +Scope (\_SB.SYST.CL10) { + Device(C032) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1000) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1000, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1004, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1008, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x100c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1010, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1014, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x102c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1034, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x103c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1050, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1054, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1058, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 32, 0xFD, 2} + }) // Domain 32 + } + + Device(C033) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1001) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1080, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1084, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1088, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x108c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1090, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1094, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x10ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x10b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x10bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x10d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x10d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x10d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 33, 0xFD, 2} + }) // Domain 33 + } +} + +Scope (\_SB.SYST.CL11) { + Device(C034) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1100) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1100, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1104, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1108, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x110c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1110, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1114, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x112c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1134, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x113c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1150, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1154, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1158, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 34, 0xFD, 2} + }) // Domain 34 + } + + Device(C035) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1101) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1180, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1184, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1188, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x118c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1190, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1194, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x11ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x11b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x11bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x11d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x11d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x11d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 35, 0xFD, 2} + }) // Domain 35 + } +} + +Scope (\_SB.SYST.CL12) { + Device(C036) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1200) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1200, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1204, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1208, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x120c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1210, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1214, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x122c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1234, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x123c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1250, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1254, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1258, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 36, 0xFD, 2} + }) // Domain 36 + } + + Device(C037) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1201) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1280, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1284, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1288, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x128c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1290, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1294, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x12ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x12b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x12bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x12d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x12d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x12d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 37, 0xFD, 2} + }) // Domain 37 + } +} + +Scope (\_SB.SYST.CL13) { + Device(C038) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1300) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1300, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1304, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1308, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x130c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1310, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1314, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x132c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1334, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x133c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1350, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1354, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1358, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 38, 0xFD, 2} + }) // Domain 38 + } + + Device(C039) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1301) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1380, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1384, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1388, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x138c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1390, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1394, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x13ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x13b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x13bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x13d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x13d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x13d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 39, 0xFD, 2} + }) // Domain 39 + } +} + +Scope (\_SB.SYST.CL14) { + Device(C040) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1400) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1400, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1404, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1408, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x140c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1410, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1414, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x142c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1434, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x143c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1450, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1454, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1458, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 40, 0xFD, 2} + }) // Domain 40 + } + + Device(C041) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1401) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1480, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1484, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1488, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x148c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1490, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1494, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x14ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x14b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x14bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x14d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x14d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x14d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 41, 0xFD, 2} + }) // Domain 41 + } +} + +Scope (\_SB.SYST.CL15) { + Device(C042) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1500) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1500, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1504, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1508, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x150c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1510, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1514, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x152c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1534, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x153c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1550, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1554, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1558, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 42, 0xFD, 2} + }) // Domain 42 + } + + Device(C043) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1501) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1580, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1584, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1588, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x158c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1590, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1594, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x15ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x15b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x15bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x15d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x15d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x15d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 43, 0xFD, 2} + }) // Domain 43 + } +} + +Scope (\_SB.SYST.CL16) { + Device(C044) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1600) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1600, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1604, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1608, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x160c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1610, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1614, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x162c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1634, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x163c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1650, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1654, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1658, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 44, 0xFD, 2} + }) // Domain 44 + } + + Device(C045) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1601) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1680, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1684, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1688, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x168c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1690, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1694, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x16ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x16b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x16bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x16d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x16d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x16d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 45, 0xFD, 2} + }) // Domain 45 + } +} + +Scope (\_SB.SYST.CL17) { + Device(C046) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1700) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1700, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1704, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1708, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x170c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1710, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1714, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x172c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1734, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x173c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1750, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1754, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1758, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 46, 0xFD, 2} + }) // Domain 46 + } + + Device(C047) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1701) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1780, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1784, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1788, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x178c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1790, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1794, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x17ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x17b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x17bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x17d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x17d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x17d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 47, 0xFD, 2} + }) // Domain 47 + } +} + +Scope (\_SB.SYST.CL18) { + Device(C048) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1800) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1800, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1804, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1808, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x180c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1810, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1814, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x182c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1834, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x183c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1850, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1854, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1858, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 48, 0xFD, 2} + }) // Domain 48 + } + + Device(C049) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1801) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1880, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1884, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1888, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x188c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1890, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1894, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x18ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x18b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x18bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x18d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x18d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x18d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 49, 0xFD, 2} + }) // Domain 49 + } +} + +Scope (\_SB.SYST.CL19) { + Device(C050) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1900) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1900, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1904, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1908, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x190c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1910, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1914, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x192c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1934, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x193c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1950, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1954, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1958, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 50, 0xFD, 2} + }) // Domain 50 + } + + Device(C051) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1901) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1980, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1984, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1988, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x198c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1990, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1994, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x19ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x19b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x19bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x19d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x19d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x19d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 51, 0xFD, 2} + }) // Domain 51 + } +} + +Scope (\_SB.SYST.CL1A) { + Device(C052) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1a00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1a00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1a14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1a2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1a34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1a3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1a50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1a54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1a58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 52, 0xFD, 2} + }) // Domain 52 + } + + Device(C053) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1a01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1a80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1a94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1aac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1ab4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1abc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1ad0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1ad4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1ad8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 53, 0xFD, 2} + }) // Domain 53 + } +} + +Scope (\_SB.SYST.CL1B) { + Device(C054) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1b00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1b00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1b14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1b2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1b34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1b3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1b50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1b54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1b58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 54, 0xFD, 2} + }) // Domain 54 + } + + Device(C055) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1b01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1b80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1b94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1bac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1bb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1bbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1bd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1bd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1bd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 55, 0xFD, 2} + }) // Domain 5 + } +} + +Scope (\_SB.SYST.CL1C) { + Device(C056) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1c00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1c00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1c14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1c2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1c34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1c3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1c50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1c54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1c58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 56, 0xFD, 2} + }) // Domain 56 + } + + Device(C057) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1c01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1c80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1c94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1cac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1cb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1cbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1cd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1cd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1cd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 57, 0xFD, 2} + }) // Domain 57 + } +} + +Scope (\_SB.SYST.CL1D) { + Device(C058) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1d00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1d00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1d2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1d34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 58, 0xFD, 2} + }) // Domain 58 + } + + Device(C059) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1d01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1d80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1dac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1db4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1dbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1dd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1dd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1dd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 59, 0xFD, 2} + }) // Domain 59 + } +} + +Scope (\_SB.SYST.CL1E) { + Device(C060) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1e00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1e00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1e14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1e2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1e34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1e3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1e50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1e54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1e58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 60, 0xFD, 2} + }) // Domain 60 + } + + Device(C061) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1e01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1e80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1e94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1eac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1eb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1ebc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1ed0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1ed4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1ed8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 61, 0xFD, 2} + }) // Domain 61 + } +} + +Scope (\_SB.SYST.CL1F) { + Device(C062) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1f00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1f00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1f14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1f2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1f34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1f3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1f50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1f54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1f58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 62, 0xFD, 2} + }) // Domain 62 + } + + Device(C063) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1f01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1f80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1f94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1fac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1fb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1fbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1fd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1fd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1fd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 63, 0xFD, 2} + }) // Domain 63 + } +} + +Scope (\_SB.SYST.CL20) { + Device(C064) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2000) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2000, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2004, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2008, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x200c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2010, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2014, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x202c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2034, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x203c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2050, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2054, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2058, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 64, 0xFD, 2} + }) // Domain 64 + } + + Device(C065) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2001) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2080, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2084, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2088, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x208c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2090, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2094, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x20ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x20b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x20bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x20d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x20d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x20d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 65, 0xFD, 2} + }) // Domain 65 + } +} + +Scope (\_SB.SYST.CL21) { + Device(C066) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2100) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2100, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2104, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2108, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x210c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2110, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2114, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x212c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2134, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x213c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2150, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2154, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2158, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 66, 0xFD, 2} + }) // Domain 66 + } + + Device(C067) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2101) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2180, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2184, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2188, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x218c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2190, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2194, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x21ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x21b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x21bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x21d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x21d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x21d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 67, 0xFD, 2} + }) // Domain 67 + } +} + +Scope (\_SB.SYST.CL22) { + Device(C068) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2200) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2200, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2204, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2208, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x220c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2210, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2214, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x222c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2234, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x223c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2250, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2254, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2258, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 68, 0xFD, 2} + }) // Domain 68 + } + + Device(C069) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2201) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2280, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2284, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2288, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x228c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2290, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2294, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x22ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x22b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x22bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x22d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x22d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x22d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 69, 0xFD, 2} + }) // Domain 69 + } +} + +Scope (\_SB.SYST.CL23) { + Device(C070) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2300) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2300, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2304, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2308, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x230c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2310, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2314, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x232c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2334, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x233c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2350, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2354, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2358, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 70, 0xFD, 2} + }) // Domain 70 + } + + Device(C071) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2301) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2380, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2384, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2388, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x238c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2390, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2394, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x23ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x23b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x23bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x23d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x23d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x23d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 71, 0xFD, 2} + }) // Domain 71 + } +} + +Scope (\_SB.SYST.CL24) { + Device(C072) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2400) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2400, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2404, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2408, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x240c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2410, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2414, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x242c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2434, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x243c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2450, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2454, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2458, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 72, 0xFD, 2} + }) // Domain 72 + } + + Device(C073) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2401) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2480, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2484, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2488, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x248c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2490, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2494, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x24ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x24b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x24bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x24d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x24d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x24d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 73, 0xFD, 2} + }) // Domain 73 + } +} + +Scope (\_SB.SYST.CL25) { + Device(C074) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2500) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2500, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2504, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2508, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x250c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2510, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2514, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x252c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2534, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x253c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2550, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2554, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2558, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 74, 0xFD, 2} + }) // Domain 74 + } + + Device(C075) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2501) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2580, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2584, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2588, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x258c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2590, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2594, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x25ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x25b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x25bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x25d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x25d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x25d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 75, 0xFD, 2} + }) // Domain 75 + } +} + +Scope (\_SB.SYST.CL26) { + Device(C076) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2600) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2600, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2604, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2608, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x260c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2610, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2614, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x262c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2634, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x263c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2650, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2654, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2658, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 76, 0xFD, 2} + }) // Domain 76 + } + + Device(C077) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2601) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2680, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2684, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2688, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x268c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2690, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2694, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x26ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x26b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x26bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x26d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x26d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x26d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 77, 0xFD, 2} + }) // Domain 77 + } +} + +Scope (\_SB.SYST.CL27) { + Device(C078) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2700) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2700, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2704, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2708, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x270c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2710, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2714, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x272c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2734, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x273c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2750, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2754, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2758, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 78, 0xFD, 2} + }) // Domain 78 + } + + Device(C079) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2701) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2780, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2784, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2788, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x278c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2790, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2794, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x27ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x27b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x27bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x27d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x27d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x27d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 79, 0xFD, 2} + }) // Domain 79 + } +} + +Scope (\_SB.SYST.CL28) { + Device(C080) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2800) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2800, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2804, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2808, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x280c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2810, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2814, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x282c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2834, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x283c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2850, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2854, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2858, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 80, 0xFD, 2} + }) // Domain 80 + } + + Device(C081) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2801) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2880, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2884, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2888, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x288c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2890, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2894, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x28ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x28b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x28bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x28d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x28d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x28d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 81, 0xFD, 2} + }) // Domain 81 + } +} + +Scope (\_SB.SYST.CL29) { + Device(C082) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2900) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2900, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2904, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2908, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x290c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2910, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2914, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x292c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2934, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x293c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2950, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2954, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2958, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 82, 0xFD, 2} + }) // Domain 82 + } + + Device(C083) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2901) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2980, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2984, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2988, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x298c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2990, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2994, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x29ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x29b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x29bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x29d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x29d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x29d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 83, 0xFD, 2} + }) // Domain 83 + } +} + +Scope (\_SB.SYST.CL2A) { + Device(C084) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2a00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2a00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2a14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2a2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2a34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2a3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2a50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2a54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2a58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 84, 0xFD, 2} + }) // Domain 84 + } + + Device(C085) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2a01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2a80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2a94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2aac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2ab4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2abc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2ad0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2ad4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2ad8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 85, 0xFD, 2} + }) // Domain 85 + } +} + +Scope (\_SB.SYST.CL2B) { + Device(C086) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2b00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2b00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2b14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2b2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2b34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2b3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2b50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2b54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2b58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 86, 0xFD, 2} + }) // Domain 86 + } + + Device(C087) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2b01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2b80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2b94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2bac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2bb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2bbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2bd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2bd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2bd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 87, 0xFD, 2} + }) // Domain 87 + } +} + +Scope (\_SB.SYST.CL2C) { + Device(C088) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2c00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2c00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2c14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2c2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2c34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2c3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2c50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2c54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2c58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 88, 0xFD, 2} + }) // Domain 88 + } + + Device(C089) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2c01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2c80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2c94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2cac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2cb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2cbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2cd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2cd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2cd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 89, 0xFD, 2} + }) // Domain 89 + } +} + +Scope (\_SB.SYST.CL2D) { + Device(C090) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2d00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2d00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2d2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2d34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 90, 0xFD, 2} + }) // Domain 90 + } + + Device(C091) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2d01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2d80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2dac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2db4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2dbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2dd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2dd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2dd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 91, 0xFD, 2} + }) // Domain 91 + } +} + +Scope (\_SB.SYST.CL2E) { + Device(C092) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2e00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2e00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2e14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2e2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2e34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2e3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2e50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2e54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2e58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 92, 0xFD, 2} + }) // Domain 92 + } + + Device(C093) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2e01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2e80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2e94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2eac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2eb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2ebc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2ed0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2ed4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2ed8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 93, 0xFD, 2} + }) // Domain 93 + } +} + +Scope (\_SB.SYST.CL2F) { + Device(C094) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2f00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2f00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2f14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2f2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2f34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2f3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2f50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2f54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2f58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 94, 0xFD, 2} + }) // Domain 94 + } + + Device(C095) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2f01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2f80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2f94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2fac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2fb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2fbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2fd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2fd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2fd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 95, 0xFD, 2} + }) // Domain 95 + } +} + +Scope (\_SB.SYST.CL30) { + Device(C096) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3000) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3000, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3004, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3008, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x300c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3010, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3014, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x302c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3034, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x303c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3050, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3054, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3058, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 96, 0xFD, 2} + }) // Domain 96 + } + + Device(C097) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3001) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3080, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3084, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3088, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x308c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3090, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3094, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x30ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x30b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x30bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x30d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x30d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x30d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 97, 0xFD, 2} + }) // Domain 97 + } +} + +Scope (\_SB.SYST.CL31) { + Device(C098) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3100) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3100, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3104, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3108, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x310c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3110, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3114, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x312c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3134, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x313c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3150, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3154, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3158, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 98, 0xFD, 2} + }) // Domain 98 + } + + Device(C099) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3101) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3180, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3184, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3188, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x318c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3190, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3194, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x31ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x31b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x31bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x31d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x31d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x31d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 99, 0xFD, 2} + }) // Domain 99 + } +} + +Scope (\_SB.SYST.CL32) { + Device(C100) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3200) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3200, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3204, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3208, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x320c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3210, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3214, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x322c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3234, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x323c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3250, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3254, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3258, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 100, 0xFD, 2} + }) // Domain 100 + } + + Device(C101) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3201) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3280, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3284, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3288, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x328c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3290, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3294, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x32ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x32b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x32bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x32d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x32d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x32d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 101, 0xFD, 2} + }) // Domain 101 + } +} + +Scope (\_SB.SYST.CL33) { + Device(C102) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3300) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3300, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3304, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3308, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x330c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3310, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3314, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x332c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3334, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x333c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3350, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3354, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3358, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 102, 0xFD, 2} + }) // Domain 102 + } + + Device(C103) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3301) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3380, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3384, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3388, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x338c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3390, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3394, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x33ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x33b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x33bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x33d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x33d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x33d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 103, 0xFD, 2} + }) // Domain 103 + } +} + +Scope (\_SB.SYST.CL34) { + Device(C104) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3400) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3400, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3404, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3408, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x340c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3410, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3414, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x342c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3434, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x343c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3450, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3454, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3458, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 104, 0xFD, 2} + }) // Domain 104 + } + + Device(C105) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3401) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3480, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3484, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3488, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x348c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3490, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3494, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x34ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x34b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x34bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x34d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x34d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x34d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 105, 0xFD, 2} + }) // Domain 105 + } +} + +Scope (\_SB.SYST.CL35) { + Device(C106) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3500) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3500, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3504, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3508, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x350c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3510, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3514, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x352c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3534, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x353c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3550, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3554, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3558, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 106, 0xFD, 2} + }) // Domain 106 + } + + Device(C107) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3501) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3580, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3584, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3588, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x358c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3590, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3594, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x35ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x35b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x35bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x35d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x35d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x35d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 107, 0xFD, 2} + }) // Domain 107 + } +} + +Scope (\_SB.SYST.CL36) { + Device(C108) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3600) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3600, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3604, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3608, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x360c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3610, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3614, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x362c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3634, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x363c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3650, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3654, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3658, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 108, 0xFD, 2} + }) // Domain 108 + } + + Device(C109) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3601) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3680, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3684, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3688, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x368c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3690, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3694, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x36ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x36b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x36bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x36d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x36d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x36d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 109, 0xFD, 2} + }) // Domain 109 + } +} + +Scope (\_SB.SYST.CL37) { + Device(C110) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3700) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3700, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3704, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3708, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x370c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3710, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3714, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x372c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3734, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x373c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3750, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3754, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3758, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 110, 0xFD, 2} + }) // Domain 110 + } + + Device(C111) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3701) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3780, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3784, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3788, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x378c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3790, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3794, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x37ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x37b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x37bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x37d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x37d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x37d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 111, 0xFD, 2} + }) // Domain 111 + } +} + +Scope (\_SB.SYST.CL38) { + Device(C112) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3800) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3800, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3804, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3808, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x380c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3810, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3814, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x382c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3834, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x383c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3850, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3854, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3858, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 112, 0xFD, 2} + }) // Domain 112 + } + + Device(C113) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3801) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3880, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3884, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3888, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x388c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3890, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3894, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x38ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x38b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x38bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x38d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x38d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x38d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 113, 0xFD, 2} + }) // Domain 113 + } +} + +Scope (\_SB.SYST.CL39) { + Device(C114) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3900) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3900, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3904, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3908, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x390c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3910, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3914, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x392c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3934, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x393c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3950, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3954, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3958, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 114, 0xFD, 2} + }) // Domain 114 + } + + Device(C115) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3901) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3980, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3984, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3988, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x398c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3990, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3994, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x39ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x39b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x39bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x39d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x39d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x39d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 115, 0xFD, 2} + }) // Domain 115 + } +} + +Scope (\_SB.SYST.CL3A) { + Device(C116) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3a00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3a00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3a14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3a2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3a34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3a3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3a50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3a54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3a58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 116, 0xFD, 2} + }) // Domain 116 + } + + Device(C117) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3a01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3a80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3a94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3aac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3ab4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3abc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3ad0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3ad4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3ad8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 117, 0xFD, 2} + }) // Domain 117 + } +} + +Scope (\_SB.SYST.CL3B) { + Device(C118) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3b00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3b00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3b14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3b2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3b34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3b3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3b50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3b54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3b58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 118, 0xFD, 2} + }) // Domain 118 + } + + Device(C119) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3b01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3b80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3b94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3bac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3bb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3bbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3bd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3bd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3bd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 119, 0xFD, 2} + }) // Domain 119 + } +} + +Scope (\_SB.SYST.CL3C) { + Device(C120) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3c00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3c00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3c14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3c2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3c34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3c3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3c50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3c54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3c58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 120, 0xFD, 2} + }) // Domain 120 + } + + Device(C121) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3c01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3c80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3c94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3cac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3cb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3cbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3cd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3cd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3cd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 121, 0xFD, 2} + }) // Domain 121 + } +} + +Scope (\_SB.SYST.CL3D) { + Device(C122) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3d00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3d00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3d2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3d34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 122, 0xFD, 2} + }) // Domain 122 + } + + Device(C123) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3d01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3d80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3dac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3db4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3dbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3dd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3dd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3dd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 123, 0xFD, 2} + }) // Domain 123 + } +} + +Scope (\_SB.SYST.CL3E) { + Device(C124) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3e00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3e00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3e14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3e2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3e34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3e3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3e50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3e54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3e58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 124, 0xFD, 2} + }) // Domain 124 + } + + Device(C125) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3e01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3e80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3e94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3eac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3eb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3ebc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3ed0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3ed4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3ed8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 125, 0xFD, 2} + }) // Domain 125 + } +} + +Scope (\_SB.SYST.CL3F) { + Device(C126) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3f00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3f00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3f14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3f2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3f34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3f3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3f50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3f54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3f58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 126, 0xFD, 2} + }) // Domain 126 + } + + Device(C127) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3f01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3f80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3f94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3fac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3fb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3fbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3fd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3fd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3fd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 127, 0xFD, 2} + }) // Domain 127 + } +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/CPU.asi b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/CPU.asi new file mode 100755 index 00000000000..2c8994eb992 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/CPU.asi @@ -0,0 +1,151 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope(\_SB) { + Name (CPCE, 1) // CPPC Enable + Name (LPIE, 0) // LPI Enable + + Method (_OSC, 4, Serialized) { // _OSC: Operating System Capabilities + CreateDWordField (Arg3, 0x00, STS0) + CreateDWordField (Arg3, 0x04, CAP0) + If (LEqual(Arg0, ToUUID ("0811b06e-4a27-44f9-8d60-3cbbc22e7b48")) /* Platform-wide Capabilities */) { + If (LNotEqual(Arg1, One)) { + And(STS0, 0xFFFFFFE0, STS0) + Or(STS0, 0x0A, STS0) // Unrecognized Revision, OSC failure + } Else { + If (LEqual(And(CAP0, 0x100), 0x100)) { + And(CAP0, 0xFFFFFEFF, CAP0) // No support for OS Initiated LPI + And(STS0, 0xFFFFFFE0, STS0) + Or(STS0, 0x12, STS0) + } + If (LEqual(LPIE, 0x1)) { + Or(CAP0, 0x80, CAP0) // Support for LPI + } Else { + And(CAP0, 0xFFFFFF7F, CAP0) // No support for LPI + } + If (LEqual(CPCE, 0x1)) { + Or(CAP0, 0x40, CAP0) // Support for CPPCv2 + } Else { + And(CAP0, 0xFFFFFFBF, CAP0) // No support for CPPCv2 + } + } + } Else { + And(STS0, 0xFFFFFFE0, STS0) + Or(STS0, 0x06, STS0) // Unrecognized Revision, Unrecognized UUID + } + Return (Arg3) + } + + Name(CLPI, Package() { + 0, // Version + 1, // Level Index + 1, // Count + Package() { + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 0, // Residency Counter Frequency + 1, // No parent state + 0x01000000, // Integer Entry method + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "Standby", + }, + }) + + Name(PLPI, Package() { + 0, // Version + 2, // Level Index + 2, // Count + // WFI for CPU (NS-WFI) + Package() { + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 0, // Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0xFFFFFFFF, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "WFI", + }, + + // WFI for CPU (S-WFI) + Package() { + 1, // Min residency (uS) + 2900, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 0, // Residency Counter Frequency + 1, // No parent state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x01, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "Standby", + }, + }) + + Device (SYST) { // System state + Name(_HID, "ACPI0010") + Name(_UID, 0) + Name (_LPI, Package() { + 0, // Version + 0, // Level Index + 1, // Count + // Retention state for Cluster + Package() { + 100, // Min residency (uS) + 99, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 100, // Residency Counter Frequency + 0, // No Parent State + 0x01000100, // Integer Entry method + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "System Standby" + }, + }) + } +} + +Include ("CPU-S0.asi") diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/Dsdt.asl b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/Dsdt.asl new file mode 100755 index 00000000000..39886ff7d9f --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/Dsdt.asl @@ -0,0 +1,950 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +DefinitionBlock("Dsdt.aml", "DSDT", 0x02, "ASRock", "ALTRA", 1) { + // + // Board Model + Name(\BDMD, "ALTRAD8UD2-1L2Q") + Name(TPMF, 0) // TPM presence + Name(AERF, 0) // PCIe AER Firmware-First + + Scope(\_SB) { + + // + // Hardware Monitor + Device(HM00) { + Name(_HID, "APMC0D29") + Name(_UID, "HWM0") + Name(_DDN, "HWM0") + Name(_CCA, ONE) + Name(_STR, Unicode("Hardware Monitor Device")) + Method(_STA, 0, NotSerialized) { + return (0xF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package() {"pcc-channel", 14} + } + }) + } + + // + // Hardware Monitor + Device(HM01) { + Name(_HID, "APMC0D29") + Name(_UID, "HWM1") + Name(_DDN, "HWM1") + Name(_CCA, ONE) + Name(_STR, Unicode("Hardware Monitor Device")) + Method(_STA, 0, NotSerialized) { + return (0xF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package() {"pcc-channel", 29} + } + }) + } + + // + // Hardware Monitor + Device(HM02) { + Name(_HID, "AMPC0005") + Name(_UID, "HWM2") + Name(_DDN, "HWM2") + Name(_CCA, ONE) + Name(_STR, Unicode("AC01 SoC Hardware Monitor Device")) + Method(_STA, 0, NotSerialized) { + return (0xF) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000088900000, // AddressMinimum - MIN + 0x000000008891FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000020000 // RangeLength - LEN + ) + }) + } + + // + // Hardware Monitor + Device(HM03) { + Name(_HID, "AMPC0005") + Name(_UID, "HWM3") + Name(_DDN, "HWM3") + Name(_CCA, ONE) + Name(_STR, Unicode("AC01 SoC Hardware Monitor Device")) + Method(_STA, 0, NotSerialized) { + return (0xF) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00000000C0000000, // AddressMinimum - MIN + 0x00000000C001FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000020000 // RangeLength - LEN + ) + }) + } + + // + // DesignWare I2C on AHBC bus + Device(I2C2) { + Name(_HID, "APMC0D0F") + Name(_UID, 2) + Name(_STR, Unicode("Altra I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002690000, // AddressMinimum - MIN + 0x000010000269FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 103 } + }) + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) + } + + // + // DesignWare I2C on AHBC bus + Device(I2C3) { + Name(_HID, "APMC0D0F") + Name(_UID, 3) + Name(_STR, Unicode("Altra I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00001000026A0000, // AddressMinimum - MIN + 0x00001000026AFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 104 } + }) + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) + } + + // + // DesignWare I2C on AHBC bus + Device(I2C4) { + Name(_HID, "APMC0D0F") + Name(_UID, 4) + Name(_STR, Unicode("Altra I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00001000026B0000, // AddressMinimum - MIN + 0x00001000026BFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 105 } + }) + + Device (IPI) { + Name(_HID, "AMPC0004") + Name(_CID, "IPI0001") + Name(_STR, Unicode("IPMI_SSIF")) + Name(_UID, 0) + Name(_CCA, ONE) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Method(_IFT) { + Return(0x04) // IPMI SSIF + } + Method(_ADR) { + Return(0x10) // SSIF slave address + } + Method(_SRV) { + Return(0x0200) // IPMI Specification Revision + } + Name(_CRS, ResourceTemplate () + { + I2cSerialBusV2 (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.I2C4", + 0x00, ResourceConsumer,, Exclusive, + // Vendor specific data: + // "BMC0", + // Flags (2 bytes): SMBUS variable length (Bit 0), Read Checksum (Bit 1), Verify Checksum (Bit 2) + RawDataBuffer () { 0x42, 0x4D, 0x43, 0x30, 0x7, 0x0 } + ) + }) + } + + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) + } + + // + // DesignWare I2C on AHBC bus + Device(I2C5) { + Name(_HID, "APMC0D0F") + Name(_UID, 5) + Name(_STR, Unicode("Altra I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00001000026C0000, // AddressMinimum - MIN + 0x00001000026CFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 106 } + }) + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) + } + + // + // DesignWare I2C on AHBC bus + Device(I2C6) { + Name(_HID, "APMC0D0F") + Name(_UID, 6) + Name(_STR, Unicode("Altra I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002750000, // AddressMinimum - MIN + 0x000010000275FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 107 } + }) + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) + } + + // + // DesignWare I2C on AHBC bus + Device(I2C7) { + Name(_HID, "APMC0D0F") + Name(_UID, 7) + Name(_STR, Unicode("Altra I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002760000, // AddressMinimum - MIN + 0x000010000276FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 108 } + }) + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) + } + + // + // DesignWare I2C on AHBC bus + Device(I2C8) { + Name(_HID, "APMC0D0F") + Name(_UID, 8) + Name(_STR, Unicode("Altra I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002770000, // AddressMinimum - MIN + 0x000010000277FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 109 } + }) + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) + } + + // + // DesignWare I2C on AHBC bus + Device(I2C9) { + Name(_HID, "APMC0D0F") + Name(_UID, 9) + Name(_STR, Unicode("Altra I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002780000, // AddressMinimum - MIN + 0x000010000278FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 110 } + }) + + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) + } + + // + // DesignWare I2C on AHBC bus + Device(I2CA) { + Name(_HID, "APMC0D0F") + Name(_UID, 10) + Name(_STR, Unicode("Altra I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002790000, // AddressMinimum - MIN + 0x000010000279FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 111 } + }) + + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) + } + + // + // Report APEI Errors to GHES via SCI notification. + // SCI notification requires one GED and one HED Device + // GED = Generic Event Device (ACPI0013) + // HED = Hardware Error Device (PNP0C33) + // + Device(GED0) { + Name(_HID, "ACPI0013") + Name(_UID, Zero) + Method(_STA) { + Return (0xF) + } + Name(_CRS, ResourceTemplate () { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 84 } // GHES + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 44 } // PCIe Hot Plug Doorbell Insertion & Ejection (DBNS4 -> GIC-IRQS44) + }) + + // @DBN4 agent base address for HP PCIe insertion/ejection event: 0x1000.0054.4000 + OperationRegion(DBN4, SystemMemory, 0x100000544010, 20) + Field (DBN4, DWordAcc, NoLock, Preserve) { + DOUT, 32, // event and PCIe port information at offset 0x10 + offset (0x10), + STA4, 32, // interrupt status at offset 0x20 + } + + Method(_EVT, 1, Serialized) { + Switch (ToInteger(Arg0)) { + Case (84) { // GHES interrupt + Notify (HED0, 0x80) + } + } + } + } + + // Shutdown button using GED. + Device(GED1) { + Name(_HID, "ACPI0013") + Name(_CID, "ACPI0013") + Name(_UID, One) + Method(_STA) { + Return (0xF) + } + Name(_CRS, ResourceTemplate () { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 327 } + }) + OperationRegion(PDDR, SystemMemory, 0x1000027B0004, 4) + Field(PDDR, DWordAcc, NoLock, Preserve) { + STDI, 8 + } + + OperationRegion(INTE, SystemMemory, 0x1000027B0030, 4) + Field(INTE, DWordAcc, NoLock, Preserve) { + STDE, 8 + } + + OperationRegion(INTT, SystemMemory, 0x1000027B0034, 4) + Field(INTT, DWordAcc, NoLock, Preserve) { + TYPE, 8 + } + + OperationRegion(INTP, SystemMemory, 0x1000027B0038, 4) + Field(INTP, DWordAcc, NoLock, Preserve) { + POLA, 8 + } + + OperationRegion(INTS, SystemMemory, 0x1000027B003c, 4) + Field(INTS, DWordAcc, NoLock, Preserve) { + STDS, 8 + } + + OperationRegion(INTC, SystemMemory, 0x1000027B0040, 4) + Field(INTC, DWordAcc, NoLock, Preserve) { + SINT, 8 + } + + OperationRegion(INTM, SystemMemory, 0x1000027B0044, 4) + Field(INTM, DWordAcc, NoLock, Preserve) { + MASK, 8 + } + + Method(_INI, 0, NotSerialized) { + // Set level type, low active (shutdown) + Store (0x00, TYPE) + Store (0x00, POLA) + // Set Input type (shutdown) + Store (0x00, STDI) + // Enable interrupt (shutdown) + Store (0x80, STDE) + // Unmask the interrupt. + Store (0x00, MASK) + } + Method(_EVT, 1, Serialized) { + Switch (ToInteger(Arg0)) { + Case (327) { + if (And (STDS, 0x80)) { + //Clear the interrupt. + Store (0x80, SINT) + // Notify OSPM the power button is pressed + Notify (\_SB.PWRB, 0x80) + } + } + } + } + } + + // Power button device description + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0) + Name(_CCA, ONE) + Method(_STA, 0, Notserialized) { + Return (0x0b) + } + } + + // + // UART0 PL011 + Device(URT0) { + Name(_HID, "ARMH0011") + Name(_UID, 0) + Name(_CCA, ONE) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002600000, // AddressMinimum - MIN + 0x0000100002600FFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000001000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 98 } + }) + } // UART0 + + // + // UART2 PL011 + Device(URT2) { + Name(_HID, "ARMH0011") + Name(_UID, 1) + Name(_CCA, ONE) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002620000, // AddressMinimum - MIN + 0x0000100002620FFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000001000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 100 } + }) + } // UART1 + + Device(HED0) + { + Name(_HID, EISAID("PNP0C33")) + Name(_UID, Zero) + } + + Device(NVDR) { + Name(_HID, "ACPI0012") + Method(_STA, 0, NotSerialized) { + return (0xf) + } + Method (_DSM, 0x4, Serialized) { + // Not support any functions for now + Return (Buffer() {0}) + } + Device (NVD1) { + Name(_ADR, 0x0330) + Name(SMRT, Buffer(13) {0}) + CreateDWordField(SMRT, 0, BSTA) + CreateWordField(SMRT, 4, BHTH) + CreateWordField(SMRT, 6, BTMP) + CreateByteField(SMRT, 8, BETH) + CreateByteField(SMRT, 9, BWTH) + CreateByteField(SMRT, 10, BNLF) + OperationRegion(BUF1, SystemMemory, 0x88980000, 16) + Field (BUF1, DWordAcc, NoLock, Preserve) { + STAT, 32, //Status + HLTH, 16, //Module Health + CTMP, 16, //Module Current Status + ETHS, 8, //Error Threshold Status + WTHS, 8, //Warning Threshold Status + NVLF, 8, //NVM Lifetime + , 40 //Reserve + } + Method (_DSM, 0x4, Serialized) { + //Accept only MSF Family type NVDIMM DSM functions + If(LEqual(Arg0, ToUUID ("1ee68b36-d4bd-4a1a-9a16-4f8e53d46e05"))) { + //Handle Func 0 query implemented commands + If(LEqual(Arg2, 0)) { + //Check revision and returned proper implemented commands + //Support only health check for now + Return (Buffer() {0x01, 0x08}) //Byte 0: 0x1 + } + //Handle MSF DSM Func 11 Get Smart and Health Info + If(LEqual(Arg2, 11)) { + Store(\_SB.NVDR.NVD1.STAT, BSTA) + Store(\_SB.NVDR.NVD1.HLTH, BHTH) + Store(\_SB.NVDR.NVD1.CTMP, BTMP) + Store(\_SB.NVDR.NVD1.ETHS, BETH) + Store(\_SB.NVDR.NVD1.WTHS, BWTH) + Store(\_SB.NVDR.NVD1.NVLF, BNLF) + Return (SMRT) + } + } + Return (Buffer() {0}) + } + Method(_STA, 0, NotSerialized) { + return (0xf) + } + } + Device (NVD2) { + Name(_ADR, 0x0770) + Name(SMRT, Buffer(13) {0}) + CreateDWordField(SMRT, 0, BSTA) + CreateWordField(SMRT, 4, BHTH) + CreateWordField(SMRT, 6, BTMP) + CreateByteField(SMRT, 8, BETH) + CreateByteField(SMRT, 9, BWTH) + CreateByteField(SMRT, 10, BNLF) + OperationRegion(BUF1, SystemMemory, 0x88988000, 16) + Field (BUF1, DWordAcc, NoLock, Preserve) { + STAT, 32, //Status + HLTH, 16, //Module Health + CTMP, 16, //Module Current Status + ETHS, 8, //Error Threshold Status + WTHS, 8, //Warning Threshold Status + NVLF, 8, //NVM Lifetime + , 40 //Reserve + } + Method (_DSM, 0x4, Serialized) { + //Accept only MSF Family type NVDIMM DSM functions + If(LEqual(Arg0, ToUUID ("1ee68b36-d4bd-4a1a-9a16-4f8e53d46e05"))) { + //Handle Func 0 query implemented commands + If(LEqual(Arg2, 0)) { + //Check revision and returned proper implemented commands + //Support only health check for now + Return (Buffer() {0x01, 0x08}) //Byte 0: 0x1 + } + //Handle MSF DSM Func 11 Get Smart and Health Info + If(LEqual(Arg2, 11)) { + Store(\_SB.NVDR.NVD2.STAT, BSTA) + Store(\_SB.NVDR.NVD2.HLTH, BHTH) + Store(\_SB.NVDR.NVD2.CTMP, BTMP) + Store(\_SB.NVDR.NVD2.ETHS, BETH) + Store(\_SB.NVDR.NVD2.WTHS, BWTH) + Store(\_SB.NVDR.NVD2.NVLF, BNLF) + Return (SMRT) + } + } + Return (Buffer() {0}) + } + Method(_STA, 0, NotSerialized) { + return (0xf) + } + } + Device (NVD3) { + Name(_ADR, 0x1330) + Name(SMRT, Buffer(13) {0}) + CreateDWordField(SMRT, 0, BSTA) + CreateWordField(SMRT, 4, BHTH) + CreateWordField(SMRT, 6, BTMP) + CreateByteField(SMRT, 8, BETH) + CreateByteField(SMRT, 9, BWTH) + CreateByteField(SMRT, 10, BNLF) + OperationRegion(BUF1, SystemMemory, 0xC0080000, 16) + Field (BUF1, DWordAcc, NoLock, Preserve) { + STAT, 32, //Status + HLTH, 16, //Module Health + CTMP, 16, //Module Current Status + ETHS, 8, //Error Threshold Status + WTHS, 8, //Warning Threshold Status + NVLF, 8, //NVM Lifetime + , 40 //Reserve + } + Method (_DSM, 0x4, Serialized) { + //Accept only MSF Family type NVDIMM DSM functions + If(LEqual(Arg0, ToUUID ("1ee68b36-d4bd-4a1a-9a16-4f8e53d46e05"))) { + //Handle Func 0 query implemented commands + If(LEqual(Arg2, 0)) { + //Check revision and returned proper implemented commands + //Support only health check for now + Return (Buffer() {0x01, 0x08}) //Byte 0: 0x1 + } + //Handle MSF DSM Func 11 Get Smart and Health Info + If(LEqual(Arg2, 11)) { + Store(\_SB.NVDR.NVD3.STAT, BSTA) + Store(\_SB.NVDR.NVD3.HLTH, BHTH) + Store(\_SB.NVDR.NVD3.CTMP, BTMP) + Store(\_SB.NVDR.NVD3.ETHS, BETH) + Store(\_SB.NVDR.NVD3.WTHS, BWTH) + Store(\_SB.NVDR.NVD3.NVLF, BNLF) + Return (SMRT) + } + } + Return (Buffer() {0}) + } + Method(_STA, 0, NotSerialized) { + return (0xf) + } + } + Device (NVD4) { + Name(_ADR, 0x1770) + Name(SMRT, Buffer(13) {0}) + CreateDWordField(SMRT, 0, BSTA) + CreateWordField(SMRT, 4, BHTH) + CreateWordField(SMRT, 6, BTMP) + CreateByteField(SMRT, 8, BETH) + CreateByteField(SMRT, 9, BWTH) + CreateByteField(SMRT, 10, BNLF) + OperationRegion(BUF1, SystemMemory, 0xC0088000, 16) + Field (BUF1, DWordAcc, NoLock, Preserve) { + STAT, 32, //Status + HLTH, 16, //Module Health + CTMP, 16, //Module Current Status + ETHS, 8, //Error Threshold Status + WTHS, 8, //Warning Threshold Status + NVLF, 8, //NVM Lifetime + , 40 //Reserve + } + Method (_DSM, 0x4, Serialized) { + //Accept only MSF Family type NVDIMM DSM functions + If(LEqual(Arg0, ToUUID ("1ee68b36-d4bd-4a1a-9a16-4f8e53d46e05"))) { + //Handle Func 0 query implemented commands + If(LEqual(Arg2, 0)) { + //Check revision and returned proper implemented commands + //Support only health check for now + Return (Buffer() {0x01, 0x08}) //Byte 0: 0x1 + } + //Handle MSF DSM Func 11 Get Smart and Health Info + If(LEqual(Arg2, 11)) { + Store(\_SB.NVDR.NVD4.STAT, BSTA) + Store(\_SB.NVDR.NVD4.HLTH, BHTH) + Store(\_SB.NVDR.NVD4.CTMP, BTMP) + Store(\_SB.NVDR.NVD4.ETHS, BETH) + Store(\_SB.NVDR.NVD4.WTHS, BWTH) + Store(\_SB.NVDR.NVD4.NVLF, BNLF) + Return (SMRT) + } + } + Return (Buffer() {0}) + } + Method(_STA, 0, NotSerialized) { + return (0xf) + } + } + } + + Device (TPM0) { + // + // TPM 2.0 + // + + // + // TAG for patching TPM2.0 _HID + // + Name (_HID, "NNNN0000") + Name (_CID, "MSFT0101") + Name (_UID, 0) + + Name (CRBB, 0x10000000) + Name (CRBL, 0x10000000) + + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x88500000, 0x1000, PCRE) + }) + + Method (_CRS, 0x0, Serialized) { + // Declare fields in PCRE + CreateDWordField(RBUF, ^PCRE._BAS, BASE) + CreateDWordField(RBUF, ^PCRE._LEN, LENG) + + // Store updatable values into them + Store(CRBB, BASE) + Store(CRBL, LENG) + + Return (RBUF) + } + + Method (_STR,0) { + Return (Unicode ("TPM 2.0 Device")) + } + + Method (_STA, 0) { + if (TPMF) { + Return (0x0f) //Enable resources + } + Return (0x0) + } + + // + // Add opregions for doorbell and PPI CRB + // The addresses for these operation regions should be patched + // with information from HOB + // + OperationRegion (TPMD, SystemMemory, 0x100000542010, 0x04) + Field (TPMD, DWordAcc, NoLock, Preserve) { + DBB0, 32 // Doorbell out register + } + + // PPI request CRB + OperationRegion (TPMC, SystemMemory, 0x88542038, 0x0C) + Field (TPMC, DWordAcc, NoLock, Preserve) { + PPIO, 32, // current PPI request + PPIR, 32, // last PPI request + PPIS, 32, // last PPI request status + } + + // Create objects to hold return values + Name (PKG2, Package (2) { Zero, Zero }) + Name (PKG3, Package (3) { Zero, Zero, Zero }) + + Method (_DSM, 0x4, Serialized) { + // Handle Physical Presence Interface(PPI) DSM method + If (LEqual (Arg0, ToUUID ("3DDDFAA6-361B-4eb4-A424-8D10089D1653"))) { + Switch (ToInteger (Arg2)) { + // + // Standard DSM query + // + Case (0) { + Return (Buffer () { 0xFF, 0x01 }) + } + + // + // Get Physical Presence Interface Version - support 1.3 + // + Case (1) { + Return ("1.3") + } + + // + // Submit TPM operation to pre-OS (Deprecated) + // + Case (2) { + Return (One) // Not supported + } + + // + // Get pending TPM operation requested by OS + // + Case (3) { + PKG2[Zero] = Zero // Success + PKG2[One] = PPIO // current PPI request + Return (PKG2) + } + + // + // Platform-specific action to transition to Pre-OS env + // + Case (4) { + Return (0x2) // Reboot + } + + // + // TPM operation Response to OS + // + Case (5) { + PKG3[Zero] = Zero // Success + PKG3[One] = PPIR // last PPI request + PKG3[2] = PPIS // last PPI request status + Return (PKG3) + } + + // + // Preferred language code (Deprecated) + // + Case (6) { + Return (0x3) // Not implemented + } + + // + // Submit TPM operation to pre-OS env 2 + // + Case (7) { + Local0 = DerefOf (Arg3 [Zero]) + // Write current PPI request and then to the doorbell + Store (Local0, PPIO) + Store (0x6a000000, DBB0) // MsgType: 6, Handler: 0xa (TPM-PPI) + Return (Zero) + } + + // + // Get User confirmation status for op + // + Case (8) { + Return (0x4) // Allowed and physically present user not required + } + } + } + Return (Buffer () {0}) + } + } + + // + // LED Device + // + Device (LED) { + Name (_HID, "AMPC0008") + Name (_CCA, ONE) + Name (_STR, Unicode ("Altra LED Device")) + + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "uuid", Package (4) { 0x5598273c, 0xa49611ea, 0xbb370242, 0xac130002 }}, + } + }) + } + + Include ("PCI-S0.asi") + Include ("PCI-PDRC.asi") + } + + Include ("CPU.asi") + Include ("PMU.asi") + +} // DSDT diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PCI-PDRC.asi b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PCI-PDRC.asi new file mode 100644 index 00000000000..c4c3ead8dac --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PCI-PDRC.asi @@ -0,0 +1,134 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + // Motherboard resource consumption for PCIE resource reservation + // as upstream discussion "ACPI namespace details for ARM64" + // https://lists.linaro.org/archives/list/linaro-acpi@lists.linaro.org/thread/Q4XMW2PPCH2JH2KZHRGX27X7BSF6AY3U/ + // Also in https://docs.kernel.org/PCI/acpi-info.html + Device (PDRC) { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + Name (PDRS, ResourceTemplate() { + QWordMemory ( // PCIE0 (RcA0) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000033FFF0000000, // AddressMinimum - MIN + 0x000033FFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( // PCIE1 (RcA1) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000037FFF0000000, // AddressMinimum - MIN + 0x000037FFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( // PCIE2 (RcA2) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00003BFFF0000000, // AddressMinimum - MIN + 0x00003BFFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( // PCIE3 (RcA3) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00003FFFF0000000, // AddressMinimum - MIN + 0x00003FFFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( // PCIE4 (RcA4) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000023FFF0000000, // AddressMinimum - MIN + 0x000023FFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( // PCIE5 (RcA5) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000027FFF0000000, // AddressMinimum - MIN + 0x000027FFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( // PCIE6 (RcA6) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00002BFFF0000000, // AddressMinimum - MIN + 0x00002BFFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( // PCIE7 (RcA7) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00002FFFF0000000, // AddressMinimum - MIN + 0x00002FFFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) { + Return (PDRS) + } + } diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PCI-S0.asi b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PCI-S0.asi new file mode 100755 index 00000000000..c5a2aee23fe --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PCI-S0.asi @@ -0,0 +1,2928 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + // @DoorBellNS1 0x1000.0054.1000. Out-Offset: 0x10 + OperationRegion(DNS1, SystemMemory, 0x100000541010 , 8) + + Field (DNS1, DWordAcc, NoLock, Preserve) { + OUTV, 32, + DIN0, 32, + } + + // PCI0 RCA0 + Device (PCI0) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID, "PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) // The default value is 0x0. Unfortunately, it breaks + // run-time patching as the representation of 0 is special + // encoding and cannot be patched to expand with extra bytes + // easily. As such, we default to 0xF and patch this based + // on whether the port was enabled or not by the BIOS. + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID, "PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 12) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI0") + Name (_STR, Unicode("PCIe 0 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 128/129/130/131 respectively. PCI0 RCA0 + // + Package() {0x0001FFFF, 0, 0, 128}, + Package() {0x0001FFFF, 1, 0, 129}, + Package() {0x0001FFFF, 2, 0, 130}, + Package() {0x0001FFFF, 3, 0, 131}, + Package() {0x0002FFFF, 0, 0, 128}, + Package() {0x0002FFFF, 1, 0, 129}, + Package() {0x0002FFFF, 2, 0, 130}, + Package() {0x0002FFFF, 3, 0, 131}, + Package() {0x0003FFFF, 0, 0, 128}, + Package() {0x0003FFFF, 1, 0, 129}, + Package() {0x0003FFFF, 2, 0, 130}, + Package() {0x0003FFFF, 3, 0, 131}, + Package() {0x0004FFFF, 0, 0, 128}, + Package() {0x0004FFFF, 1, 0, 129}, + Package() {0x0004FFFF, 2, 0, 130}, + Package() {0x0004FFFF, 3, 0, 131}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x33FFF0000000) + } + + // + // Declare a ResourceTemplate buffer to return the resource + // requirements from _CRS. + // Section 19.5.109 + // + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FE40000, 0x10000, ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000040000000, // AddressMinimum - MIN + 0x000000004FFFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000300000000000, // AddressMinimum - MIN + 0x000033FFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP,0) // PCI _OSC Support Field value + Name (CTRL,0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3, 0, CDW1) + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL, 0x1E, CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1, One)) { + Or (CDW1, 0x08, CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3, CTRL)) { + Or (CDW1, 0x10, CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL, CDW3) + Return (Arg3) + + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI0 RCA0 + + // PCI1 RCA1 + Device (PCI1) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID, "PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) // The default value is 0x0. Unfortunately, it breaks + // run-time patching as the representation of 0 is special + // encoding and cannot be patched to expand with extra bytes + // easily. As such, we default to 0xF and patch this based + // on whether the port was enabled or not by the BIOS. + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID, "PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 13) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI1") + Name (_STR, Unicode("PCIe 1 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 132/133/134/135 respectively. PCI1 RCA1 + // + Package() {0x0001FFFF, 0, 0, 132}, + Package() {0x0001FFFF, 1, 0, 133}, + Package() {0x0001FFFF, 2, 0, 134}, + Package() {0x0001FFFF, 3, 0, 135}, + Package() {0x0002FFFF, 0, 0, 132}, + Package() {0x0002FFFF, 1, 0, 133}, + Package() {0x0002FFFF, 2, 0, 134}, + Package() {0x0002FFFF, 3, 0, 135}, + Package() {0x0003FFFF, 0, 0, 132}, + Package() {0x0003FFFF, 1, 0, 133}, + Package() {0x0003FFFF, 2, 0, 134}, + Package() {0x0003FFFF, 3, 0, 135}, + Package() {0x0004FFFF, 0, 0, 132}, + Package() {0x0004FFFF, 1, 0, 133}, + Package() {0x0004FFFF, 2, 0, 134}, + Package() {0x0004FFFF, 3, 0, 135}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x37FFF0000000) + } + + // + // Declare a ResourceTemplate buffer to return the resource + // requirements from _CRS. + // Section 19.5.109 + // + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FE40000, 0x10000, ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000050000000, // AddressMinimum - MIN + 0x000000005FFFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000340000000000, // AddressMinimum - MIN + 0x000037FFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP,0) // PCI _OSC Support Field value + Name (CTRL,0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3, 0, CDW1) + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL, 0x1E, CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1, One)) { + Or (CDW1, 0x08, CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3, CTRL)) { + Or (CDW1, 0x10, CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL, CDW3) + Return (Arg3) + + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI1 RCA1 + + // PCI2 RCA2 + Device (PCI2) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID, "PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID, "PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 1) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI2") + Name (_STR, Unicode("PCIe 2 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 136/137/138/139 respectively. PCI2 RCA2 + // + Package() {0x0001FFFF, 0, 0, 136}, + Package() {0x0001FFFF, 1, 0, 137}, + Package() {0x0001FFFF, 2, 0, 138}, + Package() {0x0001FFFF, 3, 0, 139}, + Package() {0x0002FFFF, 0, 0, 136}, + Package() {0x0002FFFF, 1, 0, 137}, + Package() {0x0002FFFF, 2, 0, 138}, + Package() {0x0002FFFF, 3, 0, 139}, + Package() {0x0003FFFF, 0, 0, 136}, + Package() {0x0003FFFF, 1, 0, 137}, + Package() {0x0003FFFF, 2, 0, 138}, + Package() {0x0003FFFF, 3, 0, 139}, + Package() {0x0004FFFF, 0, 0, 136}, + Package() {0x0004FFFF, 1, 0, 137}, + Package() {0x0004FFFF, 2, 0, 138}, + Package() {0x0004FFFF, 3, 0, 139}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x3BFFF0000000) + } + + // + // Declare a ResourceTemplate buffer to return the resource + // requirements from _CRS. + // Section 19.5.109 + // + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FE80000, 0x10000, ) + + QWordMemory ( // RcA2 32-bit MMIO + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000030000000, // AddressMinimum - MIN + 0x0000000037FFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000008000000 // RangeLength - LEN + ) + + QWordMemory ( // RcA2 MMIO + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000380000000000, // AddressMinimum - MIN + 0x00003BFFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP, 0) // PCI _OSC Support Field value + Name (CTRL, 0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3,0,CDW1) + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL, 0x1E, CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1, One)) { + Or (CDW1, 0x08, CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3, CTRL)) { + Or (CDW1, 0x10, CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL, CDW3) + Return (Arg3) + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI2 RCA2 + + // PCI3 RCA3 + Device (PCI3) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID, "PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID, "PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 0) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI3") + Name (_STR, Unicode("PCIe 3 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 140/141/142/143 respectively. PCI3 RCA3 + // + Package() {0x0001FFFF, 0, 0, 140}, + Package() {0x0001FFFF, 1, 0, 141}, + Package() {0x0001FFFF, 2, 0, 142}, + Package() {0x0001FFFF, 3, 0, 143}, + Package() {0x0002FFFF, 0, 0, 140}, + Package() {0x0002FFFF, 1, 0, 141}, + Package() {0x0002FFFF, 2, 0, 142}, + Package() {0x0002FFFF, 3, 0, 143}, + Package() {0x0003FFFF, 0, 0, 140}, + Package() {0x0003FFFF, 1, 0, 141}, + Package() {0x0003FFFF, 2, 0, 142}, + Package() {0x0003FFFF, 3, 0, 143}, + Package() {0x0004FFFF, 0, 0, 140}, + Package() {0x0004FFFF, 1, 0, 141}, + Package() {0x0004FFFF, 2, 0, 142}, + Package() {0x0004FFFF, 3, 0, 143}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x3FFFF0000000) + } + + // + // Declare a ResourceTemplate buffer to Return the resource + // requirements from _CRS. + // Section 19.5.109 + // + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FE00000, 0x10000, ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000038000000, // AddressMinimum - MIN + 0x000000003FFFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000008000000 // RangeLength - LEN + ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00003C0000000000, // AddressMinimum - MIN + 0x00003FFFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP, 0) // PCI _OSC Support Field value + Name (CTRL, 0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3, 0, CDW1) + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL, 0x1E, CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1, One)) { + Or (CDW1, 0x08, CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3, CTRL)) { + Or (CDW1, 0x10, CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL, CDW3) + Return (Arg3) + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI3 RCA3 + + // PCI4 RCB0 + Device (PCI4) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID, "PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) // The default value is 0x0. Unfortunately, it breaks + // run-time patching as the representation of 0 is special + // encoding and cannot be patched to expand with extra bytes + // easily. As such, we default to 0xF and patch this based + // on whether the port was enabled or not by the BIOS. + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID, "PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 2) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI4") + Name (_STR, Unicode("PCIe 4 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 144/145/146/147 respectively. PCI4 RCB0 + // + Package() {0x0001FFFF, 0, 0, 144}, + Package() {0x0001FFFF, 1, 0, 145}, + Package() {0x0001FFFF, 2, 0, 146}, + Package() {0x0001FFFF, 3, 0, 147}, + Package() {0x0002FFFF, 0, 0, 144}, + Package() {0x0002FFFF, 1, 0, 145}, + Package() {0x0002FFFF, 2, 0, 146}, + Package() {0x0002FFFF, 3, 0, 147}, + Package() {0x0003FFFF, 0, 0, 144}, + Package() {0x0003FFFF, 1, 0, 145}, + Package() {0x0003FFFF, 2, 0, 146}, + Package() {0x0003FFFF, 3, 0, 147}, + Package() {0x0004FFFF, 0, 0, 144}, + Package() {0x0004FFFF, 1, 0, 145}, + Package() {0x0004FFFF, 2, 0, 146}, + Package() {0x0004FFFF, 3, 0, 147}, + Package() {0x0005FFFF, 0, 0, 144}, + Package() {0x0005FFFF, 1, 0, 145}, + Package() {0x0005FFFF, 2, 0, 146}, + Package() {0x0005FFFF, 3, 0, 147}, + Package() {0x0006FFFF, 0, 0, 144}, + Package() {0x0006FFFF, 1, 0, 145}, + Package() {0x0006FFFF, 2, 0, 146}, + Package() {0x0006FFFF, 3, 0, 147}, + Package() {0x0007FFFF, 0, 0, 144}, + Package() {0x0007FFFF, 1, 0, 145}, + Package() {0x0007FFFF, 2, 0, 146}, + Package() {0x0007FFFF, 3, 0, 147}, + Package() {0x0008FFFF, 0, 0, 144}, + Package() {0x0008FFFF, 1, 0, 145}, + Package() {0x0008FFFF, 2, 0, 146}, + Package() {0x0008FFFF, 3, 0, 147}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x23FFF0000000) + } + + + // + // Declare a ResourceTemplate buffer to return the resource + // requirements from _CRS. + // Section 19.5.109 + // + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FEC0000, 0x10000, ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000004000000, // AddressMinimum - MIN + 0x0000000007FFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000004000000 // RangeLength - LEN + ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000200000000000, // AddressMinimum - MIN + 0x000023FFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP,0) // PCI _OSC Support Field value + Name (CTRL,0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3, 0, CDW1) + If (LEqual (Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL, 0x1E, CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1, One)) { + Or (CDW1, 0x08, CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3, CTRL)) { + Or (CDW1, 0x10, CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL, CDW3) + Return (Arg3) + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) + { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + // + // Root Port 1 + // + Device (P2P1) { + // + // Device 1, Function 0 (Bus 0). + // + + Name (_ADR, 0x00010000) + + Device (S0F0) { + // + // On Bus 1 ([01]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000001) + } + } + + // + // Root Port 3 + // + Device (P2P3) { + // + // Device 3, Function 0 (Bus 0). + // + + Name (_ADR, 0x00030000) + + Device (S0F0) { + // + // On Bus 2 ([02]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000002) + } + } + + // + // Root Port 5 + // + Device (P2P5) { + // + // Device 5, Function 0 (Bus 0). + // + + Name (_ADR, 0x00050000) + + Device (S0F0) { + // + // On Bus 3 [03]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000003) + } + } + + // + // Root Port 7 + // + Device (P2P7) { + // + // Device 7, Function 0 (Bus 0). + // + + Name (_ADR, 0x00070000) + + Device (S0F0) { + // + // On Bus 4 ([04]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000004) + } + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI4 RCB0 + + // PCI5 RCB1 + Device (PCI5) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID, "PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID,"PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 3) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI5") + Name (_STR, Unicode("PCIe 5 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 148/149/150/151 respectively. PCI5 RCB1 + // + Package() {0x0001FFFF, 0, 0, 148}, + Package() {0x0001FFFF, 1, 0, 149}, + Package() {0x0001FFFF, 2, 0, 150}, + Package() {0x0001FFFF, 3, 0, 151}, + Package() {0x0002FFFF, 0, 0, 148}, + Package() {0x0002FFFF, 1, 0, 149}, + Package() {0x0002FFFF, 2, 0, 150}, + Package() {0x0002FFFF, 3, 0, 151}, + Package() {0x0003FFFF, 0, 0, 148}, + Package() {0x0003FFFF, 1, 0, 149}, + Package() {0x0003FFFF, 2, 0, 150}, + Package() {0x0003FFFF, 3, 0, 151}, + Package() {0x0004FFFF, 0, 0, 148}, + Package() {0x0004FFFF, 1, 0, 149}, + Package() {0x0004FFFF, 2, 0, 150}, + Package() {0x0004FFFF, 3, 0, 151}, + Package() {0x0005FFFF, 0, 0, 148}, + Package() {0x0005FFFF, 1, 0, 149}, + Package() {0x0005FFFF, 2, 0, 150}, + Package() {0x0005FFFF, 3, 0, 151}, + Package() {0x0006FFFF, 0, 0, 148}, + Package() {0x0006FFFF, 1, 0, 149}, + Package() {0x0006FFFF, 2, 0, 150}, + Package() {0x0006FFFF, 3, 0, 151}, + Package() {0x0007FFFF, 0, 0, 148}, + Package() {0x0007FFFF, 1, 0, 149}, + Package() {0x0007FFFF, 2, 0, 150}, + Package() {0x0007FFFF, 3, 0, 151}, + Package() {0x0008FFFF, 0, 0, 148}, + Package() {0x0008FFFF, 1, 0, 149}, + Package() {0x0008FFFF, 2, 0, 150}, + Package() {0x0008FFFF, 3, 0, 151}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x27FFF0000000) + } + + // + // Declare a ResourceTemplate buffer to return the resource + // requirements from _CRS. + // Section 19.5.109 + // + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FF00000, 0x10000, ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000008000000, // AddressMinimum - MIN + 0x000000000FFFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000008000000 // RangeLength - LEN + ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000240000000000, // AddressMinimum - MIN + 0x000027FFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP, 0) // PCI _OSC Support Field value + Name (CTRL, 0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3, 0, CDW1) + If (LEqual (Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL, 0x1E, CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1, One)) { + Or (CDW1, 0x08, CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3, CTRL)) { + Or (CDW1, 0x10, CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL, CDW3) + Return (Arg3) + + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) + { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + // + // Root Port 1 + // + Device (P2P1) { + // + // Device 1, Function 0 (Bus 0). + // + + Name (_ADR, 0x00010000) + + Device (S0F0) { + // + // On Bus 1 ([01]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000001) + } + } + + // + // Root Port 3 + // + Device (P2P3) { + // + // Device 3, Function 0 (Bus 0). + // + + Name (_ADR, 0x00030000) + + Device (S0F0) { + // + // On Bus 2 ([02]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000002) + } + } + + // + // Root Port 5 + // + Device (P2P5) { + // + // Device 5, Function 0 (Bus 0). + // + + Name (_ADR, 0x00050000) + + Device (S0F0) { + // + // On Bus 3 [03]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000003) + } + } + + // + // Root Port 7 + // + Device (P2P7) { + // + // Device 7, Function 0 (Bus 0). + // + + Name (_ADR, 0x00070000) + + Device (S0F0) { + // + // On Bus 4 ([04]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000004) + } + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI5 RCB1 + + + // PCI6 RCB2 + Device (PCI6) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID,"PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) // The default value is 0x0. Unfortunately, it breaks + // run-time patching as the representation of 0 is special + // encoding and cannot be patched to expand with extra bytes + // easily. As such, we default to 0xF and patch this based + // on whether the port was enabled or not by the BIOS. + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID,"PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 4) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI6") + Name (_STR, Unicode("PCIe 6 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 152/153/154/155 respectively. PCI6 RCB2 + // + Package() {0x0001FFFF, 0, 0, 152}, + Package() {0x0001FFFF, 1, 0, 153}, + Package() {0x0001FFFF, 2, 0, 154}, + Package() {0x0001FFFF, 3, 0, 155}, + Package() {0x0002FFFF, 0, 0, 152}, + Package() {0x0002FFFF, 1, 0, 153}, + Package() {0x0002FFFF, 2, 0, 154}, + Package() {0x0002FFFF, 3, 0, 155}, + Package() {0x0003FFFF, 0, 0, 152}, + Package() {0x0003FFFF, 1, 0, 153}, + Package() {0x0003FFFF, 2, 0, 154}, + Package() {0x0003FFFF, 3, 0, 155}, + Package() {0x0004FFFF, 0, 0, 152}, + Package() {0x0004FFFF, 1, 0, 153}, + Package() {0x0004FFFF, 2, 0, 154}, + Package() {0x0004FFFF, 3, 0, 155}, + Package() {0x0005FFFF, 0, 0, 152}, + Package() {0x0005FFFF, 1, 0, 153}, + Package() {0x0005FFFF, 2, 0, 154}, + Package() {0x0005FFFF, 3, 0, 155}, + Package() {0x0006FFFF, 0, 0, 152}, + Package() {0x0006FFFF, 1, 0, 153}, + Package() {0x0006FFFF, 2, 0, 154}, + Package() {0x0006FFFF, 3, 0, 155}, + Package() {0x0007FFFF, 0, 0, 152}, + Package() {0x0007FFFF, 1, 0, 153}, + Package() {0x0007FFFF, 2, 0, 154}, + Package() {0x0007FFFF, 3, 0, 155}, + Package() {0x0008FFFF, 0, 0, 152}, + Package() {0x0008FFFF, 1, 0, 153}, + Package() {0x0008FFFF, 2, 0, 154}, + Package() {0x0008FFFF, 3, 0, 155}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x2BFFF0000000) + } + + // + // Declare a ResourceTemplate buffer to return the resource + // requirements from _CRS. + // Section 19.5.109 + // + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FF40000, 0x10000, ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000010000000, // AddressMinimum - MIN + 0x0000000017FFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000008000000 // RangeLength - LEN + ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000280000000000, // AddressMinimum - MIN + 0x00002BFFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP,0) // PCI _OSC Support Field value + Name (CTRL,0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3,0,CDW1) + If (LEqual (Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3,4,CDW2) + CreateDWordField (Arg3,8,CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2,SUPP) + Store (CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL,0x1E,CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1,One)) { + Or (CDW1,0x08,CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3,CTRL)) { + Or (CDW1,0x10,CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL,CDW3) + Return (Arg3) + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1,4,CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI6 RCB2 + + // PCI7 RCB3 + Device (PCI7) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID,"PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) // The default value is 0x0. Unfortunately, it breaks + // run-time patching as the representation of 0 is special + // encoding and cannot be patched to expand with extra bytes + // easily. As such, we default to 0xF and patch this based + // on whether the port was enabled or not by the BIOS. + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID,"PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 5) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI7") + Name (_STR, Unicode("PCIe 7 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 156/157/158/159 respectively. PCI7 RCB3 + // + Package() {0x0001FFFF, 0, 0, 156}, + Package() {0x0001FFFF, 1, 0, 157}, + Package() {0x0001FFFF, 2, 0, 158}, + Package() {0x0001FFFF, 3, 0, 159}, + Package() {0x0002FFFF, 0, 0, 156}, + Package() {0x0002FFFF, 1, 0, 157}, + Package() {0x0002FFFF, 2, 0, 158}, + Package() {0x0002FFFF, 3, 0, 159}, + Package() {0x0003FFFF, 0, 0, 156}, + Package() {0x0003FFFF, 1, 0, 157}, + Package() {0x0003FFFF, 2, 0, 158}, + Package() {0x0003FFFF, 3, 0, 159}, + Package() {0x0004FFFF, 0, 0, 156}, + Package() {0x0004FFFF, 1, 0, 157}, + Package() {0x0004FFFF, 2, 0, 158}, + Package() {0x0004FFFF, 3, 0, 159}, + Package() {0x0005FFFF, 0, 0, 156}, + Package() {0x0005FFFF, 1, 0, 157}, + Package() {0x0005FFFF, 2, 0, 158}, + Package() {0x0005FFFF, 3, 0, 159}, + Package() {0x0006FFFF, 0, 0, 156}, + Package() {0x0006FFFF, 1, 0, 157}, + Package() {0x0006FFFF, 2, 0, 158}, + Package() {0x0006FFFF, 3, 0, 159}, + Package() {0x0007FFFF, 0, 0, 156}, + Package() {0x0007FFFF, 1, 0, 157}, + Package() {0x0007FFFF, 2, 0, 158}, + Package() {0x0007FFFF, 3, 0, 159}, + Package() {0x0008FFFF, 0, 0, 156}, + Package() {0x0008FFFF, 1, 0, 157}, + Package() {0x0008FFFF, 2, 0, 158}, + Package() {0x0008FFFF, 3, 0, 159}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x2FFFF0000000) + } + + // + // Declare a ResourceTemplate buffer to return the resource + // requirements from _CRS. + // Section 19.5.109 + // + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FF40000, 0x10000, ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000018000000, // AddressMinimum - MIN + 0x000000001FFFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000008000000 // RangeLength - LEN + ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00002C0000000000, // AddressMinimum - MIN + 0x00002FFFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP,0) // PCI _OSC Support Field value + Name (CTRL,0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3,0,CDW1) + If (LEqual (Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3,4,CDW2) + CreateDWordField (Arg3,8,CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2,SUPP) + Store (CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL,0x1E,CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1,One)) { + Or (CDW1,0x08,CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3,CTRL)) { + Or (CDW1,0x10,CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL,CDW3) + Return (Arg3) + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1,4,CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI7 RCB3 diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PMU-S0.asi b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PMU-S0.asi new file mode 100755 index 00000000000..78549356570 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PMU-S0.asi @@ -0,0 +1,905 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope(\_SB) { + Device(CMN0) { + Name(_HID, "ARMHC600") // Device Identification Objects + Name(_CID, "ARMHC600") + Name(_UID, 0) + Name(_CCA, ONE) + Name(_STR, Unicode("CMN0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceConsumer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100010000000, // AddressMinimum - MIN + 0x0000100013ffffff, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000004000000 // RangeLength - LEN + ) + QWordMemory ( + ResourceConsumer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100012500000, // AddressMinimum - MIN + 0x0000100013ffffff, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000001B00000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 314 } + }) + } + + Device(MC00) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 0) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000010008C000A00, // AddressMinimum - MIN + 0x000010008C000BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 312 } + }) + } + + Device(MC01) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 1) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU1")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000010008C400A00, // AddressMinimum - MIN + 0x000010008C400BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 312 } + }) + } + + Device(MC02) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 2) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU2")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000010008C800A00, // AddressMinimum - MIN + 0x000010008C800BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 312 } + }) + } + + Device(MC03) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 3) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU3")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000010008CC00A00, // AddressMinimum - MIN + 0x000010008CC00BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 312 } + }) + } + + Device(MC04) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 4) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU4")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000010008D000A00, // AddressMinimum - MIN + 0x000010008D000BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 312 } + }) + } + + Device(MC05) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 5) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU5")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000010008D400A00, // AddressMinimum - MIN + 0x000010008D400BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 312 } + }) + } + + Device(MC06) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 6) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU6")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000010008D800A00, // AddressMinimum - MIN + 0x000010008D800BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 312 } + }) + } + + Device(MC07) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 7) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU7")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000010008DC00A00, // AddressMinimum - MIN + 0x000010008DC00BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 312 } + }) + } +} + +Scope (\_SB.SYST.CL00) { + Device(DU00) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 64 } + }) + } +} + +Scope (\_SB.SYST.CL01) { + Device(DU01) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x1) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x1 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 65 } + }) + } +} + +Scope (\_SB.SYST.CL02) { + Device(DU02) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x2) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x2 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 66 } + }) + } +} + +Scope (\_SB.SYST.CL03) { + Device(DU03) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x3) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x3 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 67 } + }) + } +} + +Scope (\_SB.SYST.CL04) { + Device(DU04) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x4) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x4 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 68 } + }) + } +} + +Scope (\_SB.SYST.CL05) { + Device(DU05) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x5) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x5 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 69 } + }) + } +} + +Scope (\_SB.SYST.CL06) { + Device(DU06) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x6) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x6 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 71 } + }) + } +} + +Scope (\_SB.SYST.CL07) { + Device(DU07) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x7) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x7 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 80 } + }) + } +} + +Scope (\_SB.SYST.CL08) { + Device(DU08) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x8) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x8 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 81 } + }) + } +} + +Scope (\_SB.SYST.CL09) { + Device(DU09) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x9) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x9 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 82 } + }) + } +} + +Scope (\_SB.SYST.CL0A) { + Device(DU0A) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0xA) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0xA Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 83 } + }) + } +} + +Scope (\_SB.SYST.CL0B) { + Device(DU0B) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0xB) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0xB Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 115 } + }) + } +} + +Scope (\_SB.SYST.CL0C) { + Device(DU0C) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0xC) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0xC Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 116 } + }) + } +} + +Scope (\_SB.SYST.CL0D) { + Device(DU0D) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0xD) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0xD Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 120 } + }) + } +} + +Scope (\_SB.SYST.CL0E) { + Device(DU0E) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0xE) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0xE Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 121 } + }) + } +} + +Scope (\_SB.SYST.CL0F) { + Device(DU0F) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0xF) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0xF Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 122 } + }) + } +} + +Scope (\_SB.SYST.CL10) { + Device(DU10) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x10) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x10 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 123 } + }) + } +} + +Scope (\_SB.SYST.CL11) { + Device(DU11) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x11) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x11 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 124 } + }) + } +} + +Scope (\_SB.SYST.CL12) { + Device(DU12) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x12) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x12 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 125 } + }) + } +} + +Scope (\_SB.SYST.CL13) { + Device(DU13) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x13) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x13 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 126 } + }) + } +} + +Scope (\_SB.SYST.CL14) { + Device(DU14) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x14) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x14 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 127 } + }) + } +} + +Scope (\_SB.SYST.CL15) { + Device(DU15) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x15) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x15 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 221 } + }) + } +} + +Scope (\_SB.SYST.CL16) { + Device(DU16) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x16) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x16 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 222 } + }) + } +} + +Scope (\_SB.SYST.CL17) { + Device(DU17) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x17) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x17 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 223 } + }) + } +} + +Scope (\_SB.SYST.CL18) { + Device(DU18) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x18) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x18 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 248 } + }) + } +} + +Scope (\_SB.SYST.CL19) { + Device(DU19) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x19) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x19 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 249 } + }) + } +} + +Scope (\_SB.SYST.CL1A) { + Device(DU1A) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x1A) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x1A Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 250 } + }) + } +} + +Scope (\_SB.SYST.CL1B) { + Device(DU1B) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x1B) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x1B Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 251 } + }) + } +} + +Scope (\_SB.SYST.CL1C) { + Device(DU1C) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x1C) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x1C Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 252 } + }) + } +} + +Scope (\_SB.SYST.CL1D) { + Device(DU1D) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x1D) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x1D Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 253 } + }) + } +} + +Scope (\_SB.SYST.CL1E) { + Device(DU1E) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x1E) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x1E Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 254 } + }) + } +} + +Scope (\_SB.SYST.CL1F) { + Device(DU1F) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x1F) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x1F Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 255 } + }) + } +} + +Scope (\_SB.SYST.CL20) { + Device(DU20) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x20) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x20 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 297 } + }) + } +} + +Scope (\_SB.SYST.CL21) { + Device(DU21) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x21) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x21 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 298 } + }) + } +} + +Scope (\_SB.SYST.CL22) { + Device(DU22) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x22) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x22 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 299 } + }) + } +} + +Scope (\_SB.SYST.CL23) { + Device(DU23) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x23) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x23 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 300 } + }) + } +} + +Scope (\_SB.SYST.CL24) { + Device(DU24) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x24) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x24 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 301 } + }) + } +} + +Scope (\_SB.SYST.CL25) { + Device(DU25) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x25) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x25 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 313 } + }) + } +} + +Scope (\_SB.SYST.CL26) { + Device(DU26) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x26) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x26 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 316 } + }) + } +} + +Scope (\_SB.SYST.CL27) { + Device(DU27) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x27) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x27 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 317 } + }) + } +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PMU.asi b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PMU.asi new file mode 100644 index 00000000000..993ac396ede --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac01AcpiTables/PMU.asi @@ -0,0 +1,9 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Include ("PMU-S0.asi") diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/Ac02AcpiTables.inf b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/Ac02AcpiTables.inf new file mode 100644 index 00000000000..48275e567cc --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/Ac02AcpiTables.inf @@ -0,0 +1,20 @@ +## @file +# +# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = Ac02AcpiTables + FILE_GUID = 5CA064B6-5AA4-4E29-ABDC-8BF3B34DBF9E + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + Dsdt.asl + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/CPU-S0.asi b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/CPU-S0.asi new file mode 100644 index 00000000000..c71f9c60d1d --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/CPU-S0.asi @@ -0,0 +1,6345 @@ +/** @file + + Copyright (c) 2021 - 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope (\_SB.SYST) { + Device (CL00) { + Name(_HID, "ACPI0010") + Name(_UID, 0x1) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL01) { + Name(_HID, "ACPI0010") + Name(_UID, 0x2) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL02) { + Name(_HID, "ACPI0010") + Name(_UID, 0x3) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL03) { + Name(_HID, "ACPI0010") + Name(_UID, 0x4) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL04) { + Name(_HID, "ACPI0010") + Name(_UID, 0x5) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL05) { + Name(_HID, "ACPI0010") + Name(_UID, 0x6) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL06) { + Name(_HID, "ACPI0010") + Name(_UID, 0x7) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL07) { + Name(_HID, "ACPI0010") + Name(_UID, 0x8) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL08) { + Name(_HID, "ACPI0010") + Name(_UID, 0x9) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL09) { + Name(_HID, "ACPI0010") + Name(_UID, 0xA) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL0A) { + Name(_HID, "ACPI0010") + Name(_UID, 0xB) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL0B) { + Name(_HID, "ACPI0010") + Name(_UID, 0xC) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL0C) { + Name(_HID, "ACPI0010") + Name(_UID, 0xD) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL0D) { + Name(_HID, "ACPI0010") + Name(_UID, 0xE) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL0E) { + Name(_HID, "ACPI0010") + Name(_UID, 0xF) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL0F) { + Name(_HID, "ACPI0010") + Name(_UID, 0x10) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL10) { + Name(_HID, "ACPI0010") + Name(_UID, 0x11) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL11) { + Name(_HID, "ACPI0010") + Name(_UID, 0x12) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL12) { + Name(_HID, "ACPI0010") + Name(_UID, 0x13) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL13) { + Name(_HID, "ACPI0010") + Name(_UID, 0x14) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL14) { + Name(_HID, "ACPI0010") + Name(_UID, 0x15) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL15) { + Name(_HID, "ACPI0010") + Name(_UID, 0x16) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL16) { + Name(_HID, "ACPI0010") + Name(_UID, 0x17) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL17) { + Name(_HID, "ACPI0010") + Name(_UID, 0x18) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL18) { + Name(_HID, "ACPI0010") + Name(_UID, 0x19) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL19) { + Name(_HID, "ACPI0010") + Name(_UID, 0x1A) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL1A) { + Name(_HID, "ACPI0010") + Name(_UID, 0x1B) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL1B) { + Name(_HID, "ACPI0010") + Name(_UID, 0x1C) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL1C) { + Name(_HID, "ACPI0010") + Name(_UID, 0x1D) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL1D) { + Name(_HID, "ACPI0010") + Name(_UID, 0x1E) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL1E) { + Name(_HID, "ACPI0010") + Name(_UID, 0x1F) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL1F) { + Name(_HID, "ACPI0010") + Name(_UID, 0x20) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL20) { + Name(_HID, "ACPI0010") + Name(_UID, 0x21) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL21) { + Name(_HID, "ACPI0010") + Name(_UID, 0x22) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL22) { + Name(_HID, "ACPI0010") + Name(_UID, 0x23) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL23) { + Name(_HID, "ACPI0010") + Name(_UID, 0x24) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL24) { + Name(_HID, "ACPI0010") + Name(_UID, 0x25) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL25) { + Name(_HID, "ACPI0010") + Name(_UID, 0x26) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL26) { + Name(_HID, "ACPI0010") + Name(_UID, 0x27) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL27) { + Name(_HID, "ACPI0010") + Name(_UID, 0x28) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL28) { + Name(_HID, "ACPI0010") + Name(_UID, 0x29) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL29) { + Name(_HID, "ACPI0010") + Name(_UID, 0x2A) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL2A) { + Name(_HID, "ACPI0010") + Name(_UID, 0x2B) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL2B) { + Name(_HID, "ACPI0010") + Name(_UID, 0x2C) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL2C) { + Name(_HID, "ACPI0010") + Name(_UID, 0x2D) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL2D) { + Name(_HID, "ACPI0010") + Name(_UID, 0x2E) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL2E) { + Name(_HID, "ACPI0010") + Name(_UID, 0x2F) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL2F) { + Name(_HID, "ACPI0010") + Name(_UID, 0x30) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL30) { + Name(_HID, "ACPI0010") + Name(_UID, 0x31) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL31) { + Name(_HID, "ACPI0010") + Name(_UID, 0x32) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL32) { + Name(_HID, "ACPI0010") + Name(_UID, 0x33) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL33) { + Name(_HID, "ACPI0010") + Name(_UID, 0x34) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL34) { + Name(_HID, "ACPI0010") + Name(_UID, 0x35) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL35) { + Name(_HID, "ACPI0010") + Name(_UID, 0x36) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL36) { + Name(_HID, "ACPI0010") + Name(_UID, 0x37) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL37) { + Name(_HID, "ACPI0010") + Name(_UID, 0x38) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL38) { + Name(_HID, "ACPI0010") + Name(_UID, 0x39) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL39) { + Name(_HID, "ACPI0010") + Name(_UID, 0x3A) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL3A) { + Name(_HID, "ACPI0010") + Name(_UID, 0x3B) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL3B) { + Name(_HID, "ACPI0010") + Name(_UID, 0x3C) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL3C) { + Name(_HID, "ACPI0010") + Name(_UID, 0x3D) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL3D) { + Name(_HID, "ACPI0010") + Name(_UID, 0x3E) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL3E) { + Name(_HID, "ACPI0010") + Name(_UID, 0x3F) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } + + Device (CL3F) { + Name(_HID, "ACPI0010") + Name(_UID, 0x40) + + Method (_LPI, 0, NotSerialized) { + return(CLPI) + } + } +} + +Scope (\_SB.SYST.CL00) { + Device(C000) { + Name(_HID, "ACPI0007") + Name(_UID, 0x0) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x000, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x004, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x008, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x00c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x010, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x014, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x050, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x054, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x058, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 0, 0xFD, 2} + }) // Domain 0 + } + + Device(C001) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x080, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x084, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x088, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x08c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x090, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x094, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x0d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x0d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x0d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 1, 0xFD, 2} + }) // Domain 1 + } +} + +Scope (\_SB.SYST.CL01) { + Device(C002) { + Name(_HID, "ACPI0007") + Name(_UID, 0x100) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x100, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x104, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x108, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x10c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x114, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x12c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x134, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x13c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x150, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x154, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x158, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 2, 0xFD, 2} + }) // Domain 2 + } + + Device(C003) { + Name(_HID, "ACPI0007") + Name(_UID, 0x101) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x180, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x184, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x188, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x18c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x190, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x194, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 3, 0xFD, 2} + }) // Domain 3 + } +} + +Scope (\_SB.SYST.CL02) { + Device(C004) { + Name(_HID, "ACPI0007") + Name(_UID, 0x200) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x200, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x204, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x208, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x20c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x210, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x214, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x22c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x234, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x23c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x250, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x254, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x258, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 4, 0xFD, 2} + }) // Domain 4 + } + + Device(C005) { + Name(_HID, "ACPI0007") + Name(_UID, 0x201) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x280, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x284, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x288, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x28c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x290, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x294, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 5, 0xFD, 2} + }) // Domain 5 + } +} + +Scope (\_SB.SYST.CL03) { + Device(C006) { + Name(_HID, "ACPI0007") + Name(_UID, 0x300) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x300, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x304, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x308, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x30c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x310, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x314, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x32c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x334, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x33c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x350, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x354, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x358, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 6, 0xFD, 2} + }) // Domain 6 + } + + Device(C007) { + Name(_HID, "ACPI0007") + Name(_UID, 0x301) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x380, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x384, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x388, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x38c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x390, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x394, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 7, 0xFD, 2} + }) // Domain 7 + } +} + +Scope (\_SB.SYST.CL04) { + Device(C008) { + Name(_HID, "ACPI0007") + Name(_UID, 0x400) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x400, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x404, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x408, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x40c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x410, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x414, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x42c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x434, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x43c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x450, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x454, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x458, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 8, 0xFD, 2} + }) // Domain 8 + } + + Device(C009) { + Name(_HID, "ACPI0007") + Name(_UID, 0x401) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x480, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x484, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x488, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x48c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x490, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x494, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x4ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x4b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x4bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x4d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x4d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x4d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 9, 0xFD, 2} + }) // Domain 9 + } +} + +Scope (\_SB.SYST.CL05) { + Device(C010) { + Name(_HID, "ACPI0007") + Name(_UID, 0x500) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x500, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x504, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x508, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x50c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x510, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x514, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x52c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x534, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x53c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x550, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x554, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x558, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 10, 0xFD, 2} + }) // Domain 10 + } + + Device(C011) { + Name(_HID, "ACPI0007") + Name(_UID, 0x501) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x580, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x584, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x588, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x58c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x590, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x594, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x5ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x5b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x5bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x5d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x5d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x5d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 11, 0xFD, 2} + }) // Domain 11 + } +} + +Scope (\_SB.SYST.CL06) { + Device(C012) { + Name(_HID, "ACPI0007") + Name(_UID, 0x600) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x600, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x604, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x608, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x60c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x610, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x614, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x62c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x634, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x63c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x650, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x654, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x658, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 12, 0xFD, 2} + }) // Domain 12 + } + + Device(C013) { + Name(_HID, "ACPI0007") + Name(_UID, 0x601) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x680, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x684, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x688, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x68c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x690, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x694, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x6ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x6b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x6bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x6d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x6d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x6d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 13, 0xFD, 2} + }) // Domain 13 + } +} + +Scope (\_SB.SYST.CL07) { + Device(C014) { + Name(_HID, "ACPI0007") + Name(_UID, 0x700) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x700, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x704, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x708, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x70c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x710, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x714, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x72c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x734, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x73c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x750, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x754, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x758, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 14, 0xFD, 2} + }) // Domain 14 + } + + Device(C015) { + Name(_HID, "ACPI0007") + Name(_UID, 0x701) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x780, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x784, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x788, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x78c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x790, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x794, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x7ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x7b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x7bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x7d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x7d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x7d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 15, 0xFD, 2} + }) // Domain 15 + } +} + +Scope (\_SB.SYST.CL08) { + Device(C016) { + Name(_HID, "ACPI0007") + Name(_UID, 0x800) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x800, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x804, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x808, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x80c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x810, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x814, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x82c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x834, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x83c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x850, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x854, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x858, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 16, 0xFD, 2} + }) // Domain 16 + } + + Device(C017) { + Name(_HID, "ACPI0007") + Name(_UID, 0x801) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x880, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x884, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x888, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x88c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x890, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x894, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x8ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x8b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x8bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x8d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x8d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x8d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 17, 0xFD, 2} + }) // Domain 17 + } +} + +Scope (\_SB.SYST.CL09) { + Device(C018) { + Name(_HID, "ACPI0007") + Name(_UID, 0x900) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x900, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x904, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x908, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x90c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x910, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x914, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x92c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x934, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x93c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x950, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x954, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x958, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 18, 0xFD, 2} + }) // Domain 18 + } + + Device(C019) { + Name(_HID, "ACPI0007") + Name(_UID, 0x901) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x980, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x984, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x988, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x98c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x990, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x994, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x9ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x9b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x9bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x9d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x9d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x9d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 19, 0xFD, 2} + }) // Domain 19 + } +} + +Scope (\_SB.SYST.CL0A) { + Device(C020) { + Name(_HID, "ACPI0007") + Name(_UID, 0xa00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xa00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xa14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xa2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xa34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xa3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xa50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xa54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xa58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 20, 0xFD, 2} + }) // Domain 20 + } + + Device(C021) { + Name(_HID, "ACPI0007") + Name(_UID, 0xa01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xa80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xa90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xa94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xaac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xab4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xabc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xad0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xad4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xad8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 21, 0xFD, 2} + }) // Domain 21 + } +} + +Scope (\_SB.SYST.CL0B) { + Device(C022) { + Name(_HID, "ACPI0007") + Name(_UID, 0xb00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xb00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xb14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xb2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xb34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xb3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xb50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xb54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xb58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 22, 0xFD, 2} + }) // Domain 22 + } + + Device(C023) { + Name(_HID, "ACPI0007") + Name(_UID, 0xb01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xb80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xb90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xb94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xbac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xbb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xbbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xbd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xbd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xbd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 23, 0xFD, 2} + }) // Domain 23 + } +} + +Scope (\_SB.SYST.CL0C) { + Device(C024) { + Name(_HID, "ACPI0007") + Name(_UID, 0xc00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xc00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xc14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xc2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xc34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xc3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xc50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xc54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xc58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 24, 0xFD, 2} + }) // Domain 24 + } + + Device(C025) { + Name(_HID, "ACPI0007") + Name(_UID, 0xc01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xc80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xc90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xc94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xcac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xcb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xcbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xcd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xcd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xcd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 25, 0xFD, 2} + }) // Domain 25 + } +} + +Scope (\_SB.SYST.CL0D) { + Device(C026) { + Name(_HID, "ACPI0007") + Name(_UID, 0xd00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xd00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xd14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xd2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xd34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xd3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xd50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xd54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xd58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 26, 0xFD, 2} + }) // Domain 26 + } + + Device(C027) { + Name(_HID, "ACPI0007") + Name(_UID, 0xd01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xd80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xd90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xd94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xdac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xdb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xdbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xdd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xdd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xdd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 27, 0xFD, 2} + }) // Domain 27 + } +} + +Scope (\_SB.SYST.CL0E) { + Device(C028) { + Name(_HID, "ACPI0007") + Name(_UID, 0xe00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xe00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xe14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xe2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xe34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xe3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xe50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xe54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xe58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 28, 0xFD, 2} + }) // Domain 28 + } + + Device(C029) { + Name(_HID, "ACPI0007") + Name(_UID, 0xe01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xe80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xe90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xe94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xeac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xeb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xebc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xed0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xed4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xed8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 29, 0xFD, 2} + }) // Domain 29 + } +} + +Scope (\_SB.SYST.CL0F) { + Device(C030) { + Name(_HID, "ACPI0007") + Name(_UID, 0xf00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xf00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xf14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xf2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xf34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xf3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xf50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xf54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xf58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 30, 0xFD, 2} + }) // Domain 30 + } + + Device(C031) { + Name(_HID, "ACPI0007") + Name(_UID, 0xf01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0xf80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0xf90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xf94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0xfac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0xfb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0xfbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0xfd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0xfd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0xfd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 31, 0xFD, 2} + }) // Domain 31 + } +} + +Scope (\_SB.SYST.CL10) { + Device(C032) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1000) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1000, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1004, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1008, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x100c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1010, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1014, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x102c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1034, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x103c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1050, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1054, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1058, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 32, 0xFD, 2} + }) // Domain 32 + } + + Device(C033) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1001) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1080, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1084, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1088, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x108c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1090, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1094, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x10ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x10b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x10bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x10d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x10d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x10d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 33, 0xFD, 2} + }) // Domain 33 + } +} + +Scope (\_SB.SYST.CL11) { + Device(C034) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1100) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1100, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1104, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1108, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x110c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1110, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1114, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x112c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1134, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x113c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1150, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1154, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1158, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 34, 0xFD, 2} + }) // Domain 34 + } + + Device(C035) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1101) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1180, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1184, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1188, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x118c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1190, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1194, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x11ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x11b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x11bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x11d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x11d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x11d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 35, 0xFD, 2} + }) // Domain 35 + } +} + +Scope (\_SB.SYST.CL12) { + Device(C036) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1200) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1200, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1204, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1208, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x120c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1210, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1214, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x122c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1234, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x123c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1250, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1254, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1258, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 36, 0xFD, 2} + }) // Domain 36 + } + + Device(C037) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1201) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1280, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1284, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1288, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x128c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1290, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1294, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x12ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x12b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x12bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x12d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x12d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x12d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 37, 0xFD, 2} + }) // Domain 37 + } +} + +Scope (\_SB.SYST.CL13) { + Device(C038) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1300) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1300, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1304, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1308, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x130c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1310, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1314, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x132c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1334, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x133c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1350, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1354, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1358, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 38, 0xFD, 2} + }) // Domain 38 + } + + Device(C039) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1301) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1380, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1384, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1388, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x138c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1390, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1394, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x13ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x13b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x13bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x13d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x13d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x13d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 39, 0xFD, 2} + }) // Domain 39 + } +} + +Scope (\_SB.SYST.CL14) { + Device(C040) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1400) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1400, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1404, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1408, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x140c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1410, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1414, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x142c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1434, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x143c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1450, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1454, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1458, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 40, 0xFD, 2} + }) // Domain 40 + } + + Device(C041) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1401) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1480, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1484, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1488, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x148c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1490, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1494, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x14ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x14b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x14bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x14d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x14d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x14d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 41, 0xFD, 2} + }) // Domain 41 + } +} + +Scope (\_SB.SYST.CL15) { + Device(C042) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1500) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1500, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1504, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1508, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x150c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1510, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1514, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x152c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1534, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x153c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1550, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1554, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1558, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 42, 0xFD, 2} + }) // Domain 42 + } + + Device(C043) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1501) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1580, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1584, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1588, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x158c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1590, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1594, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x15ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x15b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x15bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x15d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x15d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x15d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 43, 0xFD, 2} + }) // Domain 43 + } +} + +Scope (\_SB.SYST.CL16) { + Device(C044) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1600) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1600, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1604, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1608, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x160c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1610, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1614, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x162c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1634, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x163c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1650, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1654, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1658, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 44, 0xFD, 2} + }) // Domain 44 + } + + Device(C045) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1601) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1680, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1684, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1688, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x168c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1690, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1694, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x16ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x16b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x16bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x16d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x16d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x16d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 45, 0xFD, 2} + }) // Domain 45 + } +} + +Scope (\_SB.SYST.CL17) { + Device(C046) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1700) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1700, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1704, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1708, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x170c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1710, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1714, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x172c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1734, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x173c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1750, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1754, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1758, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 46, 0xFD, 2} + }) // Domain 46 + } + + Device(C047) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1701) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1780, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1784, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1788, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x178c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1790, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1794, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x17ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x17b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x17bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x17d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x17d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x17d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 47, 0xFD, 2} + }) // Domain 47 + } +} + +Scope (\_SB.SYST.CL18) { + Device(C048) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1800) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1800, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1804, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1808, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x180c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1810, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1814, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x182c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1834, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x183c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1850, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1854, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1858, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 48, 0xFD, 2} + }) // Domain 48 + } + + Device(C049) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1801) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1880, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1884, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1888, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x188c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1890, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1894, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x18ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x18b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x18bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x18d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x18d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x18d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 49, 0xFD, 2} + }) // Domain 49 + } +} + +Scope (\_SB.SYST.CL19) { + Device(C050) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1900) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1900, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1904, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1908, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x190c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1910, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1914, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x192c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1934, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x193c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1950, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1954, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1958, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 50, 0xFD, 2} + }) // Domain 50 + } + + Device(C051) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1901) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1980, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1984, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1988, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x198c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1990, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1994, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x19ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x19b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x19bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x19d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x19d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x19d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 51, 0xFD, 2} + }) // Domain 51 + } +} + +Scope (\_SB.SYST.CL1A) { + Device(C052) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1a00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1a00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1a14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1a2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1a34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1a3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1a50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1a54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1a58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 52, 0xFD, 2} + }) // Domain 52 + } + + Device(C053) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1a01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1a80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1a90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1a94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1aac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1ab4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1abc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1ad0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1ad4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1ad8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 53, 0xFD, 2} + }) // Domain 53 + } +} + +Scope (\_SB.SYST.CL1B) { + Device(C054) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1b00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1b00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1b14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1b2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1b34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1b3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1b50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1b54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1b58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 54, 0xFD, 2} + }) // Domain 54 + } + + Device(C055) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1b01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1b80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1b90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1b94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1bac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1bb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1bbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1bd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1bd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1bd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 55, 0xFD, 2} + }) // Domain 5 + } +} + +Scope (\_SB.SYST.CL1C) { + Device(C056) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1c00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1c00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1c14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1c2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1c34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1c3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1c50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1c54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1c58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 56, 0xFD, 2} + }) // Domain 56 + } + + Device(C057) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1c01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1c80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1c90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1c94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1cac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1cb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1cbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1cd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1cd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1cd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 57, 0xFD, 2} + }) // Domain 57 + } +} + +Scope (\_SB.SYST.CL1D) { + Device(C058) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1d00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1d00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1d2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1d34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 58, 0xFD, 2} + }) // Domain 58 + } + + Device(C059) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1d01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1d80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1d90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1d94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1dac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1db4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1dbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1dd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1dd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1dd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 59, 0xFD, 2} + }) // Domain 59 + } +} + +Scope (\_SB.SYST.CL1E) { + Device(C060) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1e00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1e00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1e14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1e2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1e34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1e3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1e50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1e54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1e58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 60, 0xFD, 2} + }) // Domain 60 + } + + Device(C061) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1e01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1e80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1e90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1e94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1eac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1eb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1ebc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1ed0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1ed4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1ed8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 61, 0xFD, 2} + }) // Domain 61 + } +} + +Scope (\_SB.SYST.CL1F) { + Device(C062) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1f00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1f00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1f14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1f2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1f34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1f3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1f50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1f54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1f58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 62, 0xFD, 2} + }) // Domain 62 + } + + Device(C063) { + Name(_HID, "ACPI0007") + Name(_UID, 0x1f01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x1f80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x1f90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1f94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x1fac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x1fb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1fbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1fd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1fd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x1fd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 63, 0xFD, 2} + }) // Domain 63 + } +} + +Scope (\_SB.SYST.CL20) { + Device(C064) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2000) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2000, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2004, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2008, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x200c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2010, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2014, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x202c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2034, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x203c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2050, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2054, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2058, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 64, 0xFD, 2} + }) // Domain 64 + } + + Device(C065) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2001) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2080, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2084, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2088, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x208c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2090, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2094, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x20ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x20b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x20bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x20d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x20d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x20d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 65, 0xFD, 2} + }) // Domain 65 + } +} + +Scope (\_SB.SYST.CL21) { + Device(C066) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2100) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2100, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2104, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2108, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x210c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2110, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2114, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x212c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2134, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x213c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2150, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2154, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2158, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 66, 0xFD, 2} + }) // Domain 66 + } + + Device(C067) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2101) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2180, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2184, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2188, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x218c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2190, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2194, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x21ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x21b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x21bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x21d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x21d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x21d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 67, 0xFD, 2} + }) // Domain 67 + } +} + +Scope (\_SB.SYST.CL22) { + Device(C068) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2200) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2200, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2204, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2208, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x220c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2210, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2214, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x222c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2234, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x223c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2250, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2254, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2258, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 68, 0xFD, 2} + }) // Domain 68 + } + + Device(C069) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2201) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2280, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2284, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2288, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x228c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2290, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2294, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x22ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x22b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x22bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x22d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x22d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x22d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 69, 0xFD, 2} + }) // Domain 69 + } +} + +Scope (\_SB.SYST.CL23) { + Device(C070) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2300) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2300, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2304, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2308, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x230c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2310, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2314, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x232c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2334, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x233c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2350, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2354, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2358, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 70, 0xFD, 2} + }) // Domain 70 + } + + Device(C071) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2301) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2380, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2384, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2388, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x238c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2390, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2394, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x23ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x23b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x23bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x23d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x23d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x23d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 71, 0xFD, 2} + }) // Domain 71 + } +} + +Scope (\_SB.SYST.CL24) { + Device(C072) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2400) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2400, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2404, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2408, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x240c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2410, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2414, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x242c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2434, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x243c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2450, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2454, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2458, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 72, 0xFD, 2} + }) // Domain 72 + } + + Device(C073) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2401) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2480, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2484, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2488, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x248c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2490, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2494, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x24ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x24b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x24bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x24d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x24d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x24d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 73, 0xFD, 2} + }) // Domain 73 + } +} + +Scope (\_SB.SYST.CL25) { + Device(C074) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2500) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2500, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2504, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2508, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x250c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2510, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2514, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x252c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2534, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x253c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2550, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2554, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2558, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 74, 0xFD, 2} + }) // Domain 74 + } + + Device(C075) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2501) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2580, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2584, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2588, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x258c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2590, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2594, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x25ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x25b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x25bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x25d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x25d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x25d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 75, 0xFD, 2} + }) // Domain 75 + } +} + +Scope (\_SB.SYST.CL26) { + Device(C076) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2600) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2600, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2604, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2608, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x260c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2610, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2614, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x262c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2634, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x263c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2650, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2654, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2658, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 76, 0xFD, 2} + }) // Domain 76 + } + + Device(C077) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2601) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2680, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2684, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2688, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x268c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2690, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2694, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x26ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x26b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x26bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x26d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x26d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x26d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 77, 0xFD, 2} + }) // Domain 77 + } +} + +Scope (\_SB.SYST.CL27) { + Device(C078) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2700) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2700, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2704, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2708, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x270c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2710, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2714, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x272c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2734, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x273c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2750, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2754, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2758, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 78, 0xFD, 2} + }) // Domain 78 + } + + Device(C079) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2701) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2780, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2784, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2788, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x278c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2790, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2794, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x27ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x27b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x27bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x27d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x27d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x27d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 79, 0xFD, 2} + }) // Domain 79 + } +} + +Scope (\_SB.SYST.CL28) { + Device(C080) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2800) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2800, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2804, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2808, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x280c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2810, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2814, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x282c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2834, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x283c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2850, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2854, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2858, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 80, 0xFD, 2} + }) // Domain 80 + } + + Device(C081) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2801) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2880, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2884, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2888, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x288c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2890, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2894, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x28ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x28b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x28bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x28d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x28d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x28d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 81, 0xFD, 2} + }) // Domain 81 + } +} + +Scope (\_SB.SYST.CL29) { + Device(C082) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2900) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2900, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2904, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2908, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x290c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2910, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2914, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x292c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2934, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x293c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2950, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2954, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2958, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 82, 0xFD, 2} + }) // Domain 82 + } + + Device(C083) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2901) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2980, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2984, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2988, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x298c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2990, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2994, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x29ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x29b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x29bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x29d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x29d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x29d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 83, 0xFD, 2} + }) // Domain 83 + } +} + +Scope (\_SB.SYST.CL2A) { + Device(C084) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2a00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2a00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2a14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2a2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2a34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2a3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2a50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2a54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2a58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 84, 0xFD, 2} + }) // Domain 84 + } + + Device(C085) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2a01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2a80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2a90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2a94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2aac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2ab4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2abc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2ad0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2ad4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2ad8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 85, 0xFD, 2} + }) // Domain 85 + } +} + +Scope (\_SB.SYST.CL2B) { + Device(C086) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2b00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2b00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2b14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2b2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2b34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2b3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2b50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2b54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2b58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 86, 0xFD, 2} + }) // Domain 86 + } + + Device(C087) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2b01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2b80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2b90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2b94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2bac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2bb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2bbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2bd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2bd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2bd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 87, 0xFD, 2} + }) // Domain 87 + } +} + +Scope (\_SB.SYST.CL2C) { + Device(C088) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2c00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2c00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2c14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2c2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2c34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2c3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2c50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2c54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2c58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 88, 0xFD, 2} + }) // Domain 88 + } + + Device(C089) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2c01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2c80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2c90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2c94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2cac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2cb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2cbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2cd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2cd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2cd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 89, 0xFD, 2} + }) // Domain 89 + } +} + +Scope (\_SB.SYST.CL2D) { + Device(C090) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2d00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2d00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2d2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2d34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 90, 0xFD, 2} + }) // Domain 90 + } + + Device(C091) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2d01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2d80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2d90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2d94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2dac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2db4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2dbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2dd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2dd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2dd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 91, 0xFD, 2} + }) // Domain 91 + } +} + +Scope (\_SB.SYST.CL2E) { + Device(C092) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2e00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2e00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2e14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2e2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2e34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2e3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2e50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2e54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2e58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 92, 0xFD, 2} + }) // Domain 92 + } + + Device(C093) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2e01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2e80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2e90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2e94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2eac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2eb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2ebc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2ed0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2ed4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2ed8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 93, 0xFD, 2} + }) // Domain 93 + } +} + +Scope (\_SB.SYST.CL2F) { + Device(C094) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2f00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2f00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2f14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2f2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2f34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2f3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2f50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2f54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2f58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 94, 0xFD, 2} + }) // Domain 94 + } + + Device(C095) { + Name(_HID, "ACPI0007") + Name(_UID, 0x2f01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x2f80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x2f90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2f94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x2fac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x2fb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2fbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2fd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2fd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x2fd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 95, 0xFD, 2} + }) // Domain 95 + } +} + +Scope (\_SB.SYST.CL30) { + Device(C096) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3000) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3000, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3004, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3008, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x300c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3010, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3014, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x302c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3034, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x303c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3050, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3054, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3058, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 96, 0xFD, 2} + }) // Domain 96 + } + + Device(C097) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3001) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3080, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3084, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3088, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x308c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3090, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3094, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x30ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x30b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x30bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x30d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x30d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x30d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 97, 0xFD, 2} + }) // Domain 97 + } +} + +Scope (\_SB.SYST.CL31) { + Device(C098) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3100) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3100, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3104, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3108, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x310c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3110, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3114, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x312c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3134, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x313c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3150, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3154, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3158, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 98, 0xFD, 2} + }) // Domain 98 + } + + Device(C099) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3101) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3180, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3184, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3188, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x318c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3190, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3194, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x31ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x31b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x31bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x31d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x31d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x31d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 99, 0xFD, 2} + }) // Domain 99 + } +} + +Scope (\_SB.SYST.CL32) { + Device(C100) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3200) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3200, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3204, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3208, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x320c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3210, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3214, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x322c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3234, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x323c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3250, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3254, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3258, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 100, 0xFD, 2} + }) // Domain 100 + } + + Device(C101) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3201) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3280, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3284, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3288, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x328c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3290, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3294, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x32ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x32b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x32bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x32d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x32d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x32d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 101, 0xFD, 2} + }) // Domain 101 + } +} + +Scope (\_SB.SYST.CL33) { + Device(C102) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3300) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3300, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3304, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3308, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x330c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3310, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3314, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x332c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3334, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x333c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3350, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3354, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3358, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 102, 0xFD, 2} + }) // Domain 102 + } + + Device(C103) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3301) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3380, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3384, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3388, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x338c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3390, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3394, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x33ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x33b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x33bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x33d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x33d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x33d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 103, 0xFD, 2} + }) // Domain 103 + } +} + +Scope (\_SB.SYST.CL34) { + Device(C104) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3400) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3400, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3404, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3408, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x340c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3410, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3414, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x342c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3434, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x343c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3450, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3454, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3458, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 104, 0xFD, 2} + }) // Domain 104 + } + + Device(C105) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3401) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3480, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3484, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3488, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x348c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3490, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3494, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x34ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x34b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x34bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x34d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x34d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x34d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 105, 0xFD, 2} + }) // Domain 105 + } +} + +Scope (\_SB.SYST.CL35) { + Device(C106) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3500) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3500, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3504, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3508, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x350c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3510, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3514, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x352c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3534, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x353c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3550, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3554, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3558, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 106, 0xFD, 2} + }) // Domain 106 + } + + Device(C107) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3501) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3580, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3584, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3588, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x358c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3590, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3594, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x35ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x35b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x35bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x35d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x35d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x35d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 107, 0xFD, 2} + }) // Domain 107 + } +} + +Scope (\_SB.SYST.CL36) { + Device(C108) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3600) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3600, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3604, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3608, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x360c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3610, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3614, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x362c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3634, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x363c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3650, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3654, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3658, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 108, 0xFD, 2} + }) // Domain 108 + } + + Device(C109) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3601) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3680, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3684, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3688, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x368c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3690, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3694, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x36ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x36b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x36bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x36d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x36d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x36d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 109, 0xFD, 2} + }) // Domain 109 + } +} + +Scope (\_SB.SYST.CL37) { + Device(C110) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3700) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3700, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3704, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3708, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x370c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3710, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3714, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x372c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3734, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x373c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3750, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3754, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3758, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 110, 0xFD, 2} + }) // Domain 110 + } + + Device(C111) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3701) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3780, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3784, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3788, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x378c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3790, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3794, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x37ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x37b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x37bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x37d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x37d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x37d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 111, 0xFD, 2} + }) // Domain 111 + } +} + +Scope (\_SB.SYST.CL38) { + Device(C112) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3800) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3800, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3804, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3808, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x380c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3810, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3814, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x382c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3834, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x383c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3850, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3854, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3858, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 112, 0xFD, 2} + }) // Domain 112 + } + + Device(C113) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3801) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3880, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3884, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3888, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x388c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3890, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3894, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x38ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x38b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x38bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x38d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x38d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x38d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 113, 0xFD, 2} + }) // Domain 113 + } +} + +Scope (\_SB.SYST.CL39) { + Device(C114) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3900) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3900, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3904, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3908, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x390c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3910, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3914, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x392c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3934, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x393c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3950, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3954, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3958, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 114, 0xFD, 2} + }) // Domain 114 + } + + Device(C115) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3901) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3980, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3984, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3988, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x398c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3990, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3994, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x39ac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x39b4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x39bc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x39d0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x39d4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x39d8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 115, 0xFD, 2} + }) // Domain 115 + } +} + +Scope (\_SB.SYST.CL3A) { + Device(C116) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3a00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3a00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3a14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3a2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3a34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3a3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3a50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3a54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3a58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 116, 0xFD, 2} + }) // Domain 116 + } + + Device(C117) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3a01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3a80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3a90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3a94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3aac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3ab4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3abc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3ad0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3ad4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3ad8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 117, 0xFD, 2} + }) // Domain 117 + } +} + +Scope (\_SB.SYST.CL3B) { + Device(C118) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3b00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3b00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3b14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3b2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3b34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3b3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3b50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3b54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3b58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 118, 0xFD, 2} + }) // Domain 118 + } + + Device(C119) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3b01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3b80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3b90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3b94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3bac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3bb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3bbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3bd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3bd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3bd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 119, 0xFD, 2} + }) // Domain 119 + } +} + +Scope (\_SB.SYST.CL3C) { + Device(C120) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3c00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3c00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3c14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3c2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3c34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3c3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3c50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3c54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3c58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 120, 0xFD, 2} + }) // Domain 120 + } + + Device(C121) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3c01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3c80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3c90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3c94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3cac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3cb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3cbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3cd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3cd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3cd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 121, 0xFD, 2} + }) // Domain 121 + } +} + +Scope (\_SB.SYST.CL3D) { + Device(C122) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3d00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3d00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3d2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3d34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 122, 0xFD, 2} + }) // Domain 122 + } + + Device(C123) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3d01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3d80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3d90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3d94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3dac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3db4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3dbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3dd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3dd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3dd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 123, 0xFD, 2} + }) // Domain 123 + } +} + +Scope (\_SB.SYST.CL3E) { + Device(C124) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3e00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3e00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3e14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3e2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3e34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3e3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3e50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3e54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3e58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 124, 0xFD, 2} + }) // Domain 124 + } + + Device(C125) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3e01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3e80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3e90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3e94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3eac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3eb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3ebc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3ed0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3ed4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3ed8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 125, 0xFD, 2} + }) // Domain 125 + } +} + +Scope (\_SB.SYST.CL3F) { + Device(C126) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3f00) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3f00, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f04, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f08, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f0c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f10, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3f14, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3f2c, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3f34, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3f3c, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3f50, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3f54, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3f58, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package() { + Package() {5, 0, 126, 0xFD, 2} + }) // Domain 126 + } + + Device(C127) { + Name(_HID, "ACPI0007") + Name(_UID, 0x3f01) + + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + + Name(PCPC, Package() { + 23, // NumEntries + 3, // Revision + ResourceTemplate(){Register(PCC, 32, 0, 0x3f80, 2)}, // Highest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f84, 2)}, // Nominal Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f88, 2)}, // Lowest Nonlinear Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f8c, 2)}, // Lowest Performance + ResourceTemplate(){Register(PCC, 32, 0, 0x3f90, 2)}, // Guaranteed Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3f94, 2)}, // Desired Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time + ResourceTemplate(){Register(PCC, 64, 0, 0x3fac, 2)}, // Reference Counter Register + ResourceTemplate(){Register(PCC, 64, 0, 0x3fb4, 2)}, // Delivered Counter Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3fbc, 2)}, // Performance Limited Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register + ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3fd0, 2)}, // Reference Performance Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3fd4, 2)}, // Lowest Frequency Register + ResourceTemplate(){Register(PCC, 32, 0, 0x3fd8, 2)}, // Nominal Frequency Register + }) + If (LEqual(CPCE, 0x1)) { + Method (_CPC, 0, NotSerialized) { + return(PCPC) + } + } + //Performance State dependency + Name(_PSD, Package(){ + Package() {5, 0, 127, 0xFD, 2} + }) // Domain 127 + } +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/CPU.asi b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/CPU.asi new file mode 100644 index 00000000000..be8e319f6b5 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/CPU.asi @@ -0,0 +1,151 @@ +/** @file + + Copyright (c) 2021 - 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope(\_SB) { + Name (CPCE, 1) // CPPC Enable + Name (LPIE, 0) // LPI Enable + + Method (_OSC, 4, Serialized) { // _OSC: Operating System Capabilities + CreateDWordField (Arg3, 0x00, STS0) + CreateDWordField (Arg3, 0x04, CAP0) + If (LEqual(Arg0, ToUUID ("0811b06e-4a27-44f9-8d60-3cbbc22e7b48")) /* Platform-wide Capabilities */) { + If (LNotEqual(Arg1, One)) { + And(STS0, 0xFFFFFFE0, STS0) + Or(STS0, 0x0A, STS0) // Unrecognized Revision, OSC failure + } Else { + If (LEqual(And(CAP0, 0x100), 0x100)) { + And(CAP0, 0xFFFFFEFF, CAP0) // No support for OS Initiated LPI + And(STS0, 0xFFFFFFE0, STS0) + Or(STS0, 0x12, STS0) + } + If (LEqual(LPIE, 0x1)) { + Or(CAP0, 0x80, CAP0) // Support for LPI + } Else { + And(CAP0, 0xFFFFFF7F, CAP0) // No support for LPI + } + If (LEqual(CPCE, 0x1)) { + Or(CAP0, 0x40, CAP0) // Support for CPPCv2 + } Else { + And(CAP0, 0xFFFFFFBF, CAP0) // No support for CPPCv2 + } + } + } Else { + And(STS0, 0xFFFFFFE0, STS0) + Or(STS0, 0x06, STS0) // Unrecognized Revision, Unrecognized UUID + } + Return (Arg3) + } + + Name(CLPI, Package() { + 0, // Version + 1, // Level Index + 1, // Count + Package() { + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 0, // Residency Counter Frequency + 1, // No parent state + 0x01000000, // Integer Entry method + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "Standby", + }, + }) + + Name(PLPI, Package() { + 0, // Version + 2, // Level Index + 2, // Count + // WFI for CPU (NS-WFI) + Package() { + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 0, // Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0xFFFFFFFF, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "WFI", + }, + + // WFI for CPU (S-WFI) + Package() { + 1, // Min residency (uS) + 2900, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 0, // Residency Counter Frequency + 1, // No parent state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x01, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "Standby", + }, + }) + + Device (SYST) { // System state + Name(_HID, "ACPI0010") + Name(_UID, 0) + Name (_LPI, Package() { + 0, // Version + 0, // Level Index + 1, // Count + // Retention state for Cluster + Package() { + 100, // Min residency (uS) + 99, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 100, // Residency Counter Frequency + 0, // No Parent State + 0x01000100, // Integer Entry method + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "System Standby" + }, + }) + } +} + +Include ("CPU-S0.asi") diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/CommonDevices.asi b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/CommonDevices.asi new file mode 100644 index 00000000000..97482eb7b3b --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/CommonDevices.asi @@ -0,0 +1,923 @@ +/** @file + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// Hardware Monitor +Device(HM00) { + Name(_HID, "APMC0D29") + Name(_UID, "HWM0") + Name(_DDN, "HWM0") + Name(_CCA, ONE) + Name(_STR, Unicode("Hardware Monitor Device")) + Method(_STA, 0, NotSerialized) { + return (0xF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package() {"pcc-channel", 14} + } + }) +} + +// +// Hardware Monitor +Device(HM01) { + Name(_HID, "APMC0D29") + Name(_UID, "HWM1") + Name(_DDN, "HWM1") + Name(_CCA, ONE) + Name(_STR, Unicode("Hardware Monitor Device")) + Method(_STA, 0, NotSerialized) { + return (0xF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package() {"pcc-channel", 29} + } + }) +} + +// +// Hardware Monitor +Device(HM02) { + Name(_HID, "AMPC0005") + Name(_UID, "HWM2") + Name(_DDN, "HWM2") + Name(_CCA, ONE) + Name(_STR, Unicode("Altra SoC Hardware Monitor Device")) + Method(_STA, 0, NotSerialized) { + return (0xF) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000088900000, // AddressMinimum - MIN + 0x000000008891FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000020000 // RangeLength - LEN + ) + }) +} + +// +// Hardware Monitor +Device(HM03) { + Name(_HID, "AMPC0005") + Name(_UID, "HWM3") + Name(_DDN, "HWM3") + Name(_CCA, ONE) + Name(_STR, Unicode("Altra SoC Hardware Monitor Device")) + Method(_STA, 0, NotSerialized) { + return (0xF) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00000000C0000000, // AddressMinimum - MIN + 0x00000000C001FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000020000 // RangeLength - LEN + ) + }) +} + +// +// DesignWare I2C on AHBC bus +Device(I2C2) { + Name(_HID, "APMC0D0F") + Name(_UID, 2) + Name(_STR, Unicode("Altra Max I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002690000, // AddressMinimum - MIN + 0x000010000269FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 103 } + }) + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) +} + +// +// DesignWare I2C on AHBC bus +Device(I2C3) { + Name(_HID, "APMC0D0F") + Name(_UID, 3) + Name(_STR, Unicode("Altra Max I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00001000026A0000, // AddressMinimum - MIN + 0x00001000026AFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 104 } + }) + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) +} + +// +// DesignWare I2C on AHBC bus +Device(I2C4) { + Name(_HID, "APMC0D0F") + Name(_UID, 4) + Name(_STR, Unicode("Altra Max I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00001000026B0000, // AddressMinimum - MIN + 0x00001000026BFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 105 } + }) + + Device (IPI) { + Name(_HID, "AMPC0004") + Name(_CID, "IPI0001") + Name(_STR, Unicode("IPMI_SSIF")) + Name(_UID, 0) + Name(_CCA, ONE) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Method(_IFT) { + Return(0x04) // IPMI SSIF + } + Method(_ADR) { + Return(0x10) // SSIF slave address + } + Method(_SRV) { + Return(0x0200) // IPMI Specification Revision + } + Name(_CRS, ResourceTemplate () + { + I2cSerialBusV2 (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.I2C4", + 0x00, ResourceConsumer,, Exclusive, + // Vendor specific data: + // "BMC0", + // Flags (2 bytes): SMBUS variable length (Bit 0), Read Checksum (Bit 1), Verify Checksum (Bit 2) + RawDataBuffer () { 0x42, 0x4D, 0x43, 0x30, 0x7, 0x0 } + ) + }) + } + + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) +} + +// +// DesignWare I2C on AHBC bus +Device(I2C5) { + Name(_HID, "APMC0D0F") + Name(_UID, 5) + Name(_STR, Unicode("Altra Max I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00001000026C0000, // AddressMinimum - MIN + 0x00001000026CFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 106 } + }) + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) +} + +// +// DesignWare I2C on AHBC bus +Device(I2C6) { + Name(_HID, "APMC0D0F") + Name(_UID, 6) + Name(_STR, Unicode("Altra Max I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002750000, // AddressMinimum - MIN + 0x000010000275FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 107 } + }) + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) +} + +// +// DesignWare I2C on AHBC bus +Device(I2C7) { + Name(_HID, "APMC0D0F") + Name(_UID, 7) + Name(_STR, Unicode("Altra Max I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002760000, // AddressMinimum - MIN + 0x000010000276FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 108 } + }) + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) +} + +// +// DesignWare I2C on AHBC bus +Device(I2C8) { + Name(_HID, "APMC0D0F") + Name(_UID, 8) + Name(_STR, Unicode("Altra Max I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002770000, // AddressMinimum - MIN + 0x000010000277FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 109 } + }) + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) +} + +// +// DesignWare I2C on AHBC bus +Device(I2C9) { + Name(_HID, "APMC0D0F") + Name(_UID, 9) + Name(_STR, Unicode("Altra Max I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002780000, // AddressMinimum - MIN + 0x000010000278FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 110 } + }) + + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) +} + +// +// DesignWare I2C on AHBC bus +Device(I2CA) { + Name(_HID, "APMC0D0F") + Name(_UID, 10) + Name(_STR, Unicode("Altra Max I2C Device")) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CCA, ONE) + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002790000, // AddressMinimum - MIN + 0x000010000279FFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000010000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 111 } + }) + + Name(SSCN, Package() { 0x3E2, 0x47D, 0 }) + Name(FMCN, Package() { 0xA4, 0x13F, 0 }) +} + +// +// Report APEI Errors to GHES via SCI notification. +// SCI notification requires one GED and one HED Device +// GED = Generic Event Device (ACPI0013) +// HED = Hardware Error Device (PNP0C33) +// +Device(GED0) { + Name(_HID, "ACPI0013") + Name(_UID, Zero) + Method(_STA) { + Return (0xF) + } + Name(_CRS, ResourceTemplate () { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 84 } // GHES + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 44 } // PCIe Hot Plug Doorbell Insertion & Ejection (DBNS4 -> GIC-IRQS44) + }) + + // @DBN4 agent base address for HP PCIe insertion/ejection event: 0x1000.0054.4000 + OperationRegion(DBN4, SystemMemory, 0x100000544010, 20) + Field (DBN4, DWordAcc, NoLock, Preserve) { + DOUT, 32, // event and PCIe port information at offset 0x10 + offset (0x10), + STA4, 32, // interrupt status at offset 0x20 + } +} + +// Shutdown button using GED. +Device(GED1) { + Name(_HID, "ACPI0013") + Name(_CID, "ACPI0013") + Name(_UID, One) + Method(_STA) { + Return (0xF) + } + Name(_CRS, ResourceTemplate () { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 327 } + }) + OperationRegion(PDDR, SystemMemory, 0x1000027B0004, 4) + Field(PDDR, DWordAcc, NoLock, Preserve) { + STDI, 8 + } + + OperationRegion(INTE, SystemMemory, 0x1000027B0030, 4) + Field(INTE, DWordAcc, NoLock, Preserve) { + STDE, 8 + } + + OperationRegion(INTT, SystemMemory, 0x1000027B0034, 4) + Field(INTT, DWordAcc, NoLock, Preserve) { + TYPE, 8 + } + + OperationRegion(INTP, SystemMemory, 0x1000027B0038, 4) + Field(INTP, DWordAcc, NoLock, Preserve) { + POLA, 8 + } + + OperationRegion(INTS, SystemMemory, 0x1000027B003c, 4) + Field(INTS, DWordAcc, NoLock, Preserve) { + STDS, 8 + } + + OperationRegion(INTC, SystemMemory, 0x1000027B0040, 4) + Field(INTC, DWordAcc, NoLock, Preserve) { + SINT, 8 + } + + OperationRegion(INTM, SystemMemory, 0x1000027B0044, 4) + Field(INTM, DWordAcc, NoLock, Preserve) { + MASK, 8 + } + + Method(_INI, 0, NotSerialized) { + // Set level type, low active (shutdown) + Store (0x00, TYPE) + Store (0x00, POLA) + // Set Input type (shutdown) + Store (0x00, STDI) + // Enable interrupt (shutdown) + Store (0x80, STDE) + // Unmask the interrupt. + Store (0x00, MASK) + } + Method(_EVT, 1) { + Switch (ToInteger(Arg0)) { + Case (327) { + if (And (STDS, 0x80)) { + //Clear the interrupt. + Store (0x80, SINT) + // Notify OSPM the power button is pressed + Notify (\_SB.PWRB, 0x80) + } + } + } + } +} + +// Power button device description +Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_ADR, 0) + Name(_UID, 0) + Name(_CCA, ONE) + Method(_STA, 0, Notserialized) { + Return (0x0b) + } +} + +// +// UART0 PL011 +Device(URT0) { + Name(_HID, "ARMH0011") + Name(_UID, 0) + Name(_CCA, ONE) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002600000, // AddressMinimum - MIN + 0x0000100002600FFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000001000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 98 } + }) +} // UART0 + +// +// UART2 PL011 +Device(URT2) { + Name(_HID, "ARMH0011") + Name(_UID, 1) + Name(_CCA, ONE) + Method(_STA, 0, NotSerialized) { + return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100002620000, // AddressMinimum - MIN + 0x0000100002620FFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000001000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 100 } + }) +} // UART1 + +Device(HED0) +{ + Name(_HID, EISAID("PNP0C33")) + Name(_UID, Zero) +} + +Device(NVDR) { + Name(_HID, "ACPI0012") + Method(_STA, 0, NotSerialized) { + return (0xf) + } + Method (_DSM, 0x4, Serialized) { + // Not support any functions for now + Return (Buffer() {0}) + } + Device (NVD1) { + Name(_ADR, 0x0330) //NFIT Device Handle (SK0, MCU3, Channel 3, Slot 0) + Name(SMRT, Buffer(13) {0}) + CreateDWordField(SMRT, 0, BSTA) + CreateWordField(SMRT, 4, BHTH) + CreateWordField(SMRT, 6, BTMP) + CreateByteField(SMRT, 8, BETH) + CreateByteField(SMRT, 9, BWTH) + CreateByteField(SMRT, 10, BNLF) + OperationRegion(BUF1, SystemMemory, 0x88980000, 16) + Field (BUF1, DWordAcc, NoLock, Preserve) { + STAT, 32, //Status + HLTH, 16, //Module Health + CTMP, 16, //Module Current Status + ETHS, 8, //Error Threshold Status + WTHS, 8, //Warning Threshold Status + NVLF, 8, //NVM Lifetime + , 40 //Reserve + } + Method (_DSM, 0x4, Serialized) { + //Accept only MSF Family type NVDIMM DSM functions + If(LEqual(Arg0, ToUUID ("1ee68b36-d4bd-4a1a-9a16-4f8e53d46e05"))) { + //Handle Func 0 query implemented commands + If(LEqual(Arg2, 0)) { + //Check revision and returned proper implemented commands + //Support only health check for now + Return (Buffer() {0x01, 0x08}) //Byte 0: 0x1 + } + //Handle MSF DSM Func 11 Get Smart and Health Info + If(LEqual(Arg2, 11)) { + Store(\_SB.NVDR.NVD1.STAT, BSTA) + Store(\_SB.NVDR.NVD1.HLTH, BHTH) + Store(\_SB.NVDR.NVD1.CTMP, BTMP) + Store(\_SB.NVDR.NVD1.ETHS, BETH) + Store(\_SB.NVDR.NVD1.WTHS, BWTH) + Store(\_SB.NVDR.NVD1.NVLF, BNLF) + Return (SMRT) + } + } + + Return (Buffer() {0}) + } + Method(_STA, 0, NotSerialized) { + return (0xf) + } + } + Device (NVD2) { + Name(_ADR, 0x0770) //NFIT Device Handle (SK0, MCU7, Channel 7, Slot 0) + Name(SMRT, Buffer(13) {0}) + CreateDWordField(SMRT, 0, BSTA) + CreateWordField(SMRT, 4, BHTH) + CreateWordField(SMRT, 6, BTMP) + CreateByteField(SMRT, 8, BETH) + CreateByteField(SMRT, 9, BWTH) + CreateByteField(SMRT, 10, BNLF) + OperationRegion(BUF1, SystemMemory, 0x88988000, 16) + Field (BUF1, DWordAcc, NoLock, Preserve) { + STAT, 32, //Status + HLTH, 16, //Module Health + CTMP, 16, //Module Current Status + ETHS, 8, //Error Threshold Status + WTHS, 8, //Warning Threshold Status + NVLF, 8, //NVM Lifetime + , 40 //Reserve + } + Method (_DSM, 0x4, Serialized) { + //Accept only MSF Family type NVDIMM DSM functions + If(LEqual(Arg0, ToUUID ("1ee68b36-d4bd-4a1a-9a16-4f8e53d46e05"))) { + //Handle Func 0 query implemented commands + If(LEqual(Arg2, 0)) { + //Check revision and returned proper implemented commands + //Support only health check for now + Return (Buffer() {0x01, 0x08}) //Byte 0: 0x1 + } + //Handle MSF DSM Func 11 Get Smart and Health Info + If(LEqual(Arg2, 11)) { + Store(\_SB.NVDR.NVD2.STAT, BSTA) + Store(\_SB.NVDR.NVD2.HLTH, BHTH) + Store(\_SB.NVDR.NVD2.CTMP, BTMP) + Store(\_SB.NVDR.NVD2.ETHS, BETH) + Store(\_SB.NVDR.NVD2.WTHS, BWTH) + Store(\_SB.NVDR.NVD2.NVLF, BNLF) + Return (SMRT) + } + } + + Return (Buffer() {0}) + } + Method(_STA, 0, NotSerialized) { + return (0xf) + } + } + Device (NVD3) { + Name(_ADR, 0x1330) //NFIT Device Handle (SK1, MCU3, Channel 3, Slot 0) + Name(SMRT, Buffer(13) {0}) + CreateDWordField(SMRT, 0, BSTA) + CreateWordField(SMRT, 4, BHTH) + CreateWordField(SMRT, 6, BTMP) + CreateByteField(SMRT, 8, BETH) + CreateByteField(SMRT, 9, BWTH) + CreateByteField(SMRT, 10, BNLF) + OperationRegion(BUF1, SystemMemory, 0xC0080000, 16) + Field (BUF1, DWordAcc, NoLock, Preserve) { + STAT, 32, //Status + HLTH, 16, //Module Health + CTMP, 16, //Module Current Status + ETHS, 8, //Error Threshold Status + WTHS, 8, //Warning Threshold Status + NVLF, 8, //NVM Lifetime + , 40 //Reserve + } + Method (_DSM, 0x4, Serialized) { + //Accept only MSF Family type NVDIMM DSM functions + If(LEqual(Arg0, ToUUID ("1ee68b36-d4bd-4a1a-9a16-4f8e53d46e05"))) { + //Handle Func 0 query implemented commands + If(LEqual(Arg2, 0)) { + //Check revision and returned proper implemented commands + //Support only health check for now + Return (Buffer() {0x01, 0x08}) //Byte 0: 0x1 + } + //Handle MSF DSM Func 11 Get Smart and Health Info + If(LEqual(Arg2, 11)) { + Store(\_SB.NVDR.NVD3.STAT, BSTA) + Store(\_SB.NVDR.NVD3.HLTH, BHTH) + Store(\_SB.NVDR.NVD3.CTMP, BTMP) + Store(\_SB.NVDR.NVD3.ETHS, BETH) + Store(\_SB.NVDR.NVD3.WTHS, BWTH) + Store(\_SB.NVDR.NVD3.NVLF, BNLF) + Return (SMRT) + } + } + Return (Buffer() {0}) + } + Method(_STA, 0, NotSerialized) { + return (0xf) + } + } + Device (NVD4) { + Name(_ADR, 0x1770) //NFIT Device Handle (SK1, MCU7, Channel 7, Slot 0) + Name(SMRT, Buffer(13) {0}) + CreateDWordField(SMRT, 0, BSTA) + CreateWordField(SMRT, 4, BHTH) + CreateWordField(SMRT, 6, BTMP) + CreateByteField(SMRT, 8, BETH) + CreateByteField(SMRT, 9, BWTH) + CreateByteField(SMRT, 10, BNLF) + OperationRegion(BUF1, SystemMemory, 0xC0088000, 16) + Field (BUF1, DWordAcc, NoLock, Preserve) { + STAT, 32, //Status + HLTH, 16, //Module Health + CTMP, 16, //Module Current Status + ETHS, 8, //Error Threshold Status + WTHS, 8, //Warning Threshold Status + NVLF, 8, //NVM Lifetime + , 40 //Reserve + } + Method (_DSM, 0x4, Serialized) { + //Accept only MSF Family type NVDIMM DSM functions + If(LEqual(Arg0, ToUUID ("1ee68b36-d4bd-4a1a-9a16-4f8e53d46e05"))) { + //Handle Func 0 query implemented commands + If(LEqual(Arg2, 0)) { + //Check revision and returned proper implemented commands + //Support only health check for now + Return (Buffer() {0x01, 0x08}) //Byte 0: 0x1 + } + //Handle MSF DSM Func 11 Get Smart and Health Info + If(LEqual(Arg2, 11)) { + Store(\_SB.NVDR.NVD4.STAT, BSTA) + Store(\_SB.NVDR.NVD4.HLTH, BHTH) + Store(\_SB.NVDR.NVD4.CTMP, BTMP) + Store(\_SB.NVDR.NVD4.ETHS, BETH) + Store(\_SB.NVDR.NVD4.WTHS, BWTH) + Store(\_SB.NVDR.NVD4.NVLF, BNLF) + Return (SMRT) + } + } + Return (Buffer() {0}) + } + Method(_STA, 0, NotSerialized) { + return (0xf) + } + } +} + +Device(TPM0) { + Name (_HID, "NNNN0000") + Name (_CID, "MSFT0101") + Name (_UID, 0) + Name (CRBB, 0x10000000) + Name (CRBL, 0x10000000) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x88500000, 0x1000, PCRE) + }) + + Method (_CRS, 0x0, Serialized) { + + // Declare fields in PCRE + CreateDWordField(RBUF, ^PCRE._BAS, BASE) + CreateDWordField(RBUF, ^PCRE._LEN, LENG) + + // Store Updatable values into them + Store(CRBB, BASE) + Store(CRBL, LENG) + + Return (RBUF) + } + + Method(_STR,0) + { + Return (Unicode ("TPM 2.0 Device")) + } + + Method (_STA, 0) + { + if(TPMF) + { + Return (0x0f) //Enable resources + } + Return (0x0) + } + + // + // Add opregions for doorbell and PPI CRB + // The addresses for these operation regions should be patched + // with information from HOB + // + OperationRegion (TPMD, SystemMemory, 0x100000542010, 0x04) + Field (TPMD, DWordAcc, NoLock, Preserve) { + DBB0, 32 // Doorbell out register + } + + // PPI request CRB + OperationRegion (TPMC, SystemMemory, 0x88542038, 0x0C) + Field (TPMC, DWordAcc, NoLock, Preserve) { + PPIO, 32, // current PPI request + PPIR, 32, // last PPI request + PPIS, 32, // last PPI request status + } + + // Create objects to hold return values + Name (PKG2, Package (2) { Zero, Zero }) + Name (PKG3, Package (3) { Zero, Zero, Zero }) + + Method (_DSM, 0x4, Serialized) { + // Handle Physical Presence Interface(PPI) DSM method + If (LEqual (Arg0, ToUUID ("3DDDFAA6-361B-4eb4-A424-8D10089D1653"))) { + Switch (ToInteger (Arg2)) { + // + // Standard DSM query + // + Case (0) { + Return (Buffer () { 0xFF, 0x01 }) + } + + // + // Get Physical Presence Interface Version - support 1.3 + // + Case (1) { + Return ("1.3") + } + + // + // Submit TPM operation to pre-OS (Deprecated) + // + Case (2) { + Return (One) // Not supported + } + + // + // Get pending TPM operation requested by OS + // + Case (3) { + PKG2[Zero] = Zero // Success + PKG2[One] = PPIO // current PPI request + Return (PKG2) + } + + // + // Platform-specific action to transition to Pre-OS env + // + Case (4) { + Return (0x2) // Reboot + } + + // + // TPM operation Response to OS + // + Case (5) { + PKG3[Zero] = Zero // Success + PKG3[One] = PPIR // last PPI request + PKG3[2] = PPIS // last PPI request status + Return (PKG3) + } + + // + // Preferred language code (Deprecated) + // + Case (6) { + Return (0x3) // Not implemented + } + + // + // Submit TPM operation to pre-OS env 2 + // + Case (7) { + Local0 = DerefOf (Arg3 [Zero]) + // Write current PPI request and then to the doorbell + Store (Local0, PPIO) + Store (0x6a000000, DBB0) // MsgType: 6, Handler: 0xa (TPM-PPI) + Return (Zero) + } + + // + // Get User confirmation status for op + // + Case (8) { + Return (0x4) // Allowed and physically present user not required + } + } + } + Return (Buffer () {0}) + } +} + +// +// LED Device +Device(LED) { + Name(_HID, "AMPC0008") + Name(_CCA, ONE) + Name(_STR, Unicode("Altra LED Device")) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "uuid", Package (4) { 0x5598273c, 0xa49611ea, 0xbb370242, 0xac130002 }}, + } + }) +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/Dsdt.asl b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/Dsdt.asl new file mode 100644 index 00000000000..ecc7c5840c7 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/Dsdt.asl @@ -0,0 +1,37 @@ +/** @file + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +DefinitionBlock("Dsdt.aml", "DSDT", 0x02, "ASRock", "ALTRA", 1) { + // + // Board Model + Name(\BDMD, "ALTRAD8UD2-1L2Q") + Name(TPMF, 0) // TPM presence + Name(AERF, 0) // PCIe AER Firmware-First + + Scope(\_SB) { + + Include ("CommonDevices.asi") + + Scope(\_SB.GED0) { + Method(_EVT, 1, Serialized) { + Switch (ToInteger(Arg0)) { + Case (84) { // GHES interrupt + Notify (HED0, 0x80) + } + } + } + } + + Include ("PCI-S0.asi") + Include ("PCI-PDRC.asi") + } + + Include ("CPU.asi") + Include ("PMU.asi") + +} // DSDT diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PCI-PDRC.asi b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PCI-PDRC.asi new file mode 100644 index 00000000000..a07485de3c7 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PCI-PDRC.asi @@ -0,0 +1,134 @@ +/** @file + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + // Motherboard resource consumption for PCIE resource reservation + // as upstream discussion "ACPI namespace details for ARM64" + // https://lists.linaro.org/archives/list/linaro-acpi@lists.linaro.org/thread/Q4XMW2PPCH2JH2KZHRGX27X7BSF6AY3U/ + // Also in https://docs.kernel.org/PCI/acpi-info.html + Device (PDRC) { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + Name (PDRS, ResourceTemplate() { + QWordMemory ( // PCIE0 (RcA0) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000033FFF0000000, // AddressMinimum - MIN + 0x000033FFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( // PCIE1 (RcA1) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000037FFF0000000, // AddressMinimum - MIN + 0x000037FFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( // PCIE2 (RcA2) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00003BFFF0000000, // AddressMinimum - MIN + 0x00003BFFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( // PCIE3 (RcA3) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00003FFFF0000000, // AddressMinimum - MIN + 0x00003FFFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( // PCIE4 (RcA4) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000023FFF0000000, // AddressMinimum - MIN + 0x000023FFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( // PCIE5 (RcA5) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x000027FFF0000000, // AddressMinimum - MIN + 0x000027FFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( // PCIE6 (RcA6) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00002BFFF0000000, // AddressMinimum - MIN + 0x00002BFFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( // PCIE7 (RcA7) 256M CFG region for ECAM + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00002FFFF0000000, // AddressMinimum - MIN + 0x00002FFFFFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) { + Return (PDRS) + } + } diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PCI-S0.asi b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PCI-S0.asi new file mode 100644 index 00000000000..c73d8b44205 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PCI-S0.asi @@ -0,0 +1,2890 @@ +/** @file + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + // @DoorBellNS1 0x1000.0054.1000. Out-Offset: 0x10 + OperationRegion(DNS1, SystemMemory, 0x100000541010 , 8) + Field (DNS1, DWordAcc, NoLock, Preserve) { + OUTV, 32, + DIN0, 32, + } + + // PCI0 RCA0 + Device (PCI0) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID, "PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) // The default value is 0x0. Unfortunately, it breaks + // run-time patching as the representation of 0 is special + // encoding and cannot be patched to expand with extra bytes + // easily. As such, we default to 0xF and patch this based + // on whether the port was enabled or not by the BIOS. + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID, "PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 12) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI0") + Name (_STR, Unicode("PCIe 0 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 128/129/130/131 respectively. PCI0 RCA0 + // + Package() {0x0001FFFF, 0, 0, 128}, + Package() {0x0001FFFF, 1, 0, 129}, + Package() {0x0001FFFF, 2, 0, 130}, + Package() {0x0001FFFF, 3, 0, 131}, + Package() {0x0002FFFF, 0, 0, 128}, + Package() {0x0002FFFF, 1, 0, 129}, + Package() {0x0002FFFF, 2, 0, 130}, + Package() {0x0002FFFF, 3, 0, 131}, + Package() {0x0003FFFF, 0, 0, 128}, + Package() {0x0003FFFF, 1, 0, 129}, + Package() {0x0003FFFF, 2, 0, 130}, + Package() {0x0003FFFF, 3, 0, 131}, + Package() {0x0004FFFF, 0, 0, 128}, + Package() {0x0004FFFF, 1, 0, 129}, + Package() {0x0004FFFF, 2, 0, 130}, + Package() {0x0004FFFF, 3, 0, 131}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x33FFF0000000) + } + + // + // Declare a ResourceTemplate buffer to return the resource + // requirements from _CRS. + // Section 19.5.109 + // + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FE40000, 0x10000, ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000040000000, // AddressMinimum - MIN + 0x000000004FFFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000300000000000, // AddressMinimum - MIN + 0x000033FFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP,0) // PCI _OSC Support Field value + Name (CTRL,0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3, 0, CDW1) + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL, 0x1E, CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1, One)) { + Or (CDW1, 0x08, CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3, CTRL)) { + Or (CDW1, 0x10, CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL, CDW3) + Return (Arg3) + + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI0 RCA0 + + // PCI1 RCA1 + Device (PCI1) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID, "PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) // The default value is 0x0. Unfortunately, it breaks + // run-time patching as the representation of 0 is special + // encoding and cannot be patched to expand with extra bytes + // easily. As such, we default to 0xF and patch this based + // on whether the port was enabled or not by the BIOS. + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID, "PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 13) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI1") + Name (_STR, Unicode("PCIe 1 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 132/133/134/135 respectively. PCI1 RCA1 + // + Package() {0x0001FFFF, 0, 0, 132}, + Package() {0x0001FFFF, 1, 0, 133}, + Package() {0x0001FFFF, 2, 0, 134}, + Package() {0x0001FFFF, 3, 0, 135}, + Package() {0x0002FFFF, 0, 0, 132}, + Package() {0x0002FFFF, 1, 0, 133}, + Package() {0x0002FFFF, 2, 0, 134}, + Package() {0x0002FFFF, 3, 0, 135}, + Package() {0x0003FFFF, 0, 0, 132}, + Package() {0x0003FFFF, 1, 0, 133}, + Package() {0x0003FFFF, 2, 0, 134}, + Package() {0x0003FFFF, 3, 0, 135}, + Package() {0x0004FFFF, 0, 0, 132}, + Package() {0x0004FFFF, 1, 0, 133}, + Package() {0x0004FFFF, 2, 0, 134}, + Package() {0x0004FFFF, 3, 0, 135}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x37FFF0000000) + } + + // + // Declare a ResourceTemplate buffer to return the resource + // requirements from _CRS. + // Section 19.5.109 + // + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FE40000, 0x10000, ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000050000000, // AddressMinimum - MIN + 0x000000005FFFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000010000000 // RangeLength - LEN + ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + Cacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000340000000000, // AddressMinimum - MIN + 0x000037FFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP,0) // PCI _OSC Support Field value + Name (CTRL,0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3, 0, CDW1) + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL, 0x1E, CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1, One)) { + Or (CDW1, 0x08, CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3, CTRL)) { + Or (CDW1, 0x10, CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL, CDW3) + Return (Arg3) + + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI1 RCA1 + + // PCI2 RCA2 + Device (PCI2) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID, "PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID, "PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 1) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI2") + Name (_STR, Unicode("PCIe 2 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 136/137/138/139 respectively. PCI2 RCA2 + // + Package() {0x0001FFFF, 0, 0, 136}, + Package() {0x0001FFFF, 1, 0, 137}, + Package() {0x0001FFFF, 2, 0, 138}, + Package() {0x0001FFFF, 3, 0, 139}, + Package() {0x0002FFFF, 0, 0, 136}, + Package() {0x0002FFFF, 1, 0, 137}, + Package() {0x0002FFFF, 2, 0, 138}, + Package() {0x0002FFFF, 3, 0, 139}, + Package() {0x0003FFFF, 0, 0, 136}, + Package() {0x0003FFFF, 1, 0, 137}, + Package() {0x0003FFFF, 2, 0, 138}, + Package() {0x0003FFFF, 3, 0, 139}, + Package() {0x0004FFFF, 0, 0, 136}, + Package() {0x0004FFFF, 1, 0, 137}, + Package() {0x0004FFFF, 2, 0, 138}, + Package() {0x0004FFFF, 3, 0, 139}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x3BFFF0000000) + } + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FE80000, 0x10000, ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000030000000, // AddressMinimum - MIN + 0x0000000037FFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000008000000 // RangeLength - LEN + ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000380000000000, // AddressMinimum - MIN + 0x00003BFFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP, 0) // PCI _OSC Support Field value + Name (CTRL, 0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3,0,CDW1) + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL, 0x1E, CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1, One)) { + Or (CDW1, 0x08, CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3, CTRL)) { + Or (CDW1, 0x10, CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL, CDW3) + Return (Arg3) + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI2 RCA2 + + // PCI3 RCA3 + Device (PCI3) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID, "PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID, "PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 0) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI3") + Name (_STR, Unicode("PCIe 3 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 140/141/142/143 respectively. PCI3 RCA3 + // + Package() {0x0001FFFF, 0, 0, 140}, + Package() {0x0001FFFF, 1, 0, 141}, + Package() {0x0001FFFF, 2, 0, 142}, + Package() {0x0001FFFF, 3, 0, 143}, + Package() {0x0002FFFF, 0, 0, 140}, + Package() {0x0002FFFF, 1, 0, 141}, + Package() {0x0002FFFF, 2, 0, 142}, + Package() {0x0002FFFF, 3, 0, 143}, + Package() {0x0003FFFF, 0, 0, 140}, + Package() {0x0003FFFF, 1, 0, 141}, + Package() {0x0003FFFF, 2, 0, 142}, + Package() {0x0003FFFF, 3, 0, 143}, + Package() {0x0004FFFF, 0, 0, 140}, + Package() {0x0004FFFF, 1, 0, 141}, + Package() {0x0004FFFF, 2, 0, 142}, + Package() {0x0004FFFF, 3, 0, 143}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x3FFFF0000000) + } + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FE00000, 0x10000, ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000038000000, // AddressMinimum - MIN + 0x000000003FFFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000008000000 // RangeLength - LEN + ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00003C0000000000, // AddressMinimum - MIN + 0x00003FFFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP, 0) // PCI _OSC Support Field value + Name (CTRL, 0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3, 0, CDW1) + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL, 0x1E, CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1, One)) { + Or (CDW1, 0x08, CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3, CTRL)) { + Or (CDW1, 0x10, CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL, CDW3) + Return (Arg3) + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI3 RCA3 + + // PCI4 RCA4 + Device (PCI4) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID, "PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) // The default value is 0x0. Unfortunately, it breaks + // run-time patching as the representation of 0 is special + // encoding and cannot be patched to expand with extra bytes + // easily. As such, we default to 0xF and patch this based + // on whether the port was enabled or not by the BIOS. + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID, "PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 2) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI4") + Name (_STR, Unicode("PCIe 4 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 144/145/146/147 respectively. PCI4 RCA4 + // + Package() {0x0001FFFF, 0, 0, 144}, + Package() {0x0001FFFF, 1, 0, 145}, + Package() {0x0001FFFF, 2, 0, 146}, + Package() {0x0001FFFF, 3, 0, 147}, + Package() {0x0002FFFF, 0, 0, 144}, + Package() {0x0002FFFF, 1, 0, 145}, + Package() {0x0002FFFF, 2, 0, 146}, + Package() {0x0002FFFF, 3, 0, 147}, + Package() {0x0003FFFF, 0, 0, 144}, + Package() {0x0003FFFF, 1, 0, 145}, + Package() {0x0003FFFF, 2, 0, 146}, + Package() {0x0003FFFF, 3, 0, 147}, + Package() {0x0004FFFF, 0, 0, 144}, + Package() {0x0004FFFF, 1, 0, 145}, + Package() {0x0004FFFF, 2, 0, 146}, + Package() {0x0004FFFF, 3, 0, 147}, + Package() {0x0005FFFF, 0, 0, 144}, + Package() {0x0005FFFF, 1, 0, 145}, + Package() {0x0005FFFF, 2, 0, 146}, + Package() {0x0005FFFF, 3, 0, 147}, + Package() {0x0006FFFF, 0, 0, 144}, + Package() {0x0006FFFF, 1, 0, 145}, + Package() {0x0006FFFF, 2, 0, 146}, + Package() {0x0006FFFF, 3, 0, 147}, + Package() {0x0007FFFF, 0, 0, 144}, + Package() {0x0007FFFF, 1, 0, 145}, + Package() {0x0007FFFF, 2, 0, 146}, + Package() {0x0007FFFF, 3, 0, 147}, + Package() {0x0008FFFF, 0, 0, 144}, + Package() {0x0008FFFF, 1, 0, 145}, + Package() {0x0008FFFF, 2, 0, 146}, + Package() {0x0008FFFF, 3, 0, 147}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x23FFF0000000) + } + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FEC0000, 0x10000, ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000004000000, // AddressMinimum - MIN + 0x0000000007FFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000004000000 // RangeLength - LEN + ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000200000000000, // AddressMinimum - MIN + 0x000023FFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP,0) // PCI _OSC Support Field value + Name (CTRL,0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3, 0, CDW1) + If (LEqual (Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL, 0x1E, CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1, One)) { + Or (CDW1, 0x08, CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3, CTRL)) { + Or (CDW1, 0x10, CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL, CDW3) + Return (Arg3) + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) + { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + // + // Root Port 1 + // + Device (P2P1) { + // + // Device 1, Function 0 (Bus 0). + // + + Name (_ADR, 0x00010000) + + Device (S0F0) { + // + // On Bus 1 [01]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000001) + } + } + + // + // Root Port 2 + // + Device (P2P2) { + // + // Device 2, Function 0 (Bus 0). + // + + Name (_ADR, 0x00020000) + + Device (S0F0) { + // + // On Bus 2 [02]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000002) + } + } + + // + // Root Port 3 + // + Device (P2P3) { + // + // Device 3, Function 0 (Bus 0). + // + + Name (_ADR, 0x00030000) + + Device (S0F0) { + // + // On Bus 3 [03]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000003) + } + } + + // + // Root Port 4 + // + Device (P2P4) { + // + // Device 4, Function 0 (Bus 0). + // + + Name (_ADR, 0x00040000) + + Device (S0F0) { + // + // On Bus 4 ([04]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000004) + } + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI4 RCA4 + + // PCI5 RCA5 + Device (PCI5) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID, "PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID,"PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 3) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI5") + Name (_STR, Unicode("PCIe 5 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 148/149/150/151 respectively. PCI5 RCA5 + // + Package() {0x0001FFFF, 0, 0, 148}, + Package() {0x0001FFFF, 1, 0, 149}, + Package() {0x0001FFFF, 2, 0, 150}, + Package() {0x0001FFFF, 3, 0, 151}, + Package() {0x0002FFFF, 0, 0, 148}, + Package() {0x0002FFFF, 1, 0, 149}, + Package() {0x0002FFFF, 2, 0, 150}, + Package() {0x0002FFFF, 3, 0, 151}, + Package() {0x0003FFFF, 0, 0, 148}, + Package() {0x0003FFFF, 1, 0, 149}, + Package() {0x0003FFFF, 2, 0, 150}, + Package() {0x0003FFFF, 3, 0, 151}, + Package() {0x0004FFFF, 0, 0, 148}, + Package() {0x0004FFFF, 1, 0, 149}, + Package() {0x0004FFFF, 2, 0, 150}, + Package() {0x0004FFFF, 3, 0, 151}, + Package() {0x0005FFFF, 0, 0, 148}, + Package() {0x0005FFFF, 1, 0, 149}, + Package() {0x0005FFFF, 2, 0, 150}, + Package() {0x0005FFFF, 3, 0, 151}, + Package() {0x0006FFFF, 0, 0, 148}, + Package() {0x0006FFFF, 1, 0, 149}, + Package() {0x0006FFFF, 2, 0, 150}, + Package() {0x0006FFFF, 3, 0, 151}, + Package() {0x0007FFFF, 0, 0, 148}, + Package() {0x0007FFFF, 1, 0, 149}, + Package() {0x0007FFFF, 2, 0, 150}, + Package() {0x0007FFFF, 3, 0, 151}, + Package() {0x0008FFFF, 0, 0, 148}, + Package() {0x0008FFFF, 1, 0, 149}, + Package() {0x0008FFFF, 2, 0, 150}, + Package() {0x0008FFFF, 3, 0, 151}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x27FFF0000000) + } + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FF00000, 0x10000, ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000008000000, // AddressMinimum - MIN + 0x000000000FFFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000008000000 // RangeLength - LEN + ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000240000000000, // AddressMinimum - MIN + 0x000027FFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP, 0) // PCI _OSC Support Field value + Name (CTRL, 0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3, 0, CDW1) + If (LEqual (Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL, 0x1E, CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1, One)) { + Or (CDW1, 0x08, CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3, CTRL)) { + Or (CDW1, 0x10, CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL, CDW3) + Return (Arg3) + + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) + { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + // + // Root Port 1 + // + Device (P2P1) { + // + // Device 1, Function 0 (Bus 0). + // + + Name (_ADR, 0x00010000) + + Device (S0F0) { + // + // On Bus 1 [01]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000001) + } + } + + // + // Root Port 2 + // + Device (P2P2) { + // + // Device 2, Function 0 (Bus 0). + // + + Name (_ADR, 0x00020000) + + Device (S0F0) { + // + // On Bus 2 [02]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000002) + } + } + + // + // Root Port 3 + // + Device (P2P3) { + // + // Device 3, Function 0 (Bus 0). + // + + Name (_ADR, 0x00030000) + + Device (S0F0) { + // + // On Bus 3 [03]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000003) + } + } + + // + // Root Port 4 + // + Device (P2P4) { + // + // Device 4, Function 0 (Bus 0). + // + + Name (_ADR, 0x00040000) + + Device (S0F0) { + // + // On Bus 4 ([04]) + // Slot 0 (Device 0), Function 0 + // + + Name (_ADR, 0x00000000) + Name(_SUN, 0x00000004) + } + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI5 RCA5 + + + // PCI6 RCA6 + Device (PCI6) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID,"PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) // The default value is 0x0. Unfortunately, it breaks + // run-time patching as the representation of 0 is special + // encoding and cannot be patched to expand with extra bytes + // easily. As such, we default to 0xF and patch this based + // on whether the port was enabled or not by the BIOS. + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID,"PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 4) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI6") + Name (_STR, Unicode("PCIe 6 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 152/153/154/155 respectively. PCI6 RCA6 + // + Package() {0x0001FFFF, 0, 0, 152}, + Package() {0x0001FFFF, 1, 0, 153}, + Package() {0x0001FFFF, 2, 0, 154}, + Package() {0x0001FFFF, 3, 0, 155}, + Package() {0x0002FFFF, 0, 0, 152}, + Package() {0x0002FFFF, 1, 0, 153}, + Package() {0x0002FFFF, 2, 0, 154}, + Package() {0x0002FFFF, 3, 0, 155}, + Package() {0x0003FFFF, 0, 0, 152}, + Package() {0x0003FFFF, 1, 0, 153}, + Package() {0x0003FFFF, 2, 0, 154}, + Package() {0x0003FFFF, 3, 0, 155}, + Package() {0x0004FFFF, 0, 0, 152}, + Package() {0x0004FFFF, 1, 0, 153}, + Package() {0x0004FFFF, 2, 0, 154}, + Package() {0x0004FFFF, 3, 0, 155}, + Package() {0x0005FFFF, 0, 0, 152}, + Package() {0x0005FFFF, 1, 0, 153}, + Package() {0x0005FFFF, 2, 0, 154}, + Package() {0x0005FFFF, 3, 0, 155}, + Package() {0x0006FFFF, 0, 0, 152}, + Package() {0x0006FFFF, 1, 0, 153}, + Package() {0x0006FFFF, 2, 0, 154}, + Package() {0x0006FFFF, 3, 0, 155}, + Package() {0x0007FFFF, 0, 0, 152}, + Package() {0x0007FFFF, 1, 0, 153}, + Package() {0x0007FFFF, 2, 0, 154}, + Package() {0x0007FFFF, 3, 0, 155}, + Package() {0x0008FFFF, 0, 0, 152}, + Package() {0x0008FFFF, 1, 0, 153}, + Package() {0x0008FFFF, 2, 0, 154}, + Package() {0x0008FFFF, 3, 0, 155}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x2BFFF0000000) + } + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FF40000, 0x10000, ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000010000000, // AddressMinimum - MIN + 0x0000000017FFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000008000000 // RangeLength - LEN + ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000280000000000, // AddressMinimum - MIN + 0x00002BFFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP,0) // PCI _OSC Support Field value + Name (CTRL,0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3,0,CDW1) + If (LEqual (Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3,4,CDW2) + CreateDWordField (Arg3,8,CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2,SUPP) + Store (CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL,0x1E,CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1,One)) { + Or (CDW1,0x08,CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3,CTRL)) { + Or (CDW1,0x10,CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL,CDW3) + Return (Arg3) + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1,4,CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI6 RCA6 + + // PCI7 RCA7 + Device (PCI7) { + // + // Hardware ID must be PNP0A08, which maps to a PCIe root complex. + // Section 6.1.5 + // + + Name (_HID,"PNP0A08") + Name (_CCA, ONE) + + Method (_STA, 0, NotSerialized) { + Return (0xF) // The default value is 0x0. Unfortunately, it breaks + // run-time patching as the representation of 0 is special + // encoding and cannot be patched to expand with extra bytes + // easily. As such, we default to 0xF and patch this based + // on whether the port was enabled or not by the BIOS. + } + + // + // Optionally, include a compatible ID of PNP0A03, which maps to a PCI + // root complex for use with pre-PCIe operating systems. + // Section 6.1.2 + // + + Name (_CID,"PNP0A03") + + // + // Declare the segment number of this root complex. Most systems only + // have one segment, which is numbered 0. + // Section 6.5.6 + // + + Name (_SEG, 5) + + // + // Declare the base bus number, which is the bus number of the root + // bus in this root complex. This is usually 0, but need not be. + // For root complexes supporting multiple root busses, this should + // be the lowest numbered root bus. + // Section 6.5.5 + // + + Name (_BBN, 0) + + // + // The _UID value provides a way of uniquely identifying a device + // in the case where more than one instance of a specific device + // is implemented with the same _HID/_CID. For systems with a + // single root complex, this is usually just 0. For systems with + // multiple root complexes, this should be different for each + // root complex. + // Section 6.1.12 + // + + Name (_UID, "PCI7") + Name (_STR, Unicode("PCIe 7 Device")) + + // + // Declare the PCI Routing Table. + // This defines SPI mappings of the four line-based interrupts + // associated with the root complex and hierarchy below it. + // Section 6.2.12 + // + + Name (_PRT, Package() { + + // + // Routing for device 0, all functions. + // Note: ARM doesn't support LNK nodes, so the third param + // is 0 and the fourth param is the SPI number of the interrupt + // line. In this example, the A/B/C/D interrupts are wired to + // SPI lines 156/157/158/159 respectively. PCI7 RCA7 + // + Package() {0x0001FFFF, 0, 0, 156}, + Package() {0x0001FFFF, 1, 0, 157}, + Package() {0x0001FFFF, 2, 0, 158}, + Package() {0x0001FFFF, 3, 0, 159}, + Package() {0x0002FFFF, 0, 0, 156}, + Package() {0x0002FFFF, 1, 0, 157}, + Package() {0x0002FFFF, 2, 0, 158}, + Package() {0x0002FFFF, 3, 0, 159}, + Package() {0x0003FFFF, 0, 0, 156}, + Package() {0x0003FFFF, 1, 0, 157}, + Package() {0x0003FFFF, 2, 0, 158}, + Package() {0x0003FFFF, 3, 0, 159}, + Package() {0x0004FFFF, 0, 0, 156}, + Package() {0x0004FFFF, 1, 0, 157}, + Package() {0x0004FFFF, 2, 0, 158}, + Package() {0x0004FFFF, 3, 0, 159}, + Package() {0x0005FFFF, 0, 0, 156}, + Package() {0x0005FFFF, 1, 0, 157}, + Package() {0x0005FFFF, 2, 0, 158}, + Package() {0x0005FFFF, 3, 0, 159}, + Package() {0x0006FFFF, 0, 0, 156}, + Package() {0x0006FFFF, 1, 0, 157}, + Package() {0x0006FFFF, 2, 0, 158}, + Package() {0x0006FFFF, 3, 0, 159}, + Package() {0x0007FFFF, 0, 0, 156}, + Package() {0x0007FFFF, 1, 0, 157}, + Package() {0x0007FFFF, 2, 0, 158}, + Package() {0x0007FFFF, 3, 0, 159}, + Package() {0x0008FFFF, 0, 0, 156}, + Package() {0x0008FFFF, 1, 0, 157}, + Package() {0x0008FFFF, 2, 0, 158}, + Package() {0x0008FFFF, 3, 0, 159}, + }) + + // + // Declare the resources assigned to this root complex. + // Section 6.2.2 + // + Method (_CBA, 0, Serialized) { + Return (0x2FFFF0000000) + } + + Name (RBUF, ResourceTemplate () { + + // + // Declare the range of bus numbers assigned to this root + // complex. In this example, the minimum bus number will be + // 0, the maximum bus number will be 0xFF, supporting + // 256 busses total. + // Section 19.5.141 + // + + WordBusNumber ( + ResourceProducer, + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256) // RangeLength - Number of Busses + + // + // Declare the memory range to be used for BAR memory + // windows. This declares a 4GB region starting at + // 0x4000000000. + // Section 19.5.80 + // + // Memory32Fixed (ReadWrite, 0x1FF40000, 0x10000, ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000000018000000, // AddressMinimum - MIN + 0x000000001FFFFFFF, // AddressMinimum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000008000000 // RangeLength - LEN + ) + + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // NonCacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x00002C0000000000, // AddressMinimum - MIN + 0x00002FFFDFFFFFFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x000003FFE0000000 // RangeLength - LEN + ) + }) + + Method (_CRS, 0, Serialized) { + Return (RBUF) + } + + // + // Declare an _OSC (OS Control Handoff) method which takes 4 arguments. + // + // Argments: + // Arg0 A Buffer containing a UUID + // Arg1 An Integer containing a Revision ID of the buffer format + // Arg2 An Integer containing a count of entries in Arg3 + // Arg3 A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // See the APCI spec, Section 6.2.10, + // and the PCI FW spec, Section 4.5. + // + // The following is an example, and may need modification for + // specific implementations. + // + + Name (SUPP,0) // PCI _OSC Support Field value + Name (CTRL,0) // PCI _OSC Control Field value + + Method (_OSC, 4) { + + // + // Look for the PCI Host Bridge Interface UUID. + // Section 6.2.10.3 + // + + // + // Create DWord-adressable fields from the Capabilities Buffer + // Create CDW1 outside the test as it's used in the else clause. + // + + CreateDWordField (Arg3,0,CDW1) + If (LEqual (Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + CreateDWordField (Arg3,4,CDW2) + CreateDWordField (Arg3,8,CDW3) + + // + // Save Capabilities DWord 2 & 3 + // + + Store (CDW2,SUPP) + Store (CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports: + // ASPM + // Clock PM + // MSI/MSI-X + // + + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + + // + // Mask bit 0 (and undefined bits) + // + + And (CTRL,0x1E,CTRL) + } + + // + // Never allow native Hot plug, PME. + // Never allow SHPC (no SHPC controller in this system). + // Only allow PCIe AER control if PCIe AER Firmware-First is disabled + // Allows PCI Express Capability Structure control + // + + If (AERF) { + And (CTRL, 0x10, CTRL) + } Else { + And (CTRL, 0x18, CTRL) + } + + // + // Check for unknown revision. + // + + If (LNotEqual (Arg1,One)) { + Or (CDW1,0x08,CDW1) + } + + // + // Check if capabilities bits were masked. + // + + If (LNotEqual (CDW3,CTRL)) { + Or (CDW1,0x10,CDW1) + } + + // + // Update DWORD3 in the buffer. + // + + Store (CTRL,CDW3) + Return (Arg3) + } Else { + + // + // Unrecognized UUID + // + + Or (CDW1,4,CDW1) + Return (Arg3) + } + } // End _OSC + + // + // Declare a _DSM method for various functions called by the OS. + // See the APCI spec, Section 9.14.1, + // and the PCI FW spec, Section 4.6. + // See also: + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc + // + + Method (_DSM, 0x4, Serialized) { + + // + // Match against the _DSM PCI GUID. + // + + If (LEqual (Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + + Switch (ToInteger(Arg2)) { + // + // Function 0: Return supported functions as a bitfield + // with one bit for each supported function. + // Bit 0 must always be set, as that represents + // function 0 (which is what is being called here). + // Support for different functions may depend on + // the revision ID of the interface, passed as Arg1. + // + + Case (0) { + + // + // Functions 0-7 are supported. + // + + Return (Buffer() {0x01}) + } + } + } + + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + // + + Return (Buffer() {0}) + } + + // + // Root Port 0 Device within the Root Complex. + // + Device (RP0) { + // + // Device 0, Function 0. + // + + Name (_ADR, 0x00000000) + } + + Method (_PXM, 0, NotSerialized) { + // Patch by code + Return(0xFF) + } + } // PCI7 RCA7 diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PMU-S0.asi b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PMU-S0.asi new file mode 100644 index 00000000000..50e6c8948ba --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PMU-S0.asi @@ -0,0 +1,1292 @@ +/** @file + + Copyright (c) 2021 - 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope(\_SB) { + Device(CMN0) { + Name(_HID, "ARMHC600") // Device Identification Objects + Name(_CID, "ARMHC600") + Name(_UID, 0) + Name(_CCA, ONE) + Name(_STR, Unicode("CMN0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceConsumer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100010000000, // AddressMinimum - MIN + 0x0000100013ffffff, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000004000000 // RangeLength - LEN + ) + QWordMemory ( + ResourceConsumer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100012f00000, // AddressMinimum - MIN + 0x0000100013ffffff, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000001100000 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 314 } + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 314 } + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 314 } + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 314 } + }) + } + + Device(MC00) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 0) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100090000A00, // AddressMinimum - MIN + 0x0000100090000BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 248 } + }) + } + + Device(MC01) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 1) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU1")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100090400A00, // AddressMinimum - MIN + 0x0000100090400BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 249 } + }) + } + + Device(MC02) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 2) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU2")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100090800A00, // AddressMinimum - MIN + 0x0000100090800BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 250 } + }) + } + + Device(MC03) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 3) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU3")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100090C00A00, // AddressMinimum - MIN + 0x0000100090C00BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 251 } + }) + } + + Device(MC04) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 4) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU4")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100091000A00, // AddressMinimum - MIN + 0x0000100091000BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 252 } + }) + } + + Device(MC05) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 5) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU5")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100091400A00, // AddressMinimum - MIN + 0x0000100091400BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 253 } + }) + } + + Device(MC06) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 6) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU6")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100091800A00, // AddressMinimum - MIN + 0x0000100091800BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 254 } + }) + } + + Device(MC07) { + Name(_HID, "ARMHD620") + Name(_CID, "ARMHD620") + Name(_UID, 7) + Name(_CCA, ONE) + Name(_STR, Unicode("Socket 0: MCU7")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + QWordMemory ( + ResourceProducer, // ResourceUsage + PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + NonCacheable, // Cacheable + ReadWrite, // ReadAndWrite + 0x0000000000000000, // AddressGranularity - GRA + 0x0000100091C00A00, // AddressMinimum - MIN + 0x0000100091C00BFF, // AddressMaximum - MAX + 0x0000000000000000, // AddressTranslation - TRA + 0x0000000000000200 // RangeLength - LEN + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 255 } + }) + } +} + +Scope (\_SB.SYST.CL00) { + Device(DU00) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 64 } + }) + } +} + +Scope (\_SB.SYST.CL01) { + Device(DU01) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x1) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x1 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 65 } + }) + } +} + +Scope (\_SB.SYST.CL02) { + Device(DU02) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x2) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x2 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 66 } + }) + } +} + +Scope (\_SB.SYST.CL03) { + Device(DU03) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x3) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x3 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 67 } + }) + } +} + +Scope (\_SB.SYST.CL04) { + Device(DU04) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x4) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x4 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 68 } + }) + } +} + +Scope (\_SB.SYST.CL05) { + Device(DU05) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x5) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x5 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 69 } + }) + } +} + +Scope (\_SB.SYST.CL06) { + Device(DU06) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x6) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x6 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 71 } + }) + } +} + +Scope (\_SB.SYST.CL07) { + Device(DU07) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x7) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x7 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 80 } + }) + } +} + +Scope (\_SB.SYST.CL08) { + Device(DU08) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x8) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x8 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 81 } + }) + } +} + +Scope (\_SB.SYST.CL09) { + Device(DU09) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x9) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x9 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 82 } + }) + } +} + +Scope (\_SB.SYST.CL0A) { + Device(DU0A) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0xA) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0xA Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 83 } + }) + } +} + +Scope (\_SB.SYST.CL0B) { + Device(DU0B) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0xB) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0xB Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 115 } + }) + } +} + +Scope (\_SB.SYST.CL0C) { + Device(DU0C) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0xC) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0xC Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 116 } + }) + } +} + +Scope (\_SB.SYST.CL0D) { + Device(DU0D) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0xD) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0xD Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 120 } + }) + } +} + +Scope (\_SB.SYST.CL0E) { + Device(DU0E) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0xE) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0xE Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 121 } + }) + } +} + +Scope (\_SB.SYST.CL0F) { + Device(DU0F) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0xF) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0xF Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 122 } + }) + } +} + +Scope (\_SB.SYST.CL10) { + Device(DU10) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x10) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x10 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 123 } + }) + } +} + +Scope (\_SB.SYST.CL11) { + Device(DU11) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x11) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x11 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 124 } + }) + } +} + +Scope (\_SB.SYST.CL12) { + Device(DU12) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x12) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x12 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 125 } + }) + } +} + +Scope (\_SB.SYST.CL13) { + Device(DU13) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x13) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x13 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 126 } + }) + } +} + +Scope (\_SB.SYST.CL14) { + Device(DU14) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x14) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x14 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 127 } + }) + } +} + +Scope (\_SB.SYST.CL15) { + Device(DU15) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x15) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x15 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 166 } + }) + } +} + +Scope (\_SB.SYST.CL16) { + Device(DU16) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x16) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x16 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 167 } + }) + } +} + +Scope (\_SB.SYST.CL17) { + Device(DU17) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x17) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x17 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 168 } + }) + } +} + +Scope (\_SB.SYST.CL18) { + Device(DU18) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x18) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x18 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 169 } + }) + } +} + +Scope (\_SB.SYST.CL19) { + Device(DU19) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x19) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x19 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 176 } + }) + } +} + +Scope (\_SB.SYST.CL1A) { + Device(DU1A) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x1A) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x1A Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 177 } + }) + } +} + +Scope (\_SB.SYST.CL1B) { + Device(DU1B) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x1B) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x1B Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 178 } + }) + } +} + +Scope (\_SB.SYST.CL1C) { + Device(DU1C) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x1C) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x1C Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 179 } + }) + } +} + +Scope (\_SB.SYST.CL1D) { + Device(DU1D) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x1D) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x1D Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 186 } + }) + } +} + +Scope (\_SB.SYST.CL1E) { + Device(DU1E) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x1E) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x1E Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 187 } + }) + } +} + +Scope (\_SB.SYST.CL1F) { + Device(DU1F) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x1F) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x1F Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 188 } + }) + } +} + +Scope (\_SB.SYST.CL20) { + Device(DU20) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x20) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x20 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 189 } + }) + } +} + +Scope (\_SB.SYST.CL21) { + Device(DU21) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x21) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x21 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 196 } + }) + } +} + +Scope (\_SB.SYST.CL22) { + Device(DU22) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x22) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x22 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 197 } + }) + } +} + +Scope (\_SB.SYST.CL23) { + Device(DU23) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x23) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x23 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 198 } + }) + } +} + +Scope (\_SB.SYST.CL24) { + Device(DU24) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x24) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x24 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 199 } + }) + } +} + +Scope (\_SB.SYST.CL25) { + Device(DU25) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x25) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x25 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 200 } + }) + } +} + +Scope (\_SB.SYST.CL26) { + Device(DU26) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x26) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x26 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 201 } + }) + } +} + +Scope (\_SB.SYST.CL27) { + Device(DU27) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x27) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x27 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 202 } + }) + } +} + +Scope (\_SB.SYST.CL28) { + Device(DU28) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x28) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x28 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 203 } + }) + } +} + +Scope (\_SB.SYST.CL29) { + Device(DU29) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x29) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x29 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 204 } + }) + } +} + +Scope (\_SB.SYST.CL2A) { + Device(DU2A) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x2A) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x2A Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 205 } + }) + } +} + +Scope (\_SB.SYST.CL2B) { + Device(DU2B) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x2B) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x2B Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 206 } + }) + } +} + +Scope (\_SB.SYST.CL2C) { + Device(DU2C) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x2C) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x2C Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 207 } + }) + } +} + +Scope (\_SB.SYST.CL2D) { + Device(DU2D) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x2D) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x2D Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 221 } + }) + } +} + +Scope (\_SB.SYST.CL2E) { + Device(DU2E) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x2E) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x2E Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 222 } + }) + } +} + +Scope (\_SB.SYST.CL2F) { + Device(DU2F) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x2F) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x2F Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 223 } + }) + } +} + +Scope (\_SB.SYST.CL30) { + Device(DU30) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x30) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x30 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 264 } + }) + } +} + +Scope (\_SB.SYST.CL31) { + Device(DU31) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x31) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x31 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 265 } + }) + } +} + +Scope (\_SB.SYST.CL32) { + Device(DU32) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x32) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x32 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 266 } + }) + } +} + +Scope (\_SB.SYST.CL33) { + Device(DU33) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x33) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x33 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 267 } + }) + } +} + +Scope (\_SB.SYST.CL34) { + Device(DU34) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x34) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x34 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 268 } + }) + } +} + +Scope (\_SB.SYST.CL35) { + Device(DU35) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x35) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x35 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 269 } + }) + } +} + +Scope (\_SB.SYST.CL36) { + Device(DU36) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x36) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x36 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 270 } + }) + } +} + +Scope (\_SB.SYST.CL37) { + Device(DU37) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x37) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x37 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 271 } + }) + } +} + +Scope (\_SB.SYST.CL38) { + Device(DU38) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x38) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x38 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 297 } + }) + } +} + +Scope (\_SB.SYST.CL39) { + Device(DU39) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x39) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x39 Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 298 } + }) + } +} + +Scope (\_SB.SYST.CL3A) { + Device(DU3A) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x3A) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x3A Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 299 } + }) + } +} + +Scope (\_SB.SYST.CL3B) { + Device(DU3B) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x3B) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x3B Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 300 } + }) + } +} + +Scope (\_SB.SYST.CL3C) { + Device(DU3C) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x3C) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x3C Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 301 } + }) + } +} + +Scope (\_SB.SYST.CL3D) { + Device(DU3D) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x3D) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x3D Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 312 } + }) + } +} + +Scope (\_SB.SYST.CL3E) { + Device(DU3E) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x3E) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x3E Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 313 } + }) + } +} + +Scope (\_SB.SYST.CL3F) { + Device(DU3F) { + Name(_HID, "ARMHD500") + Name(_CID, "ARMHD500") + Name(_UID, 0x3F) + Name(_CCA, ONE) + Name(_STR, Unicode("DSU CPM 0x3F Socket 0")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 316 } + }) + } +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PMU.asi b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PMU.asi new file mode 100644 index 00000000000..f9dc7cec8e5 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Ac02AcpiTables/PMU.asi @@ -0,0 +1,9 @@ +/** @file + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Include ("PMU-S0.asi") diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/PciPlatformDxe/PciPlatformDxe.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/PciPlatformDxe/PciPlatformDxe.c new file mode 100644 index 00000000000..fc977475c22 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/PciPlatformDxe/PciPlatformDxe.c @@ -0,0 +1,258 @@ +/** @file + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +/** + Callback funciton for EndEnumeration notification from PCI stack. + + @param[in] RootBridgeIndex Index to identify of PCIE Root bridge. + @param[in] Phase The phase of enumeration as informed from PCI stack. +**/ +VOID +NotifyPhaseCallBack ( + IN UINTN RootBridgeIndex, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase + ) +{ + AC01_ROOT_COMPLEX *RootComplexList; + VOID *Hob; + + Hob = GetFirstGuidHob (&gRootComplexInfoHobGuid); + if (Hob == NULL) { + return; + } + + RootComplexList = (AC01_ROOT_COMPLEX *)GET_GUID_HOB_DATA (Hob); + + switch (Phase) { + case EfiPciHostBridgeEndEnumeration: + Ac01PcieCoreEndEnumeration (&RootComplexList[RootBridgeIndex]); + break; + + case EfiPciHostBridgeBeginEnumeration: + // 100ms that help fixing completion timeout issue + MicroSecondDelay (100000); + break; + + case EfiPciHostBridgeBeginBusAllocation: + case EfiPciHostBridgeEndBusAllocation: + case EfiPciHostBridgeBeginResourceAllocation: + case EfiPciHostBridgeAllocateResources: + case EfiPciHostBridgeSetResources: + case EfiPciHostBridgeFreeResources: + case EfiPciHostBridgeEndResourceAllocation: + case EfiMaxPciHostBridgeEnumerationPhase: + break; + } +} + +/** + + Perform initialization by the phase indicated. + + @param This Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. + @param HostBridge The associated PCI host bridge handle. + @param Phase The phase of the PCI controller enumeration. + @param ChipsetPhase Defines the execution phase of the PCI chipset driver. + + @retval EFI_SUCCESS Must return with success. + +**/ +EFI_STATUS +EFIAPI +PhaseNotify ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *RootBridgeDevPath; + EFI_HANDLE RootBridgeHandle = NULL; + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAlloc = NULL; + EFI_STATUS Status; + + if (ChipsetPhase != ChipsetExit) { + return EFI_SUCCESS; + } + + // + // Get HostBridgeInstance from HostBridge handle. + // + Status = gBS->HandleProtocol ( + HostBridge, + &gEfiPciHostBridgeResourceAllocationProtocolGuid, + (VOID **)&ResAlloc + ); + + while (TRUE) { + Status = ResAlloc->GetNextRootBridge (ResAlloc, &RootBridgeHandle); + if (EFI_ERROR (Status)) { + break; + } + + Status = gBS->HandleProtocol ( + RootBridgeHandle, + &gEfiDevicePathProtocolGuid, + (VOID **)&RootBridgeDevPath + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a %d: Failed to locate RootBridge DevicePath\n", __func__, __LINE__)); + break; + } + + NotifyPhaseCallBack (RootBridgeDevPath->AcpiDevicePath.UID, Phase); + } + + return EFI_SUCCESS; +} + +/** + + The PlatformPrepController() function can be used to notify the platform driver so that + it can perform platform-specific actions. No specific actions are required. + Several notification points are defined at this time. More synchronization points may be + added as required in the future. The PCI bus driver calls the platform driver twice for + every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver + is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has + been notified. + This member function may not perform any error checking on the input parameters. It also + does not return any error codes. If this member function detects any error condition, it + needs to handle those errors on its own because there is no way to surface any errors to + the caller. + + @param This Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. + @param HostBridge The associated PCI host bridge handle. + @param RootBridge The associated PCI root bridge handle. + @param PciAddress The address of the PCI device on the PCI bus. + @param Phase The phase of the PCI controller enumeration. + @param ChipsetPhase Defines the execution phase of the PCI chipset driver. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_UNSUPPORTED Not supported. + +**/ +EFI_STATUS +EFIAPI +PlatformPrepController ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS. + + @param This The pointer to the Protocol itself. + @param PciPolicy The returned Policy. + + @retval EFI_UNSUPPORTED Function not supported. + @retval EFI_INVALID_PARAMETER Invalid PciPolicy value. + +**/ +EFI_STATUS +EFIAPI +GetPlatformPolicy ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ) +{ + return EFI_UNSUPPORTED; +} + +/** + + Return a PCI ROM image for the onboard device represented by PciHandle. + + @param This Protocol instance pointer. + @param PciHandle PCI device to return the ROM image for. + @param RomImage PCI Rom Image for onboard device. + @param RomSize Size of RomImage in bytes. + + @retval EFI_SUCCESS RomImage is valid. + @retval EFI_NOT_FOUND No RomImage. + +**/ +EFI_STATUS +EFIAPI +GetPciRom ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ) +{ + return EFI_NOT_FOUND; +} + +// +// Interface defintion of PCI Platform protocol. +// +EFI_PCI_PLATFORM_PROTOCOL mPciPlatformProtocol = { + .PlatformNotify = PhaseNotify, + .PlatformPrepController = PlatformPrepController, + .GetPlatformPolicy = GetPlatformPolicy, + .GetPciRom = GetPciRom +}; + +/** + + The Entry point of the Pci Platform Driver. + + @param ImageHandle Handle to the image. + @param SystemTable Handle to System Table. + + @retval EFI_STATUS Status of the function calling. + +**/ +EFI_STATUS +PciPlatformDriverEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE PciPlatformHandle; + + // + // Install on a new handle + // + PciPlatformHandle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces ( + &PciPlatformHandle, + &gEfiPciPlatformProtocolGuid, + &mPciPlatformProtocol, + NULL + ); + + return Status; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf b/Platform/ASRockRack/AltraBoardPkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf new file mode 100644 index 00000000000..ddf6eeb759e --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf @@ -0,0 +1,41 @@ +## @file +# +# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[defines] + INF_VERSION = 0x0001001B + BASE_NAME = PciPlatformDxe + FILE_GUID = 73276F3D-DCBC-49B2-9890-7564F917501D + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PciPlatformDriverEntry + +[Sources] + PciPlatformDxe.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + +[LibraryClasses] + Ac01PcieLib + DebugLib + HobLib + TimerLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Protocols] + gEfiDevicePathProtocolGuid + gEfiPciHostBridgeResourceAllocationProtocolGuid + gEfiPciPlatformProtocolGuid + +[Guids] + gRootComplexInfoHobGuid + +[Depex] + TRUE diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c new file mode 100644 index 00000000000..a42a426ccfc --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c @@ -0,0 +1,486 @@ +/** @file + This driver parses the mSmbiosPlatformDxeDataTable structure + and reports any generated data using SMBIOS protocol. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include "SmbiosPlatformDxe.h" + +#define SIZE_OF_HII_DATABASE_DEFAULT_STRINGS \ +ADDITIONAL_STR_INDEX_MAX * SMBIOS_UNICODE_STRING_MAX_LENGTH + +STATIC EFI_HANDLE mSmbiosPlatformDxeImageHandle; +STATIC EFI_STRING mDefaultHiiDatabaseStr; +STATIC EFI_SMBIOS_PROTOCOL *mPlatformDxeSmbios = NULL; + +EFI_HII_HANDLE mSmbiosPlatformDxeHiiHandle; + +/** + Standard EFI driver point. This driver parses the mSmbiosPlatformDataTable + structure and reports any generated data using SMBIOS protocol. + + @param ImageHandle Handle for the image of this driver. + @param SystemTable Pointer to the EFI System Table. + + @retval EFI_SUCCESS The data was successfully stored. + EFI_OUT_OF_RESOURCES There is no remaining memory to satisfy the request. +**/ +EFI_STATUS +EFIAPI +SmbiosPlatformDxeEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINTN Index; + EFI_STATUS Status; + + mSmbiosPlatformDxeImageHandle = ImageHandle; + + // + // Allocate buffer to save default strings of HII Database + // + mDefaultHiiDatabaseStr = AllocateZeroPool (SIZE_OF_HII_DATABASE_DEFAULT_STRINGS); + if (mDefaultHiiDatabaseStr == NULL) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] HII Database String allocates memory resource failed.\n", + __FUNCTION__, + __LINE__ + )); + return EFI_OUT_OF_RESOURCES; + } + + // + // Locate SMBIOS protocol and get HII Database Handle + // + Status = gBS->LocateProtocol ( + &gEfiSmbiosProtocolGuid, + NULL, + (VOID **)&mPlatformDxeSmbios + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] Could not locate SMBIOS protocol. %r\n", + __FUNCTION__, + __LINE__, + Status + )); + return Status; + } + + mSmbiosPlatformDxeHiiHandle = HiiAddPackages ( + &gEfiCallerIdGuid, + mSmbiosPlatformDxeImageHandle, + SmbiosPlatformDxeStrings, + NULL + ); + if (mSmbiosPlatformDxeHiiHandle == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Iterate through all Data Tables of each Type and call + // function pointer to create and add Table accordingly + // + for (Index = 0; Index < mSmbiosPlatformDxeDataTableEntries; Index++) { + Status = (*mSmbiosPlatformDxeDataTable[Index].Function)( + mSmbiosPlatformDxeDataTable[Index].RecordData, + mSmbiosPlatformDxeDataTable[Index].StrToken + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] Could not install SMBIOS Table Type%d. %r\n", + __FUNCTION__, + __LINE__, + ((EFI_SMBIOS_TABLE_HEADER *)(mSmbiosPlatformDxeDataTable[Index].RecordData))->Type, + Status + )); + } + } + + // + // Free buffer after all Tables were installed + // + FreePool (mDefaultHiiDatabaseStr); + + return Status; +} + +/** + Adds an SMBIOS record. + + @param Buffer The data for the SMBIOS record. + The format of the record is determined by + EFI_SMBIOS_TABLE_HEADER.Type. The size of the + formatted area is defined by EFI_SMBIOS_TABLE_HEADER.Length + and either followed by a double-null (0x0000) or a set + of null terminated strings and a null. + @param SmbiosHandle A unique handle will be assigned to the SMBIOS record + if not NULL. + + @retval EFI_SUCCESS Record was added. + @retval EFI_OUT_OF_RESOURCES Record was not added due to lack of system resources. + @retval EFI_ALREADY_STARTED The SmbiosHandle passed in was already in use. + @retval EFI_INVALID_PARAMETER Buffer is NULL. +**/ +EFI_STATUS +SmbiosPlatformDxeAddRecord ( + IN UINT8 *Buffer, + IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle OPTIONAL + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_HANDLE Handle; + + if (Buffer == NULL) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] Buffer is NULL - Invalid parameter. %r\n", + __FUNCTION__, + __LINE__ + )); + return EFI_INVALID_PARAMETER; + } + + Handle = SMBIOS_HANDLE_PI_RESERVED; + if (SmbiosHandle != NULL) { + Handle = *SmbiosHandle; + } + + Status = mPlatformDxeSmbios->Add ( + mPlatformDxeSmbios, + NULL, + &Handle, + (EFI_SMBIOS_TABLE_HEADER *)Buffer + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] SMBIOS Type%d Table Log Failed! %r\n", + __FUNCTION__, + __LINE__, + ((EFI_SMBIOS_TABLE_HEADER *)Buffer)->Type, + Status + )); + } + if (SmbiosHandle != NULL) { + *SmbiosHandle = Handle; + } + + return Status; +} + +/** + Fetches the number of handles of the specified SMBIOS type. + + @param SmbiosType The type of SMBIOS record to look for. + + @retval UINTN The number of handles. +**/ +STATIC +UINTN +GetHandleCount ( + IN UINT8 SmbiosType + ) +{ + UINTN HandleCount; + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + EFI_SMBIOS_TABLE_HEADER *Record; + + HandleCount = 0; + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + // Iterate through entries to get the number + do { + Status = mPlatformDxeSmbios->GetNext ( + mPlatformDxeSmbios, + &SmbiosHandle, + &SmbiosType, + &Record, + NULL + ); + + if (Status == EFI_SUCCESS) { + HandleCount++; + } + } while (Status != EFI_NOT_FOUND); + + return HandleCount; +} + +/** + Fetches a list of the specified SMBIOS Table types. + + @param[in] SmbiosType The type of table to fetch. + @param[out] HandleArray The array of handles. + @param[out] HandleCount Number of handles in the array. +**/ +VOID +SmbiosPlatformDxeGetLinkTypeHandle ( + IN UINT8 SmbiosType, + OUT SMBIOS_HANDLE **HandleArray, + OUT UINTN *HandleCount + ) +{ + UINTN Index; + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + EFI_SMBIOS_TABLE_HEADER *Record; + + if (SmbiosType > END_OF_SMBIOS_TABLE_TYPE) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] Invalid SMBIOS Type.\n", + __FUNCTION__, + __LINE__ + )); + } + + *HandleCount = GetHandleCount (SmbiosType); + *HandleArray = AllocateZeroPool (sizeof (SMBIOS_HANDLE) * (*HandleCount)); + if (*HandleArray == NULL) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] HandleArray allocates memory resource failed.\n", + __FUNCTION__, + __LINE__ + )); + *HandleCount = 0; + return; + } + + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + + for (Index = 0; Index < (*HandleCount); Index++) { + Status = mPlatformDxeSmbios->GetNext ( + mPlatformDxeSmbios, + &SmbiosHandle, + &SmbiosType, + &Record, + NULL + ); + + if (Status == EFI_SUCCESS) { + (*HandleArray)[Index] = Record->Handle; + } else { + // It should never reach here + ASSERT (FALSE); + break; + } + } +} + +/** + Create SMBIOS Table Record with additional strings. + + @param[out] TableRecord Table Record is created. + @param[in] InputData Input Table from Data Table. + @param[in] TableTypeSize Size of Table with specified type. + @param[in] StrToken Pointer to Token of additional strings in HII Database. +**/ +VOID +SmbiosPlatformDxeCreateTable ( + OUT VOID **TableRecord, + IN VOID **InputData, + IN UINT8 TableTypeSize, + IN STR_TOKEN_INFO *StrToken + ) +{ + CHAR8 *StrStart; + UINT8 TableSize; + UINT8 SmbiosAdditionalStrLen; + UINT8 Index; + EFI_STRING SmbiosAdditionalStr; + + if (*InputData == NULL || + StrToken == NULL || + TableTypeSize < sizeof (EFI_SMBIOS_TABLE_HEADER) + ) + { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] Invalid parameter to create SMBIOS Table\n", + __FUNCTION__, + __LINE__ + )); + return; + } + + // + // Calculate size of Table. + // + if (StrToken->TokenLen != 0) { + TableSize = TableTypeSize + 1; // Last byte is Null-terminated for Table with Null-terminated additional strings + for (Index = 0; Index < StrToken->TokenLen; Index++) { + SmbiosAdditionalStr = HiiGetPackageString ( + &gEfiCallerIdGuid, + StrToken->TokenArray[Index], + NULL + ); + TableSize += StrLen (SmbiosAdditionalStr) + 1; + FreePool (SmbiosAdditionalStr); + } + } else { + TableSize = TableTypeSize + 1 + 1; // Double-null for Table with no additional strings + } + + // + // Allocate Table and copy strings from + // HII Database for additional strings. + // + *TableRecord = AllocateZeroPool (TableSize); + if (*TableRecord == NULL) { + return; + } + CopyMem (*TableRecord, *InputData, TableTypeSize); + StrStart = (CHAR8 *)(*TableRecord + TableTypeSize); + for (Index = 0; Index < StrToken->TokenLen; Index++) { + SmbiosAdditionalStr = HiiGetPackageString ( + &gEfiCallerIdGuid, + StrToken->TokenArray[Index], + NULL + ); + SmbiosAdditionalStrLen = StrLen (SmbiosAdditionalStr) + 1; + UnicodeStrToAsciiStrS ( + SmbiosAdditionalStr, + StrStart, + SmbiosAdditionalStrLen + ); + FreePool (SmbiosAdditionalStr); + StrStart += SmbiosAdditionalStrLen; + } +} + +/** + Save default strings of HII Database in case multiple tables with the same type using + these data for setting additional strings. After using, default strings will be set + back again in HII Database by using SmbiosPlatformDxeRestoreHiiDefaultString function + for other tables with the same type to use. Before saving HII Database default strings, + buffer for saving need to be available. Otherwise, that means a certain SMBIOS Table used + this function but forget using SmbiosPlatformDxeRestoreHiiDefaultString function to free + buffer for other Tables to use so this check is for that purpose. + + @param[in] StrToken Pointer to Token of additional strings in HII Database. + + @retval EFI_SUCCESS Saved default strings of HII Database successfully. + Other Failed to save default strings of HII Database. +**/ +EFI_STATUS +SmbiosPlatformDxeSaveHiiDefaultString ( + IN STR_TOKEN_INFO *StrToken + ) +{ + UINT8 Index; + UINT8 HiiDatabaseStrLen; + EFI_STRING HiiDatabaseStr; + + if (StrToken == NULL) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] Invalid String Tokens\n", + __FUNCTION__, + __LINE__ + )); + return EFI_INVALID_PARAMETER; + } + + // + // Start saving HII Default Strings + // + for (Index = 0; Index < StrToken->TokenLen; Index++) { + ASSERT (IsZeroBuffer ((VOID *)&mDefaultHiiDatabaseStr[Index * SMBIOS_STRING_MAX_LENGTH], SMBIOS_UNICODE_STRING_MAX_LENGTH - 1)); + HiiDatabaseStr = HiiGetPackageString ( + &gEfiCallerIdGuid, + StrToken->TokenArray[Index], + NULL + ); + HiiDatabaseStrLen = (StrLen (HiiDatabaseStr) + 1) * sizeof (CHAR16); + ASSERT (HiiDatabaseStrLen <= SMBIOS_UNICODE_STRING_MAX_LENGTH); + UnicodeSPrint ( + (CHAR16 *)&mDefaultHiiDatabaseStr[Index * SMBIOS_STRING_MAX_LENGTH], + HiiDatabaseStrLen, + HiiDatabaseStr + ); + FreePool (HiiDatabaseStr); + } + + return EFI_SUCCESS; +} + +/** + Restore default strings of HII Database after using for setting additional strings. + + @param[in] StrToken Pointer to Token of additional strings in HII Database. + + @retval EFI_SUCCESS Restore default strings off HII Database successfully. + Other Failed to restore default strings of HII Database. +**/ +EFI_STATUS +SmbiosPlatformDxeRestoreHiiDefaultString ( + IN STR_TOKEN_INFO *StrToken + ) +{ + UINT8 Index; + EFI_STATUS Status; + + if (StrToken == NULL) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] Invalid String Tokens\n", + __FUNCTION__, + __LINE__ + )); + return EFI_INVALID_PARAMETER; + } + + for (Index = 0; Index < StrToken->TokenLen; Index++) { + if (IsZeroBuffer ((VOID *)&mDefaultHiiDatabaseStr[Index * SMBIOS_STRING_MAX_LENGTH], SMBIOS_UNICODE_STRING_MAX_LENGTH - 1)) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] Default strings were not saved previously so failed to restore default strings.\n", + __FUNCTION__, + __LINE__ + )); + return EFI_INVALID_PARAMETER; + } + + Status = HiiSetString ( + mSmbiosPlatformDxeHiiHandle, + StrToken->TokenArray[Index], + (EFI_STRING)&mDefaultHiiDatabaseStr[Index * SMBIOS_STRING_MAX_LENGTH], + NULL + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] Failed to restore default strings\n", + __FUNCTION__, + __LINE__ + )); + return Status; + } + ZeroMem ((VOID *)&mDefaultHiiDatabaseStr[Index * SMBIOS_STRING_MAX_LENGTH], SMBIOS_UNICODE_STRING_MAX_LENGTH - 1); + } + + return Status; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.h b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.h new file mode 100644 index 00000000000..dbd67304ca8 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.h @@ -0,0 +1,201 @@ +/** @file + Header file for the SmbiosPlatformDxe Driver. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMBIOS_PLATFORM_DXE_H_ +#define SMBIOS_PLATFORM_DXE_H_ + +#include +#include + +#define NULL_TERMINATED_TYPE 0xFF +#define NULL_TERMINATED_TOKEN 0xFFFF + +#define END_OF_SMBIOS_TABLE_TYPE 127 +#define SMBIOS_UNICODE_STRING_MAX_LENGTH (SMBIOS_STRING_MAX_LENGTH * sizeof (CHAR16)) + +typedef enum { + ADDITIONAL_STR_INDEX_1 = 1, + ADDITIONAL_STR_INDEX_2, + ADDITIONAL_STR_INDEX_3, + ADDITIONAL_STR_INDEX_4, + ADDITIONAL_STR_INDEX_5, + ADDITIONAL_STR_INDEX_6, + ADDITIONAL_STR_INDEX_7, + ADDITIONAL_STR_INDEX_8, + ADDITIONAL_STR_INDEX_9, + ADDITIONAL_STR_INDEX_MAX +} ADDITIONAl_STR_INDEX; + +// +// Data table entry update function. +// +typedef EFI_STATUS (EFIAPI SMBIOS_PLATFORM_DXE_DATA_FUNCTION)( + IN VOID *RecordData, + IN VOID *StrToken +); + +#pragma pack(1) +// +// Data table entry definition. +// +typedef struct { + // + // Intermediate input data for SMBIOS record + // + VOID *RecordData; + VOID *StrToken; + SMBIOS_PLATFORM_DXE_DATA_FUNCTION *Function; +} SMBIOS_PLATFORM_DXE_DATA_TABLE; + +typedef struct { + UINT16 TokenArray[ADDITIONAL_STR_INDEX_MAX]; + UINT8 TokenLen; +} STR_TOKEN_INFO; +#pragma pack() + +// +// SMBIOS table extern definitions. +// +#define SMBIOS_PLATFORM_DXE_TABLE_EXTERNS(SMBIOS_TYPE, BASE_NAME) \ +extern SMBIOS_TYPE BASE_NAME ## Data[]; \ +extern STR_TOKEN_INFO BASE_NAME ## StrToken[]; \ +extern SMBIOS_PLATFORM_DXE_DATA_FUNCTION BASE_NAME ## Function; + +// +// SMBIOS data table entries. +// +// This is used to define tables for structure pointer, functions and +// string Tokens in order to iterate through the list of tables, populate +// them and add them into the system. +#define SMBIOS_PLATFORM_DXE_TABLE_ENTRY_DATA_AND_FUNCTION(BASE_NAME) \ +{ \ + BASE_NAME ## Data, \ + BASE_NAME ## StrToken, \ + BASE_NAME ## Function \ +} + +// +// Global definition macros. +// +#define SMBIOS_PLATFORM_DXE_TABLE_DATA(SMBIOS_TYPE, BASE_NAME) \ + SMBIOS_TYPE BASE_NAME ## Data[] + +#define SMBIOS_PLATFORM_DXE_STRING_TOKEN_DATA(BASE_NAME) \ + STR_TOKEN_INFO BASE_NAME ## StrToken[] + +#define SMBIOS_PLATFORM_DXE_TABLE_FUNCTION(BASE_NAME) \ + EFI_STATUS EFIAPI BASE_NAME ## Function( \ + IN VOID *RecordData, \ + IN VOID *StrToken \ + ) + +/** + Adds an SMBIOS record. + + @param Buffer The data for the SMBIOS record. + The format of the record is determined by + EFI_SMBIOS_TABLE_HEADER.Type. The size of the + formatted area is defined by EFI_SMBIOS_TABLE_HEADER.Length + and either followed by a double-null (0x0000) or a set + of null terminated strings and a null. + @param SmbiosHandle A unique handle will be assigned to the SMBIOS record + if not NULL. + + @retval EFI_SUCCESS Record was added. + @retval EFI_OUT_OF_RESOURCES Record was not added due to lack of system resources. + @retval EFI_ALREADY_STARTED The SmbiosHandle passed in was already in use. + @retval EFI_INVALID_PARAMETER Buffer is NULL. +**/ +EFI_STATUS +SmbiosPlatformDxeAddRecord ( + IN UINT8 *Buffer, + IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle OPTIONAL + ); + +/** + Fetches a list of the specified SMBIOS Table types. + + @param[in] SmbiosType The type of table to fetch. + @param[out] HandleArray The array of handles. + @param[out] HandleCount Number of handles in the array. +**/ +VOID +SmbiosPlatformDxeGetLinkTypeHandle ( + IN UINT8 SmbiosType, + OUT SMBIOS_HANDLE **HandleArray, + OUT UINTN *HandleCount + ); + +/** + Create SMBIOS Table Record with additional strings. + + @param[out] TableRecord Table Record is created. + @param[in] InputData Input Table from Data Table. + @param[in] TableTypeSize Size of Table with specified type. + @param[in] StrToken Pointer to Token of additional strings in HII Database. +**/ +VOID +SmbiosPlatformDxeCreateTable ( + OUT VOID **TableRecord, + IN VOID **InputData, + IN UINT8 TableTypeSize, + IN STR_TOKEN_INFO *StrToken + ); + +/** + Save default strings of HII Database in case multiple tables with the same type using + these data for setting additional strings. After using, default strings will be set + back again in HII Database for other tables with the same type to use. + + @param[in] StrToken Pointer to Token of additional strings in HII Database. + + @retval EFI_SUCCESS Saved default strings of HII Database successfully. + Other Failed to save default strings of HII Database. +**/ +EFI_STATUS +SmbiosPlatformDxeSaveHiiDefaultString ( + IN STR_TOKEN_INFO *StrToken + ); + +/** + Restore default strings of HII Database after using for setting additional strings. + + @param[in] StrToken Pointer to Token of additional strings in HII Database. + + @retval EFI_SUCCESS Restore default strings off HII Database successfully. + Other Failed to restore default strings of HII Database. +**/ +EFI_STATUS +SmbiosPlatformDxeRestoreHiiDefaultString ( + IN STR_TOKEN_INFO *StrToken + ); + +// +// Data Table Array +// +extern SMBIOS_PLATFORM_DXE_DATA_TABLE mSmbiosPlatformDxeDataTable[]; + +// +// Data Table Array Entries +// +extern UINTN mSmbiosPlatformDxeDataTableEntries; + +// +// HII Database Handle +// +extern EFI_HII_HANDLE mSmbiosPlatformDxeHiiHandle; + +extern UINT8 SmbiosPlatformDxeStrings[]; + +#endif // SMBIOS_PLATFORM_DXE_H_ diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf new file mode 100755 index 00000000000..debf16ec37b --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf @@ -0,0 +1,70 @@ +## @file +# +# Copyright (c) 2020 - 2022, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = SmbiosPlatformDxe + FILE_GUID = F0CC7D0B-CD83-4DDA-A5D4-613AB02D4E52 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = SmbiosPlatformDxeEntry + +[Sources] + SmbiosPlatformDxe.h + SmbiosPlatformDxe.c + SmbiosPlatformDxeDataTable.c + SmbiosPlatformDxeStrings.uni + Type07/PlatformCacheData.c + Type07/PlatformCacheFunction.c + Type08/PlatformPortConnectorData.c + Type08/PlatformPortConnectorFunction.c + Type09/PlatformSystemSlotData.c + Type09/PlatformSystemSlotFunction.c + Type11/PlatformOemStringData.c + Type11/PlatformOemStringFunction.c + Type12/PlatformJumperStringData.c + Type12/PlatformJumperStringFunction.c + Type16/PlatformPhysicalMemoryArrayData.c + Type16/PlatformPhysicalMemoryArrayFunction.c + Type17/PlatformMemoryDeviceData.c + Type17/PlatformMemoryDeviceFunction.c + Type19/PlatformMemoryArrayMappedAddressData.c + Type19/PlatformMemoryArrayMappedAddressFunction.c + Type38/PlatformIpmiDeviceData.c + Type38/PlatformIpmiDeviceFunction.c + Type41/PlatformOnboardDevicesExtendedData.c + Type41/PlatformOnboardDevicesExtendedFunction.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec + +[LibraryClasses] + AmpereCpuLib + BaseLib + BaseMemoryLib + DebugLib + HiiLib + JedecJep106Lib + MemoryAllocationLib + NVParamLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gEfiSmbiosProtocolGuid ## CONSUMED + +[Guids] + gCpuConfigFormSetGuid + +[Depex] + TRUE diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxeDataTable.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxeDataTable.c new file mode 100644 index 00000000000..9de7575d01e --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxeDataTable.c @@ -0,0 +1,96 @@ +/** @file + This file provides SMBIOS Type. + + Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosPlatformDxe.h" + +SMBIOS_PLATFORM_DXE_TABLE_EXTERNS ( + SMBIOS_TABLE_TYPE7, + PlatformCache + ) +SMBIOS_PLATFORM_DXE_TABLE_EXTERNS ( + SMBIOS_TABLE_TYPE8, + PlatformPortConnector + ) +SMBIOS_PLATFORM_DXE_TABLE_EXTERNS ( + SMBIOS_TABLE_TYPE9, + PlatformSystemSlot + ) +SMBIOS_PLATFORM_DXE_TABLE_EXTERNS ( + SMBIOS_TABLE_TYPE9, + PlatformOemString + ) +SMBIOS_PLATFORM_DXE_TABLE_EXTERNS ( + SMBIOS_TABLE_TYPE16, + PlatformPhysicalMemoryArray + ) +SMBIOS_PLATFORM_DXE_TABLE_EXTERNS ( + SMBIOS_TABLE_TYPE17, + PlatformMemoryDevice + ) +SMBIOS_PLATFORM_DXE_TABLE_EXTERNS ( + SMBIOS_TABLE_TYPE19, + PlatformMemoryArrayMappedAddress + ) +SMBIOS_PLATFORM_DXE_TABLE_EXTERNS ( + SMBIOS_TABLE_TYPE38, + PlatformIpmiDevice + ) +SMBIOS_PLATFORM_DXE_TABLE_EXTERNS ( + SMBIOS_TABLE_TYPE41, + PlatformOnboardDevicesExtended + ) + +SMBIOS_PLATFORM_DXE_DATA_TABLE mSmbiosPlatformDxeDataTable[] = { + //Type7 + SMBIOS_PLATFORM_DXE_TABLE_ENTRY_DATA_AND_FUNCTION ( + PlatformCache + ), + //Type8 + SMBIOS_PLATFORM_DXE_TABLE_ENTRY_DATA_AND_FUNCTION ( + PlatformPortConnector + ), + //Type9 + SMBIOS_PLATFORM_DXE_TABLE_ENTRY_DATA_AND_FUNCTION ( + PlatformSystemSlot + ), + //Type11 + SMBIOS_PLATFORM_DXE_TABLE_ENTRY_DATA_AND_FUNCTION ( + PlatformOemString + ), + //Type16 + SMBIOS_PLATFORM_DXE_TABLE_ENTRY_DATA_AND_FUNCTION ( + PlatformPhysicalMemoryArray + ), + //Type17 + SMBIOS_PLATFORM_DXE_TABLE_ENTRY_DATA_AND_FUNCTION ( + PlatformMemoryDevice + ), + //Type19 + SMBIOS_PLATFORM_DXE_TABLE_ENTRY_DATA_AND_FUNCTION ( + PlatformMemoryArrayMappedAddress + ), + //Type38 + SMBIOS_PLATFORM_DXE_TABLE_ENTRY_DATA_AND_FUNCTION ( + PlatformIpmiDevice + ), + //Type41 + SMBIOS_PLATFORM_DXE_TABLE_ENTRY_DATA_AND_FUNCTION ( + PlatformOnboardDevicesExtended + ) +}; + +// +// Number of Data Table entries. +// +UINTN mSmbiosPlatformDxeDataTableEntries = ARRAY_SIZE (mSmbiosPlatformDxeDataTable); diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxeStrings.uni b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxeStrings.uni new file mode 100644 index 00000000000..37d750362d1 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxeStrings.uni @@ -0,0 +1,23 @@ +/** @file + * Based on files under Nt32Pkg/MiscSubClassPlatformDxe/ + * + * Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ * Copyright (c) 2021, NUVIA Inc. All rights reserved.
+ * Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ * Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ * Copyright (c) 2015, Linaro Limited. All rights reserved.
+ * SPDX-License-Identifier: BSD-2-Clause-Patent + * +**/ + + +/=# + +#langdef en-US "English" + +#include "Type07/PlatformCache.uni" +#include "Type08/PlatformPortConnector.uni" +#include "Type09/PlatformSystemSlot.uni" +#include "Type11/PlatformOemString.uni" +#include "Type17/PlatformMemoryDevice.uni" +#include "Type41/PlatformOnboardDevicesExtended.uni" diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type07/PlatformCache.uni b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type07/PlatformCache.uni new file mode 100644 index 00000000000..429cb9c524c --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type07/PlatformCache.uni @@ -0,0 +1,11 @@ +/** @file + + Copyright (c) 2024, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=# + +#string STR_PLATFORM_DXE_CACHE #language en-US "L3 Cache (SLC)" diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type07/PlatformCacheData.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type07/PlatformCacheData.c new file mode 100644 index 00000000000..58bea0b0cbe --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type07/PlatformCacheData.c @@ -0,0 +1,53 @@ +/** @file + + Copyright (c) 2024, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosPlatformDxe.h" + +// +// SMBIOS Type 7 Table is already initialized and installed in +// ArmPkg/SmbiosMiscDxe for Cache Level 1 and 2. Need to add one +// Type 7 Table for System Level Cache (SLC). +// +SMBIOS_PLATFORM_DXE_TABLE_DATA (SMBIOS_TABLE_TYPE7, PlatformCache) = { + { // Table 1 + { // Header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE7), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Socket Designation + 0x182, // Write Back, Enabled, Internal, Not Socketed, Cache Level 3 + 0x8010, // Maximum Cache Size: 1M + 0x8010, // Installed Size: 1M + { 0, 0, 0, 0, 0, 1}, // Supported SRAM Type: Synchronous + { 0, 0, 0, 0, 0, 1}, // Current SRAM Type: Synchronous + 0, // Cache Speed + CacheErrorSingleBit, // Error Correction Type + CacheTypeUnified, // System Cache Type + CacheAssociativity16Way // Associativity + }, + { // Null-terminated table + { + NULL_TERMINATED_TYPE, + 0, + 0 + }, + } +}; + +// +// Define string Tokens for additional strings. +// +SMBIOS_PLATFORM_DXE_STRING_TOKEN_DATA (PlatformCache) = { + { // Table 1 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_CACHE) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + } +}; diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type07/PlatformCacheFunction.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type07/PlatformCacheFunction.c new file mode 100644 index 00000000000..3b33a5d1675 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type07/PlatformCacheFunction.c @@ -0,0 +1,168 @@ +/** @file + + Copyright (c) 2024, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "SmbiosPlatformDxe.h" + +#define MAX_CACHE_LEVEL 2 + +#define SLC_SIZE(x) (UINT16)(0x8000 | (((x) * (1 << 20)) / (64 * (1 << 10)))) +#define SLC_SIZE_2(x) (0x80000000 | (((x) * (1 << 20)) / (64 * (1 << 10)))) + +typedef enum { + CacheModeWriteThrough = 0, ///< Cache is write-through + CacheModeWriteBack, ///< Cache is write-back + CacheModeVariesWithAddress, ///< Cache mode varies by address + CacheModeUnknown, ///< Cache mode is unknown + CacheModeMax +} CACHE_OPERATION_MODE; + +typedef enum { + CacheLocationInternal = 0, ///< Cache is internal to the processor + CacheLocationExternal, ///< Cache is external to the processor + CacheLocationReserved, ///< Reserved + CacheLocationUnknown, ///< Cache location is unknown + CacheLocationMax +} CACHE_LOCATION; + +/** + Checks whether SLC cache is should be displayed or not. + + @retval TRUE Should be displayed. + FALSE Should not be displayed. +**/ +BOOLEAN +CheckSlcCache ( + VOID + ) +{ + EFI_STATUS Status; + UINT32 NumaMode; + UINTN CpuConfigDataSize; + CPU_VARSTORE_DATA CpuConfigData; + + CpuConfigDataSize = sizeof (CPU_VARSTORE_DATA); + + Status = gRT->GetVariable ( + CPU_CONFIG_VARIABLE_NAME, + &gCpuConfigFormSetGuid, + NULL, + &CpuConfigDataSize, + &CpuConfigData + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Can not get CPU configuration information - %r\n", __func__, Status)); + + Status = NVParamGet ( + NV_SI_SUBNUMA_MODE, + NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC, + &NumaMode + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Can not get SubNUMA mode - %r\n", __func__, Status)); + NumaMode = SUBNUMA_MODE_MONOLITHIC; + } + + if (!IsSlaveSocketActive () && (NumaMode == SUBNUMA_MODE_MONOLITHIC)) { + return TRUE; + } + } else if (CpuConfigData.CpuSlcAsL3 == CPU_SLC_AS_L3_ENABLE) { + return TRUE; + } + + return FALSE; +} + +/** + Fills necessary information of SLC in SMBIOS Type 7. + + @param[out] Type7Record The Type 7 structure to allocate and initialize. + + @retval EFI_SUCCESS The Type 7 structure was successfully + allocated and the strings initialized. + EFI_OUT_OF_RESOURCES Could not allocate memory needed. +**/ +VOID +ConfigSlcArchitectureInformation ( + OUT SMBIOS_TABLE_TYPE7 *InputData + ) +{ + // Cache Size + if (IsAc01Processor ()) { + // + // Altra's SLC size is 32MB + // + InputData->MaximumCacheSize = SLC_SIZE (32); + InputData->MaximumCacheSize2 = SLC_SIZE_2 (32); + } else { + // + // Altra Max's SLC size is 16MB + // + InputData->MaximumCacheSize = SLC_SIZE (16); + InputData->MaximumCacheSize2 = SLC_SIZE_2 (16); + } + + InputData->InstalledSize = InputData->MaximumCacheSize; + InputData->InstalledSize2 = InputData->MaximumCacheSize2; +} + +/** + This function adds SMBIOS Table (Type 7) records for System Level Cache (SLC). + + @param RecordData Pointer to SMBIOS Table with default values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS Table was successfully added. + @retval Other Failed to add the SMBIOS Table. + +**/ +SMBIOS_PLATFORM_DXE_TABLE_FUNCTION (PlatformCache) { + EFI_STATUS Status; + STR_TOKEN_INFO *InputStrToken; + SMBIOS_TABLE_TYPE7 *Type7Record; + SMBIOS_TABLE_TYPE7 *InputData; + + if (CheckSlcCache ()) { + InputData = (SMBIOS_TABLE_TYPE7 *)RecordData; + InputStrToken = (STR_TOKEN_INFO *)StrToken; + + while (InputData->Hdr.Type != NULL_TERMINATED_TYPE) { + ConfigSlcArchitectureInformation (InputData); + SmbiosPlatformDxeCreateTable ( + (VOID *)&Type7Record, + (VOID *)&InputData, + sizeof (SMBIOS_TABLE_TYPE7), + InputStrToken + ); + if (Type7Record == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status = SmbiosPlatformDxeAddRecord ((UINT8 *)Type7Record, NULL); + if (EFI_ERROR (Status)) { + FreePool (Type7Record); + return Status; + } + + FreePool (Type7Record); + InputData++; + InputStrToken++; + } + } + + return EFI_SUCCESS; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type08/PlatformPortConnector.uni b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type08/PlatformPortConnector.uni new file mode 100644 index 00000000000..4cb6072b21d --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type08/PlatformPortConnector.uni @@ -0,0 +1,30 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=# + +#string STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_1 #language en-US "FRNT_VGA1 - Header on Motherboard" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_1 #language en-US "VGA1" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_2 #language en-US "USB3_1" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_2 #language en-US "USB3_1_2 - Rear Bottom/Left USB 3.2 Gen1 Port" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_3 #language en-US "USB3_2" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_3 #language en-US "USB3_1_2 - Rear Top/Left USB 3.2 Gen1 Port" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_4 #language en-US "USB3_3" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_4 #language en-US "USB3_3_4 - Rear Bottom/Right USB 3.2 Gen1 Port" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_5 #language en-US "USB3_4" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_5 #language en-US "USB3_3_4 - Rear Top/Right USB 3.2 Gen1 Port" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_6 #language en-US "USB3_3_1 - USB 3.2 Gen1 Header for Front Panel" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_7 #language en-US "IPMI" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_7 #language en-US "IPMI - Right RJ-45 LAN Port (BMC)" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_8 #language en-US "LAN3" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_8 #language en-US "LAN3 - Left RJ-45 1G LAN Port (Host)" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_9 #language en-US "SFP_1_2" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_9 #language en-US "SFP1 - Bottom 25G SFP28 (Fiber, Shared BMC/Host)" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_10 #language en-US "SFP_1_2" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_10 #language en-US "SFP2 - Top 25G SFP28 (Fiber, Host)" +#string STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_11 #language en-US "COM1 - SBSA UART Serial Port Header" diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type08/PlatformPortConnectorData.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type08/PlatformPortConnectorData.c new file mode 100644 index 00000000000..ae1294945d2 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type08/PlatformPortConnectorData.c @@ -0,0 +1,237 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosPlatformDxe.h" + +// +// Define data for SMBIOS Type 8 Table. +// +SMBIOS_PLATFORM_DXE_TABLE_DATA (SMBIOS_TABLE_TYPE8, PlatformPortConnector) = { + { // Table 1 + { // Header + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE8), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Internal Reference Designator + PortConnectorTypeOther, // Internal Connector Type + ADDITIONAL_STR_INDEX_2, // External Reference Designator + PortConnectorTypeDB15Female, // External Connector Type + PortTypeVideoPort // Port Type + }, + { // Table 2 + { // Header + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE8), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Internal Reference Designator + PortConnectorTypeNone, // Internal Connector Type + ADDITIONAL_STR_INDEX_2, // External Reference Designator + PortConnectorTypeUsb, // External Connector Type + PortTypeUsb // Port Type + }, + { // Table 3 + { // Header + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE8), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Internal Reference Designator + PortConnectorTypeNone, // Internal Connector Type + ADDITIONAL_STR_INDEX_2, // External Reference Designator + PortConnectorTypeUsb, // External Connector Type + PortTypeUsb // Port Type + }, + { // Table 4 + { // Header + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE8), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Internal Reference Designator + PortConnectorTypeNone, // Internal Connector Type + ADDITIONAL_STR_INDEX_2, // External Reference Designator + PortConnectorTypeUsb, // External Connector Type + PortTypeUsb // Port Type + }, + { // Table 5 + { // Header + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE8), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Internal Reference Designator + PortConnectorTypeNone, // Internal Connector Type + ADDITIONAL_STR_INDEX_2, // External Reference Designator + PortConnectorTypeUsb, // External Connector Type + PortTypeUsb // Port Type + }, + { // Table 6 + { // Header + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE8), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Internal Reference Designator + PortConnectorTypeOther, // Internal Connector Type + 0, // External Reference Designator + PortConnectorTypeNone, // External Connector Type + PortTypeUsb // Port Type + }, + { // Table 7 + { // Header + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE8), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Internal Reference Designator + PortConnectorTypeNone, // Internal Connector Type + ADDITIONAL_STR_INDEX_2, // External Reference Designator + PortConnectorTypeRJ45, // External Connector Type + PortTypeNetworkPort // Port Type + }, + { // Table 8 + { // Header + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE8), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Internal Reference Designator + PortConnectorTypeNone, // Internal Connector Type + ADDITIONAL_STR_INDEX_2, // External Reference Designator + PortConnectorTypeRJ45, // External Connector Type + PortTypeNetworkPort // Port Type + }, + { // Table 9 + { // Header + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE8), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Internal Reference Designator + PortConnectorTypeNone, // Internal Connector Type + ADDITIONAL_STR_INDEX_2, // External Reference Designator + PortConnectorTypeOther, // External Connector Type + PortTypeNetworkPort // Port Type + }, + { // Table 10 + { // Header + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE8), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Internal Reference Designator + PortConnectorTypeNone, // Internal Connector Type + ADDITIONAL_STR_INDEX_2, // External Reference Designator + PortConnectorTypeOther, // External Connector Type + PortTypeNetworkPort // Port Type + }, + { // Table 11 + { // Header + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE8), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Internal Reference Designator + PortConnectorType9PinDualInline, // Internal Connector Type + 0, // External Reference Designator + PortConnectorTypeNone, // External Connector Type + PortTypeOther // Port Type + }, + { // Null-terminated table + { + NULL_TERMINATED_TYPE, + 0, + 0 + }, + } +}; + +// +// Define string Tokens for additional strings. +// +SMBIOS_PLATFORM_DXE_STRING_TOKEN_DATA (PlatformPortConnector) = { + { // Table 1 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_1), + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_1) + }, + ADDITIONAL_STR_INDEX_2 // Size of Tokens array + }, + { // Table 2 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_2), + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_2) + }, + ADDITIONAL_STR_INDEX_2 // Size of Tokens array + }, + { // Table 3 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_3), + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_3) + }, + ADDITIONAL_STR_INDEX_2 // Size of Tokens array + }, + { // Table 4 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_4), + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_4) + }, + ADDITIONAL_STR_INDEX_2 // Size of Tokens array + }, + { // Table 5 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_5), + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_5) + }, + ADDITIONAL_STR_INDEX_2 // Size of Tokens array + }, + { // Table 6 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_6), + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_6) + }, + ADDITIONAL_STR_INDEX_2 // Size of Tokens array + }, + { // Table 7 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_7), + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_7) + }, + ADDITIONAL_STR_INDEX_2 // Size of Tokens array + }, + { // Table 8 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_8), + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_8) + }, + ADDITIONAL_STR_INDEX_2 // Size of Tokens array + }, + { // Table 9 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_9), + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_9) + }, + ADDITIONAL_STR_INDEX_2 // Size of Tokens array + }, + { // Table 10 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_10), + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_EXTERNAL_REFERENCE_DESIGNATOR_10) + }, + ADDITIONAL_STR_INDEX_2 // Size of Tokens array + }, + { // Table 11 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_11), + STRING_TOKEN (STR_PLATFORM_DXE_PORT_CONNECTOR_INTERNAL_REFERENCE_DESIGNATOR_11) + }, + ADDITIONAL_STR_INDEX_2 // Size of Tokens array + } +}; diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type08/PlatformPortConnectorFunction.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type08/PlatformPortConnectorFunction.c new file mode 100644 index 00000000000..9ac86f76f05 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type08/PlatformPortConnectorFunction.c @@ -0,0 +1,57 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +#include "SmbiosPlatformDxe.h" + +/** + This function adds SMBIOS Table (Type 8) records. + + @param RecordData Pointer to SMBIOS Table with default values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS Table was successfully added. + @retval Other Failed to update the SMBIOS Table. + +**/ +SMBIOS_PLATFORM_DXE_TABLE_FUNCTION (PlatformPortConnector) { + EFI_STATUS Status; + STR_TOKEN_INFO *InputStrToken; + SMBIOS_TABLE_TYPE8 *InputData; + SMBIOS_TABLE_TYPE8 *Type8Record; + + InputData = (SMBIOS_TABLE_TYPE8 *)RecordData; + InputStrToken = (STR_TOKEN_INFO *)StrToken; + + while (InputData->Hdr.Type != NULL_TERMINATED_TYPE) { + SmbiosPlatformDxeCreateTable ( + (VOID *)&Type8Record, + (VOID *)&InputData, + sizeof (SMBIOS_TABLE_TYPE8), + InputStrToken + ); + if (Type8Record == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status = SmbiosPlatformDxeAddRecord ((UINT8 *)Type8Record, NULL); + if (EFI_ERROR (Status)) { + FreePool (Type8Record); + return Status; + } + + FreePool (Type8Record); + InputData++; + InputStrToken++; + } + + return Status; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type09/PlatformSystemSlot.uni b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type09/PlatformSystemSlot.uni new file mode 100644 index 00000000000..1f0e2eab6d9 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type09/PlatformSystemSlot.uni @@ -0,0 +1,21 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=# + +#string STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_1 #language en-US "PCIE4 - x16 PCIe Slot" +#string STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_2 #language en-US "PCIE5 - x16 PCIe Slot" +#string STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_3 #language en-US "PCIE6 - x16 PCIe Slot" +#string STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_4 #language en-US "PCIE7 - x16 PCIe Slot" +#string STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_5 #language en-US "M2_1 - M-key M.2 Socket (Type 2230/2280)" +#string STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_6 #language en-US "OCU1 - PCIe x4 OCuLink Connector" +#string STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_7 #language en-US "OCU2 - PCIe x4 OCuLink Connector" +#string STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_8 #language en-US "SLIMLINE1 - PCIe x8 Slimline Connector" +#string STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_9 #language en-US "SLIMLINE2 - PCIe x8 Slimline Connector" +#string STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_10 #language en-US "SLIMLINE3 - PCIe x8 Slimline Connector" +#string STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_11 #language en-US "SLIMLINE4 - PCIe x8 Slimline Connector" diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type09/PlatformSystemSlotData.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type09/PlatformSystemSlotData.c new file mode 100644 index 00000000000..31e73df4719 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type09/PlatformSystemSlotData.c @@ -0,0 +1,292 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosPlatformDxe.h" + +// +// Define data for SMBIOS Type 9 Table. +// +SMBIOS_PLATFORM_DXE_TABLE_DATA (SMBIOS_TABLE_TYPE9, PlatformSystemSlot) = { + { // Table 1 + { // Header + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type + sizeof (SMBIOS_TABLE_TYPE9), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Slot Designation + SlotTypePciExpressGen4, // Slot Type + SlotDataBusWidth16X, // Slot Data Bus Width + SlotUsageAvailable, // Current Usage + SlotLengthLong, // Slot Length + 1, // Slot ID + {0, 0, 1}, // Slot Characteristics 1 + {1, 0, 0, 1}, // Slot Characteristics 2 + 1, // Segment Group Number + 1, // Bus Number + 0, // Device Function Number + }, + { // Table 2 + { // Header + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type + sizeof (SMBIOS_TABLE_TYPE9), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Slot Designation + SlotTypePciExpressGen4, // Slot Type + SlotDataBusWidth16X, // Slot Data Bus Width + SlotUsageAvailable, // Current Usage + SlotLengthLong, // Slot Length + 2, // Slot ID + {0, 0, 1}, // Slot Characteristics 1 + {1, 0, 0, 1}, // Slot Characteristics 2 + 5, // Segment Group Number + 1, // Bus Number + 0, // Device Function Number + }, + { // Table 3 + { // Header + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type + sizeof (SMBIOS_TABLE_TYPE9), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Slot Designation + SlotTypePciExpressGen4, // Slot Type + SlotDataBusWidth16X, // Slot Data Bus Width + SlotUsageAvailable, // Current Usage + SlotLengthLong, // Slot Length + 3, // Slot ID + {0, 0, 1}, // Slot Characteristics 1 + {1, 0, 0, 1}, // Slot Characteristics 2 + 5, // Segment Group Number + 1, // Bus Number + 0, // Device Function Number + }, + { // Table 4 + { // Header + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type + sizeof (SMBIOS_TABLE_TYPE9), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Slot Designation + SlotTypePciExpressGen4, // Slot Type + SlotDataBusWidth16X, // Slot Data Bus Width + SlotUsageAvailable, // Current Usage + SlotLengthLong, // Slot Length + 4, // Slot ID + {0, 0, 1}, // Slot Characteristics 1 + {1, 0, 0, 1}, // Slot Characteristics 2 + 4, // Segment Group Number + 0, // Bus Number + 1, // Device Function Number + }, + { // Table 5 + { // Header + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type + sizeof (SMBIOS_TABLE_TYPE9), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Slot Designation + SlotTypePciExpressGen4, // Slot Type + SlotDataBusWidth4X, // Slot Data Bus Width + SlotUsageAvailable, // Current Usage + SlotLengthOther, // Slot Length + 5, // Slot ID + {0, 0, 1}, // Slot Characteristics 1 + {1}, // Slot Characteristics 2 + 2, // Segment Group Number + 1, // Bus Number + 0, // Device Function Number + }, + { // Table 6 + { // Header + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type + sizeof (SMBIOS_TABLE_TYPE9), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Slot Designation + SlotTypeM2Socket3, // Slot Type + SlotDataBusWidth4X, // Slot Data Bus Width + SlotUsageAvailable, // Current Usage + SlotLengthOther, // Slot Length + 6, // Slot ID + {0, 0, 1}, // Slot Characteristics 1 + {1}, // Slot Characteristics 2 + 2, // Segment Group Number + 0, // Bus Number + 2, // Device Function Number + }, + { // Table 7 + { // Header + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type + sizeof (SMBIOS_TABLE_TYPE9), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Slot Designation + SlotTypePciExpressGen4, // Slot Type + SlotDataBusWidth4X, // Slot Data Bus Width + SlotUsageAvailable, // Current Usage + SlotLengthOther, // Slot Length + 7, // Slot ID + {0, 0, 1}, // Slot Characteristics 1 + {1}, // Slot Characteristics 2 + 2, // Segment Group Number + 0, // Bus Number + 4, // Device Function Number + }, + { // Table 8 + { // Header + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type + sizeof (SMBIOS_TABLE_TYPE9), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Slot Designation + SlotTypePciExpressGen4, // Slot Type + SlotDataBusWidth8X, // Slot Data Bus Width + SlotUsageAvailable, // Current Usage + SlotLengthOther, // Slot Length + 8, // Slot ID + {0, 0, 1}, // Slot Characteristics 1 + {1}, // Slot Characteristics 2 + 6, // Segment Group Number + 0, // Bus Number + 1, // Device Function Number + }, + { // Table 9 + { // Header + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type + sizeof (SMBIOS_TABLE_TYPE9), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Slot Designation + SlotTypePciExpressGen4, // Slot Type + SlotDataBusWidth8X, // Slot Data Bus Width + SlotUsageAvailable, // Current Usage + SlotLengthOther, // Slot Length + 9, // Slot ID + {0, 0, 1}, // Slot Characteristics 1 + {1}, // Slot Characteristics 2 + 6, // Segment Group Number + 0, // Bus Number + 5, // Device Function Number + }, + { // Table 10 + { // Header + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type + sizeof (SMBIOS_TABLE_TYPE9), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Slot Designation + SlotTypePciExpressGen4, // Slot Type + SlotDataBusWidth8X, // Slot Data Bus Width + SlotUsageAvailable, // Current Usage + SlotLengthOther, // Slot Length + 10, // Slot ID + {0, 0, 1}, // Slot Characteristics 1 + {1}, // Slot Characteristics 2 + 7, // Segment Group Number + 0, // Bus Number + 1, // Device Function Number + }, + { // Table 11 + { // Header + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type + sizeof (SMBIOS_TABLE_TYPE9), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Slot Designation + SlotTypePciExpressGen4, // Slot Type + SlotDataBusWidth8X, // Slot Data Bus Width + SlotUsageAvailable, // Current Usage + SlotLengthOther, // Slot Length + 11, // Slot ID + {0, 0, 1}, // Slot Characteristics 1 + {1}, // Slot Characteristics 2 + 7, // Segment Group Number + 0, // Bus Number + 5, // Device Function Number + }, + { // Null-terminated table + { + NULL_TERMINATED_TYPE, + 0, + 0 + }, + } +}; + +// +// Define string Tokens for additional strings. +// +SMBIOS_PLATFORM_DXE_STRING_TOKEN_DATA (PlatformSystemSlot) = { + { // Table 1 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_1) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + }, + { // Table 2 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_2) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + }, + { // Table 3 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_3) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + }, + { // Table 4 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_4) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + }, + { // Table 5 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_5) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + }, + { // Table 6 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_6) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + }, + { // Table 7 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_7) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + }, + { // Table 8 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_8) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + }, + { // Table 9 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_9) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + }, + { // Table 10 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_10) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + }, + { // Table 11 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_SYSTEM_SLOT_DESIGNATION_11) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + }, +}; diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type09/PlatformSystemSlotFunction.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type09/PlatformSystemSlotFunction.c new file mode 100644 index 00000000000..5f90b052210 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type09/PlatformSystemSlotFunction.c @@ -0,0 +1,313 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#include "SmbiosPlatformDxe.h" + +// I2C access to the second IO Expander doesn't appear to work +#if 0 + +// +// IO Expander Assignment +// + +#define SLIM1A_PRESENT_PIN 4 +#define SLIM1B_PRESENT_PIN 5 +#define SLIM2A_PRESENT_PIN 6 +#define SLIM2B_PRESENT_PIN 7 +#define SLIM3A_PRESENT_PIN 8 +#define SLIM3B_PRESENT_PIN 9 +#define SLIM4A_PRESENT_PIN 10 +#define SLIM4B_PRESENT_PIN 11 +#define OCU2_PRESENT_PIN 13 +#define OCU1_PRESENT_PIN 14 +#define PCIE4_PRESENT_X1_PIN 17 +#define PCIE4_PRESENT_X4_PIN 18 +#define PCIE4_PRESENT_X8_PIN 19 +#define PCIE4_PRESENT_X16_PIN 20 + +#define PCIE5_PRESENT_X1_PIN 4 +#define PCIE5_PRESENT_X4_PIN 5 +#define PCIE5_PRESENT_X8_PIN 6 +#define PCIE5_PRESENT_X16_PIN 7 +#define PCIE6_PRESENT_X1_PIN 8 +#define PCIE6_PRESENT_X4_PIN 9 +#define PCIE6_PRESENT_X8_PIN 10 +#define PCIE6_PRESENT_X16_PIN 11 +#define PCIE7_PRESENT_X1_PIN 13 +#define PCIE7_PRESENT_X4_PIN 14 +#define PCIE7_PRESENT_X8_PIN 15 +#define PCIE7_PRESENT_X16_PIN 16 + +// +// CPU I2C Bus for IO Expander +// +#define IO_EXPANDER_I2C_BUS 4 + +// +// I2C address of IO Expander devices +// +#define SLIM_PCIE4_I2C_ADDRESS 32 +#define PCIE5_7_I2C_ADDRESS 33 + +typedef enum { + PCIE4_SLOT_INDEX = 0, + PCIE5_SLOT_INDEX, + PCIE6_SLOT_INDEX, + PCIE7_SLOT_INDEX, + OCU1_SLOT_INDEX, + OCU2_SLOT_INDEX, + SLIM1_SLOT_INDEX, + SLIM2_SLOT_INDEX, + SLIM3_SLOT_INDEX, + SLIM4_SLOT_INDEX, +} SLOT_INDEX; + +BOOLEAN +GetPinStatus ( + IN IO_EXPANDER_CONTROLLER *Controller, + IN UINT8 Pin + ) +{ + EFI_STATUS Status; + UINT8 PinValue; + + Status = IOExpanderSetDir ( + Controller, + Pin, + CONFIG_IOEXPANDER_PIN_AS_INPUT + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to set IO pin direction\n", __func__)); + return FALSE; + } + Status = IOExpanderGetPin ( + Controller, + Pin, + &PinValue + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to get IO pin value\n", __func__)); + return FALSE; + } + + return (PinValue > 0) ? FALSE : TRUE; +} + +VOID +SetIoExpanderController ( + SLOT_INDEX SlotIndex, + IO_EXPANDER_CONTROLLER *Controller + ) +{ + switch (SlotIndex) { + case SLIM1_SLOT_INDEX: + case SLIM2_SLOT_INDEX: + case SLIM3_SLOT_INDEX: + case SLIM4_SLOT_INDEX: + case PCIE4_SLOT_INDEX: + case OCU1_SLOT_INDEX: + case OCU2_SLOT_INDEX: + Controller->ChipID = IO_EXPANDER_TCA9534; + Controller->I2cBus = IO_EXPANDER_I2C_BUS; + Controller->I2cAddress = SLIM_PCIE4_I2C_ADDRESS; + break; + + case PCIE5_SLOT_INDEX: + case PCIE6_SLOT_INDEX: + case PCIE7_SLOT_INDEX: + Controller->ChipID = IO_EXPANDER_TCA9534; + Controller->I2cBus = IO_EXPANDER_I2C_BUS; + Controller->I2cAddress = PCIE5_7_I2C_ADDRESS; + break; + + default: + DEBUG ((DEBUG_WARN, "Warning: invalid slot index %d\n", SlotIndex)); + return; + } +} + +VOID +UpdateSmbiosType9 ( + SLOT_INDEX SlotIndex, + SMBIOS_TABLE_TYPE9 *InputData + ) +{ + IO_EXPANDER_CONTROLLER Controller; + + SetIoExpanderController (SlotIndex, &Controller); + + switch (SlotIndex) { + case SLIM1_SLOT_INDEX: + if (GetPinStatus (&Controller, SLIM1A_PRESENT_PIN) || + GetPinStatus (&Controller, SLIM1B_PRESENT_PIN)) + { + InputData->CurrentUsage = SlotUsageInUse; + } else { + InputData->CurrentUsage = SlotUsageAvailable; + } + break; + + case SLIM2_SLOT_INDEX: + if (GetPinStatus (&Controller, SLIM2A_PRESENT_PIN) || + GetPinStatus (&Controller, SLIM2B_PRESENT_PIN)) + { + InputData->CurrentUsage = SlotUsageInUse; + } else { + InputData->CurrentUsage = SlotUsageAvailable; + } + break; + + case SLIM3_SLOT_INDEX: + if (GetPinStatus (&Controller, SLIM3A_PRESENT_PIN) || + GetPinStatus (&Controller, SLIM3B_PRESENT_PIN)) + { + InputData->CurrentUsage = SlotUsageInUse; + } else { + InputData->CurrentUsage = SlotUsageAvailable; + } + break; + + case SLIM4_SLOT_INDEX: + if (GetPinStatus (&Controller, SLIM4A_PRESENT_PIN) || + GetPinStatus (&Controller, SLIM4B_PRESENT_PIN)) + { + InputData->CurrentUsage = SlotUsageInUse; + } else { + InputData->CurrentUsage = SlotUsageAvailable; + } + break; + + case OCU2_SLOT_INDEX: + if (GetPinStatus (&Controller, OCU2_PRESENT_PIN) || + GetPinStatus (&Controller, OCU2_PRESENT_PIN)) + { + InputData->CurrentUsage = SlotUsageInUse; + } else { + InputData->CurrentUsage = SlotUsageAvailable; + } + break; + + case OCU1_SLOT_INDEX: + if (GetPinStatus (&Controller, OCU1_PRESENT_PIN) || + GetPinStatus (&Controller, OCU1_PRESENT_PIN)) + { + InputData->CurrentUsage = SlotUsageInUse; + } else { + InputData->CurrentUsage = SlotUsageAvailable; + } + break; + + case PCIE4_SLOT_INDEX: + if (GetPinStatus (&Controller, PCIE4_PRESENT_X1_PIN) || + GetPinStatus (&Controller, PCIE4_PRESENT_X4_PIN) || + GetPinStatus (&Controller, PCIE4_PRESENT_X8_PIN) || + GetPinStatus (&Controller, PCIE4_PRESENT_X16_PIN)) + { + InputData->CurrentUsage = SlotUsageInUse; + } else { + InputData->CurrentUsage = SlotUsageAvailable; + } + break; + + case PCIE5_SLOT_INDEX: + if (GetPinStatus (&Controller, PCIE5_PRESENT_X1_PIN) || + GetPinStatus (&Controller, PCIE5_PRESENT_X4_PIN) || + GetPinStatus (&Controller, PCIE5_PRESENT_X8_PIN) || + GetPinStatus (&Controller, PCIE5_PRESENT_X16_PIN)) + { + InputData->CurrentUsage = SlotUsageInUse; + } else { + InputData->CurrentUsage = SlotUsageAvailable; + } + break; + + case PCIE6_SLOT_INDEX: + if (GetPinStatus (&Controller, PCIE6_PRESENT_X1_PIN) || + GetPinStatus (&Controller, PCIE6_PRESENT_X4_PIN) || + GetPinStatus (&Controller, PCIE6_PRESENT_X8_PIN) || + GetPinStatus (&Controller, PCIE6_PRESENT_X16_PIN)) + { + InputData->CurrentUsage = SlotUsageInUse; + } else { + InputData->CurrentUsage = SlotUsageAvailable; + } + break; + + case PCIE7_SLOT_INDEX: + if (GetPinStatus (&Controller, PCIE7_PRESENT_X1_PIN) || + GetPinStatus (&Controller, PCIE7_PRESENT_X4_PIN) || + GetPinStatus (&Controller, PCIE7_PRESENT_X8_PIN) || + GetPinStatus (&Controller, PCIE7_PRESENT_X16_PIN)) + { + InputData->CurrentUsage = SlotUsageInUse; + } else { + InputData->CurrentUsage = SlotUsageAvailable; + } + break; + + default: + DEBUG ((DEBUG_WARN, "Warning: unknown slot index %d\n", SlotIndex)); + return; + } +} + +#endif + +/** + This function adds SMBIOS Table (Type 9) records. + + @param RecordData Pointer to SMBIOS Table with default values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS Table was successfully added. + @retval Other Failed to update the SMBIOS Table. + +**/ +SMBIOS_PLATFORM_DXE_TABLE_FUNCTION (PlatformSystemSlot) { + EFI_STATUS Status; + // SLOT_INDEX SlotIndex; + STR_TOKEN_INFO *InputStrToken; + SMBIOS_TABLE_TYPE9 *InputData; + SMBIOS_TABLE_TYPE9 *Type9Record; + + // SlotIndex = PCIE4_SLOT_INDEX; + InputData = (SMBIOS_TABLE_TYPE9 *)RecordData; + InputStrToken = (STR_TOKEN_INFO *)StrToken; + + while (InputData->Hdr.Type != NULL_TERMINATED_TYPE) { + // UpdateSmbiosType9 (SlotIndex, InputData); + SmbiosPlatformDxeCreateTable ( + (VOID *)&Type9Record, + (VOID *)&InputData, + sizeof (SMBIOS_TABLE_TYPE9), + InputStrToken + ); + if (Type9Record == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status = SmbiosPlatformDxeAddRecord ((UINT8 *)Type9Record, NULL); + FreePool (Type9Record); + + if (EFI_ERROR (Status)) { + return Status; + } + + // SlotIndex++; + InputData++; + InputStrToken++; + } + + return Status; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type11/PlatformOemString.uni b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type11/PlatformOemString.uni new file mode 100644 index 00000000000..ede9f24aabe --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type11/PlatformOemString.uni @@ -0,0 +1,11 @@ +/** @file + + Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=# + +#string STR_PLATFORM_DXE_STRING_1 #language en-US "www.amperecomputing.com" diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type11/PlatformOemStringData.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type11/PlatformOemStringData.c new file mode 100644 index 00000000000..183432440e1 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type11/PlatformOemStringData.c @@ -0,0 +1,42 @@ +/** @file + + Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosPlatformDxe.h" + +// +// Define data for SMBIOS Type 11 Table. +// +SMBIOS_PLATFORM_DXE_TABLE_DATA (SMBIOS_TABLE_TYPE11, PlatformOemString) = { + { // Table 1 + { // Header + EFI_SMBIOS_TYPE_OEM_STRINGS, // Type + sizeof (SMBIOS_TABLE_TYPE11), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1 // String Count + }, + { // Null-terminated table + { + NULL_TERMINATED_TYPE, + 0, + 0 + }, + } +}; + +// +// Define string Tokens for additional strings. +// +SMBIOS_PLATFORM_DXE_STRING_TOKEN_DATA (PlatformOemString) = { + { // Table 1 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_STRING_1) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + } +}; diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type11/PlatformOemStringFunction.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type11/PlatformOemStringFunction.c new file mode 100644 index 00000000000..92ff3cf7393 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type11/PlatformOemStringFunction.c @@ -0,0 +1,57 @@ +/** @file + + Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +#include "SmbiosPlatformDxe.h" + +/** + This function adds SMBIOS Table (Type 11) records. + + @param RecordData Pointer to SMBIOS Table with default values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS Table was successfully added. + @retval Other Failed to update the SMBIOS Table. + +**/ +SMBIOS_PLATFORM_DXE_TABLE_FUNCTION (PlatformOemString) { + EFI_STATUS Status; + STR_TOKEN_INFO *InputStrToken; + SMBIOS_TABLE_TYPE11 *InputData; + SMBIOS_TABLE_TYPE11 *Type11Record; + + InputData = (SMBIOS_TABLE_TYPE11 *)RecordData; + InputStrToken = (STR_TOKEN_INFO *)StrToken; + + while (InputData->Hdr.Type != NULL_TERMINATED_TYPE) { + SmbiosPlatformDxeCreateTable ( + (VOID *)&Type11Record, + (VOID *)&InputData, + sizeof (SMBIOS_TABLE_TYPE11), + InputStrToken + ); + if (Type11Record == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status = SmbiosPlatformDxeAddRecord ((UINT8 *)Type11Record, NULL); + if (EFI_ERROR (Status)) { + FreePool (Type11Record); + return Status; + } + + FreePool (Type11Record); + InputData++; + InputStrToken++; + } + + return Status; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformJumperStringData.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformJumperStringData.c new file mode 100644 index 00000000000..cb87e4e9647 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformJumperStringData.c @@ -0,0 +1,42 @@ +/** @file + + Copyright (c) 2024, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosPlatformDxe.h" + +// +// Define data for SMBIOS Type 12 Table. +// +SMBIOS_PLATFORM_DXE_TABLE_DATA (SMBIOS_TABLE_TYPE12, PlatformJumperString) = { + { // Table 1 + { // Header + EFI_SMBIOS_TYPE_OEM_STRINGS, // Type + sizeof (SMBIOS_TABLE_TYPE12), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1 // String Count + }, + { // Null-terminated table + { + NULL_TERMINATED_TYPE, + 0, + 0 + }, + } +}; + +// +// Define string Tokens for additional strings. +// +SMBIOS_PLATFORM_DXE_STRING_TOKEN_DATA (PlatformJumperString) = { + { // Table 1 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_STRING_1) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + } +}; diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformJumperStringFunction.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformJumperStringFunction.c new file mode 100644 index 00000000000..275564141ca --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformJumperStringFunction.c @@ -0,0 +1,57 @@ +/** @file + + Copyright (c) 2024, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +#include "SmbiosPlatformDxe.h" + +/** + This function adds SMBIOS Table (Type 12) records. + + @param RecordData Pointer to SMBIOS Table with default values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS Table was successfully added. + @retval Other Failed to update the SMBIOS Table. + +**/ +SMBIOS_PLATFORM_DXE_TABLE_FUNCTION (PlatformJumperString) { + EFI_STATUS Status; + STR_TOKEN_INFO *InputStrToken; + SMBIOS_TABLE_TYPE12 *InputData; + SMBIOS_TABLE_TYPE12 *Type12Record; + + InputData = (SMBIOS_TABLE_TYPE12 *)RecordData; + InputStrToken = (STR_TOKEN_INFO *)StrToken; + + while (InputData->Hdr.Type != NULL_TERMINATED_TYPE) { + SmbiosPlatformDxeCreateTable ( + (VOID *)&Type12Record, + (VOID *)&InputData, + sizeof (SMBIOS_TABLE_TYPE12), + InputStrToken + ); + if (Type12Record == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status = SmbiosPlatformDxeAddRecord ((UINT8 *)Type12Record, NULL); + if (EFI_ERROR (Status)) { + FreePool (Type12Record); + return Status; + } + + FreePool (Type12Record); + InputData++; + InputStrToken++; + } + + return Status; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformJumperStrings.uni b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformJumperStrings.uni new file mode 100644 index 00000000000..38b3fdea58a --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformJumperStrings.uni @@ -0,0 +1,11 @@ +/** @file + + Copyright (c) 2024, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=# + +#string STR_PLATFORM_DXE_STRING_1 #language en-US "BMC_DIS: 1-2 BMC Enabled (default); 2-3 BMC Disabled" diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformOemString.uni b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformOemString.uni new file mode 100644 index 00000000000..26037a119f7 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type12/PlatformOemString.uni @@ -0,0 +1,11 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=# + +#string STR_PLATFORM_DXE_STRING_1 #language en-US "www.amperecomputing.com" diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type16/PlatformPhysicalMemoryArrayData.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type16/PlatformPhysicalMemoryArrayData.c new file mode 100644 index 00000000000..69b631c0298 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type16/PlatformPhysicalMemoryArrayData.c @@ -0,0 +1,48 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosPlatformDxe.h" + +// +// Define data for SMBIOS Type 16 Table. +// +SMBIOS_PLATFORM_DXE_TABLE_DATA (SMBIOS_TABLE_TYPE16, PlatformPhysicalMemoryArray) = { + { // Table 1 + { // Header + EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // Type + sizeof (SMBIOS_TABLE_TYPE16), // Length + SMBIOS_HANDLE_PI_RESERVED, // Handle + }, + MemoryArrayLocationSystemBoard, // Location + MemoryArrayUseSystemMemory, // Use + MemoryErrorCorrectionMultiBitEcc, // Memory Error Correction + 0x80000000, // Maximum Capacity + 0xFFFE, // Memory Error Information Handle + 0x8, // Number Of Memory Device + 0x20000000000ULL // Extended Maximum Capacity + }, + { // Null-terminated table + { + NULL_TERMINATED_TYPE, + 0, + 0 + }, + } +}; + +// +// Define string Tokens for additional strings. +// +SMBIOS_PLATFORM_DXE_STRING_TOKEN_DATA (PlatformPhysicalMemoryArray) = { + { // Table 1 + { // Tokens array + NULL_TERMINATED_TOKEN + }, + 0 // Size of Tokens array + } +}; diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type16/PlatformPhysicalMemoryArrayFunction.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type16/PlatformPhysicalMemoryArrayFunction.c new file mode 100644 index 00000000000..e8236f29c6b --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type16/PlatformPhysicalMemoryArrayFunction.c @@ -0,0 +1,41 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +#include "SmbiosPlatformDxe.h" + +/** + This function adds SMBIOS Table (Type 16) records. + + @param RecordData Pointer to SMBIOS Table with default values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS Table was successfully added. + @retval Other Failed to update the SMBIOS Table. + +**/ +SMBIOS_PLATFORM_DXE_TABLE_FUNCTION (PlatformPhysicalMemoryArray) { + EFI_STATUS Status; + SMBIOS_TABLE_TYPE16 *InputData; + + InputData = (SMBIOS_TABLE_TYPE16 *)RecordData; + + while (InputData->Hdr.Type != NULL_TERMINATED_TYPE) { + Status = SmbiosPlatformDxeAddRecord ((UINT8 *)InputData, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + InputData++; + } + + return Status; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDevice.uni b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDevice.uni new file mode 100644 index 00000000000..517f7f9684a --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDevice.uni @@ -0,0 +1,16 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=# + +#string STR_PLATFORM_DXE_MEMORY_DEVICE_DEVICE_LOCATOR #language en-US "Not set" +#string STR_PLATFORM_DXE_MEMORY_DEVICE_BANK_LOCATOR #language en-US "Not set" +#string STR_PLATFORM_DXE_MEMORY_DEVICE_MANUFACTURER #language en-US "Not set" +#string STR_PLATFORM_DXE_MEMORY_DEVICE_SERIAL_NUMBER #language en-US "Not set" +#string STR_PLATFORM_DXE_MEMORY_DEVICE_ASSET_TAG #language en-US "Not set" +#string STR_PLATFORM_DXE_MEMORY_DEVICE_PART_NUMBER #language en-US "Not set" diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDeviceData.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDeviceData.c new file mode 100644 index 00000000000..470e031dd3c --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDeviceData.c @@ -0,0 +1,63 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosPlatformDxe.h" + +// +// Define data for SMBIOS Type 17 Table. +// +SMBIOS_PLATFORM_DXE_TABLE_DATA (SMBIOS_TABLE_TYPE17, PlatformMemoryDevice) = { + { // Table 1 + { // Hdr + EFI_SMBIOS_TYPE_MEMORY_DEVICE, // Type + sizeof (SMBIOS_TABLE_TYPE17), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + 0xFFFF, // Memory Array Handle + 0xFFFE, // Memory Error Information Handle + 72, // Total Width + 64, // Data Width + 0, // Size + 0x09, // Form Factor + 1, // Device Set + ADDITIONAL_STR_INDEX_1, // Device Locator + ADDITIONAL_STR_INDEX_2, // Bank Locator + MemoryTypeDdr4, // Memory Type + {}, // Type Detail + 0, // Speed + ADDITIONAL_STR_INDEX_3, // Manufacturer + ADDITIONAL_STR_INDEX_4, // Serial + ADDITIONAL_STR_INDEX_5, // Asset Tag + ADDITIONAL_STR_INDEX_6, // Part Number + 0, // Attributes + }, + { // Null-terminated table + { + NULL_TERMINATED_TYPE, + 0, + 0 + }, + } +}; + +// +// Define string Tokens for additional strings. +// +SMBIOS_PLATFORM_DXE_STRING_TOKEN_DATA (PlatformMemoryDevice) = { + { // Table 1 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_MEMORY_DEVICE_DEVICE_LOCATOR), + STRING_TOKEN (STR_PLATFORM_DXE_MEMORY_DEVICE_BANK_LOCATOR), + STRING_TOKEN (STR_PLATFORM_DXE_MEMORY_DEVICE_MANUFACTURER), + STRING_TOKEN (STR_PLATFORM_DXE_MEMORY_DEVICE_SERIAL_NUMBER), + STRING_TOKEN (STR_PLATFORM_DXE_MEMORY_DEVICE_ASSET_TAG), + STRING_TOKEN (STR_PLATFORM_DXE_MEMORY_DEVICE_PART_NUMBER) + }, + ADDITIONAL_STR_INDEX_6 // Size of Tokens array + } +}; diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDeviceFunction.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDeviceFunction.c new file mode 100644 index 00000000000..91c1c1b8ea3 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type17/PlatformMemoryDeviceFunction.c @@ -0,0 +1,367 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "SmbiosPlatformDxe.h" + +#define NULL_TERMINATED_ID 0xFF + +#define ASCII_SPACE_CHARACTER_CODE 0x20 +#define ASCII_TILDE_CHARACTER_CODE 0x7E + +#define SPD_PARITY_BIT_MASK 0x80 +#define SPD_MEMORY_TYPE_OFFSET 0x02 +#define SPD_CONTINUATION_CHARACTER 0x7F + +#define DDR4_SPD_MANUFACTURER_MEMORY_TYPE 0x0C +#define DDR4_SPD_MANUFACTURER_ID_BANK_OFFSET 320 +#define DDR4_SPD_MANUFACTURER_ID_CODE_OFFSET 321 +#define DDR4_SPD_MANUFACTURER_PART_NUMBER_OFFSET 329 +#define DDR4_SPD_MANUFACTURER_SERIAL_NUMBER_OFFSET 325 + +#define MAX_DIMMS 16 + +#define PRINTABLE_CHARACTER(Character) \ + (Character >= ASCII_SPACE_CHARACTER_CODE) && (Character <= ASCII_TILDE_CHARACTER_CODE) ? \ + Character : ASCII_SPACE_CHARACTER_CODE + +typedef enum { + DEVICE_LOCATOR_TOKEN_INDEX = 0, + BANK_LOCATOR_TOKEN_INDEX, + MANUFACTURER_TOKEN_INDEX, + SERIAL_NUMBER_TOKEN_INDEX, + ASSET_TAG_TOKEN_INDEX, + PART_NUMBER_TOKEN_INDEX +} MEMORY_DEVICE_TOKEN_INDEX; + +#pragma pack(1) +typedef struct { + UINT8 VendorId; + CHAR16 *ManufacturerString; +} JEDEC_MF_ID; +#pragma pack() + +VOID +UpdateManufacturer ( + IN UINT8 *SpdData, + IN UINT16 ManufacturerToken + ) +{ + UINTN Index; + UINT8 VendorId; + UINT8 MemType; + CONST CHAR8 *ManufacturerString; + CHAR16 *UnicodeManufacturerString; + UINTN Length; + + MemType = SpdData[SPD_MEMORY_TYPE_OFFSET]; + switch (MemType) { + case DDR4_SPD_MANUFACTURER_MEMORY_TYPE: + Index = SpdData[DDR4_SPD_MANUFACTURER_ID_BANK_OFFSET] & (~SPD_PARITY_BIT_MASK); // Remove parity bit + VendorId = SpdData[DDR4_SPD_MANUFACTURER_ID_CODE_OFFSET]; + break; + + default: // Not supported + DEBUG ((DEBUG_ERROR, "Unsupported/unknown DDR memory type encountered: %d\n", MemType)); + return; + } + + ManufacturerString = Jep106GetManufacturerName (VendorId, Index); + if (ManufacturerString == NULL) { + DEBUG ((DEBUG_WARN, "Failed to get JEDEC JEP107 manufacturer from VendorID %d, Index %d\n", VendorId, Index)); + return; + } + + Length = AsciiStrSize (ManufacturerString); + UnicodeManufacturerString = AllocateZeroPool (Length * sizeof (CHAR16)); + if (UnicodeManufacturerString == NULL) { + DEBUG ((DEBUG_WARN, "Failed to allocate memory for DDR manufacturer string.\n")); + return; + } + + AsciiStrToUnicodeStrS (ManufacturerString, UnicodeManufacturerString, Length); + HiiSetString (mSmbiosPlatformDxeHiiHandle, ManufacturerToken, UnicodeManufacturerString, NULL); + FreePool (UnicodeManufacturerString); +} + +VOID +UpdateSerialNumber ( + IN UINT8 *SpdData, + IN UINT16 SerialNumberToken + ) +{ + UINT8 MemType; + UINTN Offset; + CHAR16 SerialNumberStr[SMBIOS_UNICODE_STRING_MAX_LENGTH]; + + MemType = SpdData[SPD_MEMORY_TYPE_OFFSET]; + switch (MemType) { + case DDR4_SPD_MANUFACTURER_MEMORY_TYPE: + Offset = DDR4_SPD_MANUFACTURER_SERIAL_NUMBER_OFFSET; + break; + + default: // Not supported + DEBUG ((DEBUG_ERROR, "Unsupported/unknown DDR memory type encountered: %d\n", MemType)); + return; + } + + UnicodeSPrint ( + SerialNumberStr, + sizeof (SerialNumberStr), + L"%02X%02X%02X%02X", + SpdData[Offset], + SpdData[Offset + 1], + SpdData[Offset + 2], + SpdData[Offset + 3] + ); + HiiSetString (mSmbiosPlatformDxeHiiHandle, SerialNumberToken, SerialNumberStr, NULL); +} + +VOID +UpdatePartNumber ( + IN UINT8 *SpdData, + IN UINT16 PartNumberToken + ) +{ + UINT8 MemType; + UINTN Offset; + CHAR16 PartNumberStr[SMBIOS_UNICODE_STRING_MAX_LENGTH]; + + MemType = SpdData[SPD_MEMORY_TYPE_OFFSET]; + switch (MemType) { + case DDR4_SPD_MANUFACTURER_MEMORY_TYPE: + Offset = DDR4_SPD_MANUFACTURER_PART_NUMBER_OFFSET; + break; + + default: // Not supported + DEBUG ((DEBUG_ERROR, "Unsupported/unknown DDR memory type encountered: %d\n", MemType)); + return; + } + + UnicodeSPrint ( + PartNumberStr, + sizeof (PartNumberStr), + L"%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c", + PRINTABLE_CHARACTER (SpdData[Offset]), + PRINTABLE_CHARACTER (SpdData[Offset + 1]), + PRINTABLE_CHARACTER (SpdData[Offset + 2]), + PRINTABLE_CHARACTER (SpdData[Offset + 3]), + PRINTABLE_CHARACTER (SpdData[Offset + 4]), + PRINTABLE_CHARACTER (SpdData[Offset + 5]), + PRINTABLE_CHARACTER (SpdData[Offset + 6]), + PRINTABLE_CHARACTER (SpdData[Offset + 7]), + PRINTABLE_CHARACTER (SpdData[Offset + 8]), + PRINTABLE_CHARACTER (SpdData[Offset + 9]), + PRINTABLE_CHARACTER (SpdData[Offset + 10]), + PRINTABLE_CHARACTER (SpdData[Offset + 11]), + PRINTABLE_CHARACTER (SpdData[Offset + 12]), + PRINTABLE_CHARACTER (SpdData[Offset + 13]), + PRINTABLE_CHARACTER (SpdData[Offset + 14]), + PRINTABLE_CHARACTER (SpdData[Offset + 15]), + PRINTABLE_CHARACTER (SpdData[Offset + 16]), + PRINTABLE_CHARACTER (SpdData[Offset + 17]) + ); + HiiSetString (mSmbiosPlatformDxeHiiHandle, PartNumberToken, PartNumberStr, NULL); +} + +/** + This function adds SMBIOS Table (Type 17) records. + + @param RecordData Pointer to SMBIOS Table with default values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS Table was successfully added. + @retval Other Failed to update the SMBIOS Table. + +**/ +SMBIOS_PLATFORM_DXE_TABLE_FUNCTION (PlatformMemoryDevice) { + UINTN HandleCount; + UINTN DimmIndex; + UINTN ChannelIndex; + UINTN MemorySize; + UINT16 *HandleArray; + CHAR16 UnicodeStr[SMBIOS_UNICODE_STRING_MAX_LENGTH]; + EFI_STATUS Status; + SMBIOS_HANDLE MemoryArrayHandle; + PLATFORM_DIMM *Dimm; + STR_TOKEN_INFO *InputStrToken; + PLATFORM_DIMM_LIST *DimmList; + PLATFORM_DRAM_INFO *DramInfo; + SMBIOS_TABLE_TYPE17 *InputData; + SMBIOS_TABLE_TYPE17 *Type17Record; + + HandleCount = 0; + HandleArray = NULL; + + GetDimmList (&DimmList); + if (DimmList == NULL) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] Failed to get Dimm List\n", + __FUNCTION__, + __LINE__ + )); + return EFI_NOT_FOUND; + } + + GetDramInfo (&DramInfo); + if (DramInfo == NULL) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] Failed to get DRAM Information\n", + __FUNCTION__, + __LINE__ + )); + return EFI_NOT_FOUND; + } + + SmbiosPlatformDxeGetLinkTypeHandle ( + EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, + &HandleArray, + &HandleCount + ); + if (HandleArray == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + DEBUG ((DEBUG_INFO, "HandleCount: %d\n", HandleCount)); + + if (HandleCount < 1) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] Failed to get Memory Array Handle\n", + __FUNCTION__, + __LINE__ + )); + FreePool (HandleArray); + return EFI_NOT_FOUND; + } + + InputData = (SMBIOS_TABLE_TYPE17 *)RecordData; + InputStrToken = (STR_TOKEN_INFO *)StrToken; + MemoryArrayHandle = HandleArray[0]; + + DimmIndex = 0; + + for (ChannelIndex = 0; ChannelIndex < (MAX_DIMMS / 2); ChannelIndex++) { + // + // Prepare additional strings for SMBIOS Table. + // + Dimm = &DimmList->Dimm[DimmIndex]; + if (Dimm->NodeId != 0) { + continue; + } + + Status = SmbiosPlatformDxeSaveHiiDefaultString (InputStrToken); + if (EFI_ERROR (Status)) { + FreePool (HandleArray); + return Status; + } + if (Dimm->Info.DimmStatus == DIMM_INSTALLED_OPERATIONAL) { + UpdateManufacturer (Dimm->SpdData.Data, InputStrToken->TokenArray[MANUFACTURER_TOKEN_INDEX]); + UpdateSerialNumber (Dimm->SpdData.Data, InputStrToken->TokenArray[SERIAL_NUMBER_TOKEN_INDEX]); + UpdatePartNumber (Dimm->SpdData.Data, InputStrToken->TokenArray[PART_NUMBER_TOKEN_INDEX]); + } + UnicodeSPrint (UnicodeStr, sizeof (UnicodeStr), L"DIMM %c1", 'A' + ChannelIndex); + HiiSetString (mSmbiosPlatformDxeHiiHandle, InputStrToken->TokenArray[DEVICE_LOCATOR_TOKEN_INDEX], UnicodeStr, NULL); + UnicodeSPrint (UnicodeStr, sizeof (UnicodeStr), L"Bank %d", ChannelIndex); + HiiSetString (mSmbiosPlatformDxeHiiHandle, InputStrToken->TokenArray[BANK_LOCATOR_TOKEN_INDEX], UnicodeStr, NULL); + UnicodeSPrint (UnicodeStr, sizeof (UnicodeStr), L"Asset Tag Not Set"); + HiiSetString (mSmbiosPlatformDxeHiiHandle, InputStrToken->TokenArray[ASSET_TAG_TOKEN_INDEX], UnicodeStr, NULL); + + // + // Create Table and fill up information. + // + SmbiosPlatformDxeCreateTable ( + (VOID *)&Type17Record, + (VOID *)&InputData, + sizeof (SMBIOS_TABLE_TYPE17), + InputStrToken + ); + if (Type17Record == NULL) { + FreePool (HandleArray); + return EFI_OUT_OF_RESOURCES; + } + + if (Dimm->Info.DimmStatus != DIMM_NOT_INSTALLED) { + DEBUG ((DEBUG_INFO, "DIMM Info: \n")); + DEBUG ((DEBUG_INFO, "\tStatus (1=Installed-Operational, 2=Installed-NonOperational, 3=Installed-Failed): %d\n", Dimm->Info.DimmStatus)); + DEBUG ((DEBUG_INFO, "\tPart Number: %a\n", Dimm->Info.PartNumber)); + DEBUG ((DEBUG_INFO, "\tDimmSize: %llu\n", Dimm->Info.DimmSize)); + DEBUG ((DEBUG_INFO, "\tDimmMfcId: %d\n", Dimm->Info.DimmMfcId)); + DEBUG ((DEBUG_INFO, "\tDimmNrRank: %d\n", Dimm->Info.DimmNrRank)); + DEBUG ((DEBUG_INFO, "\tDimmType: %d\n", Dimm->Info.DimmType)); + DEBUG ((DEBUG_INFO, "\tDimmDevType: %d\n", Dimm->Info.DimmDevType)); + } + + if (Dimm->Info.DimmStatus == DIMM_INSTALLED_OPERATIONAL) { + MemorySize = Dimm->Info.DimmSize * 1024; + + if (MemorySize >= 0x7FFF) { + Type17Record->Size = 0x7FFF; + Type17Record->ExtendedSize = MemorySize; + } else { + Type17Record->Size = (UINT16)MemorySize; + Type17Record->ExtendedSize = 0; + } + + Type17Record->MemoryType = MemoryTypeDdr4; + Type17Record->Speed = (UINT16)DramInfo->MaxSpeed; + Type17Record->ConfiguredMemoryClockSpeed = (UINT16)DramInfo->MaxSpeed; + Type17Record->Attributes = Dimm->Info.DimmNrRank & 0x0F; + Type17Record->ConfiguredVoltage = 1200; + Type17Record->MinimumVoltage = 1140; + Type17Record->MaximumVoltage = 1260; + Type17Record->DeviceSet = 0; // None + + if (Dimm->Info.DimmType == UDIMM || Dimm->Info.DimmType == SODIMM) { + Type17Record->TypeDetail.Unbuffered = 1; // BIT 14: unregistered + } else if (Dimm->Info.DimmType == RDIMM + || Dimm->Info.DimmType == LRDIMM + || Dimm->Info.DimmType == RSODIMM) + { + Type17Record->TypeDetail.Registered = 1; // BIT 13: registered + } + /* FIXME: Determine if need to set technology to NVDIMM-* when supported */ + Type17Record->MemoryTechnology = MemoryTechnologyDram; + } + // Update Type 16 handle + Type17Record->MemoryArrayHandle = MemoryArrayHandle; + + // + // Add Table record and free pool. + // + Status = SmbiosPlatformDxeAddRecord ((UINT8 *)Type17Record, NULL); + if (EFI_ERROR (Status)) { + FreePool (HandleArray); + FreePool (Type17Record); + return Status; + } + + FreePool (Type17Record); + Status = SmbiosPlatformDxeRestoreHiiDefaultString (InputStrToken); + if (EFI_ERROR (Status)) { + FreePool (HandleArray); + return Status; + } + + DimmIndex += 2; + } + + FreePool (HandleArray); + + return Status; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type19/PlatformMemoryArrayMappedAddressData.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type19/PlatformMemoryArrayMappedAddressData.c new file mode 100644 index 00000000000..d14099ae885 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type19/PlatformMemoryArrayMappedAddressData.c @@ -0,0 +1,47 @@ +/** @file + + Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosPlatformDxe.h" + +// +// Define data for SMBIOS Type 19 Table. +// +SMBIOS_PLATFORM_DXE_TABLE_DATA (SMBIOS_TABLE_TYPE19, PlatformMemoryArrayMappedAddress) = { + { // Table 1 + { // Header + EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // Type + sizeof (SMBIOS_TABLE_TYPE19), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + 0xFFFFFFFF, // Starting Address + 0xFFFFFFFF, // Ending Address + 0xFFFF, // Memory Array Handle + 1, // Partition Width + 0x0, // Extended Starting Address + 0x0 // Extended Ending Address + }, + { // Null-terminated table + { + NULL_TERMINATED_TYPE, + 0, + 0 + }, + } +}; + +// +// Define string Tokens for additional strings. +// +SMBIOS_PLATFORM_DXE_STRING_TOKEN_DATA (PlatformMemoryArrayMappedAddress) = { + { // Table 1 + { // Tokens array + NULL_TERMINATED_TOKEN + }, + 0 // Size of Tokens array + } +}; diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type19/PlatformMemoryArrayMappedAddressFunction.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type19/PlatformMemoryArrayMappedAddressFunction.c new file mode 100644 index 00000000000..1ee0d90c6e6 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type19/PlatformMemoryArrayMappedAddressFunction.c @@ -0,0 +1,153 @@ +/** @file + + Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#include "SmbiosPlatformDxe.h" + +/** + This function adds SMBIOS Table (Type 19) records. + + @param RecordData Pointer to SMBIOS Table with default values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS Table was successfully added. + @retval Other Failed to update the SMBIOS Table. + +**/ +SMBIOS_PLATFORM_DXE_TABLE_FUNCTION (PlatformMemoryArrayMappedAddress) { + UINT8 Index; + UINT8 SlotIndex; + UINT8 MemRegionIndex; + UINTN HandleCount; + UINTN MemorySize; + UINT16 *HandleArray; + EFI_STATUS Status; + PLATFORM_DIMM *Dimm; + STR_TOKEN_INFO *InputStrToken; + PLATFORM_DIMM_LIST *DimmList; + PLATFORM_DRAM_INFO *DramInfo; + SMBIOS_TABLE_TYPE19 *InputData; + SMBIOS_TABLE_TYPE19 *Type19Record; + + HandleCount = 0; + HandleArray = NULL; + + GetDimmList (&DimmList); + if (DimmList == NULL) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] Failed to get Dimm List\n", + __func__, + __LINE__ + )); + return EFI_NOT_FOUND; + } + + GetDramInfo (&DramInfo); + if (DramInfo == NULL) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] Failed to get DRAM Information\n", + __func__, + __LINE__ + )); + return EFI_NOT_FOUND; + } + + SmbiosPlatformDxeGetLinkTypeHandle ( + EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, + &HandleArray, + &HandleCount + ); + if (HandleArray == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + if (HandleCount != GetNumberOfSupportedSockets ()) { + DEBUG (( + DEBUG_ERROR, + "[%a]:[%dL] Failed to get Memory Array Handle\n", + __func__, + __LINE__ + )); + FreePool (HandleArray); + return EFI_NOT_FOUND; + } + + for (Index = 0; Index < GetNumberOfSupportedSockets (); Index++) { + InputData = (SMBIOS_TABLE_TYPE19 *)RecordData; + InputStrToken = (STR_TOKEN_INFO *)StrToken; + while (InputData->Hdr.Type != NULL_TERMINATED_TYPE) { + // + // Calculate memory size + // + for (SlotIndex = 0; SlotIndex < DimmList->BoardDimmSlots; SlotIndex++) { + Dimm = &DimmList->Dimm[SlotIndex]; + if (Dimm->NodeId != Index) { + continue; + } + + if (Dimm->Info.DimmStatus == DIMM_INSTALLED_OPERATIONAL) { + MemorySize = Dimm->Info.DimmSize * 1024; + } + } + + // + // Create Table and fill up information + // + for (MemRegionIndex = 0; MemRegionIndex < DramInfo->NumRegion; MemRegionIndex++) { + SmbiosPlatformDxeCreateTable ( + (VOID *)&Type19Record, + (VOID *)&InputData, + sizeof (SMBIOS_TABLE_TYPE19), + InputStrToken + ); + if (Type19Record == NULL) { + FreePool (HandleArray); + return EFI_OUT_OF_RESOURCES; + } + + if ( (DramInfo->NvdRegion[MemRegionIndex] > 0) + || (DramInfo->Socket[MemRegionIndex] != Index)) + { + continue; + } + + Type19Record->ExtendedStartingAddress = DramInfo->Base[MemRegionIndex]; + Type19Record->ExtendedEndingAddress = DramInfo->Base[MemRegionIndex] + + DramInfo->Size[MemRegionIndex] -1; + if (MemorySize != 0) { + Type19Record->PartitionWidth = (DramInfo->Size[MemRegionIndex] - 1) / MemorySize + 1; + } + + Type19Record->MemoryArrayHandle = HandleArray[Index]; + + Status = SmbiosPlatformDxeAddRecord ((UINT8 *)Type19Record, NULL); + if (EFI_ERROR (Status)) { + FreePool (HandleArray); + FreePool (Type19Record); + return Status; + } + + FreePool (Type19Record); + } + + InputData++; + InputStrToken++; + } + } + + FreePool (HandleArray); + + return Status; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type38/PlatformIpmiDeviceData.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type38/PlatformIpmiDeviceData.c new file mode 100644 index 00000000000..d4b4212e5cd --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type38/PlatformIpmiDeviceData.c @@ -0,0 +1,46 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosPlatformDxe.h" + +// +// Define data for SMBIOS Type 38 Table. +// +SMBIOS_PLATFORM_DXE_TABLE_DATA (SMBIOS_TABLE_TYPE38, PlatformIpmiDevice) = { + { // Table 1 + { // Header + EFI_SMBIOS_TYPE_IPMI_DEVICE_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE38), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + IPMIDeviceInfoInterfaceTypeSSIF, // Interface Type + 0x20, // IPMI Specification Revision + 0x20, // I2C Slave Address + 0xFF, // NV Storage Device Address + 0x20, // Base Address + }, + { // Null-terminated table + { + NULL_TERMINATED_TYPE, + 0, + 0 + }, + } +}; + +// +// Define string Tokens for additional strings. +// +SMBIOS_PLATFORM_DXE_STRING_TOKEN_DATA (PlatformIpmiDevice) = { + { // Table 1 + { // Tokens array + NULL_TERMINATED_TOKEN + }, + 0 // Size of Tokens array + } +}; diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type38/PlatformIpmiDeviceFunction.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type38/PlatformIpmiDeviceFunction.c new file mode 100644 index 00000000000..8d13c037308 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type38/PlatformIpmiDeviceFunction.c @@ -0,0 +1,39 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +#include "SmbiosPlatformDxe.h" + +/** + This function adds SMBIOS Table (Type 38) records. + + @param RecordData Pointer to SMBIOS Table with default values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS Table was successfully added. + @retval Other Failed to update the SMBIOS Table. + +**/ +SMBIOS_PLATFORM_DXE_TABLE_FUNCTION (PlatformIpmiDevice) { + EFI_STATUS Status; + SMBIOS_TABLE_TYPE38 *InputData; + + InputData = (SMBIOS_TABLE_TYPE38 *)RecordData; + while (InputData->Hdr.Type != NULL_TERMINATED_TYPE) { + Status = SmbiosPlatformDxeAddRecord ((UINT8 *)InputData, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + InputData++; + } + + return Status; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type41/PlatformOnboardDevicesExtended.uni b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type41/PlatformOnboardDevicesExtended.uni new file mode 100644 index 00000000000..332202d4600 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type41/PlatformOnboardDevicesExtended.uni @@ -0,0 +1,13 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/=# + +#string STR_PLATFORM_DXE_ONBOARD_DEVICES_EXTENDED_DEVICE_TYPE_INSTANCE1 #language en-US "Onboard VGA" +#string STR_PLATFORM_DXE_ONBOARD_DEVICES_EXTENDED_DEVICE_TYPE_INSTANCE2 #language en-US "1G LAN" +#string STR_PLATFORM_DXE_ONBOARD_DEVICES_EXTENDED_DEVICE_TYPE_INSTANCE3 #language en-US "25G SFP28 LAN" +#string STR_PLATFORM_DXE_ONBOARD_DEVICES_EXTENDED_DEVICE_TYPE_INSTANCE4 #language en-US "25G SFP28 Shared BMC/Host LAN" diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type41/PlatformOnboardDevicesExtendedData.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type41/PlatformOnboardDevicesExtendedData.c new file mode 100644 index 00000000000..18feb76a386 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type41/PlatformOnboardDevicesExtendedData.c @@ -0,0 +1,104 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmbiosPlatformDxe.h" + +// +// Define data for SMBIOS Type 41 Table. +// +SMBIOS_PLATFORM_DXE_TABLE_DATA (SMBIOS_TABLE_TYPE41, PlatformOnboardDevicesExtended) = { + { // Table 1 + { // Header + EFI_SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE41), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Reference Designation + (1 << 7) | OnBoardDeviceExtendedTypeVideo, // Device Type + 1, // Device Type Instance + 3, // Segment Group Number + 2, // Bus Number + 0 // Device Function Number + }, + { // Table 1 + { // Header + EFI_SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE41), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Reference Designation + (1 << 7) | OnBoardDeviceExtendedTypeEthernet, // Device Type + 2, // Device Type Instance + 3, // Segment Group Number + 5, // Bus Number + 0 // Device Function Number + }, + { // Table 1 + { // Header + EFI_SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE41), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Reference Designation + (1 << 7) | OnBoardDeviceExtendedTypeEthernet, // Device Type + 3, // Device Type Instance + 2, // Segment Group Number + 3, // Bus Number + 0 // Device Function Number + }, + { // Table 1 + { // Header + EFI_SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION, // Type + sizeof (SMBIOS_TABLE_TYPE41), // Length + SMBIOS_HANDLE_PI_RESERVED // Handle + }, + ADDITIONAL_STR_INDEX_1, // Reference Designation + (1 << 7) | OnBoardDeviceExtendedTypeEthernet, // Device Type + 4, // Device Type Instance + 2, // Segment Group Number + 3, // Bus Number + 1 // Device Function Number + }, + { // Null-terminated table + { + NULL_TERMINATED_TYPE, + 0, + 0 + }, + } +}; + +// +// Define string Tokens for additional strings. +// +SMBIOS_PLATFORM_DXE_STRING_TOKEN_DATA (PlatformOnboardDevicesExtended) = { + { // Table 1 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_ONBOARD_DEVICES_EXTENDED_DEVICE_TYPE_INSTANCE1) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + }, + { // Table 2 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_ONBOARD_DEVICES_EXTENDED_DEVICE_TYPE_INSTANCE2) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + }, + { // Table 3 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_ONBOARD_DEVICES_EXTENDED_DEVICE_TYPE_INSTANCE3) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + }, + { // Table 4 + { // Tokens array + STRING_TOKEN (STR_PLATFORM_DXE_ONBOARD_DEVICES_EXTENDED_DEVICE_TYPE_INSTANCE4) + }, + ADDITIONAL_STR_INDEX_1 // Size of Tokens array + }, +}; diff --git a/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type41/PlatformOnboardDevicesExtendedFunction.c b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type41/PlatformOnboardDevicesExtendedFunction.c new file mode 100644 index 00000000000..fe9524fa2b4 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Drivers/SmbiosPlatformDxe/Type41/PlatformOnboardDevicesExtendedFunction.c @@ -0,0 +1,57 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +#include "SmbiosPlatformDxe.h" + +/** + This function adds SMBIOS Table (Type 41) records. + + @param RecordData Pointer to SMBIOS Table with default values. + @param Smbios SMBIOS protocol. + + @retval EFI_SUCCESS The SMBIOS Table was successfully added. + @retval Other Failed to update the SMBIOS Table. + +**/ +SMBIOS_PLATFORM_DXE_TABLE_FUNCTION (PlatformOnboardDevicesExtended) { + EFI_STATUS Status; + STR_TOKEN_INFO *InputStrToken; + SMBIOS_TABLE_TYPE41 *InputData; + SMBIOS_TABLE_TYPE41 *Type41Record; + + InputData = (SMBIOS_TABLE_TYPE41 *)RecordData; + InputStrToken = (STR_TOKEN_INFO *)StrToken; + + while (InputData->Hdr.Type != NULL_TERMINATED_TYPE) { + SmbiosPlatformDxeCreateTable ( + (VOID *)&Type41Record, + (VOID *)&InputData, + sizeof (SMBIOS_TABLE_TYPE41), + InputStrToken + ); + if (Type41Record == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status = SmbiosPlatformDxeAddRecord ((UINT8 *)Type41Record, NULL); + if (EFI_ERROR (Status)) { + FreePool (Type41Record); + return Status; + } + + FreePool (Type41Record); + InputData++; + InputStrToken++; + } + + return Status; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Library/BoardPcieLib/BoardPcieLib.c b/Platform/ASRockRack/AltraBoardPkg/Library/BoardPcieLib/BoardPcieLib.c new file mode 100644 index 00000000000..e2444b9eeb0 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Library/BoardPcieLib/BoardPcieLib.c @@ -0,0 +1,183 @@ +/** @file + Pcie board specific driver to handle asserting PERST signal to Endpoint + card. PERST asserting is via group of GPIO pins to CPLD as Platform Specification. + + Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include + +#define RCA_MAX_PERST_GROUPVAL 62 +#define RCB_MAX_PERST_GROUPVAL 46 +#define DEFAULT_SEGMENT_NUMBER 0x0F + +#define PCIE_PERST_DELAY (100 * 1000) // 100ms + +VOID +BoardPcieReleaseAllPerst ( + IN UINT8 SocketId + ) +{ + UINT32 GpioIndex, GpioPin; + + // Write 1 to all GPIO[16..21] to release all PERST + GpioPin = AC01_GPIO_PINS_PER_SOCKET * SocketId + 16; + for (GpioIndex = 0; GpioIndex < 6; GpioIndex++) { + GpioModeConfig (GpioPin + GpioIndex, GpioConfigOutHigh); + } + + MicroSecondDelay (PCIE_PERST_DELAY); +} + +EFI_STATUS +GetGpioGroup ( + IN UINT8 RootComplexId, + IN UINT8 PcieIndex, + OUT UINT32 *GpioGroupVal + ) +{ + /* Ampere Altra Max RootComplex->ID: 4:7 */ + if (PcieIndex < 2) { + switch (RootComplexId) { + case 4: + *GpioGroupVal = 34 - (PcieIndex * 2); + break; + case 5: + *GpioGroupVal = 38 - (PcieIndex * 2); + break; + case 6: + *GpioGroupVal = 30 - (PcieIndex * 2); + break; + case 7: + *GpioGroupVal = 26 - (PcieIndex * 2); + break; + default: + return EFI_INVALID_PARAMETER; + } + } else { + /* Ampere Altra Max RootComplex->ID: 4:7 */ + switch (RootComplexId) { + case 4: + *GpioGroupVal = 46 - ((PcieIndex - 2) * 2); + break; + case 5: + *GpioGroupVal = 42 - ((PcieIndex - 2) * 2); + break; + case 6: + *GpioGroupVal = 18 - ((PcieIndex - 2) * 2); + break; + case 7: + *GpioGroupVal = 22 - ((PcieIndex - 2) * 2); + break; + default: + return EFI_INVALID_PARAMETER; + } + } + + return EFI_SUCCESS; +} + +/** + Assert PERST of PCIe controller + + @param[in] RootComplex Root Complex instance. + @param[in] PcieIndex PCIe controller index of input Root Complex. + @param[in] IsPullToHigh Target status for the PERST. + + @retval RETURN_SUCCESS The operation is successful. + @retval Others An error occurred. +**/ +RETURN_STATUS +EFIAPI +BoardPcieAssertPerst ( + IN AC01_ROOT_COMPLEX *RootComplex, + IN UINT8 PcieIndex, + IN BOOLEAN IsPullToHigh + ) +{ + UINT32 GpioGroupVal; + UINT32 Val; + UINT32 GpioIndex; + UINT32 GpioPin; + EFI_STATUS Status; + + if (!IsPullToHigh) { + if (RootComplex->Type == RootComplexTypeA) { + if (RootComplex->ID < MaxPcieControllerOfRootComplexA) { + /* Ampere Altra: 4 */ + // + // RootComplexTypeA: RootComplex->ID: 0->3 ; PcieIndex: 0->3 + // + GpioGroupVal = RCA_MAX_PERST_GROUPVAL - PcieIndex + - RootComplex->ID * MaxPcieControllerOfRootComplexA; + } else { + Status = GetGpioGroup (RootComplex->ID, PcieIndex, &GpioGroupVal); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Invalid Root Complex ID %d\n", RootComplex->ID)); + return Status; + } + } + } else { + // + // RootComplexTypeB: RootComplex->ID: 4->7 ; PcieIndex: 0->7 + // + GpioGroupVal = RCB_MAX_PERST_GROUPVAL - PcieIndex + - (RootComplex->ID - MaxRootComplexA) * MaxPcieControllerOfRootComplexB; + } + + // Update the value of GPIO[16..21]. Corresponding PERST line will be decoded by CPLD. + GpioPin = AC01_GPIO_PINS_PER_SOCKET * RootComplex->Socket + 16; + for (GpioIndex = 0; GpioIndex < 6; GpioIndex++) { + Val = (GpioGroupVal & 0x3F) & (1 << GpioIndex); + if (Val == 0) { + GpioModeConfig (GpioPin + GpioIndex, GpioConfigOutLow); + } else { + GpioModeConfig (GpioPin + GpioIndex, GpioConfigOutHigh); + } + } + + // Keep reset as low as 100 ms as specification + MicroSecondDelay (PCIE_PERST_DELAY); + } else { + BoardPcieReleaseAllPerst (RootComplex->Socket); + } + + return RETURN_SUCCESS; +} + +/** + Override the segment number for a root complex with a board specific number. + + @param[in] RootComplex Root Complex instance with properties. + + @retval Segment number corresponding to the input root complex. + Default segment number is 0x0F. +**/ +UINT16 +BoardPcieGetSegmentNumber ( + IN AC01_ROOT_COMPLEX *RootComplex + ) +{ + UINT8 Ac01BoardSegment[PLATFORM_CPU_MAX_SOCKET][AC01_PCIE_MAX_ROOT_COMPLEX] = + { + { 0x0C, 0x0D, 0x01, 0x00, 0x02, 0x03, 0x04, 0x05 }, + { 0x10, 0x11, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B } + }; + + if ( (RootComplex->Socket < PLATFORM_CPU_MAX_SOCKET) + && (RootComplex->ID < AC01_PCIE_MAX_ROOT_COMPLEX)) + { + return Ac01BoardSegment[RootComplex->Socket][RootComplex->ID]; + } + + return (RootComplex->ID - 2); +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Library/BoardPcieLib/BoardPcieLib.inf b/Platform/ASRockRack/AltraBoardPkg/Library/BoardPcieLib/BoardPcieLib.inf new file mode 100644 index 00000000000..1d722bceff2 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Library/BoardPcieLib/BoardPcieLib.inf @@ -0,0 +1,27 @@ +## @file +# +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = BoardPcieLib + FILE_GUID = 062191A6-E113-4FD6-84C7-E400B4B34759 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = BoardPcieLib + +[Sources] + BoardPcieLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + +[LibraryClasses] + DebugLib + GpioLib + TimerLib diff --git a/Platform/ASRockRack/AltraBoardPkg/Library/IOExpanderLib/IOExpanderLib.c b/Platform/ASRockRack/AltraBoardPkg/Library/IOExpanderLib/IOExpanderLib.c new file mode 100644 index 00000000000..c166a342c7d --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Library/IOExpanderLib/IOExpanderLib.c @@ -0,0 +1,402 @@ +/** @file + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include + +#include +#include +#include +#include +#include +#include + +// +// Addresses of registers inside IO expander chip +// +#define TCA6424A_INPUT_REGISTER_BANK {0x00, 0x01, 0x02} +#define TCA6424A_OUTPUT_REGISTER_BANK {0x04, 0x05, 0x06} +#define TCA6424A_POLARITY_REGISTER_BANK {0x08, 0x09, 0x0A} +#define TCA6424A_CONFIG_REGISTER_BANK {0x0C, 0x0D, 0x0E} + +#define TCA9534_INPUT_REGISTER_BANK {0x00} +#define TCA9534_OUTPUT_REGISTER_BANK {0x01} +#define TCA9534_POLARITY_REGISTER_BANK {0x02} +#define TCA9534_CONFIG_REGISTER_BANK {0x03} + +CONST UINT8 gTca6424aRegister[4][3] = { + TCA6424A_INPUT_REGISTER_BANK, + TCA6424A_OUTPUT_REGISTER_BANK, + TCA6424A_POLARITY_REGISTER_BANK, + TCA6424A_CONFIG_REGISTER_BANK +}; +CONST UINT8 gTca9534Register[4][1] = { + TCA9534_INPUT_REGISTER_BANK, + TCA9534_OUTPUT_REGISTER_BANK, + TCA9534_POLARITY_REGISTER_BANK, + TCA9534_CONFIG_REGISTER_BANK +}; + +// +// Boundary of Pin number +// +#define PINS_PER_REGISTER 8 +#define REGISTERS_PER_BANK 3 + +#define INPUT_PORT_REGISTERS 0 +#define OUTPUT_PROT_REGISTERS 1 +#define POLARITY_INVERSION_REGISTERS 2 +#define CONFIGURATION_REGISTERS 3 + +// +// Pin port/bin manipulation on TCA6424A and TCA9534 +// +#define GET_REGISTER_ORDER(p) (UINT8)(p / 10) +#define GET_BIT_OF_PIN(p) (UINT8)(p % 10) +#define GET_BIT_VALUE(register, bit) (UINT8)((register >> bit) & 0x01) +#define SET_BIT(register, bit) (UINT8)(register | ~(0xFE << bit)) +#define CLEAR_BIT(register, bit) (UINT8)(register & (0xFE << bit)) + +#define GET_REGISTER_BANK(x) ((x) ? 0 : 1) + +#define IO_EXPANDER_I2C_BUS_SPEED 100000 + +STATIC +EFI_STATUS +IOExpanderI2cRead ( + IN UINT32 I2cBus, + IN UINT32 I2cAddress, + IN UINT8 *RegisterAddress, + IN UINT32 *NumberOfRegister, + OUT UINT8 *Data + ) +{ + EFI_STATUS Status; + UINT32 NumberOfRegisterAddress; + + Status = I2cProbe (I2cBus, IO_EXPANDER_I2C_BUS_SPEED); + if (EFI_ERROR (Status)) { + return Status; + } + + NumberOfRegisterAddress = 1; + Status = I2cRead (I2cBus, I2cAddress, RegisterAddress, NumberOfRegisterAddress, Data, NumberOfRegister); + if (EFI_ERROR (Status)) { + return Status; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +IOExpanderI2cWrite ( + IN UINT32 I2cBus, + IN UINT32 I2cAddress, + IN CONST UINT8 *RegisterAddress, + IN CONST UINT32 *NumberOfRegister, + IN UINT8 *Data + ) +{ + EFI_STATUS Status; + UINT8 Buffer[*NumberOfRegister + 1]; + UINT32 WriteSize; + + Status = I2cProbe (I2cBus, IO_EXPANDER_I2C_BUS_SPEED); + if (EFI_ERROR (Status)) { + return Status; + } + + WriteSize = sizeof (Buffer) - 1; + *Buffer = *RegisterAddress; + CopyMem ((VOID *)(Buffer + 1), (VOID *)Data, WriteSize); + Status = I2cWrite (I2cBus, I2cAddress, Buffer, &WriteSize); + if (EFI_ERROR (Status)) { + return Status; + } + + return EFI_SUCCESS; +} + +/** + Return configuration for given IO expander pin. + + @param[in] Controller Object contain information of IO expander chip. + @param[in] Pin Pxx, pin of IO expanderchip. + @param[out] PinValue Contain data retrieve. + + @retval EFI_SUCCESS Get successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_UNSUPPORTED The bus is not supported. + @retval EFI_NOT_READY The device/bus is not ready. + @retval EFI_TIMEOUT Timeout why transferring data. + @retval EFI_CRC_ERROR There are errors on receiving data. +**/ +EFI_STATUS +IOExpanderGetDir ( + IN OUT IO_EXPANDER_CONTROLLER *Controller, + IN UINT8 Pin, + OUT UINT8 *Value + ) +{ + EFI_STATUS Status; + UINT32 NumberOfRegister; + UINT8 RegisterAddress; + UINT8 RegisterData; + + NumberOfRegister = 1; + switch (Controller->ChipID) { + case IO_EXPANDER_TCA6424A: + RegisterAddress = gTca6424aRegister[CONFIGURATION_REGISTERS][GET_REGISTER_ORDER (Pin)]; + break; + + case IO_EXPANDER_TCA9534: + RegisterAddress = gTca9534Register[CONFIGURATION_REGISTERS][GET_REGISTER_ORDER (Pin)]; + break; + + default: + return EFI_INVALID_PARAMETER; + break; + } + + Status = IOExpanderI2cRead ( + Controller->I2cBus, + Controller->I2cAddress, + &RegisterAddress, + &NumberOfRegister, + &RegisterData + ); + if (EFI_ERROR (Status)) { + return Status; + } + + *Value = GET_BIT_VALUE (RegisterData, GET_BIT_OF_PIN (Pin)); + + return EFI_SUCCESS; +} + +/** + Set direction for given IO expander pin. + + @param[in] Controller Object contain information of IO expander chip. + @param[in] Pin Pxx, pin of IO expanderchip. + @param[in] Value 1 for set as input and 0 for as output. + + @retval EFI_SUCCESS Get successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_UNSUPPORTED The bus is not supported. + @retval EFI_NOT_READY The device/bus is not ready. + @retval EFI_TIMEOUT Timeout why transferring data. + @retval EFI_CRC_ERROR There are errors on receiving data. +**/ +EFI_STATUS +EFIAPI +IOExpanderSetDir ( + IN IO_EXPANDER_CONTROLLER *Controller, + IN UINT8 Pin, + IN UINT8 Value + ) +{ + EFI_STATUS Status; + UINT8 PinOldValue; + UINT32 NumberOfRegister; + UINT8 RegisterAddress; + UINT8 RegisterData; + + NumberOfRegister = 1; + switch (Controller->ChipID) { + case IO_EXPANDER_TCA6424A: + RegisterAddress = gTca6424aRegister[CONFIGURATION_REGISTERS][GET_REGISTER_ORDER (Pin)]; + break; + + case IO_EXPANDER_TCA9534: + RegisterAddress = gTca9534Register[CONFIGURATION_REGISTERS][GET_REGISTER_ORDER (Pin)]; + break; + + default: + return EFI_INVALID_PARAMETER; + break; + } + + Status = IOExpanderI2cRead ( + Controller->I2cBus, + Controller->I2cAddress, + &RegisterAddress, + &NumberOfRegister, + &RegisterData + ); + if (EFI_ERROR (Status)) { + return Status; + } + PinOldValue = GET_BIT_VALUE (RegisterData, GET_BIT_OF_PIN (Pin)); + + if (Value == PinOldValue) { + return EFI_SUCCESS; + } + + if (Value) { + RegisterData = SET_BIT (RegisterData, GET_BIT_OF_PIN (Pin)); + } else { + RegisterData = CLEAR_BIT (RegisterData, GET_BIT_OF_PIN (Pin)); + } + + NumberOfRegister = 1; + Status = IOExpanderI2cWrite ( + Controller->I2cBus, + Controller->I2cAddress, + &RegisterAddress, + &NumberOfRegister, + &RegisterData + ); + if (EFI_ERROR (Status)) { + return Status; + } + + return EFI_SUCCESS; +} + +/** + if given pin is configured in Input mode, this function will retrieve data from + Input Register. Or it is in Output mode, data will be retrieved from Output + Register. + + @param[in] Controller Object contain information of IO expander chip. + @param[in] Pin Pxx, pin of IO expanderchip. + @param[out] Value Contain data retrieved. + + @retval EFI_SUCCESS Get successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_UNSUPPORTED The bus is not supported. + @retval EFI_NOT_READY The device/bus is not ready. + @retval EFI_TIMEOUT Timeout why transferring data. + @retval EFI_CRC_ERROR There are errors on receiving data. +**/ +EFI_STATUS +IOExpanderGetPin ( + IN IO_EXPANDER_CONTROLLER *Controller, + IN UINT8 Pin, + OUT UINT8 *Value + ) +{ + EFI_STATUS Status; + UINT32 NumberOfRegister; + UINT8 ConfigValue; + UINT8 RegisterAddress; + UINT8 RegisterData; + + NumberOfRegister = 1; + Status = IOExpanderGetDir ( + Controller, + Pin, + &ConfigValue + ); + if (EFI_ERROR (Status)) { + return Status; + } + + switch (Controller->ChipID) { + case IO_EXPANDER_TCA6424A: + RegisterAddress = gTca6424aRegister[GET_REGISTER_BANK (ConfigValue)][GET_REGISTER_ORDER (Pin)]; + break; + + case IO_EXPANDER_TCA9534: + RegisterAddress = gTca9534Register[GET_REGISTER_BANK (ConfigValue)][GET_REGISTER_ORDER (Pin)]; + break; + + default: + return EFI_INVALID_PARAMETER; + break; + } + + Status = IOExpanderI2cRead ( + Controller->I2cBus, + Controller->I2cAddress, + &RegisterAddress, + &NumberOfRegister, + &RegisterData + ); + if (EFI_ERROR (Status)) { + return Status; + } + + *Value = GET_BIT_VALUE (RegisterData, GET_BIT_OF_PIN (Pin)); + + return EFI_SUCCESS; +} + +/** + Set the Output value for the given Expander IO pin. + + @param[in] Controller Object contain information of IO expander chip. + @param[in] Pin Pxx, pin of IO expanderchip. + @param[in] Value Expected value of output. + + @retval EFI_SUCCESS Get successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_UNSUPPORTED The bus is not supported. + @retval EFI_NOT_READY The device/bus is not ready. + @retval EFI_TIMEOUT Timeout why transferring data. + @retval EFI_CRC_ERROR There are errors on receiving data. +**/ +EFI_STATUS +IOExpanderSetPin ( + IN IO_EXPANDER_CONTROLLER *Controller, + IN UINT8 Pin, + IN UINT8 Value + ) +{ + EFI_STATUS Status; + UINT32 NumberOfRegister; + UINT8 RegisterAddress; + UINT8 RegisterData; + + switch (Controller->ChipID) { + case IO_EXPANDER_TCA6424A: + RegisterAddress = gTca6424aRegister[OUTPUT_PROT_REGISTERS][GET_REGISTER_ORDER (Pin)]; + break; + + case IO_EXPANDER_TCA9534: + RegisterAddress = gTca9534Register[OUTPUT_PROT_REGISTERS][GET_REGISTER_ORDER (Pin)]; + break; + + default: + return EFI_INVALID_PARAMETER; + break; + } + + NumberOfRegister = 1; + Status = IOExpanderI2cRead ( + Controller->I2cBus, + Controller->I2cAddress, + &RegisterAddress, + &NumberOfRegister, + &RegisterData + ); + if (EFI_ERROR (Status)) { + return Status; + } + if (Value == GET_BIT_VALUE (RegisterData, GET_BIT_OF_PIN (Pin))) { + return EFI_SUCCESS; + } + if (Value) { + RegisterData = SET_BIT (RegisterData, GET_BIT_OF_PIN(Pin)); + } else { + RegisterData = CLEAR_BIT (RegisterData, GET_BIT_OF_PIN(Pin)); + } + + Status = IOExpanderI2cWrite ( + Controller->I2cBus, + Controller->I2cAddress, + &RegisterAddress, + &NumberOfRegister, + &RegisterData + ); + if (EFI_ERROR (Status)) { + return Status; + } + + return EFI_SUCCESS; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Library/IOExpanderLib/IOExpanderLib.inf b/Platform/ASRockRack/AltraBoardPkg/Library/IOExpanderLib/IOExpanderLib.inf new file mode 100644 index 00000000000..7926abe25c2 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Library/IOExpanderLib/IOExpanderLib.inf @@ -0,0 +1,28 @@ +## @file +# +# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = IOExpanderLib + FILE_GUID = FC3B0B1A-5512-4EFE-B260-6BD35DD840C5 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = IOExpanderLib + +[Sources] + IOExpanderLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + I2cLib diff --git a/Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208.c b/Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208.c new file mode 100644 index 00000000000..fce8029369a --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208.c @@ -0,0 +1,313 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ISL1208.h" + +#define RTC_TIMEOUT_WAIT_ACCESS 100000 /* 100 miliseconds */ +#define RTC_DEFAULT_MIN_YEAR 2000 +#define RTC_DEFAULT_MAX_YEAR 2099 + +#define RTC_ADDR 0 +#define RTC_DATA_BUF_LEN 8 + +/** + * ISL1208 register offsets + */ +#define ISL1208_OFFSET_SEC 0x0 +#define ISL1208_OFFSET_MIN 0x1 +#define ISL1208_OFFSET_HR 0x2 +#define ISL1208_OFFSET_DAY 0x3 +#define ISL1208_OFFSET_MON 0x4 +#define ISL1208_OFFSET_YEA 0x5 +#define ISL1208_OFFSET_WKD 0x6 + +/* Buffer pointers to convert Vir2Phys and Phy2Vir */ +STATIC volatile UINT64 RtcBufVir; +STATIC volatile UINT64 RtcBufPhy; + +STATIC +EFI_STATUS +RtcI2cWaitAccess ( + VOID + ) +{ + INTN Timeout; + + Timeout = RTC_TIMEOUT_WAIT_ACCESS; + while ((GpioReadBit (I2C_RTC_ACCESS_GPIO_PIN) != 0) && (Timeout > 0)) { + MicroSecondDelay (100); + Timeout -= 100; + } + + if (Timeout <= 0) { + DEBUG ((DEBUG_ERROR, "%a: Timeout while waiting access RTC\n", __FUNCTION__)); + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +RtcI2cRead ( + IN UINT8 Addr, + IN OUT UINT64 Data, + IN UINT32 DataLen + ) +{ + EFI_STATUS Status; + UINT32 TmpLen; + + if (EFI_ERROR (RtcI2cWaitAccess ())) { + return EFI_DEVICE_ERROR; + } + + Status = I2cProbe (I2C_RTC_BUS_ADDRESS, I2C_RTC_BUS_SPEED, FALSE, FALSE); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + + // + // Send the slave address for read + // + TmpLen = 1; + Status = I2cWrite (I2C_RTC_BUS_ADDRESS, I2C_RTC_CHIP_ADDRESS, (UINT8 *)&Addr, &TmpLen); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + + // + // Read back the time + // + Status = I2cRead (I2C_RTC_BUS_ADDRESS, I2C_RTC_CHIP_ADDRESS, NULL, 0, (UINT8 *)Data, &DataLen); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +RtcI2cWrite ( + IN UINT8 Addr, + IN UINT64 Data, + IN UINT32 DataLen + ) +{ + EFI_STATUS Status; + UINT8 TmpBuf[RTC_DATA_BUF_LEN + 1]; + UINT32 TmpLen; + + if (EFI_ERROR (RtcI2cWaitAccess ())) { + return EFI_DEVICE_ERROR; + } + + if (DataLen > sizeof (TmpBuf) - 1) { + return EFI_INVALID_PARAMETER; + } + + Status = I2cProbe (I2C_RTC_BUS_ADDRESS, I2C_RTC_BUS_SPEED, FALSE, FALSE); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + + // + // The first byte is the address + // + TmpBuf[0] = Addr; + TmpLen = DataLen + 1; + CopyMem ((VOID *)(TmpBuf + 1), (VOID *)Data, DataLen); + + Status = I2cWrite (I2C_RTC_BUS_ADDRESS, I2C_RTC_CHIP_ADDRESS, TmpBuf, &TmpLen); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +/** + * Returns the current time and date information of the hardware platform. + * + * @param Time A pointer to storage to receive a snapshot of the current time. + * + * + * @retval EFI_SUCCESS The operation completed successfully. + * @retval EFI_INVALID_PARAMETER Time is NULL. + * @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error. + */ +EFI_STATUS +EFIAPI +PlatformGetTime ( + OUT EFI_TIME *Time + ) +{ + EFI_STATUS Status; + UINT8 *Data; + + if (Time == NULL) { + return EFI_INVALID_PARAMETER; + } + + Status = RtcI2cRead (RTC_ADDR, RtcBufVir, RTC_DATA_BUF_LEN); + + Data = (UINT8 *)RtcBufVir; + if (Status == EFI_SUCCESS) { + Time->Second = BcdToDecimal8 (Data[ISL1208_OFFSET_SEC] & 0x7F); + Time->Minute = BcdToDecimal8 (Data[ISL1208_OFFSET_MIN] & 0x7F); + Time->Hour = BcdToDecimal8 (Data[ISL1208_OFFSET_HR] & 0x3F); + Time->Day = BcdToDecimal8 (Data[ISL1208_OFFSET_DAY] & 0x3F); + Time->Month = BcdToDecimal8 (Data[ISL1208_OFFSET_MON] & 0x1F); + Time->Year = BcdToDecimal8 (Data[ISL1208_OFFSET_YEA] & 0xFF); + Time->Year += RTC_DEFAULT_MIN_YEAR; + if (Time->Year > RTC_DEFAULT_MAX_YEAR) { + Time->Year = RTC_DEFAULT_MAX_YEAR; + } + if (Time->Year < RTC_DEFAULT_MIN_YEAR) { + Time->Year = RTC_DEFAULT_MIN_YEAR; + } + } + + return Status; +} + +/** + * Set the time and date information to the hardware platform. + * + * @param Time A pointer to storage to set the current time to hardware platform. + * + * + * @retval EFI_SUCCESS The operation completed successfully. + * @retval EFI_INVALID_PARAMETER Time is NULL. + * @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error. + **/ +EFI_STATUS +EFIAPI +PlatformSetTime ( + IN EFI_TIME *Time + ) +{ + UINT8 *Data; + EFI_STATUS Status; + + if (Time == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Time->Year < RTC_DEFAULT_MIN_YEAR || + Time->Year > RTC_DEFAULT_MAX_YEAR) + { + return EFI_INVALID_PARAMETER; + } + + Data = (UINT8 *)RtcBufVir; + Data[ISL1208_OFFSET_SEC] = DecimalToBcd8 (Time->Second); + Data[ISL1208_OFFSET_MIN] = DecimalToBcd8 (Time->Minute); + Data[ISL1208_OFFSET_HR] = DecimalToBcd8 (Time->Hour); + Data[ISL1208_OFFSET_DAY] = DecimalToBcd8 (Time->Day); + Data[ISL1208_OFFSET_MON] = DecimalToBcd8 (Time->Month); + Data[ISL1208_OFFSET_YEA] = DecimalToBcd8 (Time->Year - RTC_DEFAULT_MIN_YEAR); + + Status = RtcI2cWrite (RTC_ADDR, RtcBufVir, RTC_DATA_BUF_LEN); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to write RTC: %r\n", Status)); + } + + return Status; +} + +/** + * Callback function for hardware platform to convert data pointers to virtual address + */ +VOID +EFIAPI +PlatformVirtualAddressChangeEvent ( + VOID + ) +{ + EfiConvertPointer (0x0, (VOID **)&RtcBufVir); +} + + +typedef struct { + UINT8 TotalPowerFailure : 1; + UINT8 BatteryBackupMode : 1; + UINT8 Alarm : 1; + UINT8 Reserved1 : 1; + UINT8 Write : 1; + UINT8 Reserved2 : 1; + UINT8 ExternalCrystal : 1; + UINT8 AutoReset : 1; +} RTC_STATUS; + +/** + * Callback function for hardware platform to initialize private data + * + * + * @retval EFI_SUCCESS The operation completed successfully. + * @retval Others The error status indicates the error + */ +EFI_STATUS +EFIAPI +PlatformInitialize ( + VOID + ) +{ + EFI_STATUS Status; + + /* + * Allocate the buffer for RTC data + * The buffer can be accessible after ExitBootServices + */ + RtcBufVir = (UINT64)AllocateRuntimeZeroPool (RTC_DATA_BUF_LEN); + ASSERT_EFI_ERROR (RtcBufVir); + RtcBufPhy = (UINT64)RtcBufVir; + + Status = I2cSetupRuntime (I2C_RTC_BUS_ADDRESS); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a:%d I2cSetupRuntime() failed - %r \n", + __func__, + __LINE__, + Status + )); + return Status; + } + + Status = GpioSetupRuntime (I2C_RTC_ACCESS_GPIO_PIN); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a:%d GpioSetupRuntime() failed - %r \n", + __func__, + __LINE__, + Status + )); + return Status; + } + + return EFI_SUCCESS; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208.h b/Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208.h new file mode 100644 index 00000000000..8424c2c1dfc --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208.h @@ -0,0 +1,91 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef ISL1208_H_ +#define ISL1208_H_ + +#include + +#include +#include + +// +// I2C bus address that RTC connected to +// +#define I2C_RTC_BUS_ADDRESS 4 + +// +// I2C RTC bus speed +// +#define I2C_RTC_BUS_SPEED 100000 + +// +// I2C chip address that RTC connected to +// +#define I2C_RTC_CHIP_ADDRESS 0x6F + +// +// The GPI PIN that tell if RTC can be access +// +#define I2C_RTC_ACCESS_GPIO_PIN 28 + +/** + * Returns the current time and date information of the hardware platform. + * + * @param Time A pointer to storage to receive a snapshot of the current time. + * + * + * @retval EFI_SUCCESS The operation completed successfully. + * @retval EFI_INVALID_PARAMETER Time is NULL. + * @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error. + */ +EFI_STATUS +EFIAPI +PlatformGetTime ( + OUT EFI_TIME *Time + ); + +/** + * Set the time and date information to the hardware platform. + * + * @param Time A pointer to storage to set the current time to hardware platform. + * + * + * @retval EFI_SUCCESS The operation completed successfully. + * @retval EFI_INVALID_PARAMETER Time is NULL. + * @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error. + **/ +EFI_STATUS +EFIAPI +PlatformSetTime ( + IN EFI_TIME *Time + ); + +/** + * Callback function for hardware platform to convert data pointers to virtual address + */ +VOID +EFIAPI +PlatformVirtualAddressChangeEvent ( + VOID + ); + +/** + * Callback function for hardware platform to initialize private data + * + * + * @retval EFI_SUCCESS The operation completed successfully. + * @retval Others The error status indicates the error + */ +EFI_STATUS +EFIAPI +PlatformInitialize ( + VOID + ); + +#endif /* ISL1208_H_ */ diff --git a/Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208RealTimeClockLib.c b/Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208RealTimeClockLib.c new file mode 100644 index 00000000000..f554d98905d --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208RealTimeClockLib.c @@ -0,0 +1,265 @@ +/** @file + + Copyright (c) 2020 - 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ISL1208.h" + +#define TICKS_PER_SEC (ArmGenericTimerGetTimerFreq ()) + +STATIC EFI_EVENT mVirtualAddressChangeEvent = NULL; + +STATIC UINT64 mLastSavedSystemCount = 0; +STATIC UINT64 mLastSavedTimeEpoch = 0; + +/** + * Returns the current time and date information, and the time-keeping capabilities + * of the hardware platform. + * + * @param Time A pointer to storage to receive a snapshot of the current time. + * @param Capabilities An optional pointer to a buffer to receive the real time clock + * device's capabilities. + * + * + * @retval EFI_SUCCESS The operation completed successfully. + * @retval EFI_INVALID_PARAMETER Time is NULL. + * @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error. + */ +EFI_STATUS +EFIAPI +LibGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities + ) +{ + EFI_STATUS Status; + UINT64 CurrentSystemCount; + UINT64 TimeElapsed; + UINTN EpochSeconds; + + if ((mLastSavedTimeEpoch == 0) || EfiAtRuntime ()) { + Status = PlatformGetTime (Time); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to read clock: %r\n", Status)); + // Failed to read platform RTC so create fake time + Time->Second = 0; + Time->Minute = 0; + Time->Hour = 10; + Time->Day = 1; + Time->Month = 1; + Time->Year = 2024; + } + + EpochSeconds = EfiTimeToEpoch (Time); + if (!EfiAtRuntime ()) { + mLastSavedTimeEpoch = EpochSeconds; + mLastSavedSystemCount = ArmGenericTimerGetSystemCount (); + MailboxMsgDateConfig (Time); + } + } else { + CurrentSystemCount = ArmGenericTimerGetSystemCount (); + if (CurrentSystemCount >= mLastSavedSystemCount) { + TimeElapsed = (CurrentSystemCount - mLastSavedSystemCount) / MultU64x32 (1, TICKS_PER_SEC); + EpochSeconds = mLastSavedTimeEpoch + TimeElapsed; + } else { + // System counter overflow 64 bits + // Call GetTime again to read the date from RTC HW, not using generic timer system counter + mLastSavedTimeEpoch = 0; + return LibGetTime (Time, Capabilities); + } + } + + // Adjust for the correct timezone + if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) { + EpochSeconds += Time->TimeZone * SEC_PER_MIN; + } + + // Adjust for the correct period + if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT) { + // Convert to adjusted time, i.e. spring forwards one hour + EpochSeconds += SEC_PER_HOUR; + } + + EpochToEfiTime (EpochSeconds, Time); + + return EFI_SUCCESS; +} + +/** + * Sets the current local time and date information. + * + * @param Time A pointer to the current time. + * + * @retval EFI_SUCCESS The operation completed successfully. + * @retval EFI_INVALID_PARAMETER A time field is out of range. + * @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error. + */ +EFI_STATUS +EFIAPI +LibSetTime ( + IN EFI_TIME *Time + ) +{ + EFI_STATUS Status; + UINTN EpochSeconds; + + EpochSeconds = EfiTimeToEpoch (Time); + + // Adjust for the correct time zone, i.e. convert to UTC time zone + if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) { + EpochSeconds -= Time->TimeZone * SEC_PER_MIN; + } + + // Adjust for the correct period, i.e. fall back one hour + if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT) { + EpochSeconds -= SEC_PER_HOUR; + } + + EpochToEfiTime (EpochSeconds, Time); + + Status = PlatformSetTime (Time); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to set time: %r\n", Status)); + return Status; + } + + MailboxMsgDateConfig (Time); + + if (!EfiAtRuntime ()) { + mLastSavedTimeEpoch = EpochSeconds; + mLastSavedSystemCount = ArmGenericTimerGetSystemCount (); + } + + return EFI_SUCCESS; +} + +/** + * Returns the current wakeup alarm clock setting. + * + * @param Enabled Indicates if the alarm is currently enabled or disabled. + * @param Pending Indicates if the alarm signal is pending and requires acknowledgement. + * @param Time The current alarm setting. + * + * @retval EFI_SUCCESS The alarm settings were returned. + * @retval EFI_INVALID_PARAMETER Any parameter is NULL. + * @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error. + */ +EFI_STATUS +EFIAPI +LibGetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ) +{ + return EFI_UNSUPPORTED; +} + +/** + * Sets the system wakeup alarm clock time. + * + * @param Enabled Enable or disable the wakeup alarm. + * @param Time If Enable is TRUE, the time to set the wakeup alarm for. + * + * @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If + * Enable is FALSE, then the wakeup alarm was disabled. + * @retval EFI_INVALID_PARAMETER A time field is out of range. + * @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error. + * @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform. + */ +EFI_STATUS +EFIAPI +LibSetWakeupTime ( + IN BOOLEAN Enabled, + OUT EFI_TIME *Time + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +LibRtcVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + // + // Only needed if you are going to support the OS calling RTC functions in virtual mode. + // You will need to call EfiConvertPointer (). To convert any stored physical addresses + // to virtual address. After the OS transitions to calling in virtual mode, all future + // runtime calls will be made in virtual mode. + // + PlatformVirtualAddressChangeEvent (); +} + +/** + * This is the declaration of an EFI image entry point. This can be the entry point to an application + * written to this specification, an EFI boot service driver, or an EFI runtime driver. + * + * @param ImageHandle Handle that identifies the loaded image. + * @param SystemTable System Table for this image. + * + * @retval EFI_SUCCESS The operation completed successfully. + */ +EFI_STATUS +EFIAPI +LibRtcInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = PlatformInitialize (); + if (EFI_ERROR (Status)) { + return Status; + } + + MailboxMsgDateConfigRuntimeSetup (); + + // + // Register for the virtual address change event + // + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + LibRtcVirtualNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &mVirtualAddressChangeEvent + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208RealTimeClockLib.inf b/Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208RealTimeClockLib.inf new file mode 100644 index 00000000000..6a029367631 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Library/ISL1208RealTimeClockLib/ISL1208RealTimeClockLib.inf @@ -0,0 +1,46 @@ +## @file +# +# Copyright (c) 2020 - 2022, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + MODULE_TYPE = DXE_RUNTIME_DRIVER + BASE_NAME = ISL1208RealTimeClockLib + FILE_GUID = ba313aaa-33a8-49ec-a6fc-18cb93590143 + LIBRARY_CLASS = RealTimeClockLib|DXE_RUNTIME_DRIVER + VERSION_STRING = 1.0 + +[Sources.common] + ISL1208.c + ISL1208.h + ISL1208RealTimeClockLib.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec + +[LibraryClasses] + ArmGenericTimerCounterLib + ArmLib + BaseLib + DebugLib + GpioLib + DxeServicesTableLib + I2cLib + TimeBaseLib + TimerLib + UefiLib + UefiRuntimeLib + SystemFirmwareInterfaceLib + MailboxInterfaceLib + +[Guids] + gEfiEventVirtualAddressChangeGuid diff --git a/Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/IpmiFruInfo.c b/Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/IpmiFruInfo.c new file mode 100644 index 00000000000..98763a605ef --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/IpmiFruInfo.c @@ -0,0 +1,523 @@ +/** @file + Provides functions to read FRU information from BMC via IPMI interface. + The FRU information will be cached in the string package. + + Reference: + - Platform Management FRU Information Storage Definition V1.0 + + Copyright (c) 2024, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "IpmiFruInfo.h" + +// +// Maximum length of FRU Area Information +// +#define FRU_AREA_LENGTH_MAX 256 + +#define FRU_FIELD_DATA_DEFAULT "To be filled by O.E.M\0" + +// +// FRU Chassis Information +// +STATIC CHAR8 mFruChassisPartNumber[FRU_AREA_LENGTH_MAX] = FRU_FIELD_DATA_DEFAULT; +STATIC CHAR8 mFruChassisSerialNumber[FRU_AREA_LENGTH_MAX] = FRU_FIELD_DATA_DEFAULT; +STATIC CHAR8 mFruChassisExtra[FRU_AREA_LENGTH_MAX] = FRU_FIELD_DATA_DEFAULT; + +STATIC CHAR8 *mFruChassisInfo[] = { + mFruChassisPartNumber, + mFruChassisSerialNumber, + mFruChassisExtra +}; + +// +// FRU Board Information +// +STATIC CHAR8 mFruBoardManufacturerName[FRU_AREA_LENGTH_MAX] = FRU_FIELD_DATA_DEFAULT; +STATIC CHAR8 mFruBoardProductName[FRU_AREA_LENGTH_MAX] = FRU_FIELD_DATA_DEFAULT; +STATIC CHAR8 mFruBoardSerialNumber[FRU_AREA_LENGTH_MAX] = FRU_FIELD_DATA_DEFAULT; +STATIC CHAR8 mFruBoardPartNumber[FRU_AREA_LENGTH_MAX] = FRU_FIELD_DATA_DEFAULT; + +STATIC CHAR8 *mFruBoardInfo[] = { + mFruBoardManufacturerName, + mFruBoardProductName, + mFruBoardSerialNumber, + mFruBoardPartNumber +}; + +// +// FRU Product Information +// +STATIC CHAR8 mFruProductManufacturerName[FRU_AREA_LENGTH_MAX] = FRU_FIELD_DATA_DEFAULT; +STATIC CHAR8 mFruProductName[FRU_AREA_LENGTH_MAX] = FRU_FIELD_DATA_DEFAULT; +STATIC CHAR8 mFruProductPartNumber[FRU_AREA_LENGTH_MAX] = FRU_FIELD_DATA_DEFAULT; +STATIC CHAR8 mFruProductVersion[FRU_AREA_LENGTH_MAX] = FRU_FIELD_DATA_DEFAULT; +STATIC CHAR8 mFruProductSerialNumber[FRU_AREA_LENGTH_MAX] = FRU_FIELD_DATA_DEFAULT; +STATIC CHAR8 mFruProductAssetTag[FRU_AREA_LENGTH_MAX] = FRU_FIELD_DATA_DEFAULT; +STATIC CHAR8 mFruProductFruFileId[FRU_AREA_LENGTH_MAX] = FRU_FIELD_DATA_DEFAULT; +STATIC CHAR8 mFruProductExtra[FRU_AREA_LENGTH_MAX] = FRU_FIELD_DATA_DEFAULT; + +STATIC CHAR8 *mFruProductInfo[] = { + mFruProductManufacturerName, + mFruProductName, + mFruProductPartNumber, + mFruProductVersion, + mFruProductSerialNumber, + mFruProductAssetTag, + mFruProductFruFileId, + mFruProductExtra +}; + +// +// All FRU Information +// +STATIC CHAR8 *mFruDataInfo[] = { + mFruChassisPartNumber, + mFruChassisSerialNumber, + mFruChassisExtra, + mFruBoardManufacturerName, + mFruBoardProductName, + mFruBoardSerialNumber, + mFruBoardPartNumber, + mFruProductManufacturerName, + mFruProductName, + mFruProductPartNumber, + mFruProductVersion, + mFruProductSerialNumber, + mFruProductAssetTag, + mFruProductFruFileId, + mFruProductExtra +}; + +STATIC BOOLEAN mReadFruInfo = FALSE; + +// +// Assume that there is only one FRU device +// and Device ID for Chassis/Board Information is 0. +// +#define FRU_DEVICE_ID_DEFAULT 0 + +// +// Maximum length of response data +// +#define IPMI_FRU_RESPONSE_LENGTH_MAX 32 + +// +// Refer to Section 13.1 BCD PLUS Definition +// +STATIC CONST CHAR8 BcdPlus[] = { + '0', + '1', + '2', + '3', + '4', + '5', + '6', + '7', + '8', + '9', + ' ', + '-', + '.', + ':', + ',', + '_' +}; + +// +// Refer to Section 13. TYPE/LENGTH BYTE FORMAT +// +CHAR8 * +ConvertEncodedDataToString ( + IN UINT8 *FruData, + IN OUT UINT16 *StartingOffset + ) +{ + UINT8 TypeCode; + UINT8 Length; + UINT16 Offset; + UINT8 Index1; + UINT8 Index2; + UINT8 Index3; + UINT16 DataSize; + CHAR8 *String; + UINT32 TempData; + + if ((FruData == NULL) || (StartingOffset == NULL)) { + return NULL; + } + + DataSize = 0; + Offset = *StartingOffset; + + // + // Type/Length Byte Format + // + // Bits 7:6 - type code + // 0b00 - Binary or unspecified + // 0b01: BCD plus + // 0b10: 6-bit ASCII + // 0b11: 8-bit ASCII + // + // Bits 5:0 - number of data bytes + // + + TypeCode = (FruData[Offset] & 0xC0) >> 6; + Length = FruData[Offset++] & 0x3F; + + if (Length == 0) { + *StartingOffset = Offset; + return NULL; + } + + switch (TypeCode) { + case 0: + DEBUG (( + DEBUG_ERROR, + "TypeCode 00b (Binary or unspecified) is unsupported!\n" + )); + return NULL; + break; + + case 2: + DataSize = ((((Length + 2) * 4) / 3) & ~0x03); + break; + + case 1: + case 3: + DataSize = Length; + break; + + default: + ASSERT (FALSE); + break; + } + + String = AllocateZeroPool (DataSize + 1); + if (String == NULL) { + return NULL; + } + + switch (TypeCode) { + case 0: + DEBUG (( + DEBUG_ERROR, + "TypeCode 00b (Binary or unspecified) is unsupported!\n" + )); + FreePool (String); + return NULL; + break; + + case 1: + for (Index1 = 0; Index1 < Length; Index1++) { + String[Index1] = BcdPlus[(FruData[Offset + Index1] & 0x0F)]; + } + + String[Index1] = '\0'; + break; + + case 2: + // + // Convert 3 6-bit data (3 bytes) to 4 8-bit data (4 bytes) in turn. + // + for (Index1 = 0, Index2 = 0; Index1 < Length; Index1 += 3) { + Index3 = ((Length - Index1) < 3) ? (Length - Index1) : 3; + ZeroMem (&TempData, sizeof (TempData)); + CopyMem (&TempData, &FruData[Offset + Index1], Index3); + for (Index3 = 0; Index3 < 4; Index3++) { + // + // Converting 6-bit ASCII to 8-bit ASCII has to be offset by 0x20 + // + String[Index2++] = (TempData & 0x3F) + 0x20; + TempData >>= 6; + } + } + + String[Index2] = '\0'; + break; + + case 3: + CopyMem (String, &FruData[Offset], DataSize); + String[DataSize] = '\0'; + break; + + default: + ASSERT (FALSE); + FreePool (String); + return NULL; + } + + Offset += Length; + *StartingOffset = Offset; + + return String; +} + +EFI_STATUS +InternalReadFruData ( + IN UINT16 AreaOffset, + IN UINT8 Length, + OUT UINT8 *Data + ) +{ + EFI_STATUS Status; + IPMI_READ_FRU_DATA_REQUEST FruDataRequest; + IPMI_READ_FRU_DATA_RESPONSE *FruDataResponse; + UINT8 TempData[IPMI_FRU_RESPONSE_LENGTH_MAX + sizeof (IPMI_READ_FRU_DATA_RESPONSE)]; + UINT32 ResponseSize; + UINT16 Offset; + UINT16 Finish; + + ASSERT (Data != NULL); + + Offset = AreaOffset; + Finish = Offset + Length; + + do { + FruDataRequest.DeviceId = FRU_DEVICE_ID_DEFAULT; + FruDataRequest.InventoryOffset = Offset; + + if ((Finish - Offset) > IPMI_FRU_RESPONSE_LENGTH_MAX) { + FruDataRequest.CountToRead = IPMI_FRU_RESPONSE_LENGTH_MAX; + } else { + FruDataRequest.CountToRead = Finish - Offset; + } + + ResponseSize = sizeof (IPMI_READ_FRU_DATA_RESPONSE) + FruDataRequest.CountToRead; + Status = IpmiReadFruData (&FruDataRequest, (IPMI_READ_FRU_DATA_RESPONSE *)TempData, &ResponseSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to read FRU data!\n", __func__)); + ASSERT_EFI_ERROR (Status); + break; + } + + FruDataResponse = (IPMI_READ_FRU_DATA_RESPONSE *)TempData; + + if (FruDataResponse->CompletionCode > 0) { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to request to read FRU data - Code Complete: 0x%x\n", + __func__, + FruDataResponse->CompletionCode + )); + break; + } + + CopyMem (Data, (VOID *)&(FruDataResponse->Data), FruDataResponse->CountReturned); + + Data += FruDataResponse->CountReturned; + Offset += FruDataResponse->CountReturned; + } while (Offset < Finish); + + return Status; +} + +EFI_STATUS +UpdateFruStringPack ( + VOID + ) +{ + EFI_STATUS Status; + UINT8 AreaDataLength; + UINT16 StartingOffset; + IPMI_FRU_COMMON_HEADER *FruCommonHeader; + UINT8 ChassisInfoAreaOffset; + UINT8 BoardInfoAreaOffset; + UINT8 ProductInfoAreaOffset; + CHAR8 *String; + UINTN StringSize; + UINT8 FruData[FRU_AREA_LENGTH_MAX]; + UINT8 Index; + + Status = InternalReadFruData (0, sizeof (IPMI_FRU_COMMON_HEADER), FruData); + if (EFI_ERROR (Status)) { + return Status; + } + + FruCommonHeader = (IPMI_FRU_COMMON_HEADER *)FruData; + + // + // Area offset is multiples of 8 bytes + // + ChassisInfoAreaOffset = FruCommonHeader->ChassisInfoStartingOffset * 8; + BoardInfoAreaOffset = FruCommonHeader->BoardAreaStartingOffset * 8; + ProductInfoAreaOffset = FruCommonHeader->ProductInfoStartingOffset * 8; + + // + // Read Chassis Info Area + // + ZeroMem (FruData, sizeof (FruData)); + Status = InternalReadFruData (ChassisInfoAreaOffset, 2, FruData); + ASSERT_EFI_ERROR (Status); + if (!EFI_ERROR (Status)) { + AreaDataLength = FruData[1] * 8; + ASSERT ((AreaDataLength + sizeof (IPMI_READ_FRU_DATA_RESPONSE)) <= FRU_AREA_LENGTH_MAX); + + ZeroMem (FruData, sizeof (FruData)); + Status = InternalReadFruData (ChassisInfoAreaOffset, AreaDataLength, FruData); + ASSERT_EFI_ERROR (Status); + if (!EFI_ERROR (Status)) { + StartingOffset = 3; /* Starting offset of Chassis Part Number */ + for (Index = 0; Index < ARRAY_SIZE (mFruChassisInfo); Index++) { + String = ConvertEncodedDataToString (FruData, &StartingOffset); + if (String != NULL) { + StringSize = AsciiStrSize (String); + ASSERT (StringSize <= SMBIOS_STRING_MAX_LENGTH); + if (StringSize != 1) { + // StringSize = 1 => Contain Null-terminated character + ZeroMem ((VOID *)mFruChassisInfo[Index], FRU_AREA_LENGTH_MAX); + CopyMem ((VOID *)mFruChassisInfo[Index], (VOID *)String, StringSize); + } + + FreePool (String); + String = NULL; + } + } + } + } + + // + // Read Board Info Area + // + ZeroMem (FruData, sizeof (FruData)); + Status = InternalReadFruData (BoardInfoAreaOffset, 2, FruData); + ASSERT_EFI_ERROR (Status); + if (!EFI_ERROR (Status)) { + AreaDataLength = FruData[1] * 8; + ASSERT ((AreaDataLength + sizeof (IPMI_READ_FRU_DATA_RESPONSE)) <= FRU_AREA_LENGTH_MAX); + + ZeroMem (FruData, sizeof (FruData)); + Status = InternalReadFruData (BoardInfoAreaOffset, AreaDataLength, FruData); + ASSERT_EFI_ERROR (Status); + if (!EFI_ERROR (Status)) { + StartingOffset = 6; /* Starting offset of Board Manufacturer */ + for (Index = 0; Index < ARRAY_SIZE (mFruBoardInfo); Index++) { + String = ConvertEncodedDataToString (FruData, &StartingOffset); + if (String != NULL) { + StringSize = AsciiStrSize (String); + ASSERT (StringSize <= SMBIOS_STRING_MAX_LENGTH); + if (StringSize != 1) { + // StringSize = 1 => Contain Null-terminated character + ZeroMem ((VOID *)mFruBoardInfo[Index], FRU_AREA_LENGTH_MAX); + CopyMem ((VOID *)mFruBoardInfo[Index], (VOID *)String, StringSize); + } + + FreePool (String); + String = NULL; + } + } + } + } + + // + // Read Product Info Area + // + ZeroMem (FruData, sizeof (FruData)); + Status = InternalReadFruData (ProductInfoAreaOffset, 2, FruData); + ASSERT_EFI_ERROR (Status); + if (!EFI_ERROR (Status)) { + AreaDataLength = FruData[1] * 8; + ASSERT ((AreaDataLength + sizeof (IPMI_READ_FRU_DATA_RESPONSE)) <= FRU_AREA_LENGTH_MAX); + + ZeroMem (FruData, sizeof (FruData)); + Status = InternalReadFruData (ProductInfoAreaOffset, AreaDataLength, FruData); + ASSERT_EFI_ERROR (Status); + if (!EFI_ERROR (Status)) { + StartingOffset = 3; /* Starting offset of Product Manufacturer */ + for (Index = 0; Index < ARRAY_SIZE (mFruProductInfo); Index++) { + String = ConvertEncodedDataToString (FruData, &StartingOffset); + if (String != NULL) { + StringSize = AsciiStrSize (String); + ASSERT (StringSize <= SMBIOS_STRING_MAX_LENGTH); + if (StringSize != 1) { + // StringSize = 1 => Contain Null-terminated character + ZeroMem ((VOID *)mFruProductInfo[Index], FRU_AREA_LENGTH_MAX); + CopyMem ((VOID *)mFruProductInfo[Index], (VOID *)String, StringSize); + } + + FreePool (String); + String = NULL; + } + } + } + } + + return Status; +} + +EFI_STATUS +IpmiReadFruInfo ( + VOID + ) +{ + EFI_STATUS Status; + IPMI_GET_DEVICE_ID_RESPONSE ControllerInfo; + IPMI_GET_FRU_INVENTORY_AREA_INFO_REQUEST GetFruInventoryAreaInfoRequest; + IPMI_GET_FRU_INVENTORY_AREA_INFO_RESPONSE GetFruInventoryAreaInfoResponse; + + // + // Get all the SDR Records from BMC and retrieve the Record ID from the structure for future use. + // + Status = IpmiGetDeviceId (&ControllerInfo); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: IpmiGetDeviceId Status=%x\n", __func__, Status)); + return Status; + } + + DEBUG ((DEBUG_INFO, "%a: FruInventorySupport=%x\n", __func__, ControllerInfo.DeviceSupport.Bits.FruInventorySupport)); + + if (ControllerInfo.DeviceSupport.Bits.FruInventorySupport) { + GetFruInventoryAreaInfoRequest.DeviceId = FRU_DEVICE_ID_DEFAULT; + Status = IpmiGetFruInventoryAreaInfo (&GetFruInventoryAreaInfoRequest, &GetFruInventoryAreaInfoResponse); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: IpmiGetFruInventoryAreaInfo Status=%x\n", __func__, Status)); + return Status; + } + + DEBUG ((DEBUG_INFO, "%a: InventoryAreaSize=%x\n", __func__, GetFruInventoryAreaInfoResponse.InventoryAreaSize)); + } + + return EFI_SUCCESS; +} + +CHAR8 * +EFIAPI +IpmiFruInfoGet ( + IPMI_FRU_FIELD_ID FieldId + ) +{ + EFI_STATUS Status; + + ASSERT (FieldId < FruFieldIdMax); + + if (!mReadFruInfo) { + Status = IpmiReadFruInfo (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to read FRU Information!\n", __func__)); + } else { + // Cache FRU information to the string package + Status = UpdateFruStringPack (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to update the FRU string package!\n", __func__)); + } + } + + mReadFruInfo = TRUE; + } + + return mFruDataInfo[FieldId]; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/IpmiFruInfo.h b/Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/IpmiFruInfo.h new file mode 100644 index 00000000000..a5f8b0259a4 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/IpmiFruInfo.h @@ -0,0 +1,48 @@ +/** @file + + Copyright (c) 2022, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef IPMI_FRU_INFO_H_ +#define IPMI_FRU_INFO_H_ + +#include + +// +// IPMI FRU Field IDs +// +typedef enum { + FruChassisPartNumber = 0, + FruChassisSerialNumber, + FruChassisExtra, + FruBoardManufacturerName, + FruBoardProductName, + FruBoardSerialNumber, + FruBoardPartNumber, + FruProductManufacturerName, + FruProductName, + FruProductPartNumber, + FruProductVersion, + FruProductSerialNumber, + FruProductAssetTag, + FruProductFruFileId, + FruProductExtra, + FruFieldIdMax +} IPMI_FRU_FIELD_ID; + +CHAR8 * +EFIAPI +IpmiFruInfoGet ( + IPMI_FRU_FIELD_ID FieldId + ); + +EFI_STATUS +EFIAPI +IpmiFruGetSystemUuid ( + OUT EFI_GUID *SystemUuid + ); + +#endif /* IPMI_FRU_INFO_H_ */ diff --git a/Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/OemMiscLib.c b/Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/OemMiscLib.c new file mode 100644 index 00000000000..a52bf550efa --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/OemMiscLib.c @@ -0,0 +1,821 @@ +/** @file +* OemMiscLib.c +* +* Copyright (c) 2021 - 2024, Ampere Computing LLC. All rights reserved. +* Copyright (c) 2021, NUVIA Inc. All rights reserved. +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "IpmiFruInfo.h" + +#define PROCESSOR_VERSION_ALTRA L"Ampere(R) Altra(R) Processor" +#define PROCESSOR_VERSION_ALTRA_MAX L"Ampere(R) Altra(R) Max Processor" + +#define PLACEHOLDER_SMBIOS_STRING "To be filled by O.E.M" + +#define SCP_VERSION_STRING_MAX_LENGTH 32 + +UINTN mProcessorIndex = 0xFF; + +UINT32 +GetCacheConfig ( + IN UINT32 CacheLevel, + IN BOOLEAN DataCache, + IN BOOLEAN UnifiedCache + ) +{ + CSSELR_DATA Csselr; + UINT64 Ccsidr; + BOOLEAN SupportWB; + BOOLEAN SupportWT; + + Csselr.Data = 0; + Csselr.Bits.Level = CacheLevel - 1; + Csselr.Bits.InD = (!DataCache && !UnifiedCache); + + Ccsidr = ReadCCSIDR (Csselr.Data); + SupportWT = (Ccsidr & (1 << 31)) ? TRUE : FALSE; + SupportWB = (Ccsidr & (1 << 30)) ? TRUE : FALSE; + + if (SupportWT && SupportWB) { + return 2; // Varies with Memory Address + } + + if (SupportWT) { + return 0; // Write Through + } + + if (SupportWB) { + return 1; // Write Back + } + + return 1; // Write Back +} + +/** Gets the CPU frequency of the specified processor. + + @param ProcessorIndex Index of the processor to get the frequency for. + + @return CPU frequency in Hz +**/ +UINTN +EFIAPI +OemGetCpuFreq ( + IN UINT8 ProcessorIndex + ) +{ + return CpuGetCurrentFreq (ProcessorIndex); +} + +/** Gets information about the specified processor and stores it in + the structures provided. + + @param ProcessorIndex Index of the processor to get the information for. + @param ProcessorStatus Processor status. + @param ProcessorCharacteristics Processor characteritics. + @param MiscProcessorData Miscellaneous processor information. + + @return TRUE on success, FALSE on failure. +**/ +BOOLEAN +EFIAPI +OemGetProcessorInformation ( + IN UINTN ProcessorIndex, + IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus, + IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics, + IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData + ) +{ + if (ProcessorIndex < 1) { + ProcessorStatus->Bits.CpuStatus = 1; // CPU enabled + ProcessorStatus->Bits.Reserved1 = 0; + ProcessorStatus->Bits.SocketPopulated = 1; + ProcessorStatus->Bits.Reserved2 = 0; + } else { + ProcessorStatus->Bits.CpuStatus = 0; // CPU disabled + ProcessorStatus->Bits.Reserved1 = 0; + ProcessorStatus->Bits.SocketPopulated = 0; + ProcessorStatus->Bits.Reserved2 = 0; + } + + ProcessorCharacteristics->ProcessorReserved1 = 0; + ProcessorCharacteristics->ProcessorUnknown = 0; + ProcessorCharacteristics->Processor64BitCapable = 1; + ProcessorCharacteristics->ProcessorMultiCore = 1; + ProcessorCharacteristics->ProcessorHardwareThread = 0; + ProcessorCharacteristics->ProcessorExecuteProtection = 1; + ProcessorCharacteristics->ProcessorEnhancedVirtualization = 1; + ProcessorCharacteristics->ProcessorPowerPerformanceCtrl = 1; + ProcessorCharacteristics->Processor128BitCapable = 0; + ProcessorCharacteristics->ProcessorReserved2 = 0; + + MiscProcessorData->Voltage = CpuGetVoltage (ProcessorIndex); + MiscProcessorData->CurrentSpeed = CpuGetCurrentFreq (ProcessorIndex); + MiscProcessorData->MaxSpeed = CpuGetMaxFreq (ProcessorIndex); + MiscProcessorData->CoreCount = GetMaximumNumberOfCores (); + MiscProcessorData->ThreadCount = GetMaximumNumberOfCores (); + MiscProcessorData->CoresEnabled = GetNumberOfActiveCoresPerSocket (ProcessorIndex); + + return TRUE; +} + +/** Gets information about the cache at the specified cache level. + + @param ProcessorIndex The processor to get information for. + @param CacheLevel The cache level to get information for. + @param DataCache Whether the cache is a data cache. + @param UnifiedCache Whether the cache is a unified cache. + @param SmbiosCacheTable The SMBIOS Type7 cache information structure. + + @return TRUE on success, FALSE on failure. +**/ +BOOLEAN +EFIAPI +OemGetCacheInformation ( + IN UINT8 ProcessorIndex, + IN UINT8 CacheLevel, + IN BOOLEAN DataCache, + IN BOOLEAN UnifiedCache, + IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable + ) +{ + UINT16 CacheSize16; + UINT32 CacheSize32; + UINT64 CacheSize64; + UINT8 Granularity32; + + SmbiosCacheTable->CacheConfiguration = CacheLevel - 1; + SmbiosCacheTable->CacheConfiguration |= (1 << 7); // Enable + SmbiosCacheTable->CacheConfiguration |= (GetCacheConfig (CacheLevel, DataCache, UnifiedCache) << 8); + + SmbiosCacheTable->SupportedSRAMType.Unknown = 0; + SmbiosCacheTable->SupportedSRAMType.Synchronous = 1; + SmbiosCacheTable->CurrentSRAMType.Unknown = 0; + SmbiosCacheTable->CurrentSRAMType.Synchronous = 1; + + if (CacheLevel == CpuCacheL1) { + SmbiosCacheTable->ErrorCorrectionType = CacheErrorParity; + } else { + SmbiosCacheTable->ErrorCorrectionType = CacheErrorSingleBit; + } + + // Cache Size + CacheSize16 = SmbiosCacheTable->MaximumCacheSize; + CacheSize32 = SmbiosCacheTable->MaximumCacheSize2; + + Granularity32 = CacheSize32 >> 31; + if (Granularity32 == 0) { + CacheSize64 = CacheSize32; + } else { + CacheSize64 = (CacheSize32 & (~BIT31)) * 64; + } + + CacheSize64 *= GetNumberOfActiveCoresPerSocket (ProcessorIndex); + if (CacheSize64 < MAX_INT16) { + CacheSize16 = CacheSize64; + CacheSize32 = CacheSize16; + } else if ((CacheSize64 / 64) < MAX_INT16) { + CacheSize16 = (UINT16)(BIT15 | (CacheSize64 / 64)); + CacheSize32 = (UINT32)(BIT31 | (CacheSize64 / 64)); + } else { + if ((CacheSize64 / 1024) <= 2047) { + CacheSize32 = CacheSize64; + } else { + CacheSize32 = (UINT32)(BIT31 | (CacheSize64 / 64)); + } + + CacheSize16 = 0xFFFF; + } + + SmbiosCacheTable->MaximumCacheSize = CacheSize16; + SmbiosCacheTable->InstalledSize = CacheSize16; + SmbiosCacheTable->MaximumCacheSize2 = CacheSize32; + SmbiosCacheTable->InstalledSize2 = CacheSize32; + + return TRUE; +} + +/** Gets the maximum number of processors supported by the platform. + + @return The maximum number of processors. +**/ +UINT8 +EFIAPI +OemGetMaxProcessors ( + VOID + ) +{ + return 1; +} + +/** Gets the type of chassis for the system. + + @retval The type of the chassis. +**/ +MISC_CHASSIS_TYPE +EFIAPI +OemGetChassisType ( + VOID + ) +{ + return MiscChassisTypeRackMountChassis; +} + +/** Returns whether the specified processor is present or not. + + @param ProcessIndex The processor index to check. + + @return TRUE is the processor is present, FALSE otherwise. +**/ +BOOLEAN +EFIAPI +OemIsProcessorPresent ( + IN UINTN ProcessorIndex + ) +{ + // + // The framework always checks the presence of the processor before retrieving + // the processor information such as part number, serial number. This caches + // the processor index for subsequent use in the OemUpdateSmbiosInfo(). + // + mProcessorIndex = ProcessorIndex; + + // + // Platform only supports 2 sockets: Master and Slave. + // The master socket is always online. + // + if (ProcessorIndex == 0) { + return TRUE; + } + + return FALSE; +} + +/** + Update the firmware version in SMBIOS Type 0. + This is the combination of UEFI and Ampere system firmware version. + +**/ +VOID +UpdateFirmwareVersionString ( + OUT CHAR16 *Version + ) +{ + UINT8 UnicodeStrLen; + UINT8 FirmwareVersionStrLen; + UINT8 FirmwareVersionStrSize; + UINT8 *ScpVersion; + UINT8 *ScpBuild; + CHAR16 UnicodeStr[SMBIOS_STRING_MAX_LENGTH * sizeof (CHAR16)]; + CHAR16 *FirmwareVersionPcdPtr; + + FirmwareVersionStrLen = 0; + ZeroMem (UnicodeStr, sizeof (UnicodeStr)); + FirmwareVersionPcdPtr = (CHAR16 *)FixedPcdGetPtr (PcdFirmwareVersionString); + FirmwareVersionStrSize = SMBIOS_STRING_MAX_LENGTH * sizeof (CHAR16); + + // + // Format of PcdFirmwareVersionString is + // "(MAJOR_VER).(MINOR_VER).(BUILD) Build YYYY.MM.DD", we only need + // "(MAJOR_VER).(MINOR_VER).(BUILD)" showed in BIOS version. Using + // space character to determine this string. Another case uses null + // character to end while loop. + // + while (*FirmwareVersionPcdPtr != ' ' && *FirmwareVersionPcdPtr != '\0') { + FirmwareVersionStrLen++; + FirmwareVersionPcdPtr++; + } + + FirmwareVersionPcdPtr = (CHAR16 *)FixedPcdGetPtr (PcdFirmwareVersionString); + UnicodeStrLen = FirmwareVersionStrLen * sizeof (CHAR16); + CopyMem (UnicodeStr, FirmwareVersionPcdPtr, UnicodeStrLen); + + GetScpVersion (&ScpVersion); + GetScpBuild (&ScpBuild); + if ((ScpVersion == NULL) || (ScpBuild == NULL)) { + DEBUG (( + DEBUG_ERROR, + "%a:%d: Fail to get SMpro/PMpro information\n", + __func__, + __LINE__ + )); + UnicodeSPrint ( + Version, + FirmwareVersionStrSize, + L"TianoCore %.*s (SYS: 0.00.00000000)", + FirmwareVersionStrLen, + (UINT16 *)UnicodeStr + ); + } else { + UnicodeSPrint ( + Version, + FirmwareVersionStrSize, + L"TianoCore %.*s (SYS: %a.%a)", + FirmwareVersionStrLen, + (UINT16 *)UnicodeStr, + ScpVersion, + ScpBuild + ); + } +} + +/** Updates the HII string for the specified field. + + @param HiiHandle The HII handle. + @param TokenToUpdate The string to update. + @param Field The field to get information about. +**/ +VOID +EFIAPI +OemUpdateSmbiosInfo ( + IN EFI_HII_HANDLE HiiHandle, + IN EFI_STRING_ID TokenToUpdate, + IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field + ) +{ + EFI_STRING UnicodeString; + UINT8 StringLength; + CHAR8 *AsciiString; + UINT32 *Ecid; + + StringLength = SMBIOS_STRING_MAX_LENGTH * sizeof (CHAR16); + UnicodeString = AllocatePool (StringLength); + if (UnicodeString == NULL) { + DEBUG (( + DEBUG_ERROR, + "%a:%d: There is not enough memory remaining to satisfy the request\n", + __func__, + __LINE__ + )); + + goto Exit; + } + + switch (Field) { + case ProductNameType01: + AsciiString = IpmiFruInfoGet (FruProductName); + if (AsciiString != NULL) { + StringLength = AsciiStrLen (AsciiString) + 1; + AsciiStrToUnicodeStrS (AsciiString, UnicodeString, StringLength); + } + + break; + + case SystemManufacturerType01: + AsciiString = IpmiFruInfoGet (FruProductManufacturerName); + DEBUG ((DEBUG_INFO, "%a: Product Manufacturer: %a\n", __func__, AsciiString)); + if (AsciiStrCmp (AsciiString, PLACEHOLDER_SMBIOS_STRING) == 0) { + AsciiString = IpmiFruInfoGet (FruBoardManufacturerName); + DEBUG ((DEBUG_INFO, "%a: (2) Product Manufacturer: %a\n", __func__, AsciiString)); + } + if (AsciiString != NULL) { + StringLength = AsciiStrLen (AsciiString) + 1; + AsciiStrToUnicodeStrS (AsciiString, UnicodeString, StringLength); + } + + break; + + case VersionType01: + AsciiString = IpmiFruInfoGet (FruProductVersion); + if (AsciiString != NULL) { + StringLength = AsciiStrLen (AsciiString) + 1; + AsciiStrToUnicodeStrS (AsciiString, UnicodeString, StringLength); + } + + break; + + case SerialNumType01: + AsciiString = IpmiFruInfoGet (FruProductSerialNumber); + DEBUG ((DEBUG_INFO, "%a: Product Serial: %a\n", __func__, AsciiString)); + if (AsciiStrCmp (AsciiString, PLACEHOLDER_SMBIOS_STRING) == 0) { + AsciiString = IpmiFruInfoGet (FruBoardSerialNumber); + DEBUG ((DEBUG_INFO, "%a: (2) Product Serial: %a\n", __func__, AsciiString)); + } + if (AsciiString != NULL) { + StringLength = AsciiStrLen (AsciiString) + 1; + AsciiStrToUnicodeStrS (AsciiString, UnicodeString, StringLength); + } + + break; + + case SkuNumberType01: + AsciiString = IpmiFruInfoGet (FruProductExtra); + if (AsciiString != NULL) { + StringLength = AsciiStrLen (AsciiString) + 1; + AsciiStrToUnicodeStrS (AsciiString, UnicodeString, StringLength); + } + + break; + + case FamilyType01: + UnicodeSPrint ( + UnicodeString, + StringLength, + IsAc01Processor () ? L"Altra\0" : L"Altra Max\0" + ); + + break; + + case ProductNameType02: + AsciiString = IpmiFruInfoGet (FruBoardProductName); + if (AsciiString != NULL) { + StringLength = AsciiStrLen (AsciiString) + 1; + AsciiStrToUnicodeStrS (AsciiString, UnicodeString, StringLength); + } + + break; + + case AssetTagType02: + UnicodeSPrint ( + UnicodeString, + StringLength, + L"Not Set" + ); + + break; + + case VersionType02: + AsciiString = IpmiFruInfoGet (FruBoardPartNumber); + if (AsciiString != NULL) { + StringLength = AsciiStrLen (AsciiString) + 1; + AsciiStrToUnicodeStrS (AsciiString, UnicodeString, StringLength); + } + + break; + + case SerialNumberType02: + AsciiString = IpmiFruInfoGet (FruBoardSerialNumber); + if (AsciiString != NULL) { + StringLength = AsciiStrLen (AsciiString) + 1; + AsciiStrToUnicodeStrS (AsciiString, UnicodeString, StringLength); + } + + break; + + case BoardManufacturerType02: + AsciiString = IpmiFruInfoGet (FruBoardManufacturerName); + if (AsciiString != NULL) { + StringLength = AsciiStrLen (AsciiString) + 1; + AsciiStrToUnicodeStrS (AsciiString, UnicodeString, StringLength); + } + + break; + + case ChassisLocationType02: + UnicodeSPrint ( + UnicodeString, + StringLength, + L"Base of Chassis" + ); + + break; + + case SerialNumberType03: + AsciiString = IpmiFruInfoGet (FruChassisSerialNumber); + if (AsciiStrCmp (AsciiString, PLACEHOLDER_SMBIOS_STRING) == 0) { + AsciiString = IpmiFruInfoGet (FruBoardSerialNumber); + } + if (AsciiString != NULL) { + StringLength = AsciiStrLen (AsciiString) + 1; + AsciiStrToUnicodeStrS (AsciiString, UnicodeString, StringLength); + } + + break; + + case VersionType03: + AsciiString = IpmiFruInfoGet (FruChassisPartNumber); + if (AsciiString != NULL) { + StringLength = AsciiStrLen (AsciiString) + 1; + AsciiStrToUnicodeStrS (AsciiString, UnicodeString, StringLength); + } + + break; + + case ManufacturerType03: + AsciiString = IpmiFruInfoGet (FruBoardManufacturerName); + if (AsciiString != NULL) { + StringLength = AsciiStrLen (AsciiString) + 1; + AsciiStrToUnicodeStrS (AsciiString, UnicodeString, StringLength); + } + + break; + + case AssetTagType03: + AsciiString = IpmiFruInfoGet (FruProductAssetTag); + if (AsciiString != NULL) { + StringLength = AsciiStrLen (AsciiString) + 1; + AsciiStrToUnicodeStrS (AsciiString, UnicodeString, StringLength); + } + + break; + + case SkuNumberType03: + AsciiString = IpmiFruInfoGet (FruChassisExtra); + if (AsciiString != NULL) { + StringLength = AsciiStrLen (AsciiString) + 1; + AsciiStrToUnicodeStrS (AsciiString, UnicodeString, StringLength); + } + + break; + + case ProcessorVersionType04: + if (IsAc01Processor ()) { + UnicodeSPrint ( + UnicodeString, + StringLength, + PROCESSOR_VERSION_ALTRA + ); + } else { + UnicodeSPrint ( + UnicodeString, + StringLength, + PROCESSOR_VERSION_ALTRA_MAX + ); + } + + break; + + case ProcessorSerialNumType04: + CpuGetEcid (mProcessorIndex, &Ecid); + UnicodeSPrint ( + UnicodeString, + StringLength, + L"%08X%08X%08X%08X", + Ecid[0], + Ecid[1], + Ecid[2], + Ecid[3] + ); + + break; + + case ProcessorPartNumType04: + if (IsAc01Processor ()) { + UnicodeSPrint ( + UnicodeString, + StringLength, + L"Q%02d-%02X", + GetSkuMaxCore (mProcessorIndex), + GetSkuMaxTurbo (mProcessorIndex) + ); + } else { + UnicodeSPrint ( + UnicodeString, + StringLength, + L"M%02d-%02X", + GetSkuMaxCore (mProcessorIndex), + GetSkuMaxTurbo (mProcessorIndex) + ); + } + + break; + + case BiosVersionType00: + UpdateFirmwareVersionString (UnicodeString); + break; + + default: + UnicodeSPrint ( + UnicodeString, + StringLength, + L"Not Specified" + ); + } + + // Update string value for respective token. + HiiSetString (HiiHandle, TokenToUpdate, UnicodeString, NULL); + +Exit: + FreePool (UnicodeString); +} + +/** Fetches the Type 32 boot information status. + + @return Boot status. +**/ +MISC_BOOT_INFORMATION_STATUS_DATA_TYPE +EFIAPI +OemGetBootStatus ( + VOID + ) +{ + return BootInformationStatusNoError; +} + +/** Fetches the chassis status when it was last booted. + + @return Chassis status. +**/ +MISC_CHASSIS_STATE +EFIAPI +OemGetChassisBootupState ( + VOID + ) +{ + return ChassisStateSafe; +} + +/** Fetches the chassis power supply/supplies status when last booted. + + @return Chassis power supply/supplies status. +**/ +MISC_CHASSIS_STATE +EFIAPI +OemGetChassisPowerSupplyState ( + VOID + ) +{ + return ChassisStateSafe; +} + +/** Fetches the chassis thermal status when last booted. + + @return Chassis thermal status. +**/ +MISC_CHASSIS_STATE +EFIAPI +OemGetChassisThermalState ( + VOID + ) +{ + return ChassisStateSafe; +} + +/** Fetches the chassis security status when last booted. + + @return Chassis security status. +**/ +MISC_CHASSIS_SECURITY_STATE +EFIAPI +OemGetChassisSecurityStatus ( + VOID + ) +{ + return ChassisSecurityStatusNone; +} + +/** Fetches the chassis height in RMUs (Rack Mount Units). + + @return The height of the chassis. +**/ +UINT8 +EFIAPI +OemGetChassisHeight ( + VOID + ) +{ + return 1U; +} + +/** Fetches the number of power cords. + + @return The number of power cords. +**/ +UINT8 +EFIAPI +OemGetChassisNumPowerCords ( + VOID + ) +{ + return 1; +} + +/** Fetches the BIOS release. + + @return The BIOS release. +**/ +UINT16 +EFIAPI +OemGetBiosRelease ( + VOID + ) +{ + UINT16 BiosRelease; + + BiosRelease = (UINT16)(((PcdGet8 (PcdSmbiosTables0MajorVersion)) << 8) + | PcdGet8 (PcdSmbiosTables0MinorVersion)); + + return BiosRelease; +} + +/** + Fetches the embedded controller firmware release. + + @return UINT16 The embedded controller firmware release. +**/ +UINT16 +EFIAPI +OemGetEmbeddedControllerFirmwareRelease ( + VOID + ) +{ + CHAR8 AsciiScpVer[SCP_VERSION_STRING_MAX_LENGTH]; + UINT8 *ScpVer = NULL; + UINT8 Index; + UINT16 FirmwareRelease; + + GetScpVersion (&ScpVer); + if (ScpVer == NULL) { + DEBUG (( + DEBUG_ERROR, + "%a:%d: Fail to get SMpro/PMpro information\n", + __func__, + __LINE__ + )); + + return 0xFFFF; + } + + CopyMem ((VOID *)AsciiScpVer, (VOID *)ScpVer, AsciiStrLen ((CHAR8 *)ScpVer)); + /* The AsciiVersion is formated as "major.minor" */ + for (Index = 0; Index < (UINTN)AsciiStrLen (AsciiScpVer); Index++) { + if (AsciiScpVer[Index] == '.') { + AsciiScpVer[Index] = '\0'; + break; + } + } + + FirmwareRelease = ((UINT8)AsciiStrDecimalToUintn (AsciiScpVer) << 8) + + (UINT8)AsciiStrDecimalToUintn (AsciiScpVer + Index + 1); + + return FirmwareRelease; +} + +VOID +ConvertIpmiGuidToSmbiosGuid ( + IN OUT UINT8 *SmbiosGuid, + IN UINT8 *IpmiGuid + ) +{ + UINT8 Index; + + // + // Node and clock seq field within the GUID + // are stored most-significant byte first in + // SMBIOS spec but LSB first in IPMI spec + // ->change its offset and byte-order + // + for (Index = 0; Index < 8; Index++) { + *(SmbiosGuid + 15 - Index) = *(IpmiGuid + Index); + } + + // + // Time high, time mid and time low field + // are stored LSB first in both IPMI spec + // and SMBIOS spec + // ->only need change offset + // + *(SmbiosGuid + 6) = *(IpmiGuid + 8); + *(SmbiosGuid + 7) = *(IpmiGuid + 9); + *(SmbiosGuid + 4) = *(IpmiGuid + 10); + *(SmbiosGuid + 5) = *(IpmiGuid + 11); + *SmbiosGuid = *(IpmiGuid + 12); + *(SmbiosGuid + 1) = *(IpmiGuid + 13); + *(SmbiosGuid + 2) = *(IpmiGuid + 14); + *(SmbiosGuid + 3) = *(IpmiGuid + 15); +} + +/** + Fetches the system UUID. + + @param[out] SystemUuid The pointer to the buffer to store the System UUID. +**/ +VOID +EFIAPI +OemGetSystemUuid ( + OUT GUID *SystemUuid + ) +{ + EFI_STATUS Status; + EFI_GUID Uuid; + + if (SystemUuid == NULL) { + return; + } + + Status = IpmiGetSystemUuid (&Uuid); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a %d Can not get System UUID!\n", __func__, __LINE__)); + } + + ConvertIpmiGuidToSmbiosGuid ((UINT8 *)SystemUuid, (UINT8 *)&Uuid); +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/OemMiscLib.inf b/Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/OemMiscLib.inf new file mode 100644 index 00000000000..c9a76e7e112 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Library/OemMiscLib/OemMiscLib.inf @@ -0,0 +1,49 @@ +#/** @file +# OemMiscLib.inf +# +# Copyright (c) 2021 - 2024, Ampere Computing LLC. All rights reserved. +# Copyright (c) 2021, NUVIA Inc. All rights reserved. +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = OemMiscLib + FILE_GUID = A84551A1-CF71-4CC4-A63B-B087048A87AD + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = OemMiscLib + +[Sources.common] + IpmiFruInfo.h + IpmiFruInfo.c + OemMiscLib.c + +[Packages] + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec + +[LibraryClasses] + AmpereCpuLib + ArmLib + BaseLib + BaseMemoryLib + DebugLib + IpmiCommandLib + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gAmpereTokenSpaceGuid.PcdSmbiosTables0MajorVersion + gAmpereTokenSpaceGuid.PcdSmbiosTables0MinorVersion + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + +[Depex] + TRUE diff --git a/Platform/ASRockRack/AltraBoardPkg/Library/PlatformBmcReadyLib/PlatformBmcReadyLib.c b/Platform/ASRockRack/AltraBoardPkg/Library/PlatformBmcReadyLib/PlatformBmcReadyLib.c new file mode 100644 index 00000000000..60329f6a655 --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Library/PlatformBmcReadyLib/PlatformBmcReadyLib.c @@ -0,0 +1,26 @@ +/** @file + + Copyright (c) 2024, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + This function checks whether BMC is ready for transaction or not. + + @retval TRUE The BMC is ready. + @retval FALSE The BMC is not ready. + +**/ +BOOLEAN +EFIAPI +PlatformBmcReady ( + VOID + ) +{ + // + // This platform doesn't have a BMC READY GPIO line. + // + return TRUE; +} diff --git a/Platform/ASRockRack/AltraBoardPkg/Library/PlatformBmcReadyLib/PlatformBmcReadyLib.inf b/Platform/ASRockRack/AltraBoardPkg/Library/PlatformBmcReadyLib/PlatformBmcReadyLib.inf new file mode 100755 index 00000000000..21e2178324e --- /dev/null +++ b/Platform/ASRockRack/AltraBoardPkg/Library/PlatformBmcReadyLib/PlatformBmcReadyLib.inf @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2024, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = PlatformBmcReadyLib + FILE_GUID = D7D58480-96D5-4820-AC2D-472F4E0B9903 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformBmcReadyLib + +[Sources] + PlatformBmcReadyLib.c From 73b18a39f041ea5274178f8ce8e6ed15e3462601 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Tue, 11 Feb 2025 09:04:11 -0700 Subject: [PATCH 31/35] Silicon/Ampere: Fix GetNumberOfSupportedSockets GetNumberOfSupportedSockets currently always returns 2 because there's a fixed number of elements in the array. Instead, check if SkuMaxLink2pSpeed is non-zero, in which case there are 2 sockets. Signed-off-by: Rebecca Cran --- .../Library/AmpereCpuLib/AmpereCpuLibCommon.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLibCommon.c b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLibCommon.c index a30bb986611..3e9b3f55131 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLibCommon.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLibCommon.c @@ -446,6 +446,7 @@ GetNumberOfSupportedSockets ( ) { PLATFORM_INFO_HOB *PlatformHob; + UINT8 NumSockets; PlatformHob = GetPlatformHob (); if (PlatformHob == NULL) { @@ -455,7 +456,13 @@ GetNumberOfSupportedSockets ( return 1; } - return (sizeof (PlatformHob->ClusterEn) / sizeof (PLATFORM_CLUSTER_EN)); + if (PlatformHob->SkuMaxLink2pSpeed != 0) { + NumSockets = 2; + } else { + NumSockets = 1; + } + + return NumSockets; } /** From 8b8c18b0bc1cf7fd51dfd3e9f83bc08a3e0dcd62 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Tue, 11 Feb 2025 09:04:17 -0700 Subject: [PATCH 32/35] Silicon/Ampere: Check if INCLUDE_TFTP_COMMAND is TRUE Instead of checking if INCLUDE_TFTP_COMMAND is _defined_, check whether it's TRUE. This prevents it erronenously being included if it's set to FALSE. Signed-off-by: Rebecca Cran --- Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc index a80b63403bc..3968db3ddc3 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -860,7 +860,7 @@ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 } -!ifdef $(INCLUDE_TFTP_COMMAND) +!if $(INCLUDE_TFTP_COMMAND) == TRUE ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf { gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE From a4d9f2974a2c1b46911bd4f9948492b9581abcda Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Tue, 11 Feb 2025 09:04:22 -0700 Subject: [PATCH 33/35] Ampere: Rename SECURE_BOOT_ENABLE to UEFI_SECURE_BOOT_ENABLE Since there are two types of Secure Boot in modern platforms - one which secures from UEFI onwards, and one which secures the entire SoC boot process from a root of trust in ROM, rename 'SECURE_BOOT_ENABLE' to 'UEFI_SECURE_BOOT_ENABLE' to differentiate it from the latter. The SoC Secure Boot is enabled via a separate, different process. Signed-off-by: Rebecca Cran --- .../ASRockRack/Altra1L2QPkg/Altra1L2Q.dsc | 8 ++-- .../ASRockRack/Altra1L2QPkg/Altra1L2Q.fdf | 4 +- Platform/Ampere/JadePkg/Jade.dsc | 6 +-- Platform/Ampere/JadePkg/Jade.fdf | 4 +- Platform/Ampere/buildfw.sh | 37 ++++++++++--------- .../AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 8 ++-- 6 files changed, 34 insertions(+), 33 deletions(-) diff --git a/Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.dsc b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.dsc index ef01771e1be..00630a9b23a 100644 --- a/Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.dsc +++ b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.dsc @@ -59,7 +59,7 @@ DEFINE FIRMWARE_VER_HEX = 0x00010100 DEFINE CAPSULE_ENABLE = TRUE DEFINE INCLUDE_TFA_FW = TRUE - DEFINE SECURE_BOOT_ENABLE = TRUE + DEFINE UEFI_SECURE_BOOT_ENABLE = TRUE DEFINE TPM2_ENABLE = TRUE DEFINE SHELL_ENABLE = TRUE DEFINE INCLUDE_TFTP_COMMAND = TRUE @@ -186,7 +186,7 @@ # upgrade experience (e.g. a progress bar). gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleOnDiskSupport|FALSE -!if $(SECURE_BOOT_ENABLE) == TRUE +!if $(UEFI_SECURE_BOOT_ENABLE) == TRUE gEfiSecurityPkgTokenSpaceGuid.PcdRsa2048Sha256PublicKeyBuffer|{0} !include Platform/ASRockRack/Altra1L2QPkg/root.cer.gEfiSecurityPkgTokenSpaceGuid.PcdPkcs7CertBuffer.inc !endif @@ -209,7 +209,7 @@ # point only, for entry point versions >= 3.0. gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 -!if $(SECURE_BOOT_ENABLE) == TRUE +!if $(UEFI_SECURE_BOOT_ENABLE) == TRUE # Override the default values from SecurityPkg to ensure images # from all sources are verified in secure boot gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 @@ -230,7 +230,7 @@ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 -!if $(SECURE_BOOT_ENABLE) == TRUE +!if $(UEFI_SECURE_BOOT_ENABLE) == TRUE gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|600 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|400 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1500 diff --git a/Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.fdf b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.fdf index cf0968119ea..e57af98e2c9 100644 --- a/Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.fdf +++ b/Platform/ASRockRack/Altra1L2QPkg/Altra1L2Q.fdf @@ -88,7 +88,7 @@ DATA = { # Blockmap[1]: End 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ## This is the VARIABLE_STORE_HEADER - # It is compatible with SECURE_BOOT_ENABLE == FALSE as well. + # It is compatible with UEFI_SECURE_BOOT_ENABLE == FALSE as well. # Signature: gEfiAuthenticatedVariableGuid = # { 0xaaf32c78, 0x947b, 0x439a, # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} @@ -250,7 +250,7 @@ APRIORI DXE { INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf -!if $(SECURE_BOOT_ENABLE) == TRUE +!if $(UEFI_SECURE_BOOT_ENABLE) == TRUE INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc index 2c4fd5c3dfb..79c4be0ff33 100644 --- a/Platform/Ampere/JadePkg/Jade.dsc +++ b/Platform/Ampere/JadePkg/Jade.dsc @@ -56,7 +56,7 @@ DEFINE FIRMWARE_VER_HEX = 0x00010100 DEFINE CAPSULE_ENABLE = TRUE DEFINE INCLUDE_TFA_FW = TRUE - DEFINE SECURE_BOOT_ENABLE = TRUE + DEFINE UEFI_SECURE_BOOT_ENABLE = TRUE DEFINE TPM2_ENABLE = TRUE DEFINE SHELL_ENABLE = TRUE DEFINE INCLUDE_TFTP_COMMAND = TRUE @@ -200,7 +200,7 @@ # upgrade experience (e.g. a progress bar). gEfiMdeModulePkgTokenSpaceGuid.PcdCapsuleOnDiskSupport|FALSE -!if $(SECURE_BOOT_ENABLE) == TRUE +!if $(UEFI_SECURE_BOOT_ENABLE) == TRUE gEfiSecurityPkgTokenSpaceGuid.PcdRsa2048Sha256PublicKeyBuffer|{0} !include Platform/Ampere/JadePkg/root.cer.gEfiSecurityPkgTokenSpaceGuid.PcdPkcs7CertBuffer.inc !endif @@ -221,7 +221,7 @@ # point only, for entry point versions >= 3.0. gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 -!if $(SECURE_BOOT_ENABLE) == TRUE +!if $(UEFI_SECURE_BOOT_ENABLE) == TRUE # Override the default values from SecurityPkg to ensure images # from all sources are verified in secure boot gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf index f9c794a467a..b8326ba34f1 100644 --- a/Platform/Ampere/JadePkg/Jade.fdf +++ b/Platform/Ampere/JadePkg/Jade.fdf @@ -82,7 +82,7 @@ DATA = { # Blockmap[1]: End 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ## This is the VARIABLE_STORE_HEADER - # It is compatible with SECURE_BOOT_ENABLE == FALSE as well. + # It is compatible with UEFI_SECURE_BOOT_ENABLE == FALSE as well. # Signature: gEfiAuthenticatedVariableGuid = # { 0xaaf32c78, 0x947b, 0x439a, # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} @@ -240,7 +240,7 @@ APRIORI DXE { INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf -!if $(SECURE_BOOT_ENABLE) == TRUE +!if $(UEFI_SECURE_BOOT_ENABLE) == TRUE !include ArmPlatformPkg/SecureBootDefaultKeys.fdf.inc INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf diff --git a/Platform/Ampere/buildfw.sh b/Platform/Ampere/buildfw.sh index 0ba80d942e4..081f49d43a5 100755 --- a/Platform/Ampere/buildfw.sh +++ b/Platform/Ampere/buildfw.sh @@ -283,24 +283,25 @@ if [ -f "${TFA_SLIM}" ]; then cp -vf "${TFA_SLIM}" "Build/${BOARD_NAME}/altra_atf.slim" fi -build -a AARCH64 -t ${TOOLCHAIN} -b ${BLDTYPE} -n ${BUILD_THREADS} \ - -D FIRMWARE_VER_FULL="${VER} TF-A ${TFA_VERSION}" \ - -D FIRMWARE_VER="${VER}" \ - -D FIRMWARE_VER_HEX="${VER_HEX}" \ - -D MAJOR_VER=${MAJOR_VER} -D MINOR_VER=${MINOR_VER} \ - -D SECURE_BOOT_ENABLE=${EDK2_SECURE_BOOT_ENABLE} \ - -D NETWORK_ENABLE=${EDK2_NETWORK_ENABLE} \ - -D INCLUDE_TFTP_COMMAND=${EDK2_INCLUDE_TFTP_COMMAND} \ - -D NETWORK_IP6_ENABLE=${EDK2_NETWORK_IP6_ENABLE} \ - -D NETWORK_ALLOW_HTTP_CONNECTIONS=${EDK2_NETWORK_ALLOW_HTTP_CONNECTIONS} \ - -D NETWORK_TLS_ENABLE=${EDK2_NETWORK_TLS_ENABLE} \ - -D REDFISH_ENABLE=${EDK2_REDFISH_ENABLE} \ - -D PERFORMANCE_MEASUREMENT_ENABLE=${EDK2_PERFORMANCE_MEASUREMENT_ENABLE} \ - -D TPM2_ENABLE=${EDK2_TPM2_ENABLE} \ - -D HEAP_GUARD_ENABLE=${EDK2_HEAP_GUARD_ENABLE} \ - -D X86_EMULATOR_ENABLE=${EDK2_X86_EMULATOR_ENABLE} \ - -D SHELL_ENABLE=${EDK2_SHELL_ENABLE} \ - -Y COMPILE_INFO -y BuildReport.log \ +# shellcheck disable=SC2086 +build -a AARCH64 -t ${TOOLCHAIN} -b ${BLDTYPE} -n ${BUILD_THREADS} \ + -D FIRMWARE_VER_FULL="${VER} TF-A ${TFA_VERSION}" \ + -D FIRMWARE_VER="${VER}" \ + -D FIRMWARE_VER_HEX="${VER_HEX}" \ + -D MAJOR_VER=${MAJOR_VER} -D MINOR_VER=${MINOR_VER} \ + -D UEFI_SECURE_BOOT_ENABLE=${EDK2_SECURE_BOOT_ENABLE} \ + -D NETWORK_ENABLE=${EDK2_NETWORK_ENABLE} \ + -D INCLUDE_TFTP_COMMAND=${EDK2_INCLUDE_TFTP_COMMAND} \ + -D NETWORK_IP6_ENABLE=${EDK2_NETWORK_IP6_ENABLE} \ + -D NETWORK_ALLOW_HTTP_CONNECTIONS=${EDK2_NETWORK_ALLOW_HTTP_CONNECTIONS} \ + -D NETWORK_TLS_ENABLE=${EDK2_NETWORK_TLS_ENABLE} \ + -D REDFISH_ENABLE=${EDK2_REDFISH_ENABLE} \ + -D PERFORMANCE_MEASUREMENT_ENABLE=${EDK2_PERFORMANCE_MEASUREMENT_ENABLE} \ + -D TPM2_ENABLE=${EDK2_TPM2_ENABLE} \ + -D HEAP_GUARD_ENABLE=${EDK2_HEAP_GUARD_ENABLE} \ + -D X86_EMULATOR_ENABLE=${EDK2_X86_EMULATOR_ENABLE} \ + -D SHELL_ENABLE=${EDK2_SHELL_ENABLE} \ + -Y COMPILE_INFO -y BuildReport.log \ -p Platform/${MANUFACTURER}/${BOARD_NAME}Pkg/${BOARD_NAME}${LINUXBOOT}.dsc \ ${EXTRA_BUILD_FLAGS} diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc index 3968db3ddc3..d3a9755a996 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -136,7 +136,7 @@ # # Secure Boot dependencies # -!if $(SECURE_BOOT_ENABLE) == TRUE +!if $(UEFI_SECURE_BOOT_ENABLE) == TRUE IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf @@ -299,7 +299,7 @@ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf !endif ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf -!if $(SECURE_BOOT_ENABLE) == TRUE +!if $(UEFI_SECURE_BOOT_ENABLE) == TRUE BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf !endif DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf @@ -660,7 +660,7 @@ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { -!if $(SECURE_BOOT_ENABLE) == TRUE +!if $(UEFI_SECURE_BOOT_ENABLE) == TRUE NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf !endif !if $(TPM2_ENABLE) == TRUE @@ -668,7 +668,7 @@ !endif } -!if $(SECURE_BOOT_ENABLE) == TRUE +!if $(UEFI_SECURE_BOOT_ENABLE) == TRUE SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf SecurityPkg/EnrollFromDefaultKeysApp/EnrollFromDefaultKeysApp.inf SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf From 4c71b68783906c08a84731079365404e99d85aab Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Tue, 11 Feb 2025 09:04:28 -0700 Subject: [PATCH 34/35] Silicon/Ampere: sync up with edk2 ArmPkg changes Catch to with changes in edk2 ArmPkg: delete ArmGicArchLib instance and add instances of ArmFfaLib and ArmSvcLib. Signed-off-by: Rebecca Cran --- Silicon/Ampere/AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc | 1 - Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc index 288811bbb07..1b05500dbd1 100755 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraLinuxBootPkg.dsc.inc @@ -129,7 +129,6 @@ !if $(PERFORMANCE_MEASUREMENT_ENABLE) == TRUE PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf !endif - ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf [LibraryClasses.common.PEI_CORE] HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc index d3a9755a996..80d85d68d38 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -80,6 +80,8 @@ I2cLib|Silicon/Ampere/AmpereAltraPkg/Library/DwI2cLib/DwI2cLib.inf GpioLib|Silicon/Ampere/AmpereAltraPkg/Library/DwGpioLib/DwGpioLib.inf MmCommunicationLib|Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.inf + ArmFfaLib|ArmPkg/Library/ArmFfaLib/ArmFfaDxeLib.inf + ArmSvcLib|ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf FlashLib|Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLib.inf ManageabilityTransportHelperLib|ManageabilityPkg/Library/BaseManageabilityTransportHelperLib/BaseManageabilityTransportHelper.inf FirmwareUpdateLib|Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareUpdateLib/SystemFirmwareUpdateLib.inf From ac2900d35b803371bb29cf66c2364a2f6ac633db Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Tue, 11 Feb 2025 09:04:53 -0700 Subject: [PATCH 35/35] Platform/Ampere: List the build.conf defaults in help output To help people understand the default configuration, list configuration knobs along with their default values in the `--help` output. Signed-off-by: Rebecca Cran --- Platform/Ampere/buildfw.sh | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Platform/Ampere/buildfw.sh b/Platform/Ampere/buildfw.sh index 081f49d43a5..d0962c6eaf5 100755 --- a/Platform/Ampere/buildfw.sh +++ b/Platform/Ampere/buildfw.sh @@ -60,6 +60,19 @@ usage () { echo " DOWNLOAD_MS_SB_KEYS - force re-download of Microsoft Secure Boot KEK and DB certificates" echo " CERT_PASSWORD - password to use when generating Platform and Update Keys and certificates" echo " defaults to \"password\" if not specified." + echo "" + echo " EDK2_SECURE_BOOT_ENABLE (TRUE)" + echo " EDK2_NETWORK_ENABLE (TRUE)" + echo " EDK2_INCLUDE_TFTP_COMMAND (TRUE)" + echo " EDK2_NETWORK_IP6_ENABLE (TRUE)" + echo " EDK2_NETWORK_ALLOW_HTTP_CONNECTIONS (TRUE)" + echo " EDK2_NETWORK_TLS_ENABLE (TRUE)" + echo " EDK2_REDFISH_ENABLE (TRUE)" + echo " EDK2_PERFORMANCE_MEASUREMENT_ENABLE (FALSE)" + echo " EDK2_TPM2_ENABLE (TRUE)" + echo " EDK2_HEAP_GUARD_ENABLE (FALSE)" + echo " EDK2_X86_EMULATOR_ENABLE (TRUE)" + echo " EDK2_SHELL_ENABLE (TRUE)" exit 1 }