interfaces.md

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module pwm has the following hardware interfaces defined

• Primary Clock: clk_i
• Other Clocks: clk_core_i
• Bus Device Interfaces (TL-UL): tl
• Bus Host Interfaces (TL-UL): none
• Interrupts: none

Peripheral Pins for Chip IO

Pin name	Direction	Description
pwm[5:0]	output	Pulse output. Note that though this output is always enabled, there is a formal set of enable pins (pwm_en_o) which are required for top-level integration of comportable IPs.

Inter-Module Signals

Port Name	Package::Struct	Type	Act	Width	Description
racl_policies	top_racl_pkg::racl_policy_vec	uni	rcv	1	Incoming RACL policy vector from a racl_ctrl instance. The policy selection vector (parameter) selects the policy for each register.
racl_error	logic	uni	req	1	RACL error indication signal. If 1, the error log contains valid information.
racl_error_log	top_racl_pkg::racl_error_log	uni	req	1	RACL error log information of this module.
tl	tlul_pkg::tl	req_rsp	rsp	1

Security Alerts

Alert Name	Description
fatal_fault	This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures

Countermeasure ID	Description
PWM.BUS.INTEGRITY	End-to-end bus integrity scheme.