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SOC_W_PCM.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
# Date created = 22:35:20 November 13, 2014
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# SOC_W_PCM_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY PCM_MM
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:35:20 NOVEMBER 13, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 14.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_Y2 -to clk
set_location_assignment PIN_M23 -to reset
set_location_assignment PIN_Y7 -to sdram_wire_addr[12]
set_location_assignment PIN_AA5 -to sdram_wire_addr[11]
set_location_assignment PIN_R5 -to sdram_wire_addr[10]
set_location_assignment PIN_Y6 -to sdram_wire_addr[9]
set_location_assignment PIN_Y5 -to sdram_wire_addr[8]
set_location_assignment PIN_AA7 -to sdram_wire_addr[7]
set_location_assignment PIN_W7 -to sdram_wire_addr[6]
set_location_assignment PIN_W8 -to sdram_wire_addr[5]
set_location_assignment PIN_V5 -to sdram_wire_addr[4]
set_location_assignment PIN_P1 -to sdram_wire_addr[3]
set_location_assignment PIN_U8 -to sdram_wire_addr[2]
set_location_assignment PIN_V8 -to sdram_wire_addr[1]
set_location_assignment PIN_R6 -to sdram_wire_addr[0]
set_location_assignment PIN_R4 -to sdram_wire_ba[1]
set_location_assignment PIN_U7 -to sdram_wire_ba[0]
set_location_assignment PIN_V7 -to sdram_wire_cas_n
set_location_assignment PIN_AA6 -to sdram_wire_cke
set_location_assignment PIN_AE5 -to sdram_wire_clk
set_location_assignment PIN_T4 -to sdram_wire_cs_n
set_location_assignment PIN_U1 -to sdram_wire_dq[31]
set_location_assignment PIN_U4 -to sdram_wire_dq[30]
set_location_assignment PIN_T3 -to sdram_wire_dq[29]
set_location_assignment PIN_R3 -to sdram_wire_dq[28]
set_location_assignment PIN_R2 -to sdram_wire_dq[27]
set_location_assignment PIN_R1 -to sdram_wire_dq[26]
set_location_assignment PIN_R7 -to sdram_wire_dq[25]
set_location_assignment PIN_U5 -to sdram_wire_dq[24]
set_location_assignment PIN_L7 -to sdram_wire_dq[23]
set_location_assignment PIN_M7 -to sdram_wire_dq[22]
set_location_assignment PIN_M4 -to sdram_wire_dq[21]
set_location_assignment PIN_N4 -to sdram_wire_dq[20]
set_location_assignment PIN_N3 -to sdram_wire_dq[19]
set_location_assignment PIN_P2 -to sdram_wire_dq[18]
set_location_assignment PIN_L8 -to sdram_wire_dq[17]
set_location_assignment PIN_M8 -to sdram_wire_dq[16]
set_location_assignment PIN_AC2 -to sdram_wire_dq[15]
set_location_assignment PIN_AB3 -to sdram_wire_dq[14]
set_location_assignment PIN_AC1 -to sdram_wire_dq[13]
set_location_assignment PIN_AB2 -to sdram_wire_dq[12]
set_location_assignment PIN_AA3 -to sdram_wire_dq[11]
set_location_assignment PIN_AB1 -to sdram_wire_dq[10]
set_location_assignment PIN_Y4 -to sdram_wire_dq[9]
set_location_assignment PIN_Y3 -to sdram_wire_dq[8]
set_location_assignment PIN_U3 -to sdram_wire_dq[7]
set_location_assignment PIN_V1 -to sdram_wire_dq[6]
set_location_assignment PIN_V2 -to sdram_wire_dq[5]
set_location_assignment PIN_V3 -to sdram_wire_dq[4]
set_location_assignment PIN_W1 -to sdram_wire_dq[3]
set_location_assignment PIN_V4 -to sdram_wire_dq[2]
set_location_assignment PIN_W2 -to sdram_wire_dq[1]
set_location_assignment PIN_W3 -to sdram_wire_dq[0]
set_location_assignment PIN_N8 -to sdram_wire_dqm[3]
set_location_assignment PIN_K8 -to sdram_wire_dqm[2]
set_location_assignment PIN_W4 -to sdram_wire_dqm[1]
set_location_assignment PIN_U2 -to sdram_wire_dqm[0]
set_location_assignment PIN_U6 -to sdram_wire_ras_n
set_location_assignment PIN_V6 -to sdram_wire_we_n
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME testbench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "2000 ns" -section_id testbench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench -section_id testbench
set_global_assignment -name EDA_TEST_BENCH_FILE testbench.sv -section_id testbench
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/datapath_control.sv"
set_global_assignment -name SYSTEMVERILOG_FILE testbench.sv
set_global_assignment -name SYSTEMVERILOG_FILE PCM_MM_reg.sv
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/TSB.sv"
set_global_assignment -name SYSTEMVERILOG_FILE PCM_MM.sv
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/test_memory.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/SLC3_2.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/SLC.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/SEXT11.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/SEXT9.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/SEXT6.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/SEXT5.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/RegFile.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/RegAddrMux.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/Reg16.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/NZPreg.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/Mux4.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/Mux2.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/Mem2IO.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/ISDU.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/HexDriver.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/CPU.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "SLC3-M/ALU.sv"
set_global_assignment -name QIP_FILE nois_system/synthesis/nois_system.qip
set_global_assignment -name SYSTEMVERILOG_FILE nois_system/synthesis/SOC_W_PCM.sv
set_global_assignment -name SYSTEMVERILOG_FILE nois_system/synthesis/PCCM.sv
set_location_assignment PIN_M21 -to ctn_button
set_location_assignment PIN_Y19 -to HEX3[6]
set_location_assignment PIN_AF23 -to HEX3[5]
set_location_assignment PIN_AD24 -to HEX3[4]
set_location_assignment PIN_AA21 -to HEX3[3]
set_location_assignment PIN_AB20 -to HEX3[2]
set_location_assignment PIN_U21 -to HEX3[1]
set_location_assignment PIN_V21 -to HEX3[0]
set_location_assignment PIN_W28 -to HEX2[6]
set_location_assignment PIN_W27 -to HEX2[5]
set_location_assignment PIN_Y26 -to HEX2[4]
set_location_assignment PIN_W26 -to HEX2[3]
set_location_assignment PIN_Y25 -to HEX2[2]
set_location_assignment PIN_AA26 -to HEX2[1]
set_location_assignment PIN_AA25 -to HEX2[0]
set_location_assignment PIN_U24 -to HEX1[6]
set_location_assignment PIN_U23 -to HEX1[5]
set_location_assignment PIN_W25 -to HEX1[4]
set_location_assignment PIN_W22 -to HEX1[3]
set_location_assignment PIN_W21 -to HEX1[2]
set_location_assignment PIN_Y22 -to HEX1[1]
set_location_assignment PIN_M24 -to HEX1[0]
set_location_assignment PIN_H22 -to HEX0[6]
set_location_assignment PIN_J22 -to HEX0[5]
set_location_assignment PIN_L25 -to HEX0[4]
set_location_assignment PIN_L26 -to HEX0[3]
set_location_assignment PIN_E17 -to HEX0[2]
set_location_assignment PIN_F22 -to HEX0[1]
set_location_assignment PIN_G18 -to HEX0[0]
set_location_assignment PIN_H16 -to LED[11]
set_location_assignment PIN_J15 -to LED[10]
set_location_assignment PIN_G17 -to LED[9]
set_location_assignment PIN_J17 -to LED[8]
set_location_assignment PIN_H19 -to LED[7]
set_location_assignment PIN_J19 -to LED[6]
set_location_assignment PIN_E18 -to LED[5]
set_location_assignment PIN_F18 -to LED[4]
set_location_assignment PIN_F21 -to LED[3]
set_location_assignment PIN_E19 -to LED[2]
set_location_assignment PIN_F19 -to LED[1]
set_location_assignment PIN_G19 -to LED[0]
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top