LTSpice projects

A more modular Fluigi Codebase

S-expression data structure parser/manipulator intended for parsing and manipulating lisp program, lisp data, netlists like EDIF and KiCAD, etc.

This project showcases the design and simulation of a 7T MCPL SRAM using adiabatic logic for low-power efficiency, developed for ECL 312 at IIIT Nagpur. It compares the 6T and 7T SRAM designs in terms of power, energy, and stability, with simulations done in WinSpice and Microwind.

Visualization for Netlist

This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.

Course Assignment - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay

NetFI-3: Netlist Fault Injection system - Version 3

This is my openlane repository in which we perform synthesis of our design/module.

This guide will teach you all the basics of KiCad from schematic building to PCB design. It will also teach you how to add libraries, create your own symbols & footprints, export the drill and gerber files, and many more tips to get you started on your KiCad journey!

This repository contains a python script that converts a Boolean Expression to a .SIM file (circuit netlist description).

A few experiments using the SpyDrNet netlist library.

tile-based digital logic sandbox

Perform gate-level simulations from python

Contains VHDL netlists of basic digital circuits

SUTD 2020 50.002 Computation Structures Code Dump

Electronic PCB Programmig Language: Create an Electronic Netlist and Schematic using JavaScript and limitless automations.

MODNET (MODify NETlist): VHDL/Verilog Fault Injection system

TMR utilities for the SpyDrNet project