forked from steveicarus/iverilog
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathelab_expr.cc
6160 lines (5221 loc) · 194 KB
/
elab_expr.cc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright (c) 1999-2016 Stephen Williams ([email protected])
* Copyright CERN 2013 / Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
# include "config.h"
# include <typeinfo>
# include <cstdlib>
# include <cstring>
# include <climits>
# include "compiler.h"
# include "PPackage.h"
# include "pform.h"
# include "netlist.h"
# include "netclass.h"
# include "netenum.h"
# include "netparray.h"
# include "netvector.h"
# include "discipline.h"
# include "netmisc.h"
# include "netdarray.h"
# include "netstruct.h"
# include "netscalar.h"
# include "util.h"
# include "ivl_assert.h"
bool type_is_vectorable(ivl_variable_type_t type)
{
switch (type) {
case IVL_VT_BOOL:
case IVL_VT_LOGIC:
return true;
default:
return false;
}
}
static ivl_nature_t find_access_function(const pform_name_t&path)
{
if (path.size() != 1)
return 0;
else
return access_function_nature[peek_tail_name(path)];
}
/*
* Look at the signal to see if there is already a branch that
* connects the sig to the gnd. If there is, then return it. If not,
* return 0.
*/
static NetBranch* find_existing_implicit_branch(NetNet*sig, NetNet*gnd)
{
Nexus*nex = sig->pin(0).nexus();
for (Link*cur = nex->first_nlink() ; cur ; cur = cur->next_nlink()) {
if (cur->is_equal(sig->pin(0)))
continue;
if (cur->get_pin() != 0)
continue;
NetBranch*tmp = dynamic_cast<NetBranch*> (cur->get_obj());
if (tmp == 0)
continue;
if (tmp->name())
continue;
if (tmp->pin(1).is_linked(gnd->pin(0)))
return tmp;
}
return 0;
}
NetExpr* elaborate_rval_expr(Design*des, NetScope*scope, ivl_type_t lv_net_type,
ivl_variable_type_t lv_type, unsigned lv_width,
PExpr*expr, bool need_const, bool force_unsigned)
{
if (debug_elaborate) {
cerr << expr->get_fileline() << ": elaborate_rval_expr: "
<< "expr=" << *expr;
if (lv_net_type)
cerr << ", lv_net_type=" << *lv_net_type;
else
cerr << ", lv_net_type=<nil>";
cerr << ", lv_type=" << lv_type
<< ", lv_width=" << lv_width
<< endl;
}
int context_wid = -1;
switch (lv_type) {
case IVL_VT_DARRAY:
case IVL_VT_QUEUE:
// For these types, use a different elab_and_eval that
// uses the lv_net_type. We should eventually transition
// all the types to this new form.
if (lv_net_type)
return elab_and_eval(des, scope, expr, lv_net_type, need_const);
break;
case IVL_VT_REAL:
case IVL_VT_STRING:
break;
case IVL_VT_BOOL:
case IVL_VT_LOGIC:
context_wid = lv_width;
break;
case IVL_VT_VOID:
case IVL_VT_NO_TYPE:
ivl_assert(*expr, 0);
break;
case IVL_VT_CLASS:
cerr << expr->get_fileline() << ": sorry: "
<< "I do not know how to elaborate r-value as IVL_VT_CLASS." << endl;
des->errors += 1;
return 0;
break;
}
return elab_and_eval(des, scope, expr, context_wid, need_const,
false, lv_type, force_unsigned);
}
/*
* If the mode is UPSIZE, make sure the final expression width is at
* least integer_width, but return the calculated lossless width to
* the caller.
*/
unsigned PExpr::fix_width_(width_mode_t mode)
{
unsigned width = expr_width_;
if ((mode == UPSIZE) && type_is_vectorable(expr_type_)
&& (width < integer_width))
expr_width_ = integer_width;
return width;
}
unsigned PExpr::test_width(Design*des, NetScope*, width_mode_t&)
{
cerr << get_fileline() << ": internal error: I do not know how to"
<< " test the width of this expression. " << endl;
cerr << get_fileline() << ": : Expression is: " << *this
<< endl;
des->errors += 1;
return 1;
}
NetExpr* PExpr::elaborate_expr(Design*des, NetScope*, ivl_type_t, unsigned) const
{
cerr << get_fileline() << ": internal error: I do not know how to"
<< " elaborate (ivl_type_t) this expression. " << endl;
cerr << get_fileline() << ": : Expression is: " << *this
<< endl;
cerr << get_fileline() << ": : Expression type: " << typeid(*this).name() << endl;
des->errors += 1;
return 0;
}
NetExpr* PExpr::elaborate_expr(Design*des, NetScope*, unsigned, unsigned) const
{
cerr << get_fileline() << ": internal error: I do not know how to"
<< " elaborate this expression. " << endl;
cerr << get_fileline() << ": : Expression is: " << *this
<< endl;
des->errors += 1;
return 0;
}
/*
* For now, assume that assignment patterns are for dynamic
* objects. This is not really true as this expression type, fully
* supported, can assign to packed arrays and structs, unpacked arrays
* and dynamic arrays.
*/
unsigned PEAssignPattern::test_width(Design*, NetScope*, width_mode_t&)
{
expr_type_ = IVL_VT_DARRAY;
expr_width_ = 1;
min_width_ = 1;
signed_flag_= false;
return 1;
}
NetExpr*PEAssignPattern::elaborate_expr(Design*des, NetScope*scope,
ivl_type_t ntype, unsigned flags) const
{
// Special case: If this is an empty pattern (i.e. '{}) and
// the expected type is a DARRAY, then convert this to a null
// handle. Internally, Icarus Verilog uses this to represent
// nil dynamic arrays.
if (parms_.size() == 0 && ntype->base_type()==IVL_VT_DARRAY) {
NetENull*tmp = new NetENull;
tmp->set_line(*this);
return tmp;
}
if (ntype->base_type()==IVL_VT_DARRAY)
return elaborate_expr_darray_(des, scope, ntype, flags);
cerr << get_fileline() << ": sorry: I don't know how to elaborate "
<< "assignment_pattern expressions yet." << endl;
cerr << get_fileline() << ": : Expression is: " << *this
<< endl;
des->errors += 1;
return 0;
}
NetExpr*PEAssignPattern::elaborate_expr_darray_(Design*des, NetScope*scope,
ivl_type_t ntype, unsigned flags) const
{
const netdarray_t*array_type = dynamic_cast<const netdarray_t*> (ntype);
ivl_assert(*this, array_type);
// This is an array pattern, so run through the elements of
// the expression and elaborate each as if they are
// element_type expressions.
ivl_type_t elem_type = array_type->element_type();
vector<NetExpr*> elem_exprs (parms_.size());
for (size_t idx = 0 ; idx < parms_.size() ; idx += 1) {
NetExpr*tmp = parms_[idx]->elaborate_expr(des, scope, elem_type, flags);
elem_exprs[idx] = tmp;
}
NetEArrayPattern*res = new NetEArrayPattern(array_type, elem_exprs);
res->set_line(*this);
return res;
}
NetExpr* PEAssignPattern::elaborate_expr(Design*des, NetScope*, unsigned, unsigned) const
{
cerr << get_fileline() << ": sorry: I do not know how to"
<< " elaborate assignment patterns using old method." << endl;
cerr << get_fileline() << ": : Expression is: " << *this
<< endl;
des->errors += 1;
ivl_assert(*this, 0);
return 0;
}
unsigned PEBinary::test_width(Design*des, NetScope*scope, width_mode_t&mode)
{
ivl_assert(*this, left_);
ivl_assert(*this, right_);
unsigned r_width = right_->test_width(des, scope, mode);
width_mode_t saved_mode = mode;
unsigned l_width = left_->test_width(des, scope, mode);
if (debug_elaborate) {
cerr << get_fileline() << ": PEBinary::test_width: "
<< "op_=" << op_ << ", l_width=" << l_width
<< ", r_width=" << r_width
<< ", saved_mode=" << saved_mode << endl;
}
// If the width mode changed, retest the right operand, as it
// may choose a different width if it is in a lossless context.
if ((mode >= LOSSLESS) && (saved_mode < LOSSLESS))
r_width = right_->test_width(des, scope, mode);
ivl_variable_type_t l_type = left_->expr_type();
ivl_variable_type_t r_type = right_->expr_type();
if (l_type == IVL_VT_REAL || r_type == IVL_VT_REAL)
expr_type_ = IVL_VT_REAL;
else if (l_type == IVL_VT_LOGIC || r_type == IVL_VT_LOGIC)
expr_type_ = IVL_VT_LOGIC;
else
expr_type_ = IVL_VT_BOOL;
if (expr_type_ == IVL_VT_REAL) {
expr_width_ = 1;
min_width_ = 1;
signed_flag_ = true;
} else {
expr_width_ = max(l_width, r_width);
min_width_ = max(left_->min_width(), right_->min_width());
signed_flag_ = left_->has_sign() && right_->has_sign();
// If the operands are different types, the expression is
// forced to unsigned. In this case the lossless width
// calculation is unreliable and we need to make sure the
// final expression width is at least integer_width.
if ((mode == LOSSLESS) && (left_->has_sign() != right_->has_sign()))
mode = UPSIZE;
switch (op_) {
case '+':
case '-':
if (mode >= EXPAND)
expr_width_ += 1;
break;
case '*':
if (mode >= EXPAND)
expr_width_ = l_width + r_width;
break;
case '%':
case '/':
min_width_ = UINT_MAX; // disable width pruning
break;
case 'l': // << Should be handled by PEBShift
case 'r': // >> Should be handled by PEBShift
case 'R': // >>> Should be handled by PEBShift
case '<': // < Should be handled by PEBComp
case '>': // > Should be handled by PEBComp
case 'e': // == Should be handled by PEBComp
case 'E': // === Should be handled by PEBComp
case 'L': // <= Should be handled by PEBComp
case 'G': // >= Should be handled by PEBComp
case 'n': // != Should be handled by PEBComp
case 'N': // !== Should be handled by PEBComp
case 'p': // ** should be handled by PEBPower
ivl_assert(*this, 0);
default:
break;
}
}
return fix_width_(mode);
}
/*
* Elaborate binary expressions. This involves elaborating the left
* and right sides, and creating one of a variety of different NetExpr
* types.
*/
NetExpr* PEBinary::elaborate_expr(Design*des, NetScope*scope,
unsigned expr_wid, unsigned flags) const
{
flags &= ~SYS_TASK_ARG; // don't propagate the SYS_TASK_ARG flag
ivl_assert(*this, left_);
ivl_assert(*this, right_);
// Handle the special case that one of the operands is a real
// value and the other is a vector type. In that case,
// elaborate the vectorable argument as self-determined.
// Propagate the expression type (signed/unsigned) down to
// any context-determined operands.
unsigned l_width = expr_wid;
unsigned r_width = expr_wid;
if (left_->expr_type()==IVL_VT_REAL
&& type_is_vectorable(right_->expr_type())) {
r_width = right_->expr_width();
} else {
right_->cast_signed(signed_flag_);
}
if (right_->expr_type()==IVL_VT_REAL
&& type_is_vectorable(left_->expr_type())) {
l_width = left_->expr_width();
} else {
left_->cast_signed(signed_flag_);
}
NetExpr*lp = left_->elaborate_expr(des, scope, l_width, flags);
NetExpr*rp = right_->elaborate_expr(des, scope, r_width, flags);
if ((lp == 0) || (rp == 0)) {
delete lp;
delete rp;
return 0;
}
return elaborate_expr_base_(des, lp, rp, expr_wid);
}
/*
* This is the common elaboration of the operator. It presumes that the
* operands are elaborated as necessary, and all I need to do is make
* the correct NetEBinary object and connect the parameters.
*/
NetExpr* PEBinary::elaborate_expr_base_(Design*des,
NetExpr*lp, NetExpr*rp,
unsigned expr_wid) const
{
if (debug_elaborate) {
cerr << get_fileline() << ": debug: elaborate expression "
<< *this << " expr_width=" << expr_wid << endl;
}
NetExpr*tmp;
switch (op_) {
default:
tmp = new NetEBinary(op_, lp, rp, expr_wid, signed_flag_);
tmp->set_line(*this);
break;
case 'a':
case 'o':
cerr << get_fileline() << ": internal error: "
<< "Elaboration of " << human_readable_op(op_)
<< " Should have been handled in NetEBLogic::elaborate."
<< endl;
des->errors += 1;
return 0;
case 'p':
cerr << get_fileline() << ": internal error: "
<< "Elaboration of " << human_readable_op(op_)
<< " Should have been handled in NetEBPower::elaborate."
<< endl;
des->errors += 1;
return 0;
case '*':
tmp = elaborate_expr_base_mult_(des, lp, rp, expr_wid);
break;
case '%':
case '/':
tmp = elaborate_expr_base_div_(des, lp, rp, expr_wid);
break;
case 'l':
case 'r':
case 'R':
cerr << get_fileline() << ": internal error: "
<< "Elaboration of " << human_readable_op(op_)
<< " Should have been handled in NetEBShift::elaborate."
<< endl;
des->errors += 1;
return 0;
case '^':
case '&':
case '|':
case 'O': // NOR (~|)
case 'A': // NAND (~&)
case 'X':
tmp = elaborate_expr_base_bits_(des, lp, rp, expr_wid);
break;
case '+':
case '-':
tmp = new NetEBAdd(op_, lp, rp, expr_wid, signed_flag_);
tmp->set_line(*this);
break;
case 'E': /* === */
case 'N': /* !== */
case 'e': /* == */
case 'n': /* != */
case 'L': /* <= */
case 'G': /* >= */
case '<':
case '>':
cerr << get_fileline() << ": internal error: "
<< "Elaboration of " << human_readable_op(op_)
<< " Should have been handled in NetEBComp::elaborate."
<< endl;
des->errors += 1;
return 0;
case 'm': // min(l,r)
case 'M': // max(l,r)
tmp = new NetEBMinMax(op_, lp, rp, expr_wid, signed_flag_);
tmp->set_line(*this);
break;
}
return tmp;
}
NetExpr* PEBinary::elaborate_expr_base_bits_(Design*des,
NetExpr*lp, NetExpr*rp,
unsigned expr_wid) const
{
if (lp->expr_type() == IVL_VT_REAL || rp->expr_type() == IVL_VT_REAL) {
cerr << get_fileline() << ": error: "
<< human_readable_op(op_)
<< " operator may not have REAL operands." << endl;
des->errors += 1;
return 0;
}
NetEBBits*tmp = new NetEBBits(op_, lp, rp, expr_wid, signed_flag_);
tmp->set_line(*this);
return tmp;
}
NetExpr* PEBinary::elaborate_expr_base_div_(Design*des,
NetExpr*lp, NetExpr*rp,
unsigned expr_wid) const
{
/* The % operator does not support real arguments in
baseline Verilog. But we allow it in our extended
form of Verilog. */
if (op_ == '%' && ! gn_icarus_misc_flag) {
if (lp->expr_type() == IVL_VT_REAL ||
rp->expr_type() == IVL_VT_REAL) {
cerr << get_fileline() << ": error: Modulus operator "
"may not have REAL operands." << endl;
des->errors += 1;
}
}
NetEBDiv*tmp = new NetEBDiv(op_, lp, rp, expr_wid, signed_flag_);
tmp->set_line(*this);
return tmp;
}
NetExpr* PEBinary::elaborate_expr_base_mult_(Design*,
NetExpr*lp, NetExpr*rp,
unsigned expr_wid) const
{
// Keep constants on the right side.
if (dynamic_cast<NetEConst*>(lp)) {
NetExpr*tmp = lp;
lp = rp;
rp = tmp;
}
// Handle a few special case multiplies against constants.
if (NetEConst*rp_const = dynamic_cast<NetEConst*> (rp)) {
verinum rp_val = rp_const->value();
if (!rp_val.is_defined() && (lp->expr_type() == IVL_VT_LOGIC)) {
NetEConst*tmp = make_const_x(expr_wid);
tmp->cast_signed(signed_flag_);
tmp->set_line(*this);
return tmp;
}
if (rp_val.is_zero() && (lp->expr_type() == IVL_VT_BOOL)) {
NetEConst*tmp = make_const_0(expr_wid);
tmp->cast_signed(signed_flag_);
tmp->set_line(*this);
return tmp;
}
}
NetEBMult*tmp = new NetEBMult(op_, lp, rp, expr_wid, signed_flag_);
tmp->set_line(*this);
return tmp;
}
unsigned PEBComp::test_width(Design*des, NetScope*scope, width_mode_t&)
{
ivl_assert(*this, left_);
ivl_assert(*this, right_);
// The width and type of a comparison are fixed and well known.
expr_type_ = IVL_VT_LOGIC;
expr_width_ = 1;
min_width_ = 1;
signed_flag_ = false;
// The widths of the operands are semi-self-determined. They
// affect each other, but not the result.
width_mode_t mode = SIZED;
unsigned r_width = right_->test_width(des, scope, mode);
width_mode_t saved_mode = mode;
unsigned l_width = left_->test_width(des, scope, mode);
// If the width mode changed, retest the right operand, as it
// may choose a different width if it is in a lossless context.
if ((mode >= LOSSLESS) && (saved_mode < LOSSLESS))
r_width = right_->test_width(des, scope, mode);
ivl_variable_type_t l_type = left_->expr_type();
ivl_variable_type_t r_type = right_->expr_type();
l_width_ = l_width;
if (type_is_vectorable(l_type) && (r_width > l_width))
l_width_ = r_width;
r_width_ = r_width;
if (type_is_vectorable(r_type) && (l_width > r_width))
r_width_ = l_width;
// If the expression is lossless and smaller than the integer
// minimum, then tweak the size up.
// NOTE: I really would rather try to figure out what it would
// take to get expand the sub-expressions so that they are
// exactly the right width to behave just like infinite
// width. I suspect that adding 1 more is sufficient in all
// cases, but I'm not certain. Ideas?
if (mode >= EXPAND) {
if (type_is_vectorable(l_type) && (l_width_ < integer_width))
l_width_ += 1;
if (type_is_vectorable(r_type) && (r_width_ < integer_width))
r_width_ += 1;
}
if (debug_elaborate) {
cerr << get_fileline() << ": debug: "
<< "Comparison expression operands are "
<< l_type << " " << l_width << " bits and "
<< r_type << " " << r_width << " bits. Resorting to "
<< l_width_ << " bits and "
<< r_width_ << " bits." << endl;
}
return expr_width_;
}
NetExpr* PEBComp::elaborate_expr(Design*des, NetScope*scope,
unsigned expr_wid, unsigned flags) const
{
flags &= ~SYS_TASK_ARG; // don't propagate the SYS_TASK_ARG flag
ivl_assert(*this, left_);
ivl_assert(*this, right_);
// Propagate the comparison type (signed/unsigned) down to
// the operands.
if (type_is_vectorable(left_->expr_type()) && !left_->has_sign())
right_->cast_signed(false);
if (type_is_vectorable(right_->expr_type()) && !right_->has_sign())
left_->cast_signed(false);
NetExpr*lp = left_->elaborate_expr(des, scope, l_width_, flags);
NetExpr*rp = right_->elaborate_expr(des, scope, r_width_, flags);
if ((lp == 0) || (rp == 0)) {
delete lp;
delete rp;
return 0;
}
eval_expr(lp, l_width_);
eval_expr(rp, r_width_);
// Handle some operand-specific special cases...
switch (op_) {
case 'E': /* === */
case 'N': /* !== */
if (lp->expr_type() == IVL_VT_REAL ||
lp->expr_type() == IVL_VT_STRING ||
rp->expr_type() == IVL_VT_REAL ||
rp->expr_type() == IVL_VT_STRING) {
cerr << get_fileline() << ": error: "
<< human_readable_op(op_)
<< " operator may not have REAL or STRING operands."
<< endl;
des->errors += 1;
return 0;
}
break;
default:
break;
}
NetExpr*tmp = new NetEBComp(op_, lp, rp);
tmp->set_line(*this);
return pad_to_width(tmp, expr_wid, signed_flag_, *this);
}
unsigned PEBLogic::test_width(Design*, NetScope*, width_mode_t&)
{
// The width and type of a logical operation are fixed.
expr_type_ = IVL_VT_LOGIC;
expr_width_ = 1;
min_width_ = 1;
signed_flag_ = false;
// The widths of the operands are self determined. We don't need
// them now, so they can be tested when they are elaborated.
return expr_width_;
}
NetExpr*PEBLogic::elaborate_expr(Design*des, NetScope*scope,
unsigned expr_wid, unsigned flags) const
{
ivl_assert(*this, left_);
ivl_assert(*this, right_);
bool need_const = NEED_CONST & flags;
NetExpr*lp = elab_and_eval(des, scope, left_, -1, need_const);
NetExpr*rp = elab_and_eval(des, scope, right_, -1, need_const);
if ((lp == 0) || (rp == 0)) {
delete lp;
delete rp;
return 0;
}
lp = condition_reduce(lp);
rp = condition_reduce(rp);
NetExpr*tmp = new NetEBLogic(op_, lp, rp);
tmp->set_line(*this);
return pad_to_width(tmp, expr_wid, signed_flag_, *this);
}
unsigned PEBLeftWidth::test_width(Design*des, NetScope*scope, width_mode_t&mode)
{
ivl_assert(*this, left_);
ivl_assert(*this, right_);
if (debug_elaborate) {
cerr << get_fileline() << ": PEBLeftWidth::test_width: "
<< "op_=" << op_
<< ", left_=" << *left_
<< ", right_=" << *right_
<< ", mode=" << width_mode_name(mode) << endl;
}
// The right operand is self determined. Test its type and
// width for use later. We only need to know its width now
// if the left operand is unsized and we need to calculate
// the lossless width.
width_mode_t r_mode = SIZED;
unsigned r_width = right_->test_width(des, scope, r_mode);
// The left operand is what will determine the size of the
// expression. The l_mode will be converted to UNSIZED if the
// expression does not have a well-determined size.
width_mode_t l_mode = SIZED;
expr_width_ = left_->test_width(des, scope, l_mode);
expr_type_ = left_->expr_type();
signed_flag_ = left_->has_sign();
if (mode==SIZED)
mode = l_mode;
// The left operand width defines the size of the
// expression. If the expression has a well-defined size, the
// left_->test_width() above would have set mode==SIZED and we
// can skip a lot of stuff. But if the mode is an undetermined
// size, we need to figure out what we really want to keep a
// lossless value. That's what the following if(...) {...} is
// all about.
if ((mode >= EXPAND) && type_is_vectorable(expr_type_)) {
// We need to make our best guess at the right operand
// value, to minimize the calculated width. This is
// particularly important for the power operator...
// Start off by assuming the maximum value for the
// type and width of the right operand.
long r_val = LONG_MAX;
if (r_width < sizeof(long)*8) {
r_val = (1L << r_width) - 1L;
if ((op_ == 'p') && right_->has_sign())
r_val >>= 1;
}
// If the right operand is constant, we can use the
// actual value.
NetExpr*rp = right_->elaborate_expr(des, scope, r_width, NO_FLAGS);
if (rp) {
eval_expr(rp, r_width);
} else {
// error recovery
PEVoid*tmp = new PEVoid();
tmp->set_line(*this);
delete right_;
right_ = tmp;
}
NetEConst*rc = dynamic_cast<NetEConst*> (rp);
// Adjust the expression width that can be converter depending
// on if the R-value is signed or not.
unsigned c_width = sizeof(long)*8;
if (! right_->has_sign()) c_width -= 1;
if (rc && (r_width <= c_width)) r_val = rc->value().as_long();
if (debug_elaborate && rc) {
cerr << get_fileline() << ": PEBLeftWidth::test_width: "
<< "Evaluated rc=" << *rc
<< ", r_val=" << r_val
<< ", width_cap=" << width_cap << endl;
}
// Clip to a sensible range to avoid underflow/overflow
// in the following calculations.
if (r_val < 0)
r_val = 0;
if ((unsigned long)r_val > width_cap)
r_val = width_cap;
// If the left operand is a simple unsized number, we
// can calculate the actual width required for the power
// operator.
PENumber*lc = dynamic_cast<PENumber*> (left_);
// Now calculate the lossless width.
unsigned use_width = expr_width_;
switch (op_) {
case 'l': // <<
if (l_mode != SIZED)
use_width += (unsigned)r_val;
break;
case 'r': // >>
case 'R': // >>>
// A logical shift will effectively coerce a signed
// operand to unsigned. We have to assume an arithmetic
// shift may do the same, as we don't yet know the final
// expression type.
if ((mode == LOSSLESS) && signed_flag_)
mode = UPSIZE;
break;
case 'p': // **
if (lc && rc) {
verinum result = pow(lc->value(), rc->value());
use_width = max(use_width, result.len());
} else {
if (signed_flag_) use_width -= 1;
use_width *= (unsigned)r_val;
if (signed_flag_) use_width += 2;
}
break;
default:
cerr << get_fileline() << ": internal error: "
<< "Unexpected opcode " << human_readable_op(op_)
<< " in PEBLeftWidth::test_width." << endl;
des->errors += 1;
}
// If the right operand is not constant, we could end up
// grossly overestimating the required width. So in this
// case, don't expand beyond the width of an integer
// (which meets the requirements of the standard).
if ((rc == 0) && (use_width > expr_width_) && (use_width > integer_width))
use_width = integer_width;
if (use_width >= width_cap) {
cerr << get_fileline() << ": warning: "
<< "Unsized expression (" << *this << ")"
<< " expanded beyond and was clipped to " << use_width
<< " bits. Try using sized operands." << endl;
}
expr_width_ = use_width;
}
if (op_ == 'l')
min_width_ = left_->min_width();
else
min_width_ = UINT_MAX; // disable width pruning
if (debug_elaborate) {
cerr << get_fileline() << ": PEBLeftWidth::test_width: "
<< "Done calculating expr_width_=" << expr_width_
<< ", min_width_=" << min_width_
<< ", mode=" << width_mode_name(mode) << endl;
}
return fix_width_(mode);
}
NetExpr*PEBLeftWidth::elaborate_expr(Design*des, NetScope*scope,
unsigned expr_wid, unsigned flags) const
{
flags &= ~SYS_TASK_ARG; // don't propagate the SYS_TASK_ARG flag
ivl_assert(*this, left_);
// The left operand is always context determined, so propagate
// down the expression type (signed/unsigned).
left_->cast_signed(signed_flag_);
unsigned r_width = right_->expr_width();
NetExpr*lp = left_->elaborate_expr(des, scope, expr_wid, flags);
NetExpr*rp = right_->elaborate_expr(des, scope, r_width, flags);
if (lp == 0 || rp == 0) {
delete lp;
delete rp;
return 0;
}
// For shift operations, the right operand is always treated as
// unsigned, so coerce it if necessary.
if ((op_ != 'p') && rp->has_sign()) {
rp = new NetESelect(rp, 0, rp->expr_width());
rp->cast_signed(false);
rp->set_line(*this);
}
eval_expr(lp, expr_wid);
eval_expr(rp, r_width);
return elaborate_expr_leaf(des, lp, rp, expr_wid);
}
NetExpr*PEBPower::elaborate_expr_leaf(Design*, NetExpr*lp, NetExpr*rp,
unsigned expr_wid) const
{
if (debug_elaborate) {
cerr << get_fileline() << ": debug: elaborate expression "
<< *this << " expr_wid=" << expr_wid << endl;
}
NetExpr*tmp = new NetEBPow(op_, lp, rp, expr_wid, signed_flag_);
tmp->set_line(*this);
return tmp;
}
NetExpr*PEBShift::elaborate_expr_leaf(Design*des, NetExpr*lp, NetExpr*rp,
unsigned expr_wid) const
{
switch (op_) {
case 'l': // <<
case 'r': // >>
case 'R': // >>>
break;
default:
cerr << get_fileline() << ": internal error: "
<< "Unexpected opcode " << human_readable_op(op_)
<< " in PEBShift::elaborate_expr_leaf." << endl;
des->errors += 1;
return 0;
}
if (lp->expr_type() == IVL_VT_REAL || rp->expr_type() == IVL_VT_REAL) {
cerr << get_fileline() << ": error: "
<< human_readable_op(op_)
<< " operator may not have REAL operands." << endl;
des->errors += 1;
delete lp;
delete rp;
return 0;
}
NetExpr*tmp;
// If the left expression is constant, then there are some
// special cases we can work with. If the left expression is
// not constant, but the right expression is constant, then
// there are some other interesting cases. But if neither are
// constant, then there is the general case.
if (NetEConst*lpc = dynamic_cast<NetEConst*> (lp)) {
// Special case: The left expression is zero. If the
// shift value contains no 'x' or 'z' bits, the result
// is going to be zero.
if (lpc->value().is_defined() && lpc->value().is_zero()
&& (rp->expr_type() == IVL_VT_BOOL)) {
if (debug_elaborate)
cerr << get_fileline() << ": debug: "
<< "Shift of zero always returns zero."
<< " Elaborate as constant zero." << endl;
tmp = make_const_0(expr_wid);
tmp->cast_signed(signed_flag_);
tmp->set_line(*this);
return tmp;
}
} else if (NetEConst*rpc = dynamic_cast<NetEConst*> (rp)) {
// Special case: The shift value contains 'x' or 'z' bits.
// Elaborate as a constant-x.
if (!rpc->value().is_defined()) {
if (debug_elaborate)
cerr << get_fileline() << ": debug: "
<< "Shift by undefined value. "
<< "Elaborate as constant 'x'." << endl;
tmp = make_const_x(expr_wid);
tmp->cast_signed(signed_flag_);
tmp->set_line(*this);
delete lp;
delete rp;
return tmp;
}