diff --git a/DART-MIMX8MM_manifest_v3_10.xml b/DART-MIMX8MM_manifest_v3_10.xml
new file mode 100644
index 000000000..17a6d6b66
--- /dev/null
+++ b/DART-MIMX8MM_manifest_v3_10.xml
@@ -0,0 +1,4775 @@
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+ Evaluation Kit for the i.MX 8M Mini Applications Processor
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+ i.MX 8M Mini Quad
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+
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+
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+
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+
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+
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+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
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+
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+
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+
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+
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+
+
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+
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+
+
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+
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+
+
+
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+
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+
+
+
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+
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+
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+
+
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+
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+
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+
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+
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+
+
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+
+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
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+
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+
+
+
+
+
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+
+
+
+
+
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+
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+
+
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+
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+
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+
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+
+
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+
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+
+
+
+
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+
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+
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+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/RTE_Device.h b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/RTE_Device.h
new file mode 100644
index 000000000..ea588fde1
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/RTE_Device.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2018,2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _RTE_DEVICE_H
+#define _RTE_DEVICE_H
+
+extern void ECSPI1_InitPins();
+extern void ECSPI1_DeinitPins();
+
+/* Driver name mapping. */
+#define RTE_SPI1 1
+#define RTE_SPI1_DMA_EN 0
+
+/* ECSPI configuration. */
+#define RTE_SPI1_PIN_INIT ECSPI1_InitPins
+#define RTE_SPI1_PIN_DEINIT ECSPI1_DeinitPins
+#define RTE_SPI1_TRANSFER_CHANNEL kECSPI_Channel0
+
+#endif /* _RTE_DEVICE_H */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/CMakeLists.txt b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..edf87df9e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/CMakeLists.txt
@@ -0,0 +1,122 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(cmsis_ecspi_int_loopback_transfer)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME cmsis_ecspi_int_loopback_transfer.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../cmsis_ecspi_int_loopback_transfer.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../RTE_Device.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6/cmsis_drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+ ${SdkRootDirPath}/CMSIS/Driver/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_cmsis_ecspi_MIMX8MM6)
+
+include(driver_ecspi_sdma_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(driver_ecspi_MIMX8MM6)
+
+include(CMSIS_Driver_Include_SPI_MIMX8MM6)
+
+include(CMSIS_Driver_Include_Common_MIMX8MM6)
+
+include(driver_sdma_MIMX8MM6)
+
+include(driver_memory_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/cmsis_ecspi_int_loopback_transfer.bin)
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_all.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_all.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_flash_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_flash_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/clean.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/clean.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/config.cmake b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/flags.cmake b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/board.c b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/board.h b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/clock_config.c b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/clock_config.h b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/cmsis_ecspi_int_loopback_transfer.c b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/cmsis_ecspi_int_loopback_transfer.c
new file mode 100644
index 000000000..ae6814d19
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/cmsis_ecspi_int_loopback_transfer.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_ecspi_cmsis.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DRIVER_MASTER_SPI Driver_SPI1
+#define EXAMPLE_MASTER_SPI_BASE ECSPI1
+#define TRANSFER_SIZE 256U /*! Transfer dataSize */
+#define TRANSFER_BAUDRATE 500000U /*! Transfer baudrate - 500k */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+void ECSPI_EnableLoopBackTransfer(ECSPI_Type *base);
+/* ECSPI user SignalEvent */
+void ECSPI_MasterSignalEvent_t(uint32_t event);
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+uint32_t masterRxData[TRANSFER_SIZE] = {0U};
+uint32_t masterTxData[TRANSFER_SIZE] = {0U};
+
+volatile bool isTransferCompleted = false;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+uint32_t ECSPI1_GetFreq(void)
+{
+ return (CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootEcspi1)) /
+ (CLOCK_GetRootPostDivider(kCLOCK_RootEcspi1)));
+}
+
+void ECSPI_EnableLoopBackTransfer(ECSPI_Type *base)
+{
+ base->TESTREG |= ECSPI_TESTREG_LBC(1);
+}
+void ECSPI_MasterSignalEvent_t(uint32_t event)
+{
+ /* user code */
+ isTransferCompleted = true;
+ PRINTF("\r\n This is ECSPI_MasterSignalEvent_t.\r\n");
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ uint32_t errorCount;
+ uint32_t i;
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ CLOCK_SetRootMux(kCLOCK_RootEcspi1, kCLOCK_EcspiRootmuxSysPll1); /* Set ECSPI1 source to SYSTEM PLL1 800MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootEcspi1, 2U, 5U); /* Set root clock to 800MHZ / 10 = 80MHZ */
+
+ PRINTF("This is ECSPI CMSIS interrupt loopback transfer example.\r\n");
+ PRINTF("The ECSPI will connect the transmitter and receiver sections internally.\r\n");
+
+ /*DSPI master init*/
+ DRIVER_MASTER_SPI.Initialize(ECSPI_MasterSignalEvent_t);
+ DRIVER_MASTER_SPI.PowerControl(ARM_POWER_FULL);
+ DRIVER_MASTER_SPI.Control(ARM_SPI_MODE_MASTER, TRANSFER_BAUDRATE);
+
+ /* Enable loopback transfer. */
+ ECSPI_EnableLoopBackTransfer(EXAMPLE_MASTER_SPI_BASE);
+ /* Set up the transfer data */
+ for (i = 0U; i < TRANSFER_SIZE; i++)
+ {
+ masterTxData[i] = i % 256U;
+ masterRxData[i] = 0U;
+ }
+
+ isTransferCompleted = false;
+ PRINTF("Start transfer...\r\n");
+ /* Start master transfer */
+ DRIVER_MASTER_SPI.Transfer(masterTxData, masterRxData, TRANSFER_SIZE);
+
+ /* Wait slave received all data. */
+ while (!isTransferCompleted)
+ {
+ }
+
+ PRINTF("\r\nTransfer completed!");
+ errorCount = 0U;
+ for (i = 0U; i < TRANSFER_SIZE; i++)
+ {
+ if (masterTxData[i] != masterRxData[i])
+ {
+ errorCount++;
+ }
+ }
+ if (errorCount == 0U)
+ {
+ PRINTF("\r\nECSPI transfer all data matched! \r\n");
+ }
+ else
+ {
+ PRINTF(" \r\nError occurred in ECSPI loopback transfer ! \r\n");
+ }
+
+ DRIVER_MASTER_SPI.PowerControl(ARM_POWER_OFF);
+ DRIVER_MASTER_SPI.Uninitialize();
+
+ while (1)
+ {
+ }
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/cmsis_ecspi_int_loopback_transfer_v3_10.xml b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/cmsis_ecspi_int_loopback_transfer_v3_10.xml
new file mode 100644
index 000000000..354437978
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/cmsis_ecspi_int_loopback_transfer_v3_10.xml
@@ -0,0 +1,138 @@
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diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/empty_rsc_table.c b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/fsl_iomuxc.h b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/pin_mux.c b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/pin_mux.c
new file mode 100644
index 000000000..85873dcb0
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/pin_mux.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+ECSPI1_DeinitPins:
+- options: {callFromInitBoot: 'false', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: GPIO5, signal: 'gpio_io, 26', pin_signal: UART3_RXD}
+ - {pin_num: D18, peripheral: GPIO5, signal: 'gpio_io, 27', pin_signal: UART3_TXD}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : ECSPI1_DeinitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void ECSPI1_DeinitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_GPIO5_IO26, 0U);
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_GPIO5_IO27, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+ECSPI1_InitPins:
+- options: {callFromInitBoot: 'false', coreID: cm4}
+- pin_list: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : ECSPI1_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void ECSPI1_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/pin_mux.h b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/pin_mux.h
new file mode 100644
index 000000000..8899a88b8
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/pin_mux.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+
+/* Symbols to be used with GPIO driver */
+#define ECSPI2_DEINITPINS_UART4_RXD_GPIO_PIN_MASK (1U << 28U) /*!< GPIO pin mask */
+
+/* Symbols to be used with GPIO driver */
+#define ECSPI2_DEINITPINS_UART4_TXD_GPIO_PIN_MASK (1U << 29U) /*!< GPIO pin mask */
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void ECSPI1_DeinitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void ECSPI1_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/readme.txt b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/readme.txt
new file mode 100644
index 000000000..2f0285846
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/int_loopback_transfer/readme.txt
@@ -0,0 +1,66 @@
+Overview
+========
+CMSIS-Driver defines generic peripheral driver interfaces for middleware making it reusable across a wide
+range of supported microcontroller devices. The API connects microcontroller peripherals with middleware
+that implements for example communication stacks, file systems, or graphic user interfaces.
+More information and usage method please refer to http://www.keil.com/pack/doc/cmsis/Driver/html/index.html.
+
+The cmsis_ecspi_int_loopback_transfer example shows how to use CMSIS ECSPI driver in interrupt way:
+
+In this example , ECSPI will do a loopback transfer in interrupt way, so, there is no need to set up any pins.
+And we should set the ECSPIx->TESTREG[LBC] bit, this bit is used in Master mode only. When this bit is set,
+the ECSPI connects the transmitter and receiver sections internally, and the data shifted out from the
+most-significant bit of the shift register is looped back into the least-significant bit of the Shift register.
+In this way, a self-test of the complete transmit/receive path can be made. The output pins are not affected,
+and the input pins are ignored.
+
+
+
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
+
+
+Running the demo
+================
+When the demo runs successfully, the log would be seen on the debug terminal like:
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+This is ECSPI CMSIS interrupt loopback transfer example.
+The ECSPI will connect the transmitter and receiver sections internally.
+Start transfer...
+
+ This is ECSPI_MasterSignalEvent_t.
+
+Transfer completed!
+ECSPI transfer all data matched!
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/RTE_Device.h b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/RTE_Device.h
new file mode 100644
index 000000000..c2d22dcd5
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/RTE_Device.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2018,2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _RTE_DEVICE_H
+#define _RTE_DEVICE_H
+
+extern void ECSPI1_InitPins();
+extern void ECSPI1_DeinitPins();
+
+/* Driver name mapping. */
+#define RTE_SPI1 1
+#define RTE_SPI1_DMA_EN 1
+
+/* ECSPI configuration. */
+#define RTE_SPI1_TRANSFER_CHANNEL kECSPI_Channel0
+#define RTE_SPI1_PIN_INIT ECSPI1_InitPins
+#define RTE_SPI1_PIN_DEINIT ECSPI1_DeinitPins
+#define RTE_SPI1_DMA_TX_DMA_BASE SDMAARM1
+#define RTE_SPI1_DMA_TX_CH (2U)
+#define RTE_SPI1_DMA_TX_CH_REQUEST (1U)
+#define RTE_SPI1_DMA_TX_CH_PRIORITY (3U)
+#define RTE_SPI1_DMA_RX_DMA_BASE SDMAARM1
+#define RTE_SPI1_DMA_RX_CH (1U)
+#define RTE_SPI1_DMA_RX_CH_REQUEST (0U)
+#define RTE_SPI1_DMA_RX_CH_PRIORITY (2U)
+
+#endif /* _RTE_DEVICE_H */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/CMakeLists.txt b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..bdbb19e77
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/CMakeLists.txt
@@ -0,0 +1,124 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(cmsis_ecspi_sdma_loopback_transfer)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME cmsis_ecspi_sdma_loopback_transfer.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../cmsis_ecspi_sdma_loopback_transfer.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../RTE_Device.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/cmsis_drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+ ${SdkRootDirPath}/CMSIS/Driver/Include
+)
+
+# include modules
+include(driver_cache_lmem_MIMX8MM6)
+
+include(driver_ecspi_sdma_MIMX8MM6)
+
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_cmsis_ecspi_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(driver_sdma_MIMX8MM6)
+
+include(driver_memory_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(driver_ecspi_MIMX8MM6)
+
+include(CMSIS_Driver_Include_SPI_MIMX8MM6)
+
+include(CMSIS_Driver_Include_Common_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/cmsis_ecspi_sdma_loopback_transfer.bin)
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_all.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_all.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_flash_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_flash_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/clean.bat b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/clean.sh b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/config.cmake b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/flags.cmake b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/board.c b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/board.c
new file mode 100644
index 000000000..7ac3cfc4e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/board.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+#include "fsl_cache.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /*
+ * Flush the system cache before updating the cache policy. Without flushing, the
+ * previously done initialization of the non-cacheable sections will be discarded
+ * as the cache for this region was enabled with the write-back attribute before.
+ */
+ L1CACHE_CleanSystemCache();
+ __DSB();
+ __ISB();
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/board.h b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/clock_config.c b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/clock_config.h b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/cmsis_ecspi_sdma_loopback_transfer.c b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/cmsis_ecspi_sdma_loopback_transfer.c
new file mode 100644
index 000000000..f9bbd0940
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/cmsis_ecspi_sdma_loopback_transfer.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_ecspi_cmsis.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DRIVER_MASTER_SPI Driver_SPI1
+#define DRIVER_MASTER_SPI_DMA_BASE SDMAARM1
+#define EXAMPLE_MASTER_SPI_BASE ECSPI1
+#define TRANSFER_SIZE 64U /*! Transfer dataSize */
+#define TRANSFER_BAUDRATE 500000U /*! Transfer baudrate - 500k */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+void ECSPI_EnableLoopBackTransfer(ECSPI_Type *base);
+/* ECSPI user SignalEvent */
+void ECSPI_MasterSignalEvent_t(uint32_t event);
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint8_t masterRxData[TRANSFER_SIZE], 4) = {0};
+AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint8_t masterTxData[TRANSFER_SIZE], 4) = {0};
+
+volatile bool isTransferCompleted = false;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+uint32_t ECSPI1_GetFreq(void)
+{
+ return (CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootEcspi1)) /
+ (CLOCK_GetRootPostDivider(kCLOCK_RootEcspi1)));
+}
+
+void ECSPI_EnableLoopBackTransfer(ECSPI_Type *base)
+{
+ base->TESTREG |= ECSPI_TESTREG_LBC(1);
+}
+void ECSPI_MasterSignalEvent_t(uint32_t event)
+{
+ /* user code */
+ isTransferCompleted = true;
+ PRINTF("\r\n This is ECSPI_MasterSignalEvent_t\r\n");
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ uint32_t errorCount;
+ uint32_t i;
+
+ sdma_config_t sdmaConfig;
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ /* Init the SDMA module */
+ SDMA_GetDefaultConfig(&sdmaConfig);
+ SDMA_Init(DRIVER_MASTER_SPI_DMA_BASE, &sdmaConfig);
+
+ CLOCK_SetRootMux(kCLOCK_RootEcspi1, kCLOCK_EcspiRootmuxSysPll1); /* Set ECSPI1 source to SYSTEM PLL1 800MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootEcspi1, 2U, 5U); /* Set root clock to 800MHZ / 10 = 80MHZ */
+
+ PRINTF("This is ECSPI CMSIS SDMA loopback transfer example.\r\n");
+ PRINTF("The ECSPI will connect the transmitter and receiver sections internally.\r\n");
+
+ /*DSPI master init*/
+ DRIVER_MASTER_SPI.Initialize(ECSPI_MasterSignalEvent_t);
+ DRIVER_MASTER_SPI.PowerControl(ARM_POWER_FULL);
+ DRIVER_MASTER_SPI.Control(ARM_SPI_MODE_MASTER, TRANSFER_BAUDRATE);
+
+ /* Enable loopback transfer. */
+ ECSPI_EnableLoopBackTransfer(EXAMPLE_MASTER_SPI_BASE);
+ /* Set up the transfer data */
+ for (i = 0U; i < TRANSFER_SIZE; i++)
+ {
+ masterTxData[i] = i % 256U;
+ masterRxData[i] = 0U;
+ }
+
+ isTransferCompleted = false;
+ PRINTF("Start transfer...\r\n");
+ /* Start master transfer */
+ DRIVER_MASTER_SPI.Transfer(masterTxData, masterRxData, TRANSFER_SIZE);
+
+ /* Wait slave received all data. */
+ while (!isTransferCompleted)
+ {
+ }
+
+ PRINTF("\r\nTransfer completed!");
+ errorCount = 0U;
+ for (i = 0U; i < TRANSFER_SIZE; i++)
+ {
+ if (masterTxData[i] != masterRxData[i])
+ {
+ errorCount++;
+ }
+ }
+ if (errorCount == 0U)
+ {
+ PRINTF(" \r\nECSPI transfer all data matched! \r\n");
+ }
+ else
+ {
+ PRINTF(" \r\nError occurred in ECSPI loopback transfer ! \r\n");
+ }
+
+ DRIVER_MASTER_SPI.PowerControl(ARM_POWER_OFF);
+ DRIVER_MASTER_SPI.Uninitialize();
+
+ while (1)
+ {
+ }
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/cmsis_ecspi_sdma_loopback_transfer_v3_10.xml b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/cmsis_ecspi_sdma_loopback_transfer_v3_10.xml
new file mode 100644
index 000000000..bb39a17a6
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/cmsis_ecspi_sdma_loopback_transfer_v3_10.xml
@@ -0,0 +1,138 @@
+
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diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/empty_rsc_table.c b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/fsl_iomuxc.h b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/pin_mux.c b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/pin_mux.c
new file mode 100644
index 000000000..85873dcb0
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/pin_mux.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+ECSPI1_DeinitPins:
+- options: {callFromInitBoot: 'false', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: GPIO5, signal: 'gpio_io, 26', pin_signal: UART3_RXD}
+ - {pin_num: D18, peripheral: GPIO5, signal: 'gpio_io, 27', pin_signal: UART3_TXD}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : ECSPI1_DeinitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void ECSPI1_DeinitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_GPIO5_IO26, 0U);
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_GPIO5_IO27, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+ECSPI1_InitPins:
+- options: {callFromInitBoot: 'false', coreID: cm4}
+- pin_list: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : ECSPI1_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void ECSPI1_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/pin_mux.h b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/pin_mux.h
new file mode 100644
index 000000000..8899a88b8
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/pin_mux.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+
+/* Symbols to be used with GPIO driver */
+#define ECSPI2_DEINITPINS_UART4_RXD_GPIO_PIN_MASK (1U << 28U) /*!< GPIO pin mask */
+
+/* Symbols to be used with GPIO driver */
+#define ECSPI2_DEINITPINS_UART4_TXD_GPIO_PIN_MASK (1U << 29U) /*!< GPIO pin mask */
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void ECSPI1_DeinitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void ECSPI1_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/readme.txt b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/readme.txt
new file mode 100644
index 000000000..eb4d6a23a
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/ecspi/sdma_loopback_transfer/readme.txt
@@ -0,0 +1,63 @@
+Overview
+========
+CMSIS-Driver defines generic peripheral driver interfaces for middleware making it reusable across a wide
+range of supported microcontroller devices. The API connects microcontroller peripherals with middleware
+that implements for example communication stacks, file systems, or graphic user interfaces.
+More information and usage method please refer to http://www.keil.com/pack/doc/cmsis/Driver/html/index.html.
+
+The cmsis_ecspi_sdma_loopback_transfer example shows how to use CMSIS ECSPI driver in SDMA way:
+
+In this example , ECSPI will do a loopback transfer in SDMA way, so, there is no need to set up any pins.
+And we should set the ECSPIx->TESTREG[LBC] bit, this bit is used in Master mode only. When this bit is set,
+the ECSPI connects the transmitter and receiver sections internally, and the data shifted out from the
+most-significant bit of the shift register is looped back into the least-significant bit of the Shift register.
+In this way, a self-test of the complete transmit/receive path can be made. The output pins are not affected,
+and the input pins are ignored.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
+
+
+Running the demo
+================
+When the demo runs successfully, the log would be seen on the debug terminal like:
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+This is ECSPI CMSIS SDMA loopback transfer example.
+The ECSPI will connect the transmitter and receiver sections internally.
+Start transfer...
+
+ This is ECSPI_MasterSignalEvent_t
+
+Transfer completed!
+ECSPI transfer all data matched!
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/RTE_Device.h b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/RTE_Device.h
new file mode 100644
index 000000000..efe03d48b
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/RTE_Device.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _RTE_DEVICE_H
+#define _RTE_DEVICE_H
+
+extern void I2C4_InitPins();
+extern void I2C4_DeinitPins();
+
+/*Driver name mapping*/
+/* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance.
+ */
+#define RTE_I2C4 1
+#define RTE_I2C4_PIN_INIT I2C4_InitPins
+#define RTE_I2C4_PIN_DEINIT I2C4_DeinitPins
+
+/*I2C configuration*/
+
+#endif /* _RTE_DEVICE_H */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/CMakeLists.txt b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..21eea597f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/CMakeLists.txt
@@ -0,0 +1,116 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(cmsis_ii2c_int_b2b_transfer_master)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME cmsis_ii2c_int_b2b_transfer_master.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../cmsis_i2c_int_b2b_transfer_master.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../RTE_Device.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6/cmsis_drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+ ${SdkRootDirPath}/CMSIS/Driver/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_cmsis_ii2c_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(driver_ii2c_MIMX8MM6)
+
+include(CMSIS_Driver_Include_I2C_MIMX8MM6)
+
+include(CMSIS_Driver_Include_Common_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/cmsis_ii2c_int_b2b_transfer_master.bin)
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_all.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_all.bat
new file mode 100644
index 000000000..6868c7569
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_all.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_all.sh
new file mode 100755
index 000000000..888128e66
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..8771607cb
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..1f660e5af
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..0dfc882b6
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..cbb10c43f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_debug.bat
new file mode 100644
index 000000000..0636e21b5
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_debug.sh
new file mode 100755
index 000000000..30c0ab2d5
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..f0275ea6a
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..35370ab2f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_flash_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..51e8b73fc
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_flash_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..ef8236b19
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_release.bat
new file mode 100644
index 000000000..a34003e0e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_release.sh
new file mode 100755
index 000000000..012619cda
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/clean.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/clean.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/config.cmake b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/flags.cmake b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/board.c b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/board.h b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/clock_config.c b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/clock_config.h b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/cmsis_i2c_int_b2b_transfer_master.c b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/cmsis_i2c_int_b2b_transfer_master.c
new file mode 100644
index 000000000..01c0fa077
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/cmsis_i2c_int_b2b_transfer_master.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Standard C Included Files */
+#include
+/* SDK Included Files */
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_i2c.h"
+#include "Driver_I2C.h"
+#include "fsl_i2c_cmsis.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_I2C_MASTER Driver_I2C4
+#define I2C_MASTER_SLAVE_ADDR 0x7EU
+#define I2C_DATA_LENGTH 32U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+uint8_t g_master_txBuff[I2C_DATA_LENGTH];
+uint8_t g_master_rxBuff[I2C_DATA_LENGTH];
+volatile bool g_MasterCompletionFlag = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+uint32_t I2C4_GetFreq(void)
+{
+ return (CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootI2c4)) /
+ (CLOCK_GetRootPostDivider(kCLOCK_RootI2c4)) / 5); /* SYSTEM PLL1 DIV5 */
+}
+
+
+void I2C_MasterSignalEvent_t(uint32_t event)
+{
+ if (event == ARM_I2C_EVENT_TRANSFER_DONE)
+ {
+ g_MasterCompletionFlag = true;
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ CLOCK_SetRootMux(kCLOCK_RootI2c4, kCLOCK_I2cRootmuxSysPll1Div5); /* Set I2C source to SysPLL1 Div5 160MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootI2c4, 1U, 10U); /* Set root clock to 160MHZ / 10 = 16MHZ */
+
+ /*Init I2C*/
+ EXAMPLE_I2C_MASTER.Initialize(I2C_MasterSignalEvent_t);
+
+ /* Enable i2c moduole and i2c clock */
+ EXAMPLE_I2C_MASTER.PowerControl(ARM_POWER_FULL);
+
+ /*config transmit speed*/
+ EXAMPLE_I2C_MASTER.Control(ARM_I2C_BUS_SPEED, ARM_I2C_BUS_SPEED_STANDARD);
+
+ PRINTF("\r\nCMSIS I2C board2board interrupt example -- Master transfer.\r\n");
+
+ /*Set up i2c master to send data to master*/
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ g_master_txBuff[i] = i;
+ }
+ PRINTF("Master will send data :");
+
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ if (i % 8 == 0)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF("0x%2x ", g_master_txBuff[i]);
+ }
+ PRINTF("\r\n\r\n");
+
+ /*start transfer*/
+ EXAMPLE_I2C_MASTER.MasterTransmit(I2C_MASTER_SLAVE_ADDR, g_master_txBuff, I2C_DATA_LENGTH, false);
+
+ /*wait for master complete*/
+ while (!g_MasterCompletionFlag)
+ {
+ }
+
+ /* Reset master completion flag to false. */
+ g_MasterCompletionFlag = false;
+
+ PRINTF("Receive sent data from slave :");
+
+ EXAMPLE_I2C_MASTER.MasterReceive(I2C_MASTER_SLAVE_ADDR, g_master_rxBuff, I2C_DATA_LENGTH, false);
+
+ /*wait for master complete*/
+ while (!g_MasterCompletionFlag)
+ {
+ }
+ /* Reset master completion flag to false. */
+ g_MasterCompletionFlag = false;
+
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ if (i % 8 == 0)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF("0x%2x ", g_master_rxBuff[i]);
+ }
+ PRINTF("\r\n\r\n");
+
+ /* Transfer completed. Check the data.*/
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ if (g_master_rxBuff[i] != g_master_txBuff[i])
+ {
+ PRINTF("\r\nError occurred in the transfer ! \r\n");
+ break;
+ }
+ }
+
+ PRINTF("\r\nEnd of I2C example .\r\n");
+ while (1)
+ {
+ }
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/cmsis_ii2c_int_b2b_transfer_master_v3_10.xml b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/cmsis_ii2c_int_b2b_transfer_master_v3_10.xml
new file mode 100644
index 000000000..f82bad828
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/cmsis_ii2c_int_b2b_transfer_master_v3_10.xml
@@ -0,0 +1,135 @@
+
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diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/empty_rsc_table.c b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/fsl_iomuxc.h b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/pin_mux.c b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/pin_mux.c
new file mode 100644
index 000000000..5a9040917
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/pin_mux.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, SION: DISABLED, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+I2C4_DeinitPins:
+- options: {callFromInitBoot: 'false', coreID: cm4}
+- pin_list:
+ - {pin_num: D13, peripheral: GPIO5, signal: 'gpio_io, 20', pin_signal: I2C4_SCL}
+ - {pin_num: E13, peripheral: GPIO5, signal: 'gpio_io, 21', pin_signal: I2C4_SDA}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : I2C4_DeinitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void I2C4_DeinitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SCL_GPIO5_IO20, 0U);
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_GPIO5_IO21, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+I2C4_InitPins:
+- options: {callFromInitBoot: 'false', coreID: cm4}
+- pin_list:
+ - {pin_num: D13, peripheral: I2C4, signal: i2c_scl, pin_signal: I2C4_SCL, PE: Disabled, PUE: Disabled, HYS: Enabled, SION: ENABLED, DSE: X6_0}
+ - {pin_num: E13, peripheral: I2C4, signal: i2c_sda, pin_signal: I2C4_SDA, PE: Disabled, HYS: Enabled, SION: ENABLED, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : I2C4_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void I2C4_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SCL_I2C4_SCL, 1U);
+ IOMUXC_SetPinConfig(IOMUXC_I2C4_SCL_I2C4_SCL,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_I2C4_SDA, 1U);
+ IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_I2C4_SDA,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/pin_mux.h b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/pin_mux.h
new file mode 100644
index 000000000..9f9b5590e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/pin_mux.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+
+/* Symbols to be used with GPIO driver */
+#define I2C4_DEINITPINS_I2C4_SCL_GPIO_PIN_MASK (1U << 20U) /*!< GPIO pin mask */
+
+/* Symbols to be used with GPIO driver */
+#define I2C4_DEINITPINS_I2C4_SDA_GPIO_PIN_MASK (1U << 21U) /*!< GPIO pin mask */
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void I2C4_DeinitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void I2C4_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/readme.txt b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/readme.txt
new file mode 100644
index 000000000..e7a91c060
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/master/readme.txt
@@ -0,0 +1,70 @@
+Overview
+========
+CMSIS-Driver defines generic peripheral driver interfaces for middleware making it reusable across a wide
+range of supported microcontroller devices. The API connects microcontroller peripherals with middleware
+that implements for example communication stacks, file systems, or graphic user interfaces.
+More information and usage method please refer to http://www.keil.com/pack/doc/cmsis/Driver/html/index.html.
+
+The i2c_interrupt_b2b_transfer_master example shows how to use CMSIS i2c driver as master to do board to board transfer
+with interrupt:
+
+In this example, one i2c instance as master and another i2c instance on the other board as slave. Master sends a
+piece of data to slave, and receive a piece of data from slave. This example checks if the data received from
+slave is correct.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+I2C one board:
+ + Transfer data from MASTER_BOARD to SLAVE_BOARD of I2C interface, I2C4 pins of MASTER_BOARD are connected with
+ I2C4 pins of SLAVE_BOARD
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+SLAVE_BOARD CONNECTS TO MASTER_BOARD
+Pin Name Board Location Pin Name Board Location
+For I2C4 connection, refer to: https://variwiki.com/index.php?title=MCUXpresso&release=MCUXPRESSO_2.13.0_V1.0_DART-MX8M-MINI#Demos_pins
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the demo runs successfully, the following message is displayed in the terminal:
+
+CMSIS I2C board2board interrupt example -- Master transfer.
+Master will send data :
+0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7
+0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f
+0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
+
+Receive sent data from slave :
+0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7
+0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f
+0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
+
+
+End of I2C example .
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/RTE_Device.h b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/RTE_Device.h
new file mode 100644
index 000000000..efe03d48b
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/RTE_Device.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _RTE_DEVICE_H
+#define _RTE_DEVICE_H
+
+extern void I2C4_InitPins();
+extern void I2C4_DeinitPins();
+
+/*Driver name mapping*/
+/* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance.
+ */
+#define RTE_I2C4 1
+#define RTE_I2C4_PIN_INIT I2C4_InitPins
+#define RTE_I2C4_PIN_DEINIT I2C4_DeinitPins
+
+/*I2C configuration*/
+
+#endif /* _RTE_DEVICE_H */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/CMakeLists.txt b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..645eee1a6
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/CMakeLists.txt
@@ -0,0 +1,116 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(cmsis_ii2c_int_b2b_transfer_slave)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME cmsis_ii2c_int_b2b_transfer_slave.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../cmsis_i2c_int_b2b_transfer_slave.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../RTE_Device.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6/cmsis_drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+ ${SdkRootDirPath}/CMSIS/Driver/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_cmsis_ii2c_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(driver_ii2c_MIMX8MM6)
+
+include(CMSIS_Driver_Include_I2C_MIMX8MM6)
+
+include(CMSIS_Driver_Include_Common_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/cmsis_ii2c_int_b2b_transfer_slave.bin)
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_all.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_all.bat
new file mode 100644
index 000000000..6868c7569
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_all.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_all.sh
new file mode 100755
index 000000000..888128e66
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..8771607cb
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..1f660e5af
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..0dfc882b6
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..cbb10c43f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_debug.bat
new file mode 100644
index 000000000..0636e21b5
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_debug.sh
new file mode 100755
index 000000000..30c0ab2d5
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..f0275ea6a
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..35370ab2f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_flash_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..51e8b73fc
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_flash_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..ef8236b19
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_release.bat
new file mode 100644
index 000000000..a34003e0e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_release.sh
new file mode 100755
index 000000000..012619cda
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/clean.bat b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/clean.sh b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/config.cmake b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/flags.cmake b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/board.c b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/board.h b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/clock_config.c b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/clock_config.h b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/cmsis_i2c_int_b2b_transfer_slave.c b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/cmsis_i2c_int_b2b_transfer_slave.c
new file mode 100644
index 000000000..834301ac0
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/cmsis_i2c_int_b2b_transfer_slave.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Standard C Included Files */
+#include
+/* SDK Included Files */
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_i2c.h"
+#include "Driver_I2C.h"
+#include "fsl_i2c_cmsis.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_I2C_SLAVE Driver_I2C4
+#define I2C_MASTER_SLAVE_ADDR 0x7EU
+#define I2C_DATA_LENGTH 32U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+uint8_t g_slave_buff[I2C_DATA_LENGTH];
+volatile bool g_SlaveCompletionFlag = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+uint32_t I2C4_GetFreq(void)
+{
+ return (CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootI2c4)) /
+ (CLOCK_GetRootPostDivider(kCLOCK_RootI2c4)) / 5); /* SYSTEM PLL1 DIV5 */
+}
+
+
+void I2C_SlaveSignalEvent_t(uint32_t event)
+{
+ if (event == ARM_I2C_EVENT_TRANSFER_DONE)
+ {
+ g_SlaveCompletionFlag = true;
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ CLOCK_SetRootMux(kCLOCK_RootI2c4, kCLOCK_I2cRootmuxSysPll1Div5); /* Set I2C source to SysPLL1 Div5 160MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootI2c4, 1U, 10U); /* Set root clock to 160MHZ / 10 = 16MHZ */
+
+ PRINTF("\r\nCMSIS I2C board2board interrupt example -- Slave transfer.\r\n\r\n");
+
+ /*Init I2C*/
+ EXAMPLE_I2C_SLAVE.Initialize(I2C_SlaveSignalEvent_t);
+
+ /* Enable i2c moduole and i2c clock */
+ EXAMPLE_I2C_SLAVE.PowerControl(ARM_POWER_FULL);
+
+ /*config slave addr*/
+ EXAMPLE_I2C_SLAVE.Control(ARM_I2C_OWN_ADDRESS, I2C_MASTER_SLAVE_ADDR);
+
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ g_slave_buff[i] = 0;
+ }
+
+ /*start transfer*/
+ EXAMPLE_I2C_SLAVE.SlaveReceive(g_slave_buff, I2C_DATA_LENGTH);
+
+ /* Wait for transfer completed. */
+ while (!g_SlaveCompletionFlag)
+ {
+ }
+
+ /* Reset slave completion flag to false. */
+ g_SlaveCompletionFlag = false;
+
+ EXAMPLE_I2C_SLAVE.SlaveTransmit(g_slave_buff, I2C_DATA_LENGTH);
+
+ /* Wait for master receive completed.*/
+
+ PRINTF("Slave received data :");
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ if (i % 8 == 0)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF("0x%2x ", g_slave_buff[i]);
+ }
+ PRINTF("\r\n\r\n");
+
+ while (!g_SlaveCompletionFlag)
+ {
+ }
+ g_SlaveCompletionFlag = false;
+
+ PRINTF("\r\nEnd of I2C example .\r\n");
+ while (1)
+ {
+ }
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/cmsis_ii2c_int_b2b_transfer_slave_v3_10.xml b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/cmsis_ii2c_int_b2b_transfer_slave_v3_10.xml
new file mode 100644
index 000000000..2e48a88d2
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/cmsis_ii2c_int_b2b_transfer_slave_v3_10.xml
@@ -0,0 +1,135 @@
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diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/empty_rsc_table.c b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/fsl_iomuxc.h b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/pin_mux.c b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/pin_mux.c
new file mode 100644
index 000000000..5a9040917
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/pin_mux.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, SION: DISABLED, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+I2C4_DeinitPins:
+- options: {callFromInitBoot: 'false', coreID: cm4}
+- pin_list:
+ - {pin_num: D13, peripheral: GPIO5, signal: 'gpio_io, 20', pin_signal: I2C4_SCL}
+ - {pin_num: E13, peripheral: GPIO5, signal: 'gpio_io, 21', pin_signal: I2C4_SDA}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : I2C4_DeinitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void I2C4_DeinitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SCL_GPIO5_IO20, 0U);
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_GPIO5_IO21, 0U);
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+I2C4_InitPins:
+- options: {callFromInitBoot: 'false', coreID: cm4}
+- pin_list:
+ - {pin_num: D13, peripheral: I2C4, signal: i2c_scl, pin_signal: I2C4_SCL, PE: Disabled, PUE: Disabled, HYS: Enabled, SION: ENABLED, DSE: X6_0}
+ - {pin_num: E13, peripheral: I2C4, signal: i2c_sda, pin_signal: I2C4_SDA, PE: Disabled, HYS: Enabled, SION: ENABLED, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : I2C4_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void I2C4_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SCL_I2C4_SCL, 1U);
+ IOMUXC_SetPinConfig(IOMUXC_I2C4_SCL_I2C4_SCL,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_I2C4_SDA, 1U);
+ IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_I2C4_SDA,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/pin_mux.h b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/pin_mux.h
new file mode 100644
index 000000000..9f9b5590e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/pin_mux.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+
+/* Symbols to be used with GPIO driver */
+#define I2C4_DEINITPINS_I2C4_SCL_GPIO_PIN_MASK (1U << 20U) /*!< GPIO pin mask */
+
+/* Symbols to be used with GPIO driver */
+#define I2C4_DEINITPINS_I2C4_SDA_GPIO_PIN_MASK (1U << 21U) /*!< GPIO pin mask */
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void I2C4_DeinitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void I2C4_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/readme.txt b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/readme.txt
new file mode 100644
index 000000000..fe826019d
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/i2c/int_b2b_transfer/slave/readme.txt
@@ -0,0 +1,67 @@
+Overview
+========
+CMSIS-Driver defines generic peripheral driver interfaces for middleware making it reusable across a wide
+range of supported microcontroller devices. The API connects microcontroller peripherals with middleware
+that implements for example communication stacks, file systems, or graphic user interfaces.
+More information and usage method please refer to http://www.keil.com/pack/doc/cmsis/Driver/html/index.html.
+
+The i2c_interrupt_b2b_transfer_master example shows how to use CMSIS i2c driver as master to do board to board transfer
+with interrupt:
+
+In this example, one i2c instance as master and another i2c instance on the other board as slave. Master sends a
+piece of data to slave, and receive a piece of data from slave. This example checks if the data received from
+slave is correct.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+I2C one board:
+ + Transfer data from SLAVE_BOARD to MASTER_BOARD of I2C interface, I2C4 pins of SLAVE_BOARD are connected with
+ I2C4 pins of MASTER_BOARD
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+SLAVE_BOARD CONNECTS TO MASTER_BOARD
+Pin Name Board Location Pin Name Board Location
+For I2C4 connection, refer to: https://variwiki.com/index.php?title=MCUXpresso&release=MCUXPRESSO_2.13.0_V1.0_DART-MX8M-MINI#Demos_pins
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the demo runs successfully, the following message is displayed in the terminal:
+
+CMSIS I2C board2board interrupt example -- Slave transfer.
+
+
+Slave received data :
+0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7
+0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f
+0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
+
+
+End of I2C example .
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/RTE_Device.h b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/RTE_Device.h
new file mode 100644
index 000000000..0921ebb79
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/RTE_Device.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _RTE_DEVICE_H
+#define _RTE_DEVICE_H
+
+extern void UART3_InitPins();
+extern void UART3_DeinitPins();
+
+/* Driver name mapping. */
+/* User needs to provide the implementation of UARTX_GetFreq/UARTX_InitPins/UARTX_DeinitPins for the enabled UART
+ * instance. */
+#define RTE_USART3 1
+#define RTE_USART3_PIN_INIT UART3_InitPins
+#define RTE_USART3_PIN_DEINIT UART3_DeinitPins
+#define RTE_USART3_DMA_EN 0
+
+/* UART configuration. */
+#define USART_RX_BUFFER_LEN 64
+#define USART4_RX_BUFFER_ENABLE 1
+
+#endif /* _RTE_DEVICE_H */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/CMakeLists.txt b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..1be4088ad
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/CMakeLists.txt
@@ -0,0 +1,120 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(cmsis_iuart_interrupt_transfer)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME cmsis_iuart_interrupt_transfer.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../cmsis_usart_interrupt_transfer.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../RTE_Device.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6/cmsis_drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+ ${SdkRootDirPath}/CMSIS/Driver/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_cmsis_iuart_MIMX8MM6)
+
+include(driver_iuart_sdma_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(CMSIS_Driver_Include_USART_MIMX8MM6)
+
+include(CMSIS_Driver_Include_Common_MIMX8MM6)
+
+include(driver_sdma_MIMX8MM6)
+
+include(driver_memory_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/cmsis_iuart_interrupt_transfer.bin)
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_all.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_all.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_flash_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_flash_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/clean.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/clean.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/config.cmake b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/flags.cmake b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/board.c b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/board.h b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/clock_config.c b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/clock_config.h b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/cmsis_iuart_interrupt_transfer_v3_10.xml b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/cmsis_iuart_interrupt_transfer_v3_10.xml
new file mode 100644
index 000000000..d67e38733
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/cmsis_iuart_interrupt_transfer_v3_10.xml
@@ -0,0 +1,137 @@
+
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diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/cmsis_usart_interrupt_transfer.c b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/cmsis_usart_interrupt_transfer.c
new file mode 100644
index 000000000..9e0bcbad5
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/cmsis_usart_interrupt_transfer.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+#include "fsl_uart_cmsis.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DEMO_USART Driver_USART3
+#define ECHO_BUFFER_LENGTH 8
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/* USART user SignalEvent */
+void USART_SignalEvent_t(uint32_t event);
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+const uint8_t g_tipString[] =
+ "USART CMSIS interrupt example\r\nBoard receives 8 characters then sends them out\r\nNow please input:\r\n";
+uint8_t g_txBuffer[ECHO_BUFFER_LENGTH] = {0};
+uint8_t g_rxBuffer[ECHO_BUFFER_LENGTH] = {0};
+volatile bool rxBufferEmpty = true;
+volatile bool txBufferFull = false;
+volatile bool txOnGoing = false;
+volatile bool rxOnGoing = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+uint32_t UART3_GetFreq(void)
+{
+ return BOARD_DEBUG_UART_CLK_FREQ;
+}
+void USART_SignalEvent_t(uint32_t event)
+{
+ if (ARM_USART_EVENT_SEND_COMPLETE == event)
+ {
+ txBufferFull = false;
+ txOnGoing = false;
+ }
+
+ if (ARM_USART_EVENT_RECEIVE_COMPLETE == event)
+ {
+ rxBufferEmpty = false;
+ rxOnGoing = false;
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ uint32_t i;
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitMemory();
+
+ DEMO_USART.Initialize(USART_SignalEvent_t);
+ DEMO_USART.PowerControl(ARM_POWER_FULL);
+
+ /* Set baudrate. */
+ DEMO_USART.Control(ARM_USART_MODE_ASYNCHRONOUS, BOARD_DEBUG_UART_BAUDRATE);
+
+ txOnGoing = true;
+ DEMO_USART.Send(g_tipString, sizeof(g_tipString) - 1);
+
+ /* Wait send finished */
+ while (txOnGoing)
+ {
+ }
+
+ while (1)
+ {
+ /* If g_txBuffer is empty and g_rxBuffer is full, copy g_rxBuffer to g_txBuffer. */
+ if ((!rxBufferEmpty) && (!txBufferFull))
+ {
+ memcpy(g_txBuffer, g_rxBuffer, ECHO_BUFFER_LENGTH);
+ rxBufferEmpty = true;
+ txBufferFull = true;
+ }
+
+ /* If RX is idle and g_rxBuffer is empty, start to read data to g_rxBuffer. */
+ if ((!rxOnGoing) && rxBufferEmpty)
+ {
+ rxOnGoing = true;
+ DEMO_USART.Receive(g_rxBuffer, ECHO_BUFFER_LENGTH);
+ }
+
+ /* If TX is idle and g_txBuffer is full, start to send data. */
+ if ((!txOnGoing) && txBufferFull)
+ {
+ txOnGoing = true;
+ DEMO_USART.Send(g_txBuffer, ECHO_BUFFER_LENGTH);
+ }
+
+ /* Delay some time, simulate the app is processing other things, input data save to ring buffer. */
+ i = 0x10000U;
+ while (i--)
+ {
+ __NOP();
+ }
+ }
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/empty_rsc_table.c b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/fsl_iomuxc.h b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/pin_mux.c b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/pin_mux.c
new file mode 100644
index 000000000..dfe15f088
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/pin_mux.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+UART3_InitPins:
+- options: {callFromInitBoot: 'false', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : UART3_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void UART3_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+UART3_DeinitPins:
+- options: {callFromInitBoot: 'false', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : UART3_DeinitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void UART3_DeinitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/pin_mux.h b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/pin_mux.h
new file mode 100644
index 000000000..37fe8a517
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/pin_mux.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void UART3_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void UART3_DeinitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/readme.txt b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/readme.txt
new file mode 100644
index 000000000..5acc4f4ee
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/interrupt_transfer/readme.txt
@@ -0,0 +1,56 @@
+Overview
+========
+CMSIS-Driver defines generic peripheral driver interfaces for middleware making it reusable across a wide
+range of supported microcontroller devices. The API connects microcontroller peripherals with middleware
+that implements for example communication stacks, file systems, or graphic user interfaces.
+More information and usage method please refer to http://www.keil.com/pack/doc/cmsis/Driver/html/index.html.
+
+The cmsis_uart_interrupt_transfer example shows how to use uart cmsis driver in interrupt way:
+
+In this example, one uart instance connect to PC through uart, the board will
+send back all characters that PC send to the board.
+
+Note: The example echo every 8 characters, so input 8 characters every time.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
+
+
+Running the demo
+================
+When the demo runs successfully, the log would be seen on the debug terminal like:
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+USART CMSIS interrupt example
+Board receives 8 characters then sends them out
+Now please input:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/RTE_Device.h b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/RTE_Device.h
new file mode 100644
index 000000000..7466a2111
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/RTE_Device.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _RTE_DEVICE_H
+#define _RTE_DEVICE_H
+
+extern void UART3_InitPins();
+extern void UART3_DeinitPins();
+
+/* Driver name mapping. */
+/* User needs to provide the implementation of UARTX_GetFreq/UARTX_InitPins/UARTX_DeinitPins for the enabled UART
+ * instance. */
+#define RTE_USART3 1
+#define RTE_USART3_PIN_INIT UART3_InitPins
+#define RTE_USART3_PIN_DEINIT UART3_DeinitPins
+#define RTE_USART3_DMA_EN 1
+
+/* UART configuration. */
+#define USART_RX_BUFFER_LEN 64
+#define USART4_RX_BUFFER_ENABLE 0
+
+#define RTE_USART3_SDMA_TX_CH 2
+#define RTE_USART3_SDMA_TX_REQUEST (27)
+#define RTE_USART3_SDMA_TX_DMA_BASE SDMAARM1
+#define RTE_USART3_SDMA_TX_PRIORITY (3)
+#define RTE_USART3_SDMA_RX_CH 1
+#define RTE_USART3_SDMA_RX_REQUEST (26)
+#define RTE_USART3_SDMA_RX_DMA_BASE SDMAARM1
+#define RTE_USART3_SDMA_RX_PRIORITY (4)
+
+#endif /* _RTE_DEVICE_H */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/CMakeLists.txt b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..9a37ebb37
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/CMakeLists.txt
@@ -0,0 +1,122 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(cmsis_iuart_sdma_transfer)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME cmsis_iuart_sdma_transfer.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../cmsis_usart_sdma_transfer.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../RTE_Device.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/cmsis_drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+ ${SdkRootDirPath}/CMSIS/Driver/Include
+)
+
+# include modules
+include(driver_cache_lmem_MIMX8MM6)
+
+include(driver_iuart_sdma_MIMX8MM6)
+
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_cmsis_iuart_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(driver_sdma_MIMX8MM6)
+
+include(driver_memory_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(CMSIS_Driver_Include_USART_MIMX8MM6)
+
+include(CMSIS_Driver_Include_Common_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/cmsis_iuart_sdma_transfer.bin)
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_all.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_all.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_flash_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_flash_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_release.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_release.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/clean.bat b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/clean.sh b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/config.cmake b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/flags.cmake b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/board.c b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/board.c
new file mode 100644
index 000000000..7ac3cfc4e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/board.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+#include "fsl_cache.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /*
+ * Flush the system cache before updating the cache policy. Without flushing, the
+ * previously done initialization of the non-cacheable sections will be discarded
+ * as the cache for this region was enabled with the write-back attribute before.
+ */
+ L1CACHE_CleanSystemCache();
+ __DSB();
+ __ISB();
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/board.h b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/clock_config.c b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/clock_config.h b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/cmsis_iuart_sdma_transfer_v3_10.xml b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/cmsis_iuart_sdma_transfer_v3_10.xml
new file mode 100644
index 000000000..f5df6e278
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/cmsis_iuart_sdma_transfer_v3_10.xml
@@ -0,0 +1,137 @@
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diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/cmsis_usart_sdma_transfer.c b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/cmsis_usart_sdma_transfer.c
new file mode 100644
index 000000000..b5575feb2
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/cmsis_usart_sdma_transfer.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+#include "fsl_uart_cmsis.h"
+#include "fsl_rdc.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DEMO_USART Driver_USART3
+#define EXAMPLE_UART_DMA_BASEADDR SDMAARM1
+#define ECHO_BUFFER_LENGTH 8
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+AT_NONCACHEABLE_SECTION_INIT(uint8_t g_tipString[]) =
+ "USART CMSIS SDMA example.\r\nBoard receives 8 characters then sends them out.\r\nNow please input:\r\n";
+AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint8_t g_txBuffer[ECHO_BUFFER_LENGTH], 4) = {0};
+AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint8_t g_rxBuffer[ECHO_BUFFER_LENGTH], 4) = {0};
+
+volatile bool rxBufferEmpty = true;
+volatile bool txBufferFull = false;
+volatile bool txOnGoing = false;
+volatile bool rxOnGoing = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+uint32_t UART3_GetFreq(void)
+{
+ return BOARD_DEBUG_UART_CLK_FREQ;
+}
+
+/* USART callback */
+void USART_Callback(uint32_t event)
+{
+ if (event == ARM_USART_EVENT_SEND_COMPLETE)
+ {
+ txBufferFull = false;
+ txOnGoing = false;
+ }
+
+ if (event == ARM_USART_EVENT_RECEIVE_COMPLETE)
+ {
+ rxBufferEmpty = false;
+ rxOnGoing = false;
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ sdma_config_t sdmaConfig;
+ /* Only configure the RDC if RDC peripheral write access is allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, RDC_GetCurrentMasterDomainId(RDC))) != 0U)
+ {
+ /*set SDMA1 PERIPH to M4 Domain(DID=1),due to UART not be accessible by DID=0 by default*/
+ rdc_domain_assignment_t assignment = {0};
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_SDMA1_PERIPH, &assignment);
+ }
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitMemory();
+
+ /* Init the SDMA module */
+ SDMA_GetDefaultConfig(&sdmaConfig);
+ SDMA_Init(EXAMPLE_UART_DMA_BASEADDR, &sdmaConfig);
+ DEMO_USART.Initialize(USART_Callback);
+ DEMO_USART.PowerControl(ARM_POWER_FULL);
+
+ /* Set baudrate. */
+ DEMO_USART.Control(ARM_USART_MODE_ASYNCHRONOUS, BOARD_DEBUG_UART_BAUDRATE);
+
+ /* Send g_tipString out. */
+ txOnGoing = true;
+
+ DEMO_USART.Send(g_tipString, sizeof(g_tipString) - 1);
+
+ /* Wait send finished */
+ while (txOnGoing)
+ {
+ }
+
+ while (1)
+ {
+ /* If RX is idle and g_rxBuffer is empty, start to read data to g_rxBuffer. */
+ if ((!rxOnGoing) && rxBufferEmpty)
+ {
+ rxOnGoing = true;
+ DEMO_USART.Receive(g_rxBuffer, ECHO_BUFFER_LENGTH);
+ }
+
+ /* If TX is idle and g_txBuffer is full, start to send data. */
+ if ((!txOnGoing) && txBufferFull)
+ {
+ txOnGoing = true;
+ DEMO_USART.Send(g_txBuffer, ECHO_BUFFER_LENGTH);
+ }
+
+ /* If g_txBuffer is empty and g_rxBuffer is full, copy g_rxBuffer to g_txBuffer. */
+ if ((!rxBufferEmpty) && (!txBufferFull))
+ {
+ memcpy(g_txBuffer, g_rxBuffer, ECHO_BUFFER_LENGTH);
+ rxBufferEmpty = true;
+ txBufferFull = true;
+ }
+ }
+}
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/empty_rsc_table.c b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/fsl_iomuxc.h b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/pin_mux.c b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/pin_mux.c
new file mode 100644
index 000000000..dfe15f088
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/pin_mux.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+UART3_InitPins:
+- options: {callFromInitBoot: 'false', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : UART3_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void UART3_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+UART3_DeinitPins:
+- options: {callFromInitBoot: 'false', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : UART3_DeinitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void UART3_DeinitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/pin_mux.h b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/pin_mux.h
new file mode 100644
index 000000000..37fe8a517
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/pin_mux.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void UART3_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void UART3_DeinitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/readme.txt b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/readme.txt
new file mode 100644
index 000000000..06c0f12c7
--- /dev/null
+++ b/boards/dart_mx8mm/cmsis_driver_examples/uart/sdma_transfer/readme.txt
@@ -0,0 +1,56 @@
+Overview
+========
+CMSIS-Driver defines generic peripheral driver interfaces for middleware making it reusable across a wide
+range of supported microcontroller devices. The API connects microcontroller peripherals with middleware
+that implements for example communication stacks, file systems, or graphic user interfaces.
+More information and usage method please refer to http://www.keil.com/pack/doc/cmsis/Driver/html/index.html.
+
+The cmsis_uart_sdma_transfer example shows how to use uart cmsis driver with SDMA:
+
+In this example, one uart instance connect to PC through uart, the board will
+send back all characters that PC send to the board.
+
+Note: The example echo every 8 characters, so input 8 characters every time.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
+
+
+Running the demo
+================
+When the demo runs successfully, the log would be seen on the debug terminal like:
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+USART CMSIS SDMA example
+Board receives 8 characters then sends them out
+Now please input:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/CMakeLists.txt b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..e53f793dc
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/CMakeLists.txt
@@ -0,0 +1,105 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(hello_world)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME hello_world.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../hello_world.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/hello_world.bin)
+
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_all.bat b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_all.bat
new file mode 100644
index 000000000..02d62fd34
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_all.sh b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_all.sh
new file mode 100755
index 000000000..702783475
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..c84d78542
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..5aa41a2df
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..3fd6f4a78
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c9e344144
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_debug.bat b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_debug.bat
new file mode 100644
index 000000000..15123387e
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_debug.sh b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_debug.sh
new file mode 100755
index 000000000..42803761b
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..acb3c2d91
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..1ce9d36e7
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_flash_release.bat b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..83f20fc3c
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_flash_release.sh b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..f3694ad2e
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_release.bat b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_release.bat
new file mode 100644
index 000000000..a88e3d668
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_release.sh b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_release.sh
new file mode 100755
index 000000000..47cfb057c
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/clean.bat b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/clean.sh b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/config.cmake b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/armgcc/flags.cmake b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/flags.cmake
new file mode 100755
index 000000000..089d1ed37
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/armgcc/flags.cmake
@@ -0,0 +1,527 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DPRINTF_FLOAT_ENABLE=0 \
+ -DSCANF_FLOAT_ENABLE=0 \
+ -DPRINTF_ADVANCED_ENABLE=0 \
+ -DSCANF_ADVANCED_ENABLE=0 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DPRINTF_FLOAT_ENABLE=0 \
+ -DSCANF_FLOAT_ENABLE=0 \
+ -DPRINTF_ADVANCED_ENABLE=0 \
+ -DSCANF_ADVANCED_ENABLE=0 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DPRINTF_FLOAT_ENABLE=0 \
+ -DSCANF_FLOAT_ENABLE=0 \
+ -DPRINTF_ADVANCED_ENABLE=0 \
+ -DSCANF_ADVANCED_ENABLE=0 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DPRINTF_FLOAT_ENABLE=0 \
+ -DSCANF_FLOAT_ENABLE=0 \
+ -DPRINTF_ADVANCED_ENABLE=0 \
+ -DSCANF_ADVANCED_ENABLE=0 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DPRINTF_FLOAT_ENABLE=0 \
+ -DSCANF_FLOAT_ENABLE=0 \
+ -DPRINTF_ADVANCED_ENABLE=0 \
+ -DSCANF_ADVANCED_ENABLE=0 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DPRINTF_FLOAT_ENABLE=0 \
+ -DSCANF_FLOAT_ENABLE=0 \
+ -DPRINTF_ADVANCED_ENABLE=0 \
+ -DSCANF_ADVANCED_ENABLE=0 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/board.c b/boards/dart_mx8mm/demo_apps/hello_world/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/board.h b/boards/dart_mx8mm/demo_apps/hello_world/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/clock_config.c b/boards/dart_mx8mm/demo_apps/hello_world/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/clock_config.h b/boards/dart_mx8mm/demo_apps/hello_world/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/empty_rsc_table.c b/boards/dart_mx8mm/demo_apps/hello_world/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/fsl_iomuxc.h b/boards/dart_mx8mm/demo_apps/hello_world/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/hello_world.bin b/boards/dart_mx8mm/demo_apps/hello_world/hello_world.bin
new file mode 100755
index 000000000..8c2c0ca55
Binary files /dev/null and b/boards/dart_mx8mm/demo_apps/hello_world/hello_world.bin differ
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/hello_world.c b/boards/dart_mx8mm/demo_apps/hello_world/hello_world.c
new file mode 100644
index 000000000..d1f35d920
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/hello_world.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ char ch;
+
+ /* Init board hardware. */
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ PRINTF("hello world.\r\n");
+
+ while (1)
+ {
+ ch = GETCHAR();
+ PUTCHAR(ch);
+ }
+}
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/hello_world_v3_10.xml b/boards/dart_mx8mm/demo_apps/hello_world/hello_world_v3_10.xml
new file mode 100644
index 000000000..6e9df0782
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/hello_world_v3_10.xml
@@ -0,0 +1,136 @@
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diff --git a/boards/dart_mx8mm/demo_apps/hello_world/pin_mux.c b/boards/dart_mx8mm/demo_apps/hello_world/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/pin_mux.h b/boards/dart_mx8mm/demo_apps/hello_world/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/demo_apps/hello_world/readme.txt b/boards/dart_mx8mm/demo_apps/hello_world/readme.txt
new file mode 100644
index 000000000..c454b2805
--- /dev/null
+++ b/boards/dart_mx8mm/demo_apps/hello_world/readme.txt
@@ -0,0 +1,47 @@
+Overview
+========
+The Hello World demo application provides a sanity check for the new SDK build environments and board bring up. The Hello
+World demo prints the "Hello World" string to the terminal using the SDK UART drivers. The purpose of this demo is to
+show how to use the UART, and to provide a simple project for debugging and further development.
+Note: Please input one character at a time. If you input too many characters each time, the receiver may overflow
+because the low level UART uses simple polling way for receiving. If you want to try inputting many characters each time,
+just define DEBUG_CONSOLE_TRANSFER_NON_BLOCKING in your project to use the advanced debug console utility.
+
+Toolchain supported
+===================
+- GCC ARM Embedded 10.3.1
+- IAR embedded Workbench 9.32.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+The log below shows the output of the hello world demo in the terminal window:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+hello world.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..7d16df03f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(ecspi_loopback)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME ecspi_loopback.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../ecspi_loopback.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_ecspi_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ecspi_loopback.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/flags.cmake
new file mode 100755
index 000000000..089d1ed37
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/armgcc/flags.cmake
@@ -0,0 +1,527 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DPRINTF_FLOAT_ENABLE=0 \
+ -DSCANF_FLOAT_ENABLE=0 \
+ -DPRINTF_ADVANCED_ENABLE=0 \
+ -DSCANF_ADVANCED_ENABLE=0 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DPRINTF_FLOAT_ENABLE=0 \
+ -DSCANF_FLOAT_ENABLE=0 \
+ -DPRINTF_ADVANCED_ENABLE=0 \
+ -DSCANF_ADVANCED_ENABLE=0 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DPRINTF_FLOAT_ENABLE=0 \
+ -DSCANF_FLOAT_ENABLE=0 \
+ -DPRINTF_ADVANCED_ENABLE=0 \
+ -DSCANF_ADVANCED_ENABLE=0 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DPRINTF_FLOAT_ENABLE=0 \
+ -DSCANF_FLOAT_ENABLE=0 \
+ -DPRINTF_ADVANCED_ENABLE=0 \
+ -DSCANF_ADVANCED_ENABLE=0 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DPRINTF_FLOAT_ENABLE=0 \
+ -DSCANF_FLOAT_ENABLE=0 \
+ -DPRINTF_ADVANCED_ENABLE=0 \
+ -DSCANF_ADVANCED_ENABLE=0 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DPRINTF_FLOAT_ENABLE=0 \
+ -DSCANF_FLOAT_ENABLE=0 \
+ -DPRINTF_ADVANCED_ENABLE=0 \
+ -DSCANF_ADVANCED_ENABLE=0 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/board.c b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/board.h b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/clock_config.c b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/clock_config.h b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/ecspi_loopback.c b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/ecspi_loopback.c
new file mode 100644
index 000000000..deab8fabd
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/ecspi_loopback.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "fsl_ecspi.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define ECSPI_TRANSFER_SIZE 64
+#define ECSPI_TRANSFER_BAUDRATE 500000U
+#define ECSPI_MASTER_BASEADDR ECSPI1
+#define ECSPI_MASTER_CLK_FREQ \
+ (CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootEcspi1)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootEcspi1)))
+#define ECSPI_MASTER_TRANSFER_CHANNEL kECSPI_Channel0
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ uint8_t i;
+ ecspi_transfer_t masterXfer;
+ ecspi_master_config_t masterConfig;
+ uint32_t masterRxData[ECSPI_TRANSFER_SIZE] = {0};
+ uint32_t masterTxData[ECSPI_TRANSFER_SIZE] = {0};
+
+ /* Init board hardware. */
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ CLOCK_SetRootMux(kCLOCK_RootEcspi1, kCLOCK_EcspiRootmuxSysPll1); /* Set ECSPI1 source to SYSTEM PLL1 800MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootEcspi1, 2U, 5U); /* Set root clock to 800MHZ / 10 = 80MHZ */
+
+ PRINTF("\r\n***ECSPI Loopback Demo***\r\n");
+ PRINTF("\r\nThis demo is a loopback transfer test for ECSPI.\r\n");
+ PRINTF("The ECSPI will connect the transmitter and receiver sections internally.\r\n");
+ PRINTF("So, there is no need to connect the MOSI and MISO pins.\r\n");
+
+ /* Master config:
+ * masterConfig.channel = kECSPI_Channel0;
+ * masterConfig.burstLength = 8;
+ * masterConfig.samplePeriodClock = kECSPI_spiClock;
+ * masterConfig.baudRate_Bps = TRANSFER_BAUDRATE;
+ * masterConfig.chipSelectDelay = 0;
+ * masterConfig.samplePeriod = 0;
+ * masterConfig.txFifoThreshold = 1;
+ * masterConfig.rxFifoThreshold = 0;
+ * masterConfig.enableLoopback = true;
+ */
+ ECSPI_MasterGetDefaultConfig(&masterConfig);
+ masterConfig.baudRate_Bps = ECSPI_TRANSFER_BAUDRATE;
+ masterConfig.enableLoopback = true;
+ ECSPI_MasterInit(ECSPI_MASTER_BASEADDR, &masterConfig, ECSPI_MASTER_CLK_FREQ);
+
+ for (i = 0; i < ECSPI_TRANSFER_SIZE; i++)
+ {
+ masterTxData[i] = i;
+ }
+ /*Start master transfer*/
+ masterXfer.txData = masterTxData;
+ masterXfer.rxData = masterRxData;
+ masterXfer.dataSize = ECSPI_TRANSFER_SIZE;
+ masterXfer.channel = ECSPI_MASTER_TRANSFER_CHANNEL;
+ ECSPI_MasterTransferBlocking(ECSPI_MASTER_BASEADDR, &masterXfer);
+
+ /* Compare Tx and Rx data. */
+ for (i = 0; i < ECSPI_TRANSFER_SIZE; i++)
+ {
+ if (masterTxData[i] != masterRxData[i])
+ {
+ break;
+ }
+ }
+
+ if (ECSPI_TRANSFER_SIZE == i)
+ {
+ PRINTF("\r\nECSPI loopback test pass!");
+ }
+ else
+ {
+ PRINTF("\r\nECSPI loopback test fail!");
+ }
+
+ /* Deinit the ECSPI. */
+ ECSPI_Deinit(ECSPI_MASTER_BASEADDR);
+
+ while (1)
+ {
+ __NOP();
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/ecspi_loopback_v3_10.xml b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/ecspi_loopback_v3_10.xml
new file mode 100644
index 000000000..066f5e2f3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/ecspi_loopback_v3_10.xml
@@ -0,0 +1,135 @@
+
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diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/pin_mux.c b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/pin_mux.h b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/readme.txt b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/readme.txt
new file mode 100644
index 000000000..79744fa60
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/ecspi_loopback/readme.txt
@@ -0,0 +1,52 @@
+Overview
+========
+The ecspi_loopback demo shows how the ecspi do a loopback transfer internally.
+The ECSPI connects the transmitter and receiver sections internally, and the data shifted out from the
+most-significant bit of the shift register is looped back into the least-significant bit of the Shift register.
+In this way, a self-test of the complete transmit/receive path can be made. The output pins are not affected,
+and the input pins are ignored.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- MCIMX8MM6-EVK board
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+If the demo run successfully, the below log will be print in the terminal window:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+***ECSPI Loopback Demo***
+
+This demo is a loopback transfer test for ECSPI.
+The ECSPI will connect the transmitter and receiver sections internally.
+So, there is no need to connect the MOSI and MISO pins.
+
+ECSPI loopback test pass!
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..f7d28c210
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(ecspi_interrupt_b2b_transfer_master)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME ecspi_interrupt_b2b_transfer_master.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../ecspi_interrupt_b2b_transfer_master.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_ecspi_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ecspi_interrupt_b2b_transfer_master.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_all.bat
new file mode 100644
index 000000000..6868c7569
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_all.sh
new file mode 100755
index 000000000..888128e66
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..8771607cb
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..1f660e5af
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..0dfc882b6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..cbb10c43f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_debug.bat
new file mode 100644
index 000000000..0636e21b5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_debug.sh
new file mode 100755
index 000000000..30c0ab2d5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..f0275ea6a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..35370ab2f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..51e8b73fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..ef8236b19
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_release.bat
new file mode 100644
index 000000000..a34003e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_release.sh
new file mode 100755
index 000000000..012619cda
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/board.c b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/board.h b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/clock_config.c b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/clock_config.h b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/ecspi_interrupt_b2b_transfer_master.c b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/ecspi_interrupt_b2b_transfer_master.c
new file mode 100644
index 000000000..601f35fba
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/ecspi_interrupt_b2b_transfer_master.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "fsl_ecspi.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_ECSPI_MASTER_BASEADDR ECSPI1
+#define EXAMPLE_ECSPI_DEALY_COUNT 1000000
+#define ECSPI_MASTER_CLK_FREQ \
+ (CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootEcspi1)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootEcspi1)))
+#define TRANSFER_SIZE 64U /*! Transfer dataSize */
+#define TRANSFER_BAUDRATE 500000U /*! Transfer baudrate - 500k */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/* ECSPI user callback */
+void ECSPI_MasterUserCallback(ECSPI_Type *base, ecspi_master_handle_t *handle, status_t status, void *userData);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+uint32_t masterRxData[TRANSFER_SIZE] = {0U};
+uint32_t masterTxData[TRANSFER_SIZE] = {0U};
+
+ecspi_master_handle_t g_m_handle;
+volatile bool isTransferCompleted = false;
+volatile uint32_t g_systickCounter = 20U;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void SysTick_Handler(void)
+{
+ if (g_systickCounter != 0U)
+ {
+ g_systickCounter--;
+ }
+}
+
+void ECSPI_MasterUserCallback(ECSPI_Type *base, ecspi_master_handle_t *handle, status_t status, void *userData)
+{
+ if (status == kStatus_Success)
+ {
+ isTransferCompleted = true;
+ }
+
+ if (status == kStatus_ECSPI_HardwareOverFlow)
+ {
+ PRINTF("Hardware overflow occurred in this transfer. \r\n");
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ CLOCK_SetRootMux(kCLOCK_RootEcspi1, kCLOCK_EcspiRootmuxSysPll1); /* Set ECSPI1 source to SYSTEM PLL1 800MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootEcspi1, 2U, 5U); /* Set root clock to 800MHZ / 10 = 80MHZ */
+
+ PRINTF("ECSPI board to board interrupt example.\r\n");
+ PRINTF("This example use one board as master and another as slave.\r\n");
+ PRINTF("Master and slave uses interrupt way. Slave should start first. \r\n");
+ PRINTF("Please make sure you make the correct line connection. Basically, the connection is: \r\n");
+ PRINTF("ECSPI_master -- ECSPI_slave \r\n");
+ PRINTF(" CLK -- CLK \r\n");
+ PRINTF(" PCS -- PCS \r\n");
+ PRINTF(" MOSI -- MOSI \r\n");
+ PRINTF(" MISO -- MISO \r\n");
+ PRINTF(" GND -- GND \r\n");
+
+ uint32_t errorCount;
+ uint32_t loopCount = 1;
+ uint32_t i;
+ ecspi_master_config_t masterConfig;
+ ecspi_transfer_t masterXfer;
+
+ /* Master config:
+ * masterConfig.channel = kECSPI_Channel0;
+ * masterConfig.burstLength = 8;
+ * masterConfig.samplePeriodClock = kECSPI_spiClock;
+ * masterConfig.baudRate_Bps = TRANSFER_BAUDRATE;
+ * masterConfig.chipSelectDelay = 0;
+ * masterConfig.samplePeriod = 0;
+ * masterConfig.txFifoThreshold = 1;
+ * masterConfig.rxFifoThreshold = 0;
+ */
+ ECSPI_MasterGetDefaultConfig(&masterConfig);
+ masterConfig.baudRate_Bps = TRANSFER_BAUDRATE;
+
+ ECSPI_MasterInit(EXAMPLE_ECSPI_MASTER_BASEADDR, &masterConfig, ECSPI_MASTER_CLK_FREQ);
+
+ ECSPI_MasterTransferCreateHandle(EXAMPLE_ECSPI_MASTER_BASEADDR, &g_m_handle, ECSPI_MasterUserCallback, NULL);
+
+ while (1)
+ {
+ /* Set up the transfer data */
+ for (i = 0U; i < TRANSFER_SIZE; i++)
+ {
+ masterTxData[i] = (i + loopCount) % 256U;
+ masterRxData[i] = 0U;
+ }
+
+ /* Print out transmit buffer */
+ PRINTF("\r\n Master transmit:\r\n");
+ for (i = 0U; i < TRANSFER_SIZE; i++)
+ {
+ /* Print 16 numbers in a line */
+ if ((i & 0x0FU) == 0U)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF(" %02X", masterTxData[i]);
+ }
+ PRINTF("\r\n");
+
+ /* Start master transfer, send data to slave */
+ isTransferCompleted = false;
+ masterXfer.txData = masterTxData;
+ masterXfer.rxData = NULL;
+ masterXfer.dataSize = TRANSFER_SIZE;
+ masterXfer.channel = kECSPI_Channel0;
+ ECSPI_MasterTransferNonBlocking(EXAMPLE_ECSPI_MASTER_BASEADDR, &g_m_handle, &masterXfer);
+
+ /* Wait transfer complete */
+ while (!isTransferCompleted)
+ {
+ }
+
+ /* Delay to wait slave is ready */
+ if (SysTick_Config(SystemCoreClock / 1000U))
+ {
+ while (1)
+ {
+ }
+ }
+ /* Delay 20 ms */
+ g_systickCounter = 20U;
+ while (g_systickCounter != 0U)
+ {
+ }
+
+ /* Start master transfer, receive data from slave */
+ isTransferCompleted = false;
+ masterXfer.txData = NULL;
+ masterXfer.rxData = masterRxData;
+ masterXfer.dataSize = TRANSFER_SIZE;
+ masterXfer.channel = kECSPI_Channel0;
+ PRINTF("Start receive data from slave.\r\n");
+ ECSPI_MasterTransferNonBlocking(EXAMPLE_ECSPI_MASTER_BASEADDR, &g_m_handle, &masterXfer);
+
+ while (!isTransferCompleted)
+ {
+ }
+
+ errorCount = 0U;
+ for (i = 0U; i < TRANSFER_SIZE; i++)
+ {
+ if (masterTxData[i] != masterRxData[i])
+ {
+ errorCount++;
+ }
+ }
+ if (errorCount == 0U)
+ {
+ PRINTF(" \r\nECSPI transfer all data matched! \r\n");
+ /* Print out receive buffer */
+ PRINTF("\r\n Master received:\r\n");
+ for (i = 0U; i < TRANSFER_SIZE; i++)
+ {
+ /* Print 16 numbers in a line */
+ if ((i & 0x0FU) == 0U)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF(" %02X", masterRxData[i]);
+ }
+ PRINTF("\r\n");
+ }
+ else
+ {
+ PRINTF(" \r\nError occurred in ECSPI transfer ! \r\n");
+ }
+
+ /* Wait for press any key */
+ PRINTF("\r\n Press any key to run again\r\n");
+ GETCHAR();
+
+ /* Increase loop count to change transmit buffer */
+ loopCount++;
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/ecspi_interrupt_b2b_transfer_master_v3_10.xml b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/ecspi_interrupt_b2b_transfer_master_v3_10.xml
new file mode 100644
index 000000000..2957d6ba0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/ecspi_interrupt_b2b_transfer_master_v3_10.xml
@@ -0,0 +1,131 @@
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diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/pin_mux.c b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/pin_mux.c
new file mode 100644
index 000000000..e4062d1b6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/pin_mux.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2018, 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v10.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 0.10.12
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D6, peripheral: ECSPI1, signal: ecspi_sclk, pin_signal: ECSPI1_SCLK, PE: Enabled, PUE: Disabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ - {pin_num: B6, peripheral: ECSPI1, signal: 'ecspi_ss, 0', pin_signal: ECSPI1_SS0, PE: Enabled, PUE: Enabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ - {pin_num: B7, peripheral: ECSPI1, signal: ecspi_mosi, pin_signal: ECSPI1_MOSI, PE: Disabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ - {pin_num: A7, peripheral: ECSPI1, signal: ecspi_miso, pin_signal: ECSPI1_MISO, PE: Disabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_MISO_ECSPI1_MISO, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_MISO_ECSPI1_MISO,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
+ IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_SS0_ECSPI1_SS0, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_SS0_ECSPI1_SS0,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
+ IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/pin_mux.h b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/pin_mux.h
new file mode 100644
index 000000000..1d906205a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/pin_mux.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/readme.txt b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/readme.txt
new file mode 100644
index 000000000..71219af77
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/master/readme.txt
@@ -0,0 +1,83 @@
+Overview
+========
+The ecspi_interrupt_b2b_transfer example shows how to use ECSPI driver in interrupt way:
+
+In this example , we need two boards, one board used as ECSPI master and another board used as ECSPI slave.
+The file 'ecspi_interrupt_b2b_transfer_master.c' includes the ECSPI master code.
+This example uses the transactional API in ECSPI driver.
+
+1. ECSPI master send/received data to/from ECSPI slave in interrupt . (ECSPI Slave using interrupt to receive/send the data)
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+ECSPI board to board:
+Transfers data through the instance 1 of the ECSPI interface. ECSPI1 pins of the master board are
+connected to the ECSPI1 pins of the slave board.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MASTER BOARD CONNECTS TO SLAVE BOARD
+Pin Name Board Location Pin Name Board Location
+For ECSPI1 connection, refer to: https://variwiki.com/index.php?title=MCUXpresso&release=MCUXPRESSO_2.13.0_V1.0_DART-MX8M-MINI#Demos_pins
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the demo runs successfully, the log would be seen on the debug terminal like:
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ECSPI board to board interrupt example.
+This example use one board as master and another as slave.
+Master and slave uses interrupt way. Slave should start first.
+Please make sure you make the correct line connection. Basically, the connection is:
+ECSPI_master -- ECSPI_slave
+ CLK -- CLK
+ PCS -- PCS
+ MOSI -- MOSI
+ MISO -- MISO
+ GND -- GND
+
+ Master transmit:
+
+ 1 2 3 4 5 6 7 8 9 A B C D E F 10
+ 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
+ 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30
+ 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40
+
+Start receive data from slave.
+
+ECSPI transfer all data matched!
+
+ Master received:
+
+ 1 2 3 4 5 6 7 8 9 A B C D E F 10
+ 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
+ 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30
+ 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40
+
+ Press any key to run again
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..240e9f43d
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(ecspi_interrupt_b2b_transfer_slave)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME ecspi_interrupt_b2b_transfer_slave.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../ecspi_interrupt_b2b_transfer_slave.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_ecspi_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ecspi_interrupt_b2b_transfer_slave.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_all.bat
new file mode 100644
index 000000000..6868c7569
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_all.sh
new file mode 100755
index 000000000..888128e66
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..8771607cb
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..1f660e5af
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..0dfc882b6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..cbb10c43f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_debug.bat
new file mode 100644
index 000000000..0636e21b5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_debug.sh
new file mode 100755
index 000000000..30c0ab2d5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..f0275ea6a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..35370ab2f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..51e8b73fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..ef8236b19
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_release.bat
new file mode 100644
index 000000000..a34003e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_release.sh
new file mode 100755
index 000000000..012619cda
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/board.c b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/board.h b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/clock_config.c b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/clock_config.h b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/ecspi_interrupt_b2b_transfer_slave.c b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/ecspi_interrupt_b2b_transfer_slave.c
new file mode 100644
index 000000000..56f67e423
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/ecspi_interrupt_b2b_transfer_slave.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "fsl_ecspi.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_ECSPI_SLAVE_BASEADDR ECSPI1
+#define TRANSFER_SIZE 64U /*! Transfer dataSize */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/* ECSPI user callback */
+void ECSPI_SlaveUserCallback(ECSPI_Type *base, ecspi_slave_handle_t *handle, status_t status, void *userData);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+uint32_t slaveRxData[TRANSFER_SIZE] = {0U};
+ecspi_slave_handle_t g_s_handle;
+
+volatile bool isTransferCompleted = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void ECSPI_SlaveUserCallback(ECSPI_Type *base, ecspi_slave_handle_t *handle, status_t status, void *userData)
+{
+ if (status == kStatus_Success)
+ {
+ PRINTF("This is ECSPI slave transfer completed callback. \r\n");
+ PRINTF("It's a successful transfer. \r\n\r\n");
+ isTransferCompleted = true;
+ }
+
+ if (status == kStatus_ECSPI_HardwareOverFlow)
+ {
+ PRINTF("Hardware overflow occurred in this transfer. \r\n");
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ PRINTF("ECSPI board to board interrupt example.\r\n");
+
+ uint32_t i;
+ ecspi_slave_config_t slaveConfig;
+ ecspi_transfer_t slaveXfer;
+
+ /* Slave config:
+ * slaveConfig.channel = kECSPI_Channel0;
+ * slaveConfig.burstLength = 8;
+ * slaveConfig.txFifoThreshold = 1;
+ * slaveConfig.rxFifoThreshold = 0;
+ */
+ ECSPI_SlaveGetDefaultConfig(&slaveConfig);
+ ECSPI_SlaveInit(EXAMPLE_ECSPI_SLAVE_BASEADDR, &slaveConfig);
+
+ ECSPI_SlaveTransferCreateHandle(EXAMPLE_ECSPI_SLAVE_BASEADDR, &g_s_handle, ECSPI_SlaveUserCallback, NULL);
+
+ while (1)
+ {
+ PRINTF("\r\n Slave example is running...\r\n\r\n");
+
+ /* Reset the receive buffer */
+ for (i = 0; i < TRANSFER_SIZE; i++)
+ {
+ slaveRxData[i] = 0U;
+ }
+
+ /* Set slave transfer ready to receive data */
+ isTransferCompleted = false;
+ slaveXfer.txData = NULL;
+ slaveXfer.rxData = slaveRxData;
+ slaveXfer.dataSize = TRANSFER_SIZE;
+ slaveXfer.channel = kECSPI_Channel0;
+
+ /* Slave start receive */
+ PRINTF("Slave starts to receive data!\r\n");
+ ECSPI_SlaveTransferNonBlocking(EXAMPLE_ECSPI_SLAVE_BASEADDR, &g_s_handle, &slaveXfer);
+
+ while (!isTransferCompleted)
+ {
+ }
+
+ /* Set slave transfer ready to send back data */
+ isTransferCompleted = false;
+ slaveXfer.txData = slaveRxData;
+ slaveXfer.rxData = NULL;
+ slaveXfer.dataSize = TRANSFER_SIZE;
+ slaveXfer.channel = kECSPI_Channel0;
+
+ /* Slave start send */
+ PRINTF("Slave starts to transmit data!\r\n");
+ ECSPI_SlaveTransferNonBlocking(EXAMPLE_ECSPI_SLAVE_BASEADDR, &g_s_handle, &slaveXfer);
+
+ while (!isTransferCompleted)
+ {
+ }
+
+ /* Print out receive buffer */
+ PRINTF("\r\n Slave receive:");
+ for (i = 0U; i < TRANSFER_SIZE; i++)
+ {
+ /* Print 16 numbers in a line */
+ if ((i & 0x0FU) == 0U)
+ {
+ PRINTF("\r\n ");
+ }
+ PRINTF(" %02X", slaveRxData[i]);
+ }
+ PRINTF("\r\n");
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/ecspi_interrupt_b2b_transfer_slave_v3_10.xml b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/ecspi_interrupt_b2b_transfer_slave_v3_10.xml
new file mode 100644
index 000000000..e6b9758c5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/ecspi_interrupt_b2b_transfer_slave_v3_10.xml
@@ -0,0 +1,131 @@
+
+
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diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/pin_mux.c b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/pin_mux.c
new file mode 100644
index 000000000..e4062d1b6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/pin_mux.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2018, 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v10.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 0.10.12
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D6, peripheral: ECSPI1, signal: ecspi_sclk, pin_signal: ECSPI1_SCLK, PE: Enabled, PUE: Disabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ - {pin_num: B6, peripheral: ECSPI1, signal: 'ecspi_ss, 0', pin_signal: ECSPI1_SS0, PE: Enabled, PUE: Enabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ - {pin_num: B7, peripheral: ECSPI1, signal: ecspi_mosi, pin_signal: ECSPI1_MOSI, PE: Disabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ - {pin_num: A7, peripheral: ECSPI1, signal: ecspi_miso, pin_signal: ECSPI1_MISO, PE: Disabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_MISO_ECSPI1_MISO, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_MISO_ECSPI1_MISO,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
+ IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_SS0_ECSPI1_SS0, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_SS0_ECSPI1_SS0,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
+ IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/pin_mux.h b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/pin_mux.h
new file mode 100644
index 000000000..1d906205a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/pin_mux.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/readme.txt b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/readme.txt
new file mode 100644
index 000000000..989bda708
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/interrupt_b2b_transfer/slave/readme.txt
@@ -0,0 +1,73 @@
+Overview
+========
+The ecspi_interrupt_b2b_transfer example shows how to use ECSPI driver in interrupt way:
+
+In this example , we need two boards, one board used as ECSPI master and another board used as ECSPI slave.
+The file 'ecspi_interrupt_b2b_transfer_slave.c' includes the ECSPI slave code.
+This example uses the transactional API in ECSPI driver.
+
+1. ECSPI master send/received data to/from ECSPI slave in interrupt . (ECSPI Slave using interrupt to receive/send the data)
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+ECSPI board to board:
+Transfers data through the instance 1 of the ECSPI interface. ECSPI1 pins of the master board are
+connected to the ECSPI1 pins of the slave board.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MASTER BOARD CONNECTS TO SLAVE BOARD
+Pin Name Board Location Pin Name Board Location
+For ECSPI1 connection, refer to: https://variwiki.com/index.php?title=MCUXpresso&release=MCUXPRESSO_2.13.0_V1.0_DART-MX8M-MINI#Demos_pins
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the demo runs successfully, the log would be seen on the debug terminal like:
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ECSPI board to board interrupt example.
+
+ Slave example is running...
+
+ Slave starts to receive data!
+ This is ECSPI slave transfer completed callback.
+ It's a successful transfer.
+
+ Slave starts to transmit data!
+ This is ECSPI slave transfer completed callback.
+ It's a successful transfer.
+
+ Slave receive:
+ 1 2 3 4 5 6 7 8 9 A B C D E F 10
+ 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
+ 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30
+ 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40
+
+ Slave example is running...
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..24ff05149
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(ecspi_polling_b2b_transfer_master)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME ecspi_polling_b2b_transfer_master.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../ecspi_polling_b2b_transfer_master.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_ecspi_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ecspi_polling_b2b_transfer_master.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_all.bat
new file mode 100644
index 000000000..6868c7569
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_all.sh
new file mode 100755
index 000000000..888128e66
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..8771607cb
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..1f660e5af
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..0dfc882b6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..cbb10c43f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_debug.bat
new file mode 100644
index 000000000..0636e21b5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_debug.sh
new file mode 100755
index 000000000..30c0ab2d5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..f0275ea6a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..35370ab2f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..51e8b73fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..ef8236b19
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_release.bat
new file mode 100644
index 000000000..a34003e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_release.sh
new file mode 100755
index 000000000..012619cda
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/board.c b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/board.h b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/clock_config.c b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/clock_config.h b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/ecspi_polling_b2b_transfer_master.c b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/ecspi_polling_b2b_transfer_master.c
new file mode 100644
index 000000000..38f5aaffe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/ecspi_polling_b2b_transfer_master.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "fsl_ecspi.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_ECSPI_MASTER_BASEADDR ECSPI1
+#define EXAMPLE_ECSPI_DEALY_COUNT 1000000U
+#define ECSPI_MASTER_CLK_FREQ \
+ (CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootEcspi1)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootEcspi1)))
+#define TRANSFER_SIZE 64U /*! Transfer dataSize */
+#define TRANSFER_BAUDRATE 500000U /*! Transfer baudrate - 500k */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+uint32_t masterRxData[TRANSFER_SIZE] = {0U};
+uint32_t masterTxData[TRANSFER_SIZE] = {0U};
+volatile uint32_t g_systickCounter = 20U;
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void SysTick_Handler(void)
+{
+ if (g_systickCounter != 0U)
+ {
+ g_systickCounter--;
+ }
+}
+
+int main(void)
+{
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ CLOCK_SetRootMux(kCLOCK_RootEcspi1, kCLOCK_EcspiRootmuxSysPll1); /* Set ECSPI1 source to SYSTEM PLL1 800MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootEcspi1, 2U, 5U); /* Set root clock to 800MHZ / 10 = 80MHZ */
+
+ PRINTF("ECSPI board to board polling example.\r\n");
+ PRINTF("This example use one board as master and another as slave.\r\n");
+ PRINTF("Master uses polling way and slave uses interrupt way. \r\n");
+ PRINTF("Please make sure you make the correct line connection. Basically, the connection is: \r\n");
+ PRINTF("ECSPI_master -- ECSPI_slave \r\n");
+ PRINTF(" CLK -- CLK \r\n");
+ PRINTF(" PCS -- PCS \r\n");
+ PRINTF(" MOSI -- MOSI \r\n");
+ PRINTF(" MISO -- MISO \r\n");
+ PRINTF(" GND -- GND \r\n");
+
+ uint32_t errorCount;
+ uint32_t loopCount = 1U;
+ uint32_t i;
+ ecspi_master_config_t masterConfig;
+ ecspi_transfer_t masterXfer;
+
+ /* Master config:
+ * masterConfig.channel = kECSPI_Channel0;
+ * masterConfig.burstLength = 8;
+ * masterConfig.samplePeriodClock = kECSPI_spiClock;
+ * masterConfig.baudRate_Bps = TRANSFER_BAUDRATE;
+ * masterConfig.chipSelectDelay = 0;
+ * masterConfig.samplePeriod = 0;
+ * masterConfig.txFifoThreshold = 1;
+ * masterConfig.rxFifoThreshold = 0;
+ */
+ ECSPI_MasterGetDefaultConfig(&masterConfig);
+ masterConfig.baudRate_Bps = TRANSFER_BAUDRATE;
+
+ ECSPI_MasterInit(EXAMPLE_ECSPI_MASTER_BASEADDR, &masterConfig, ECSPI_MASTER_CLK_FREQ);
+
+ while (1)
+ {
+ /* Set up the transfer data */
+ for (i = 0U; i < TRANSFER_SIZE; i++)
+ {
+ masterTxData[i] = (i + loopCount) % 256U;
+ masterRxData[i] = 0U;
+ }
+
+ /* Print out transmit buffer */
+ PRINTF("\r\n Master transmit:\r\n");
+ for (i = 0U; i < TRANSFER_SIZE; i++)
+ {
+ /* Print 16 numbers in a line */
+ if ((i & 0x0FU) == 0U)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF(" %02X", masterTxData[i]);
+ }
+ PRINTF("\r\n");
+
+ /* Start master transfer, send data to slave */
+ masterXfer.txData = masterTxData;
+ masterXfer.rxData = NULL;
+ masterXfer.dataSize = TRANSFER_SIZE;
+ masterXfer.channel = kECSPI_Channel0;
+ ECSPI_MasterTransferBlocking(EXAMPLE_ECSPI_MASTER_BASEADDR, &masterXfer);
+
+ /* Delay to wait slave is ready */
+ if (SysTick_Config(SystemCoreClock / 1000U))
+ {
+ while (1)
+ {
+ }
+ }
+ /* Delay 20 ms */
+ g_systickCounter = 20U;
+ while (g_systickCounter != 0U)
+ {
+ }
+
+ /* Start master transfer, receive data from slave */
+ masterXfer.txData = NULL;
+ masterXfer.rxData = masterRxData;
+ masterXfer.dataSize = TRANSFER_SIZE;
+ masterXfer.channel = kECSPI_Channel0;
+ PRINTF("Start receive data from slave.\r\n");
+ ECSPI_MasterTransferBlocking(EXAMPLE_ECSPI_MASTER_BASEADDR, &masterXfer);
+
+ errorCount = 0U;
+ for (i = 0U; i < TRANSFER_SIZE; i++)
+ {
+ if (masterTxData[i] != masterRxData[i])
+ {
+ errorCount++;
+ }
+ }
+
+ if (errorCount == 0U)
+ {
+ PRINTF(" \r\nECSPI transfer all data matched! \r\n");
+
+ /* Print out receive buffer */
+ PRINTF("\r\n Master received:\r\n");
+ for (i = 0U; i < TRANSFER_SIZE; i++)
+ {
+ /* Print 16 numbers in a line */
+ if ((i & 0x0FU) == 0U)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF(" %02X", masterRxData[i]);
+ }
+ PRINTF("\r\n");
+ }
+ else
+ {
+ PRINTF("\r\nError occurred in ECSPI transfer ! \r\n");
+ }
+
+ /* Wait for press any key */
+ PRINTF("\r\n Press any key to run again\r\n");
+ GETCHAR();
+
+ /* Increase loop count to change transmit buffer */
+ loopCount++;
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/ecspi_polling_b2b_transfer_master_v3_10.xml b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/ecspi_polling_b2b_transfer_master_v3_10.xml
new file mode 100644
index 000000000..1cbfb5360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/ecspi_polling_b2b_transfer_master_v3_10.xml
@@ -0,0 +1,131 @@
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diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/pin_mux.c b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/pin_mux.c
new file mode 100644
index 000000000..e4062d1b6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/pin_mux.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2018, 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v10.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 0.10.12
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D6, peripheral: ECSPI1, signal: ecspi_sclk, pin_signal: ECSPI1_SCLK, PE: Enabled, PUE: Disabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ - {pin_num: B6, peripheral: ECSPI1, signal: 'ecspi_ss, 0', pin_signal: ECSPI1_SS0, PE: Enabled, PUE: Enabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ - {pin_num: B7, peripheral: ECSPI1, signal: ecspi_mosi, pin_signal: ECSPI1_MOSI, PE: Disabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ - {pin_num: A7, peripheral: ECSPI1, signal: ecspi_miso, pin_signal: ECSPI1_MISO, PE: Disabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_MISO_ECSPI1_MISO, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_MISO_ECSPI1_MISO,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
+ IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_SS0_ECSPI1_SS0, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_SS0_ECSPI1_SS0,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
+ IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/pin_mux.h b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/pin_mux.h
new file mode 100644
index 000000000..1d906205a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/pin_mux.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/readme.txt b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/readme.txt
new file mode 100644
index 000000000..faa6bd582
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/master/readme.txt
@@ -0,0 +1,82 @@
+Overview
+========
+The ecspi_polling_b2b_transfer example shows how to use ECSPI driver in polling way:
+
+In this example , we need two boards, one board used as ECSPI master and another board used as ECSPI slave.
+The file 'ecspi_polling_b2b_transfer_master.c' includes the ECSPI master code.
+
+1. ECSPI master send/received data to/from ECSPI slave in polling . (ECSPI Slave using interrupt to receive/send the data)
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+ECSPI board to board:
+Transfers data through the instance 1 of the ECSPI interface. ECSPI1 pins of the master board are
+connected to the ECSPI1 pins of the slave board.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MASTER BOARD CONNECTS TO SLAVE BOARD
+Pin Name Board Location Pin Name Board Location
+For ECSPI1 connection, refer to: https://variwiki.com/index.php?title=MCUXpresso&release=MCUXPRESSO_2.13.0_V1.0_DART-MX8M-MINI#Demos_pins
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the demo runs successfully, the log would be seen on the debug terminal like:
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ECSPI board to board polling example.
+This example use one board as master and another as slave.
+Master uses polling way and slave uses interrupt way.
+Please make sure you make the correct line connection. Basically, the connection is:
+ECSPI_master -- ECSPI_slave
+ CLK -- CLK
+ PCS -- PCS
+ MOSI -- MOSI
+ MISO -- MISO
+ GND -- GND
+
+ Master transmit:
+
+ 1 2 3 4 5 6 7 8 9 A B C D E F 10
+ 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
+ 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30
+ 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40
+
+Start receive data from slave.
+
+ECSPI transfer all data matched!
+
+ Master received:
+
+ 1 2 3 4 5 6 7 8 9 A B C D E F 10
+ 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
+ 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30
+ 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40
+
+ Press any key to run again
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..5eb84733e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(ecspi_polling_b2b_transfer_slave)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME ecspi_polling_b2b_transfer_slave.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../ecspi_polling_b2b_transfer_slave.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_ecspi_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ecspi_polling_b2b_transfer_slave.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_all.bat
new file mode 100644
index 000000000..6868c7569
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_all.sh
new file mode 100755
index 000000000..888128e66
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..8771607cb
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..1f660e5af
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..0dfc882b6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..cbb10c43f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_debug.bat
new file mode 100644
index 000000000..0636e21b5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_debug.sh
new file mode 100755
index 000000000..30c0ab2d5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..f0275ea6a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..35370ab2f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..51e8b73fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..ef8236b19
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_release.bat
new file mode 100644
index 000000000..a34003e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_release.sh
new file mode 100755
index 000000000..012619cda
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/board.c b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/board.h b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/clock_config.c b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/clock_config.h b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/ecspi_polling_b2b_transfer_slave.c b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/ecspi_polling_b2b_transfer_slave.c
new file mode 100644
index 000000000..479ee835a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/ecspi_polling_b2b_transfer_slave.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "fsl_ecspi.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_ECSPI_SLAVE_BASEADDR ECSPI1
+#define TRANSFER_SIZE 64U /*! Transfer dataSize */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/* ECSPI user callback */
+void ECSPI_SlaveUserCallback(ECSPI_Type *base, ecspi_slave_handle_t *handle, status_t status, void *userData);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+uint32_t slaveRxData[TRANSFER_SIZE] = {0U};
+
+ecspi_slave_handle_t g_s_handle;
+volatile bool isTransferCompleted = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void ECSPI_SlaveUserCallback(ECSPI_Type *base, ecspi_slave_handle_t *handle, status_t status, void *userData)
+{
+ if (status == kStatus_Success)
+ {
+ PRINTF("This is ECSPI slave transfer completed callback. \r\n");
+ PRINTF("It's a successful transfer. \r\n\r\n");
+ isTransferCompleted = true;
+ }
+
+ if (status == kStatus_ECSPI_HardwareOverFlow)
+ {
+ PRINTF("Hardware overflow occurred in this transfer. \r\n");
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ PRINTF("ECSPI board to board polling example.\r\n");
+
+ uint32_t i;
+ ecspi_slave_config_t slaveConfig;
+ ecspi_transfer_t slaveXfer;
+
+ /* Slave config:
+ * slaveConfig.channel = kECSPI_Channel0;
+ * slaveConfig.burstLength = 8;
+ * slaveConfig.txFifoThreshold = 1;
+ * slaveConfig.rxFifoThreshold = 0;
+ */
+ ECSPI_SlaveGetDefaultConfig(&slaveConfig);
+ ECSPI_SlaveInit(EXAMPLE_ECSPI_SLAVE_BASEADDR, &slaveConfig);
+
+ ECSPI_SlaveTransferCreateHandle(EXAMPLE_ECSPI_SLAVE_BASEADDR, &g_s_handle, ECSPI_SlaveUserCallback, NULL);
+
+ while (1)
+ {
+ PRINTF("\r\n Slave example is running...\r\n\r\n");
+
+ /* Reset the receive buffer */
+ for (i = 0U; i < TRANSFER_SIZE; i++)
+ {
+ slaveRxData[i] = 0U;
+ }
+
+ /* Set slave transfer ready to receive data */
+ isTransferCompleted = false;
+ slaveXfer.txData = NULL;
+ slaveXfer.rxData = slaveRxData;
+ slaveXfer.dataSize = TRANSFER_SIZE;
+ slaveXfer.channel = kECSPI_Channel0;
+
+ /* Slave start receive */
+ PRINTF("Slave starts to receive data!\r\n");
+ ECSPI_SlaveTransferNonBlocking(EXAMPLE_ECSPI_SLAVE_BASEADDR, &g_s_handle, &slaveXfer);
+
+ while (!isTransferCompleted)
+ {
+ }
+
+ /* Set slave transfer ready to send back data */
+ isTransferCompleted = false;
+ slaveXfer.txData = slaveRxData;
+ slaveXfer.rxData = NULL;
+ slaveXfer.dataSize = TRANSFER_SIZE;
+ slaveXfer.channel = kECSPI_Channel0;
+
+ /* Slave start send */
+ PRINTF("Slave starts to transmit data!\r\n");
+ ECSPI_SlaveTransferNonBlocking(EXAMPLE_ECSPI_SLAVE_BASEADDR, &g_s_handle, &slaveXfer);
+
+ while (!isTransferCompleted)
+ {
+ }
+
+ /* Print out receive buffer */
+ PRINTF("\r\n Slave received:");
+ for (i = 0U; i < TRANSFER_SIZE; i++)
+ {
+ /* Print 16 numbers in a line */
+ if ((i & 0x0FU) == 0U)
+ {
+ PRINTF("\r\n ");
+ }
+ PRINTF(" %02X", slaveRxData[i]);
+ }
+ PRINTF("\r\n");
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/ecspi_polling_b2b_transfer_slave_v3_10.xml b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/ecspi_polling_b2b_transfer_slave_v3_10.xml
new file mode 100644
index 000000000..976a4031f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/ecspi_polling_b2b_transfer_slave_v3_10.xml
@@ -0,0 +1,131 @@
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diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/pin_mux.c b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/pin_mux.c
new file mode 100644
index 000000000..e4062d1b6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/pin_mux.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2018, 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v10.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 0.10.12
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D6, peripheral: ECSPI1, signal: ecspi_sclk, pin_signal: ECSPI1_SCLK, PE: Enabled, PUE: Disabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ - {pin_num: B6, peripheral: ECSPI1, signal: 'ecspi_ss, 0', pin_signal: ECSPI1_SS0, PE: Enabled, PUE: Enabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ - {pin_num: B7, peripheral: ECSPI1, signal: ecspi_mosi, pin_signal: ECSPI1_MOSI, PE: Disabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ - {pin_num: A7, peripheral: ECSPI1, signal: ecspi_miso, pin_signal: ECSPI1_MISO, PE: Disabled, HYS: Enabled, SION: DISABLED, FSEL: SLOW0, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_MISO_ECSPI1_MISO, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_MISO_ECSPI1_MISO,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
+ IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
+ IOMUXC_SetPinMux(IOMUXC_ECSPI1_SS0_ECSPI1_SS0, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_ECSPI1_SS0_ECSPI1_SS0,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
+ IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/pin_mux.h b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/pin_mux.h
new file mode 100644
index 000000000..1d906205a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/pin_mux.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/readme.txt b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/readme.txt
new file mode 100644
index 000000000..eb9e64fbc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/ecspi/polling_b2b_transfer/slave/readme.txt
@@ -0,0 +1,72 @@
+Overview
+========
+The ecspi_polling_b2b_transfer example shows how to use ECSPI driver in polling way:
+
+In this example , we need two boards, one board used as ECSPI master and another board used as ECSPI slave.
+The file 'ecspi_polling_b2b_transfer_slave.c' includes the ECSPI slave code.
+
+1. ECSPI master send/received data to/from ECSPI slave in polling . (ECSPI Slave using interrupt to receive/send the data)
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+ECSPI board to board:
+Transfers data through the instance 1 of the ECSPI interface. ECSPI1 pins of the master board are
+connected to the ECSPI1 pins of the slave board.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MASTER BOARD CONNECTS TO SLAVE BOARD
+Pin Name Board Location Pin Name Board Location
+For ECSPI1 connection, refer to: https://variwiki.com/index.php?title=MCUXpresso&release=MCUXPRESSO_2.13.0_V1.0_DART-MX8M-MINI#Demos_pins
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the demo runs successfully, the log would be seen on the debug terminal like:
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ECSPI board to board polling example.
+
+ Slave example is running...
+
+ Slave starts to receive data!
+ This is ECSPI slave transfer completed callback.
+ It's a successful transfer.
+
+ Slave starts to transmit data!
+ This is ECSPI slave transfer completed callback.
+ It's a successful transfer.
+
+ Slave receive:
+ 1 2 3 4 5 6 7 8 9 A B C D E F 10
+ 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
+ 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30
+ 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40
+
+ Slave example is running...
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..1566c8182
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(igpio_led_output)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME igpio_led_output.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../gpio_led_output.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_igpio_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/igpio_led_output.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/board.c b/boards/dart_mx8mm/driver_examples/gpio/led_output/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/board.h b/boards/dart_mx8mm/driver_examples/gpio/led_output/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/clock_config.c b/boards/dart_mx8mm/driver_examples/gpio/led_output/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/clock_config.h b/boards/dart_mx8mm/driver_examples/gpio/led_output/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/gpio/led_output/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/gpio/led_output/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/gpio_led_output.c b/boards/dart_mx8mm/driver_examples/gpio/led_output/gpio_led_output.c
new file mode 100644
index 000000000..1e5f60463
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/gpio_led_output.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_LED_GPIO GPIO4
+#define EXAMPLE_LED_GPIO_PIN 3U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* The PIN status */
+volatile bool g_pinSet = false;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ /* Define the init structure for the output LED pin*/
+ gpio_pin_config_t led_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
+
+ /* Board pin, clock, debug console init */
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ /* Print a note to terminal. */
+ PRINTF("\r\n GPIO Driver example\r\n");
+ PRINTF("\r\n The LED is blinking.\r\n");
+
+ /* Init output LED GPIO. */
+ GPIO_PinInit(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, &led_config);
+
+ while (1)
+ {
+ SDK_DelayAtLeastUs(100000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+#if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1))
+ GPIO_PortToggle(EXAMPLE_LED_GPIO, 1u << EXAMPLE_LED_GPIO_PIN);
+#else
+ if (g_pinSet)
+ {
+ GPIO_PinWrite(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, 0U);
+ g_pinSet = false;
+ }
+ else
+ {
+ GPIO_PinWrite(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, 1U);
+ g_pinSet = true;
+ }
+#endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/igpio_led_output_v3_10.xml b/boards/dart_mx8mm/driver_examples/gpio/led_output/igpio_led_output_v3_10.xml
new file mode 100644
index 000000000..8ec288d50
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/igpio_led_output_v3_10.xml
@@ -0,0 +1,131 @@
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diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/pin_mux.c b/boards/dart_mx8mm/driver_examples/gpio/led_output/pin_mux.c
new file mode 100644
index 000000000..6858864f9
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/pin_mux.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: B8, peripheral: GPIO4, signal: 'gpio_io, 03', pin_signal: SAI1_RXD1}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_SAI1_RXD1_GPIO4_IO03, 0U);
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/pin_mux.h b/boards/dart_mx8mm/driver_examples/gpio/led_output/pin_mux.h
new file mode 100644
index 000000000..3b186c9db
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/pin_mux.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_SAI1_RXD1_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/gpio/led_output/readme.txt b/boards/dart_mx8mm/driver_examples/gpio/led_output/readme.txt
new file mode 100644
index 000000000..1e6ae159c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpio/led_output/readme.txt
@@ -0,0 +1,49 @@
+Overview
+========
+The GPIO Example project is a demonstration program that uses the KSDK software to manipulate the general-purpose
+outputs.
+The example is supported by the set, clear, and toggle write-only registers for each port output data register. The
+example take turns to shine the LED.
+
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+- Oscilloscope
+
+Board settings
+==============
+For GPIO output pin refer to: https://variwiki.com/index.php?title=MCUXpresso&release=MCUXPRESSO_2.13.0_V1.0_DART-MX8M-MINI#Demos_pins
+
+#### Please note this application can't support running with Linux BSP! ####
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the example runs successfully, the following message is displayed in the terminal:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ GPIO Driver example
+ The LED is blinking.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..fc09f5f51
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(gpt_capture)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME gpt_capture.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../gpt_capture.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_gpt_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/gpt_capture.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/board.c b/boards/dart_mx8mm/driver_examples/gpt/capture/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/board.h b/boards/dart_mx8mm/driver_examples/gpt/capture/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/clock_config.c b/boards/dart_mx8mm/driver_examples/gpt/capture/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/clock_config.h b/boards/dart_mx8mm/driver_examples/gpt/capture/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/gpt/capture/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/gpt/capture/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/gpt_capture.c b/boards/dart_mx8mm/driver_examples/gpt/capture/gpt_capture.c
new file mode 100644
index 000000000..07f45764d
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/gpt_capture.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_gpt.h"
+
+#include "fsl_common.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DEMO_GPT_IRQn GPT1_IRQn
+#define DEMO_GPT_BASE GPT1
+/* GPT channel used for input capture */
+#define BOARD_GPT_INPUT_CAPTURE_CHANNEL kGPT_InputCapture_Channel1
+/* Interrupt to enable and flag to read; depends on the GPT channel used */
+#define EXAMPLE_GPT_CAPTURE_IRQHandler GPT1_IRQHandler
+#define BOARD_GPT_CHANNEL_INTERRUPT_ENABLE kGPT_InputCapture1InterruptEnable
+#define BOARD_GPT_CHANNEL_FLAG kGPT_InputCapture1Flag
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+volatile bool gptIsrFlag = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void EXAMPLE_GPT_CAPTURE_IRQHandler(void)
+{
+ /* Clear interrupt flag.*/
+ GPT_ClearStatusFlags(DEMO_GPT_BASE, BOARD_GPT_CHANNEL_FLAG);
+
+ gptIsrFlag = true;
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M7F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U || __CORTEX_M == 7U)
+ __DSB();
+#endif
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ uint32_t captureVal = 0;
+ gpt_config_t gptConfig;
+
+ /* Board pin, clock, debug console init */
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ /* Print a note to terminal */
+ PRINTF("\r\nGPT input capture example\r\n");
+ PRINTF("\r\nOnce the input signal is received the input capture value is printed\r\n");
+
+ GPT_GetDefaultConfig(&gptConfig);
+
+ /* Initialize GPT module */
+ GPT_Init(DEMO_GPT_BASE, &gptConfig);
+
+ /* Setup input capture on a gpt channel */
+ GPT_SetInputOperationMode(DEMO_GPT_BASE, BOARD_GPT_INPUT_CAPTURE_CHANNEL, kGPT_InputOperation_RiseEdge);
+
+ /* Enable GPT Input Capture1 interrupt */
+ GPT_EnableInterrupts(DEMO_GPT_BASE, BOARD_GPT_CHANNEL_INTERRUPT_ENABLE);
+
+ /* Enable at the Interrupt */
+ EnableIRQ(DEMO_GPT_IRQn);
+
+ /* Start Timer */
+ GPT_StartTimer(DEMO_GPT_BASE);
+
+ while (true)
+ {
+ /* Check whether occur interupt */
+ if (true == gptIsrFlag)
+ {
+ captureVal = GPT_GetInputCaptureValue(DEMO_GPT_BASE, BOARD_GPT_INPUT_CAPTURE_CHANNEL);
+ PRINTF("\r\n Capture value =%x\r\n", captureVal);
+ gptIsrFlag = false;
+ }
+ else
+ {
+ __WFI();
+ }
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/gpt_capture_v3_10.xml b/boards/dart_mx8mm/driver_examples/gpt/capture/gpt_capture_v3_10.xml
new file mode 100644
index 000000000..097368a6d
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/gpt_capture_v3_10.xml
@@ -0,0 +1,131 @@
+
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diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/pin_mux.c b/boards/dart_mx8mm/driver_examples/gpt/capture/pin_mux.c
new file mode 100644
index 000000000..533f7a949
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/pin_mux.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: AG8, peripheral: GPT1, signal: 'gpt_capture, 1', pin_signal: SAI3_RXFS}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_SAI3_RXFS_GPT1_CAPTURE1, 0U);
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/pin_mux.h b/boards/dart_mx8mm/driver_examples/gpt/capture/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/gpt/capture/readme.txt b/boards/dart_mx8mm/driver_examples/gpt/capture/readme.txt
new file mode 100644
index 000000000..010172d37
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/capture/readme.txt
@@ -0,0 +1,49 @@
+Overview
+========
+The gpt_capture project is a simple demonstration program of the SDK GPT driver's input capture feature.
+The example sets up a GPT channel for rise-edge capture. Once the input signal is received,
+this example will print the capture value.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+Connect input signal to the Test Point.
+
+#### Please note this application can't run if WM8904 is mounted ####
+GPT1_CAPTURE1/2 functions are only available from SAI3 pads used by WM8904.
+These pads are exported to the external connector only if WM8904 is not mounted.
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the example runs successfully, following information can be seen on the terminal:
+
+~~~~~~~~~~~~~~~~~~~~~
+GPT input capture example
+Once the input signal is received the input capture value is printed
+~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..afcd673cd
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(gpt_timer)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME gpt_timer.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../gpt_timer.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_gpt_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/gpt_timer.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/board.c b/boards/dart_mx8mm/driver_examples/gpt/timer/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/board.h b/boards/dart_mx8mm/driver_examples/gpt/timer/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/clock_config.c b/boards/dart_mx8mm/driver_examples/gpt/timer/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/clock_config.h b/boards/dart_mx8mm/driver_examples/gpt/timer/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/gpt/timer/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/gpt/timer/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/gpt_timer.c b/boards/dart_mx8mm/driver_examples/gpt/timer/gpt_timer.c
new file mode 100644
index 000000000..e5c9c1190
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/gpt_timer.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_gpt.h"
+
+#include "fsl_common.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define GPT_IRQ_ID GPT1_IRQn
+#define EXAMPLE_GPT GPT1
+#define EXAMPLE_GPT_CLK_FREQ \
+ (CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootGpt1)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootGpt1)) / 2) /* SYSTEM PLL1 DIV2 */
+#define EXAMPLE_GPT_IRQHandler GPT1_IRQHandler
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+volatile bool gptIsrFlag = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void EXAMPLE_GPT_IRQHandler(void)
+{
+ /* Clear interrupt flag.*/
+ GPT_ClearStatusFlags(EXAMPLE_GPT, kGPT_OutputCompare1Flag);
+
+ gptIsrFlag = true;
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M7F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U || __CORTEX_M == 7U)
+ __DSB();
+#endif
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ uint32_t gptFreq;
+ gpt_config_t gptConfig;
+
+ /* Board pin, clock, debug console init */
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ CLOCK_SetRootMux(kCLOCK_RootGpt1, kCLOCK_GptRootmuxSysPll1Div2); /* Set GPT1 source to SYSTEM PLL1 DIV2 400MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootGpt1, 1U, 4U); /* Set root clock to 400MHZ / 4 = 100MHZ */
+
+ GPT_GetDefaultConfig(&gptConfig);
+
+ /* Initialize GPT module */
+ GPT_Init(EXAMPLE_GPT, &gptConfig);
+
+ /* Divide GPT clock source frequency by 3 inside GPT module */
+ GPT_SetClockDivider(EXAMPLE_GPT, 3);
+
+ /* Get GPT clock frequency */
+ gptFreq = EXAMPLE_GPT_CLK_FREQ;
+
+ /* GPT frequency is divided by 3 inside module */
+ gptFreq /= 3;
+
+ /* Set both GPT modules to 1 second duration */
+ GPT_SetOutputCompareValue(EXAMPLE_GPT, kGPT_OutputCompare_Channel1, gptFreq);
+
+ /* Enable GPT Output Compare1 interrupt */
+ GPT_EnableInterrupts(EXAMPLE_GPT, kGPT_OutputCompare1InterruptEnable);
+
+ /* Enable at the Interrupt */
+ EnableIRQ(GPT_IRQ_ID);
+
+ PRINTF("\r\nPress any key to start the example");
+ GETCHAR();
+
+ /* Start Timer */
+ PRINTF("\r\nStarting GPT timer ...");
+ GPT_StartTimer(EXAMPLE_GPT);
+
+ while (true)
+ {
+ /* Check whether occur interupt and toggle LED */
+ if (true == gptIsrFlag)
+ {
+ PRINTF("\r\n GPT interrupt is occurred !");
+ gptIsrFlag = false;
+ }
+ else
+ {
+ __WFI();
+ }
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/gpt_timer_v3_10.xml b/boards/dart_mx8mm/driver_examples/gpt/timer/gpt_timer_v3_10.xml
new file mode 100644
index 000000000..4ede3b9b5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/gpt_timer_v3_10.xml
@@ -0,0 +1,131 @@
+
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diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/pin_mux.c b/boards/dart_mx8mm/driver_examples/gpt/timer/pin_mux.c
new file mode 100644
index 000000000..9f7a73c29
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/pin_mux.h b/boards/dart_mx8mm/driver_examples/gpt/timer/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/gpt/timer/readme.txt b/boards/dart_mx8mm/driver_examples/gpt/timer/readme.txt
new file mode 100644
index 000000000..7305d4340
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/gpt/timer/readme.txt
@@ -0,0 +1,59 @@
+Overview
+========
+The gpt_timer project is a simple demonstration program of the SDK GPT driver. It sets up the GPT
+hardware block to trigger a periodic interrupt after every 1 second. When the GPT interrupt is triggered
+a message a printed on the UART terminal.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special is needed.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the example runs successfully, following information can be seen on the terminal:
+
+~~~~~~~~~~~~~~~~~~~~~
+
+Press any key to start the example
+s
+Starting GPT timer ...
+ GPT interrupt is occurred !
+ GPT interrupt is occurred !
+ GPT interrupt is occurred !
+ GPT interrupt is occurred !
+ .
+ .
+ .
+ GPT interrupt is occurred !
+ .
+ .
+ .
+~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..46d7e6efa
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(ii2c_interrupt_b2b_transfer_master)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME ii2c_interrupt_b2b_transfer_master.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../i2c_interrupt_b2b_transfer_master.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_ii2c_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ii2c_interrupt_b2b_transfer_master.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_all.bat
new file mode 100644
index 000000000..6868c7569
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_all.sh
new file mode 100755
index 000000000..888128e66
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..8771607cb
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..1f660e5af
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..0dfc882b6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..cbb10c43f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_debug.bat
new file mode 100644
index 000000000..0636e21b5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_debug.sh
new file mode 100755
index 000000000..30c0ab2d5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..f0275ea6a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..35370ab2f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..51e8b73fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..ef8236b19
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_release.bat
new file mode 100644
index 000000000..a34003e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_release.sh
new file mode 100755
index 000000000..012619cda
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/board.c b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/board.h b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/clock_config.c b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/clock_config.h b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/i2c_interrupt_b2b_transfer_master.c b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/i2c_interrupt_b2b_transfer_master.c
new file mode 100644
index 000000000..294dddc7e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/i2c_interrupt_b2b_transfer_master.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Standard C Included Files */
+#include
+/* SDK Included Files */
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_i2c.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_I2C_MASTER_BASEADDR I2C4
+#define I2C_MASTER_CLK_FREQ \
+ (CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootI2c4)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootI2c4)) / 5) /* SYSTEM PLL1 DIV5 */
+
+#define I2C_MASTER_SLAVE_ADDR_7BIT 0x7EU
+#define I2C_BAUDRATE 100000U
+#define I2C_DATA_LENGTH 32U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+uint8_t g_master_txBuff[I2C_DATA_LENGTH];
+uint8_t g_master_rxBuff[I2C_DATA_LENGTH];
+i2c_master_handle_t g_m_handle;
+volatile bool g_MasterCompletionFlag = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void i2c_master_callback(I2C_Type *base, i2c_master_handle_t *handle, status_t status, void *userData)
+{
+ /* Signal transfer success when received success status. */
+ if (status == kStatus_Success)
+ {
+ g_MasterCompletionFlag = true;
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ i2c_master_config_t masterConfig;
+ uint32_t sourceClock;
+ i2c_master_transfer_t masterXfer;
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ CLOCK_SetRootMux(kCLOCK_RootI2c4, kCLOCK_I2cRootmuxSysPll1Div5); /* Set I2C source to SysPLL1 Div5 160MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootI2c4, 1U, 10U); /* Set root clock to 160MHZ / 10 = 16MHZ */
+
+ PRINTF("\r\nI2C board2board interrupt example -- Master transfer.\r\n");
+
+ /* Set up i2c master to send data to slave*/
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ g_master_txBuff[i] = i;
+ }
+
+ PRINTF("Master will send data :");
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ if (i % 8 == 0)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF("0x%2x ", g_master_txBuff[i]);
+ }
+ PRINTF("\r\n\r\n");
+
+ /*
+ * masterConfig->baudRate_Bps = 100000U;
+ * masterConfig->enableHighDrive = false;
+ * masterConfig->enableStopHold = false;
+ * masterConfig->glitchFilterWidth = 0U;
+ * masterConfig->enableMaster = true;
+ */
+ I2C_MasterGetDefaultConfig(&masterConfig);
+ masterConfig.baudRate_Bps = I2C_BAUDRATE;
+
+ sourceClock = I2C_MASTER_CLK_FREQ;
+
+ I2C_MasterInit(EXAMPLE_I2C_MASTER_BASEADDR, &masterConfig, sourceClock);
+
+ memset(&g_m_handle, 0, sizeof(g_m_handle));
+ memset(&masterXfer, 0, sizeof(masterXfer));
+
+ masterXfer.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT;
+ masterXfer.direction = kI2C_Write;
+ masterXfer.subaddress = (uint32_t)NULL;
+ masterXfer.subaddressSize = 0;
+ masterXfer.data = g_master_txBuff;
+ masterXfer.dataSize = I2C_DATA_LENGTH;
+ masterXfer.flags = kI2C_TransferDefaultFlag;
+
+ I2C_MasterTransferCreateHandle(EXAMPLE_I2C_MASTER_BASEADDR, &g_m_handle, i2c_master_callback, NULL);
+ I2C_MasterTransferNonBlocking(EXAMPLE_I2C_MASTER_BASEADDR, &g_m_handle, &masterXfer);
+
+ /* Wait for transfer completed. */
+ while (!g_MasterCompletionFlag)
+ {
+ }
+ g_MasterCompletionFlag = false;
+
+ PRINTF("Receive sent data from slave :");
+
+ masterXfer.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT;
+ masterXfer.direction = kI2C_Read;
+ masterXfer.subaddress = (uint32_t)NULL;
+ masterXfer.subaddressSize = 0;
+ masterXfer.data = g_master_rxBuff;
+ masterXfer.dataSize = I2C_DATA_LENGTH;
+
+ masterXfer.flags = kI2C_TransferDefaultFlag;
+
+ I2C_MasterTransferNonBlocking(EXAMPLE_I2C_MASTER_BASEADDR, &g_m_handle, &masterXfer);
+
+ /* Reset master completion flag to false. */
+ g_MasterCompletionFlag = false;
+
+ /* Wait for transfer completed. */
+ while (!g_MasterCompletionFlag)
+ {
+ }
+ g_MasterCompletionFlag = false;
+
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ if (i % 8 == 0)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF("0x%2x ", g_master_rxBuff[i]);
+ }
+ PRINTF("\r\n\r\n");
+
+ /* Transfer completed. Check the data.*/
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ if (g_master_rxBuff[i] != g_master_txBuff[i])
+ {
+ PRINTF("\r\nError occurred in the transfer ! \r\n");
+ break;
+ }
+ }
+
+ PRINTF("\r\nEnd of I2C example .\r\n");
+ while (1)
+ {
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/ii2c_interrupt_b2b_transfer_master_v3_10.xml b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/ii2c_interrupt_b2b_transfer_master_v3_10.xml
new file mode 100644
index 000000000..f2beafadf
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/ii2c_interrupt_b2b_transfer_master_v3_10.xml
@@ -0,0 +1,131 @@
+
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diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/pin_mux.c b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/pin_mux.c
new file mode 100644
index 000000000..962a24e6a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/pin_mux.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D13, peripheral: I2C4, signal: i2c_scl, pin_signal: I2C4_SCL, PE: Disabled, HYS: Enabled, SION: ENABLED, DSE: X6_0}
+ - {pin_num: E13, peripheral: I2C4, signal: i2c_sda, pin_signal: I2C4_SDA, PE: Disabled, HYS: Enabled, SION: ENABLED, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SCL_I2C4_SCL, 1U);
+ IOMUXC_SetPinConfig(IOMUXC_I2C4_SCL_I2C4_SCL,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_I2C4_SDA, 1U);
+ IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_I2C4_SDA,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/pin_mux.h b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/readme.txt b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/readme.txt
new file mode 100644
index 000000000..fe63c44d3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/master/readme.txt
@@ -0,0 +1,65 @@
+Overview
+========
+The i2c_interrupt_b2b_transfer_master example shows how to use i2c driver as master to do board to board transfer
+with interrupt:
+
+In this example, one i2c instance as master and another i2c instance on the other board as slave. Master sends a
+piece of data to slave, and receive a piece of data from slave. This example checks if the data received from
+slave is correct.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+I2C one board:
+ + Transfer data from MASTER_BOARD to SLAVE_BOARD of I2C interface, I2C4 pins of MASTER_BOARD are connected with
+ I2C4 pins of SLAVE_BOARD
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+SLAVE_BOARD CONNECTS TO MASTER_BOARD
+Pin Name Board Location Pin Name Board Location
+For I2C4 connection, refer to: https://variwiki.com/index.php?title=MCUXpresso&release=MCUXPRESSO_2.13.0_V1.0_DART-MX8M-MINI#Demos_pins
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the demo runs successfully, the following message is displayed in the terminal:
+
+I2C board2board interrupt example -- Master transfer.
+Master will send data :
+0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7
+0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f
+0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
+
+Receive sent data from slave :
+0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7
+0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f
+0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
+
+
+End of I2C example .
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..cb1a1eaca
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(ii2c_interrupt_b2b_transfer_slave)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME ii2c_interrupt_b2b_transfer_slave.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../i2c_interrupt_b2b_transfer_slave.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_ii2c_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ii2c_interrupt_b2b_transfer_slave.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_all.bat
new file mode 100644
index 000000000..6868c7569
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_all.sh
new file mode 100755
index 000000000..888128e66
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..8771607cb
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..1f660e5af
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..0dfc882b6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..cbb10c43f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_debug.bat
new file mode 100644
index 000000000..0636e21b5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_debug.sh
new file mode 100755
index 000000000..30c0ab2d5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..f0275ea6a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..35370ab2f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..51e8b73fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..ef8236b19
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_release.bat
new file mode 100644
index 000000000..a34003e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_release.sh
new file mode 100755
index 000000000..012619cda
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/board.c b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/board.h b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/clock_config.c b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/clock_config.h b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/i2c_interrupt_b2b_transfer_slave.c b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/i2c_interrupt_b2b_transfer_slave.c
new file mode 100644
index 000000000..8ea7adf1f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/i2c_interrupt_b2b_transfer_slave.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Standard C Included Files */
+#include
+/* SDK Included Files */
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_i2c.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_I2C_SLAVE_BASEADDR I2C4
+
+#define I2C_MASTER_SLAVE_ADDR_7BIT 0x7EU
+#define I2C_DATA_LENGTH 32U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+uint8_t g_slave_buff[I2C_DATA_LENGTH];
+i2c_slave_handle_t g_s_handle;
+volatile bool g_SlaveCompletionFlag = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData)
+{
+ switch (xfer->event)
+ {
+ /* Transmit request */
+ case kI2C_SlaveTransmitEvent:
+ /* Update information for transmit process */
+ xfer->data = g_slave_buff;
+ xfer->dataSize = I2C_DATA_LENGTH;
+ break;
+
+ /* Receive request */
+ case kI2C_SlaveReceiveEvent:
+ /* Update information for received process */
+ xfer->data = g_slave_buff;
+ xfer->dataSize = I2C_DATA_LENGTH;
+ break;
+
+ /* Transfer done */
+ case kI2C_SlaveCompletionEvent:
+ g_SlaveCompletionFlag = true;
+ break;
+
+ default:
+ g_SlaveCompletionFlag = true;
+ break;
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ i2c_slave_config_t slaveConfig;
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ PRINTF("\r\nI2C board2board interrupt example -- Slave transfer.\r\n\r\n");
+
+ /*1.Set up i2c slave first*/
+ /*
+ * slaveConfig->addressingMode = kI2C_Address7bit;
+ * slaveConfig->enableGeneralCall = false;
+ * slaveConfig->enableWakeUp = false;
+ * slaveConfig->enableHighDrive = false;
+ * slaveConfig->enableBaudRateCtl = false;
+ * slaveConfig->enableSlave = true;
+ */
+ I2C_SlaveGetDefaultConfig(&slaveConfig);
+
+ slaveConfig.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT;
+
+ I2C_SlaveInit(EXAMPLE_I2C_SLAVE_BASEADDR, &slaveConfig);
+
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ g_slave_buff[i] = 0;
+ }
+
+ memset(&g_s_handle, 0, sizeof(g_s_handle));
+
+ I2C_SlaveTransferCreateHandle(EXAMPLE_I2C_SLAVE_BASEADDR, &g_s_handle, i2c_slave_callback, NULL);
+
+ /* Set up slave transfer. */
+ I2C_SlaveTransferNonBlocking(EXAMPLE_I2C_SLAVE_BASEADDR, &g_s_handle, kI2C_SlaveCompletionEvent);
+
+ /* Wait for transfer completed. */
+ while (!g_SlaveCompletionFlag)
+ {
+ }
+ g_SlaveCompletionFlag = false;
+
+ PRINTF("Slave received data :");
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ if (i % 8 == 0)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF("0x%2x ", g_slave_buff[i]);
+ }
+ PRINTF("\r\n\r\n");
+
+ /* Wait for master receive completed.*/
+ while (!g_SlaveCompletionFlag)
+ {
+ }
+ g_SlaveCompletionFlag = false;
+
+ PRINTF("\r\nEnd of I2C example .\r\n");
+ while (1)
+ {
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/ii2c_interrupt_b2b_transfer_slave_v3_10.xml b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/ii2c_interrupt_b2b_transfer_slave_v3_10.xml
new file mode 100644
index 000000000..e703ca346
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/ii2c_interrupt_b2b_transfer_slave_v3_10.xml
@@ -0,0 +1,131 @@
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diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/pin_mux.c b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/pin_mux.c
new file mode 100644
index 000000000..962a24e6a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/pin_mux.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D13, peripheral: I2C4, signal: i2c_scl, pin_signal: I2C4_SCL, PE: Disabled, HYS: Enabled, SION: ENABLED, DSE: X6_0}
+ - {pin_num: E13, peripheral: I2C4, signal: i2c_sda, pin_signal: I2C4_SDA, PE: Disabled, HYS: Enabled, SION: ENABLED, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SCL_I2C4_SCL, 1U);
+ IOMUXC_SetPinConfig(IOMUXC_I2C4_SCL_I2C4_SCL,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_I2C4_SDA, 1U);
+ IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_I2C4_SDA,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/pin_mux.h b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/readme.txt b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/readme.txt
new file mode 100644
index 000000000..7923d3cf3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/interrupt_b2b_transfer/slave/readme.txt
@@ -0,0 +1,62 @@
+Overview
+========
+The i2c_interrupt_b2b_transfer_slave example shows how to use i2c driver as slave to do board to board transfer
+with interrupt:
+
+In this example, one i2c instance as slave and another i2c instance on the other board as master. Master sends a
+piece of data to slave, and receive a piece of data from slave. This example checks if the data received from
+slave is correct.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+I2C one board:
+ + Transfer data from SLAVE_BOARD to MASTER_BOARD of I2C interface, I2C4 pins of SLAVE_BOARD are connected with
+ I2C4 pins of MASTER_BOARD
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+SLAVE_BOARD CONNECTS TO MASTER_BOARD
+Pin Name Board Location Pin Name Board Location
+For I2C4 connection, refer to: https://variwiki.com/index.php?title=MCUXpresso&release=MCUXPRESSO_2.13.0_V1.0_DART-MX8M-MINI#Demos_pins
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the demo runs successfully, the following message is displayed in the terminal:
+
+I2C board2board interrupt example -- Slave transfer.
+
+
+Slave received data :
+0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7
+0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f
+0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
+
+
+End of I2C example .
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..14f8ea86d
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(ii2c_polling_b2b_transfer_master)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME ii2c_polling_b2b_transfer_master.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../i2c_polling_b2b_transfer_master.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_ii2c_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ii2c_polling_b2b_transfer_master.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_all.bat
new file mode 100644
index 000000000..6868c7569
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_all.sh
new file mode 100755
index 000000000..888128e66
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..8771607cb
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..1f660e5af
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..0dfc882b6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..cbb10c43f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_debug.bat
new file mode 100644
index 000000000..0636e21b5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_debug.sh
new file mode 100755
index 000000000..30c0ab2d5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..f0275ea6a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..35370ab2f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..51e8b73fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..ef8236b19
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_release.bat
new file mode 100644
index 000000000..a34003e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_release.sh
new file mode 100755
index 000000000..012619cda
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/board.c b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/board.h b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/clock_config.c b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/clock_config.h b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/i2c_polling_b2b_transfer_master.c b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/i2c_polling_b2b_transfer_master.c
new file mode 100644
index 000000000..568d8bcdb
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/i2c_polling_b2b_transfer_master.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Standard C Included Files */
+#include
+/* SDK Included Files */
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_i2c.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_I2C_MASTER_BASEADDR I2C4
+#define I2C_MASTER_CLK_FREQ \
+ (CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootI2c4)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootI2c4)) / 5) /* SYSTEM PLL1 DIV5 */
+
+#define I2C_MASTER_SLAVE_ADDR_7BIT 0x7EU
+#define I2C_BAUDRATE 100000U
+#define I2C_DATA_LENGTH 32U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+uint8_t g_master_txBuff[I2C_DATA_LENGTH];
+uint8_t g_master_rxBuff[I2C_DATA_LENGTH];
+volatile bool g_MasterCompletionFlag = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ i2c_master_config_t masterConfig;
+ uint32_t sourceClock;
+ i2c_master_transfer_t masterXfer;
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ CLOCK_SetRootMux(kCLOCK_RootI2c4, kCLOCK_I2cRootmuxSysPll1Div5); /* Set I2C source to SysPLL1 Div5 160MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootI2c4, 1U, 10U); /* Set root clock to 160MHZ / 10 = 16MHZ */
+
+ PRINTF("\r\nI2C board2board polling example -- Master transfer.\r\n");
+
+ /*2.Set up i2c master to send data to slave*/
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ g_master_txBuff[i] = i;
+ }
+
+ PRINTF("Master will send data :");
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ if (i % 8 == 0)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF("0x%2x ", g_master_txBuff[i]);
+ }
+ PRINTF("\r\n\r\n");
+
+ /*
+ * masterConfig->baudRate_Bps = 100000U;
+ * masterConfig->enableHighDrive = false;
+ * masterConfig->enableStopHold = false;
+ * masterConfig->glitchFilterWidth = 0U;
+ * masterConfig->enableMaster = true;
+ */
+ I2C_MasterGetDefaultConfig(&masterConfig);
+ masterConfig.baudRate_Bps = I2C_BAUDRATE;
+
+ sourceClock = I2C_MASTER_CLK_FREQ;
+
+ I2C_MasterInit(EXAMPLE_I2C_MASTER_BASEADDR, &masterConfig, sourceClock);
+
+ memset(&masterXfer, 0, sizeof(masterXfer));
+
+ masterXfer.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT;
+ masterXfer.direction = kI2C_Write;
+ masterXfer.subaddress = (uint32_t)NULL;
+ masterXfer.subaddressSize = 0;
+ masterXfer.data = g_master_txBuff;
+ masterXfer.dataSize = I2C_DATA_LENGTH;
+ masterXfer.flags = kI2C_TransferDefaultFlag;
+
+ I2C_MasterTransferBlocking(EXAMPLE_I2C_MASTER_BASEADDR, &masterXfer);
+
+ PRINTF("Receive sent data from slave :");
+
+ masterXfer.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT;
+ masterXfer.direction = kI2C_Read;
+ masterXfer.subaddress = (uint32_t)NULL;
+ masterXfer.subaddressSize = 0;
+ masterXfer.data = g_master_rxBuff;
+ masterXfer.dataSize = I2C_DATA_LENGTH;
+
+ masterXfer.flags = kI2C_TransferDefaultFlag;
+
+ I2C_MasterTransferBlocking(EXAMPLE_I2C_MASTER_BASEADDR, &masterXfer);
+
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ if (i % 8 == 0)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF("0x%2x ", g_master_rxBuff[i]);
+ }
+ PRINTF("\r\n\r\n");
+
+ /* 6.Transfer completed. Check the data.*/
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ if (g_master_rxBuff[i] != g_master_txBuff[i])
+ {
+ PRINTF("\r\nError occurred in the transfer ! \r\n");
+ break;
+ }
+ }
+
+ PRINTF("\r\nEnd of I2C example .\r\n");
+ while (1)
+ {
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/ii2c_polling_b2b_transfer_master_v3_10.xml b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/ii2c_polling_b2b_transfer_master_v3_10.xml
new file mode 100644
index 000000000..dec7f8baa
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/ii2c_polling_b2b_transfer_master_v3_10.xml
@@ -0,0 +1,131 @@
+
+
+
+
+
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+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/pin_mux.c b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/pin_mux.c
new file mode 100644
index 000000000..962a24e6a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/pin_mux.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D13, peripheral: I2C4, signal: i2c_scl, pin_signal: I2C4_SCL, PE: Disabled, HYS: Enabled, SION: ENABLED, DSE: X6_0}
+ - {pin_num: E13, peripheral: I2C4, signal: i2c_sda, pin_signal: I2C4_SDA, PE: Disabled, HYS: Enabled, SION: ENABLED, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SCL_I2C4_SCL, 1U);
+ IOMUXC_SetPinConfig(IOMUXC_I2C4_SCL_I2C4_SCL,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_I2C4_SDA, 1U);
+ IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_I2C4_SDA,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/pin_mux.h b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/readme.txt b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/readme.txt
new file mode 100644
index 000000000..402c73abe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/master/readme.txt
@@ -0,0 +1,66 @@
+Overview
+========
+The i2c_polling_b2b_transfer_master example shows how to use i2c driver as master to do board to board transfer
+using polling method:
+
+In this example, one i2c instance as master and another i2c instance on the other board as slave. Master sends a
+piece of data to slave, and receive a piece of data from slave. This example checks if the data received from
+slave is correct.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+I2C one board:
+ + Transfer data from MASTER_BOARD to SLAVE_BOARD of I2C interface, I2C4 pins of MASTER_BOARD are connected with
+ I2C4 pins of SLAVE_BOARD
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+SLAVE_BOARD CONNECTS TO MASTER_BOARD
+Pin Name Board Location Pin Name Board Location
+For I2C4 connection, refer to: https://variwiki.com/index.php?title=MCUXpresso&release=MCUXPRESSO_2.13.0_V1.0_DART-MX8M-MINI#Demos_pins
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the demo runs successfully, the following message is displayed in the terminal:
+
+
+I2C board2board polling example -- Master transfer.
+Master will send data :
+0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7
+0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f
+0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
+
+Receive sent data from slave :
+0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7
+0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f
+0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
+
+
+End of I2C example .
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..070ae9a24
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(ii2c_polling_b2b_transfer_slave)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME ii2c_polling_b2b_transfer_slave.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../i2c_polling_b2b_transfer_slave.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_ii2c_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ii2c_polling_b2b_transfer_slave.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_all.bat
new file mode 100644
index 000000000..6868c7569
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_all.sh
new file mode 100755
index 000000000..888128e66
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..8771607cb
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..1f660e5af
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..0dfc882b6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..cbb10c43f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_debug.bat
new file mode 100644
index 000000000..0636e21b5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_debug.sh
new file mode 100755
index 000000000..30c0ab2d5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..f0275ea6a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..35370ab2f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..51e8b73fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..ef8236b19
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_release.bat
new file mode 100644
index 000000000..a34003e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_release.sh
new file mode 100755
index 000000000..012619cda
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/board.c b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/board.h b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/clock_config.c b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/clock_config.h b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/i2c_polling_b2b_transfer_slave.c b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/i2c_polling_b2b_transfer_slave.c
new file mode 100644
index 000000000..156ef8160
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/i2c_polling_b2b_transfer_slave.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Standard C Included Files */
+#include
+/* SDK Included Files */
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_i2c.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_I2C_SLAVE_BASEADDR I2C4
+
+#define I2C_MASTER_SLAVE_ADDR_7BIT 0x7EU
+#define I2C_DATA_LENGTH 32U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+uint8_t g_slave_buff[I2C_DATA_LENGTH];
+i2c_slave_handle_t g_s_handle;
+volatile bool g_SlaveCompletionFlag = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData)
+{
+ switch (xfer->event)
+ {
+ /* Transmit request */
+ case kI2C_SlaveTransmitEvent:
+ /* Update information for transmit process */
+ xfer->data = g_slave_buff;
+ xfer->dataSize = I2C_DATA_LENGTH;
+ break;
+
+ /* Receive request */
+ case kI2C_SlaveReceiveEvent:
+ /* Update information for received process */
+ xfer->data = g_slave_buff;
+ xfer->dataSize = I2C_DATA_LENGTH;
+ break;
+
+ /* Transfer done */
+ case kI2C_SlaveCompletionEvent:
+ g_SlaveCompletionFlag = true;
+ break;
+
+ default:
+ g_SlaveCompletionFlag = true;
+ break;
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ i2c_slave_config_t slaveConfig;
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ PRINTF("\r\nI2C board2board polling example -- Slave transfer.\r\n\r\n");
+
+ /*1.Set up i2c slave first*/
+ /*
+ * slaveConfig->addressingMode = kI2C_Address7bit;
+ * slaveConfig->enableGeneralCall = false;
+ * slaveConfig->enableWakeUp = false;
+ * slaveConfig->enableHighDrive = false;
+ * slaveConfig->enableBaudRateCtl = false;
+ * slaveConfig->enableSlave = true;
+ */
+ I2C_SlaveGetDefaultConfig(&slaveConfig);
+
+ slaveConfig.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT;
+
+ I2C_SlaveInit(EXAMPLE_I2C_SLAVE_BASEADDR, &slaveConfig);
+
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ g_slave_buff[i] = 0;
+ }
+
+ memset(&g_s_handle, 0, sizeof(g_s_handle));
+
+ I2C_SlaveTransferCreateHandle(EXAMPLE_I2C_SLAVE_BASEADDR, &g_s_handle, i2c_slave_callback, NULL);
+
+ /* Set up slave transfer. */
+ I2C_SlaveTransferNonBlocking(EXAMPLE_I2C_SLAVE_BASEADDR, &g_s_handle, kI2C_SlaveCompletionEvent);
+
+ /* Wait for transfer completed. */
+ while (!g_SlaveCompletionFlag)
+ {
+ }
+ g_SlaveCompletionFlag = false;
+
+ PRINTF("Slave received data :");
+ for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++)
+ {
+ if (i % 8 == 0)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF("0x%2x ", g_slave_buff[i]);
+ }
+ PRINTF("\r\n\r\n");
+
+ /* Wait for master receive completed.*/
+ while (!g_SlaveCompletionFlag)
+ {
+ }
+ g_SlaveCompletionFlag = false;
+
+ PRINTF("\r\nEnd of I2C example .\r\n");
+ while (1)
+ {
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/ii2c_polling_b2b_transfer_slave_v3_10.xml b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/ii2c_polling_b2b_transfer_slave_v3_10.xml
new file mode 100644
index 000000000..8586fddd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/ii2c_polling_b2b_transfer_slave_v3_10.xml
@@ -0,0 +1,131 @@
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diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/pin_mux.c b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/pin_mux.c
new file mode 100644
index 000000000..962a24e6a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/pin_mux.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D13, peripheral: I2C4, signal: i2c_scl, pin_signal: I2C4_SCL, PE: Disabled, HYS: Enabled, SION: ENABLED, DSE: X6_0}
+ - {pin_num: E13, peripheral: I2C4, signal: i2c_sda, pin_signal: I2C4_SDA, PE: Disabled, HYS: Enabled, SION: ENABLED, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SCL_I2C4_SCL, 1U);
+ IOMUXC_SetPinConfig(IOMUXC_I2C4_SCL_I2C4_SCL,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_I2C4_SDA, 1U);
+ IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_I2C4_SDA,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/pin_mux.h b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/readme.txt b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/readme.txt
new file mode 100644
index 000000000..bda335af4
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/i2c/polling_b2b_transfer/slave/readme.txt
@@ -0,0 +1,61 @@
+Overview
+========
+The i2c_polling_b2b_transfer_slave example shows how to use i2c driver as slave to do board to board transfer
+with a polling master:
+
+In this example, one i2c instance as slave and another i2c instance on the other board as master. Master sends a
+piece of data to slave, and receive a piece of data from slave. This example checks if the data received from
+slave is correct.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+I2C one board:
+ + Transfer data from MASTER_BOARD to SLAVE_BOARD of I2C interface, I2C4 pins of MASTER_BOARD are connected with
+ I2C4 pins of SLAVE_BOARD
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+SLAVE_BOARD CONNECTS TO MASTER_BOARD
+Pin Name Board Location Pin Name Board Location
+For I2C4 connection, refer to: https://variwiki.com/index.php?title=MCUXpresso&release=MCUXPRESSO_2.13.0_V1.0_DART-MX8M-MINI#Demos_pins
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the demo runs successfully, the following message is displayed in the terminal:
+
+I2C board2board polling example -- Slave transfer.
+
+
+Slave received data :
+0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7
+0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f
+0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
+
+
+End of I2C example .
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/pwm/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..2411ca83a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(ipwm)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME ipwm.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../pwm.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(driver_ipwm_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/ipwm.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/pwm/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/pwm/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/pwm/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_all.bat
new file mode 100644
index 000000000..02d62fd34
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_all.sh
new file mode 100755
index 000000000..702783475
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..c84d78542
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..5aa41a2df
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..3fd6f4a78
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c9e344144
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_debug.bat
new file mode 100644
index 000000000..15123387e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_debug.sh
new file mode 100755
index 000000000..42803761b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..acb3c2d91
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..1ce9d36e7
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..83f20fc3c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..f3694ad2e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_release.bat
new file mode 100644
index 000000000..a88e3d668
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_release.sh
new file mode 100755
index 000000000..47cfb057c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/pwm/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/pwm/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/pwm/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/pwm/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/pwm/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/pwm/board.c b/boards/dart_mx8mm/driver_examples/pwm/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/pwm/board.h b/boards/dart_mx8mm/driver_examples/pwm/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/pwm/clock_config.c b/boards/dart_mx8mm/driver_examples/pwm/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/pwm/clock_config.h b/boards/dart_mx8mm/driver_examples/pwm/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/pwm/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/pwm/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/pwm/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/pwm/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/pwm/ipwm_v3_10.xml b/boards/dart_mx8mm/driver_examples/pwm/ipwm_v3_10.xml
new file mode 100644
index 000000000..c626b53d8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/ipwm_v3_10.xml
@@ -0,0 +1,131 @@
+
+
+
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diff --git a/boards/dart_mx8mm/driver_examples/pwm/pin_mux.c b/boards/dart_mx8mm/driver_examples/pwm/pin_mux.c
new file mode 100644
index 000000000..c431eb538
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/pin_mux.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: AF9, peripheral: PWM3, signal: pwm_out, pin_signal: SPDIF_TX, PE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_SPDIF_TX_PWM3_OUT, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_SPDIF_TX_PWM3_OUT,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/pwm/pin_mux.h b/boards/dart_mx8mm/driver_examples/pwm/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/pwm/pwm.c b/boards/dart_mx8mm/driver_examples/pwm/pwm.c
new file mode 100644
index 000000000..f0d87871d
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/pwm.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_pwm.h"
+
+#include "fsl_common.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DEMO_PWM_BASEADDR PWM3
+#define DEMO_PWM_IRQn PWM3_IRQn
+#define DEMO_PWM_IRQHandler PWM3_IRQHandler
+/*! @brief PWM period value. PWMO (Hz) = PCLK(Hz) / (period +2) */
+#define PWM_PERIOD_VALUE 30
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+volatile uint32_t pwmDutycycle = 0U;
+volatile bool pwmDutyUp = true; /* Indicate PWM Duty cycle is increase or decrease */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void DEMO_PWM_IRQHandler(void)
+{
+ /* Gets interrupt kPWM_FIFOEmptyFlag */
+ if (PWM_GetStatusFlags(DEMO_PWM_BASEADDR) & kPWM_FIFOEmptyFlag)
+ {
+ if (pwmDutyUp)
+ {
+ /* Increase duty cycle until it reach limited value. */
+ if (++pwmDutycycle > PWM_PERIOD_VALUE)
+ {
+ pwmDutycycle = PWM_PERIOD_VALUE;
+ pwmDutyUp = false;
+ }
+ }
+ else
+ {
+ /* Decrease duty cycle until it reach limited value. */
+ if (--pwmDutycycle == 0U)
+ {
+ pwmDutyUp = true;
+ }
+ }
+ /* Write duty cycle to PWM sample register. */
+ PWM_SetSampleValue(DEMO_PWM_BASEADDR, pwmDutycycle);
+ /* Clear kPWM_FIFOEmptyFlag */
+ PWM_clearStatusFlags(DEMO_PWM_BASEADDR, kPWM_FIFOEmptyFlag);
+ }
+ SDK_ISR_EXIT_BARRIER;
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ pwm_config_t pwmConfig;
+
+ /* Board pin, clock, debug console init */
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ PRINTF("\r\nPWM driver example.\r\n");
+
+ /*!
+ * config->enableStopMode = false;
+ * config->enableDozeMode = false;
+ * config->enableWaitMode = false;
+ * config->enableDebugMode = false;
+ * config->clockSource = kPWM_LowFrequencyClock;
+ * config->prescale = 0U;
+ * config->outputConfig = kPWM_SetAtRolloverAndClearAtcomparison;
+ * config->fifoWater = kPWM_FIFOWaterMark_2;
+ * config->sampleRepeat = kPWM_EachSampleOnce;
+ * config->byteSwap = kPWM_ByteNoSwap;
+ * config->halfWordSwap = kPWM_HalfWordNoSwap;
+ */
+ PWM_GetDefaultConfig(&pwmConfig);
+
+ /* Initialize PWM module */
+ PWM_Init(DEMO_PWM_BASEADDR, &pwmConfig);
+
+ /* Enable FIFO empty interrupt */
+ PWM_EnableInterrupts(DEMO_PWM_BASEADDR, kPWM_FIFOEmptyInterruptEnable);
+
+ /* Three initial samples be written to the PWM Sample Register */
+ for (pwmDutycycle = 0u; pwmDutycycle < 3; pwmDutycycle++)
+ {
+ PWM_SetSampleValue(DEMO_PWM_BASEADDR, pwmDutycycle);
+ }
+
+ /* Check and Clear interrupt status flags */
+ if (PWM_GetStatusFlags(DEMO_PWM_BASEADDR))
+ {
+ PWM_clearStatusFlags(DEMO_PWM_BASEADDR,
+ kPWM_FIFOEmptyFlag | kPWM_RolloverFlag | kPWM_CompareFlag | kPWM_FIFOWriteErrorFlag);
+ }
+
+ /* Write the period to the PWM Period Register */
+ PWM_SetPeriodValue(DEMO_PWM_BASEADDR, PWM_PERIOD_VALUE);
+
+ /* Enable PWM interrupt request */
+ EnableIRQ(DEMO_PWM_IRQn);
+
+ PWM_StartTimer(DEMO_PWM_BASEADDR);
+
+ while (1)
+ {
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/pwm/readme.txt b/boards/dart_mx8mm/driver_examples/pwm/readme.txt
new file mode 100644
index 000000000..3bf77a9fa
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/pwm/readme.txt
@@ -0,0 +1,50 @@
+Overview
+========
+The PWM project is a simple demonstration program of the SDK PWM driver. It sets up the PWM hardware
+block to output PWM signals on one PWM channel. The example also shows PWM duty cycle is increase or decrease.
+The FIFO empty interrupt is provided. A new value will be loaded into FIFO when FIFO empty status bit is set.
+The PWM will run at the last set duty-cycle setting if all the values of the FIFO has been utilized,
+until the FIFO is reloaded or the PWM is disabled. When a new value is written, the duty cycle changes after the current period is over.
+The outputs can be observed by oscilloscope.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+For PWM output pin refer to: https://variwiki.com/index.php?title=MCUXpresso&release=MCUXPRESSO_2.13.0_V1.0_DART-MX8M-MINI#Demos_pins
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+
+Running the demo
+================
+These instructions are displayed/shown on the terminal window:
+~~~~~~~~~~~~~~~~~~~~~~~
+PWM driver example.
+~~~~~~~~~~~~~~~~~~~~~~~
+
+
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/rdc/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..2752433b7
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/CMakeLists.txt
@@ -0,0 +1,111 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(rdc)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME rdc.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../rdc.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_igpio_MIMX8MM6)
+
+include(driver_cache_lmem_MIMX8MM6)
+
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(driver_rdc_sema42_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/rdc.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/rdc/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/rdc/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/rdc/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_all.bat
new file mode 100644
index 000000000..02d62fd34
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_all.sh
new file mode 100755
index 000000000..702783475
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..c84d78542
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..5aa41a2df
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..3fd6f4a78
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c9e344144
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_debug.bat
new file mode 100644
index 000000000..15123387e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_debug.sh
new file mode 100755
index 000000000..42803761b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..acb3c2d91
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..1ce9d36e7
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..83f20fc3c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..f3694ad2e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_release.bat
new file mode 100644
index 000000000..a88e3d668
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_release.sh
new file mode 100755
index 000000000..47cfb057c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/rdc/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/rdc/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/rdc/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/rdc/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/rdc/armgcc/flags.cmake
new file mode 100755
index 000000000..6b357f7c7
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/armgcc/flags.cmake
@@ -0,0 +1,509 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -D__SEMIHOST_HARDFAULT_DISABLE=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -D__SEMIHOST_HARDFAULT_DISABLE=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -D__SEMIHOST_HARDFAULT_DISABLE=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -D__SEMIHOST_HARDFAULT_DISABLE=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -D__SEMIHOST_HARDFAULT_DISABLE=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -D__SEMIHOST_HARDFAULT_DISABLE=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/rdc/board.c b/boards/dart_mx8mm/driver_examples/rdc/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/rdc/board.h b/boards/dart_mx8mm/driver_examples/rdc/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/rdc/clock_config.c b/boards/dart_mx8mm/driver_examples/rdc/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/rdc/clock_config.h b/boards/dart_mx8mm/driver_examples/rdc/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/rdc/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/rdc/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/rdc/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/rdc/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/rdc/pin_mux.c b/boards/dart_mx8mm/driver_examples/rdc/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/rdc/pin_mux.h b/boards/dart_mx8mm/driver_examples/rdc/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/rdc/rdc.c b/boards/dart_mx8mm/driver_examples/rdc/rdc.c
new file mode 100644
index 000000000..c54d890c8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/rdc.c
@@ -0,0 +1,358 @@
+/*
+ * Copyright 2017-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_rdc_sema42.h"
+
+#include "fsl_gpio.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define APP_RDC RDC
+#define APP_CUR_MASTER kRDC_Master_M4
+#define APP_CUR_MASTER_DID BOARD_DOMAIN_ID /* Current master domain ID. */
+#define APP_RDC_PERIPH kRDC_Periph_GPIO1
+#define APP_RDC_SEMA42 RDC_SEMAPHORE1 /* Current master domain ID. */
+#define APP_RDC_SEMA42_GATE (((uint8_t)APP_RDC_PERIPH) & 0x3F)
+
+/* OCRAM is used for demonstration here. */
+#define APP_RDC_MEM kRDC_Mem_MRC3_0
+#define APP_RDC_MEM_BASE_ADDR 0x900000
+#define APP_RDC_MEM_END_ADDR 0x920000
+
+/*
+ * Master index:
+ * All masters excluding ARM core: 0
+ * A53 core: 1
+ * M4 core: 6
+ * SDMA 3
+ */
+#define APP_MASTER_INDEX 6
+
+/*
+ * If cache is enabled, this example should maintain the cache to make sure
+ * CPU core accesses the memory, not cache only.
+ */
+#define APP_USING_CACHE 1
+
+typedef enum
+{
+ kRDC_DEMO_None = 0,
+ kRDC_DEMO_Periph = 1,
+ kRDC_DEMO_PeriphSema42 = 2,
+ kRDC_DEMO_Mem = 3,
+} rdc_demo_state_t;
+
+#define DEMO_CHECK(x) \
+ if (!(x)) \
+ { \
+ PRINTF("Example error\r\n"); \
+ for (;;) \
+ ; \
+ }
+
+/* For some platforms, the core's domain ID
+ * is not configured by RDC, for example, it
+ * is fixed value and not configurable.
+ * In this case, APP_ASSIGN_DOMAIN_ID_BY_RDC
+ * could be over-written to 0, and a function
+ * APP_AssignCoreDomain assigns the core's domain.
+ */
+#ifndef APP_ASSIGN_DOMAIN_ID_BY_RDC
+#define APP_ASSIGN_DOMAIN_ID_BY_RDC 1
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+void APP_TouchPeriph(void);
+void APP_TouchMem(void);
+/*
+ * In this function, sema42 is not required. The peripheral is set inaccessible
+ * by current domain. When touch the peripheral, hardfault is triggered. In
+ * hardfault handler, the peripheral is set accessible by current domain.
+ */
+static void APP_RDC_Periph(void);
+
+/*
+ * In this function, sema42 is required. The peripheral is set accessible by
+ * current domain, before touch the peripheral, the sema42 gate should be locked.
+ * So in this function, core touch the peripheral before locking the sema42 gate,
+ * then hardfault happens. In hardfault handler, core locks the sema42, then
+ * the peripheral is accessible.
+ */
+static void APP_RDC_PeriphWithSema42(void);
+
+/*
+ * In this function, the memory region is set inaccessible by current domain.
+ * When touch the memory, hardfault is triggered. In hardfault handler, the
+ * memory region is set accessible by current domain.
+ */
+static void APP_RDC_Mem(void);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Current demo state. */
+static volatile rdc_demo_state_t s_demoState = kRDC_DEMO_None;
+/* HardFault happened or not. */
+static volatile bool s_faultFlag = false;
+/* How many error happens during memory region demo. */
+static volatile uint32_t memDemoError = 0;
+
+rdc_domain_assignment_t assignment;
+rdc_periph_access_config_t periphConfig;
+rdc_mem_access_config_t memConfig;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void APP_TouchPeriph(void)
+{
+ GPIO_PinRead(GPIO1, 0);
+}
+
+void APP_TouchMem(void)
+{
+ /* Touch the memory. */
+ (*(volatile uint32_t *)APP_RDC_MEM_BASE_ADDR)++;
+}
+#if APP_USING_CACHE
+#include "fsl_cache.h"
+#endif
+
+static void Fault_Handler(void)
+{
+ rdc_mem_status_t memStatus;
+
+ s_faultFlag = true;
+
+ if (kRDC_DEMO_Periph == s_demoState)
+ {
+ /* Make peripheral accessible. */
+ periphConfig.policy |= RDC_ACCESS_POLICY(APP_CUR_MASTER_DID, kRDC_ReadWrite);
+ RDC_SetPeriphAccessConfig(APP_RDC, &periphConfig);
+ }
+ else if (kRDC_DEMO_PeriphSema42 == s_demoState)
+ {
+ /* Lock the SEMA42 gate, then the peripheral should be accessible. */
+ RDC_SEMA42_Lock(APP_RDC_SEMA42, APP_RDC_SEMA42_GATE, APP_MASTER_INDEX, APP_CUR_MASTER_DID);
+ }
+ else if (kRDC_DEMO_Mem == s_demoState)
+ {
+ /* Check error status. */
+ RDC_GetMemViolationStatus(APP_RDC, APP_RDC_MEM, &memStatus);
+
+ if (false == memStatus.hasViolation)
+ {
+ memDemoError++;
+ }
+
+ if (APP_CUR_MASTER_DID != memStatus.domainID)
+ {
+ memDemoError++;
+ }
+
+ if (APP_RDC_MEM_BASE_ADDR != memStatus.address)
+ {
+ memDemoError++;
+ }
+
+ /* Make memory region accessible. */
+ memConfig.policy |= RDC_ACCESS_POLICY(APP_CUR_MASTER_DID, kRDC_ReadWrite);
+ RDC_SetMemAccessConfig(APP_RDC, &memConfig);
+
+ RDC_ClearMemViolationFlag(APP_RDC, APP_RDC_MEM);
+ }
+ __DSB();
+}
+
+void HardFault_Handler(void)
+{
+ Fault_Handler();
+}
+
+void BusFault_Handler(void)
+{
+ Fault_Handler();
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ /* Init GPIO used for peripheral access demonstration. */
+ gpio_pin_config_t pinConfig = {
+ kGPIO_DigitalOutput,
+ 0,
+ kGPIO_IntRisingEdge,
+ };
+
+ GPIO_PinInit(GPIO1, 0, &pinConfig);
+
+ /* Set the IOMUXC_GPR10[2:3], thus the memory violation triggers the hardfault. */
+ *(volatile uint32_t *)0x30340028 |= (0x0C);
+
+ PRINTF("\r\nRDC Example:\r\n");
+
+ RDC_Init(APP_RDC);
+ RDC_SEMA42_Init(APP_RDC_SEMA42);
+
+#if APP_ASSIGN_DOMAIN_ID_BY_RDC
+ /* Assign current master domain. */
+ RDC_GetDefaultMasterDomainAssignment(&assignment);
+ assignment.domainId = APP_CUR_MASTER_DID;
+ RDC_SetMasterDomainAssignment(APP_RDC, APP_CUR_MASTER, &assignment);
+#else
+ APP_AssignCoreDomain();
+#endif
+
+ APP_RDC_Periph();
+
+ APP_RDC_PeriphWithSema42();
+
+ APP_RDC_Mem();
+
+ PRINTF("\r\nRDC Example Success\r\n");
+
+ while (1)
+ {
+ }
+}
+
+static void APP_RDC_Periph(void)
+{
+ PRINTF("RDC Peripheral access control\r\n");
+
+ s_demoState = kRDC_DEMO_Periph;
+
+ /*
+ * Item 1: Peripheral accessible.
+ */
+ RDC_GetDefaultPeriphAccessConfig(&periphConfig);
+ periphConfig.periph = APP_RDC_PERIPH;
+
+ /* Set peripheral to accessible by all domains. */
+ RDC_SetPeriphAccessConfig(APP_RDC, &periphConfig);
+
+ s_faultFlag = false;
+
+ APP_TouchPeriph();
+
+ /* Peripheral is accessible, there should not be hardfault. */
+ DEMO_CHECK(false == s_faultFlag);
+
+ /*
+ * Item 2: Peripheral inaccessible.
+ */
+ /* Make peripheral not accessible. */
+ periphConfig.policy &= ~(RDC_ACCESS_POLICY(APP_CUR_MASTER_DID, kRDC_ReadWrite));
+ RDC_SetPeriphAccessConfig(APP_RDC, &periphConfig);
+
+ s_faultFlag = false;
+ APP_TouchPeriph();
+
+ /* Peripheral is not accessible, there should be hardfault. */
+ DEMO_CHECK(true == s_faultFlag);
+}
+
+static void APP_RDC_PeriphWithSema42(void)
+{
+ PRINTF("RDC Peripheral access control with SEMA42\r\n");
+
+ /* Demo the SEMA42 used together with RDC. */
+ s_demoState = kRDC_DEMO_PeriphSema42;
+
+ RDC_GetDefaultPeriphAccessConfig(&periphConfig);
+ periphConfig.periph = APP_RDC_PERIPH;
+ periphConfig.enableSema = true;
+
+ RDC_SetPeriphAccessConfig(APP_RDC, &periphConfig);
+
+ /* Make sure current core does not hold the SEMA42 gate. */
+ RDC_SEMA42_Unlock(APP_RDC_SEMA42, APP_RDC_SEMA42_GATE);
+ DEMO_CHECK(APP_CUR_MASTER_DID != RDC_SEMA42_GetLockDomainID(APP_RDC_SEMA42, APP_RDC_SEMA42_GATE));
+
+ s_faultFlag = false;
+
+ APP_TouchPeriph();
+
+ /* Peripheral is not accessible because SEMA42 gate not locked, there should be hardfault. */
+ DEMO_CHECK(true == s_faultFlag);
+
+ /* Demo finished, make the peripheral to default policy. */
+ RDC_GetDefaultPeriphAccessConfig(&periphConfig);
+
+ /* Set peripheral to accessible by all domains. */
+ RDC_SetPeriphAccessConfig(APP_RDC, &periphConfig);
+
+ RDC_SEMA42_Unlock(APP_RDC_SEMA42, APP_RDC_SEMA42_GATE);
+}
+
+static void APP_RDC_Mem(void)
+{
+ /*
+ * In memory protection, please notice the cache's effect.
+ * For example, if a memory region has been loaded to cache
+ * before it is set not accessible, then CPU only access the
+ * cache but not the memory, application could not detect
+ * access violation.
+ */
+ PRINTF("RDC memory region access control\r\n");
+
+ s_demoState = kRDC_DEMO_Mem;
+
+ RDC_GetDefaultMemAccessConfig(&memConfig);
+
+ memConfig.mem = APP_RDC_MEM;
+ memConfig.baseAddress = APP_RDC_MEM_BASE_ADDR;
+ memConfig.endAddress = APP_RDC_MEM_END_ADDR;
+
+ /* Make memory not accessible. */
+ memConfig.policy &= ~(RDC_ACCESS_POLICY(APP_CUR_MASTER_DID, kRDC_ReadWrite));
+
+ RDC_SetMemAccessConfig(APP_RDC, &memConfig);
+
+#if APP_USING_CACHE
+ /*
+ * Invalidate the cache, so new read will read from memory directly,
+ * to make sure trigger read error.
+ */
+ DCACHE_InvalidateByRange(APP_RDC_MEM_BASE_ADDR, APP_RDC_MEM_END_ADDR - APP_RDC_MEM_BASE_ADDR);
+#endif
+
+ s_faultFlag = false;
+
+ APP_TouchMem();
+
+#if APP_USING_CACHE
+ /*
+ * Flush the cache, so the modified data is written to memory,
+ * to make sure trigger write error.
+ */
+ DCACHE_CleanInvalidateByRange(APP_RDC_MEM_BASE_ADDR, APP_RDC_MEM_END_ADDR - APP_RDC_MEM_BASE_ADDR);
+ __DSB();
+#endif
+
+ /* Memory is not accessible, there should be hardfault. */
+ DEMO_CHECK(true == s_faultFlag);
+ DEMO_CHECK(0 == memDemoError);
+}
diff --git a/boards/dart_mx8mm/driver_examples/rdc/rdc_v3_10.xml b/boards/dart_mx8mm/driver_examples/rdc/rdc_v3_10.xml
new file mode 100644
index 000000000..897d49017
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/rdc_v3_10.xml
@@ -0,0 +1,134 @@
+
+
+
+
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+
diff --git a/boards/dart_mx8mm/driver_examples/rdc/readme.txt b/boards/dart_mx8mm/driver_examples/rdc/readme.txt
new file mode 100644
index 000000000..374cb3c2c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/rdc/readme.txt
@@ -0,0 +1,47 @@
+Overview
+========
+
+The RDC example shows how to control the peripheral and memory region
+asscess policy using RDC and RDC_SEMA42
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+The log below is shown in the terminal window:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+RDC Example:
+RDC Peripheral access control
+RDC Peripheral access control with SEMA42
+RDC memory region access control
+
+RDC Example Success
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..7c0417b2d
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/CMakeLists.txt
@@ -0,0 +1,111 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(sdma_memory_to_memory)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME sdma_memory_to_memory.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../sdma_memory_to_memory.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_cache_lmem_MIMX8MM6)
+
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_sdma_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(driver_memory_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdma_memory_to_memory.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/board.c b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/board.c
new file mode 100644
index 000000000..7ac3cfc4e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/board.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+#include "fsl_cache.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /*
+ * Flush the system cache before updating the cache policy. Without flushing, the
+ * previously done initialization of the non-cacheable sections will be discarded
+ * as the cache for this region was enabled with the write-back attribute before.
+ */
+ L1CACHE_CleanSystemCache();
+ __DSB();
+ __ISB();
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/board.h b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/clock_config.c b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/clock_config.h b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/pin_mux.c b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/pin_mux.h b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/readme.txt b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/readme.txt
new file mode 100644
index 000000000..1e434619e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/readme.txt
@@ -0,0 +1,54 @@
+Overview
+========
+The EDMA memory to memory example is a simple demonstration program that uses the SDK software.
+It excuates one shot transfer from source buffer to destination buffer using the SDK EDMA drivers.
+The purpose of this example is to show how to use the EDMA and to provide a simple example for
+debugging and further development.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the example runs successfully, you can see the similar information from the terminal as below.
+~~~~~~~~~~~~~~~~~~~~~
+SDMA memory to memory transfer example begin.
+
+Destination Buffer:
+0 0 0 0
+
+SDMA memory to memory transfer example finish.
+
+Destination Buffer:
+1 2 3 4
+~~~~~~~~~~~~~~~~~~~~~
+
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/sdma_memory_to_memory.c b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/sdma_memory_to_memory.c
new file mode 100644
index 000000000..9cc07178f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/sdma_memory_to_memory.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_sdma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_SDMAARM SDMAARM3
+#define DEMO_SDMA_CLOCK_RATIO kSDMA_ARMClockFreq
+#define BUFF_LENGTH 4U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+sdma_handle_t g_SDMA_Handle = {0};
+
+volatile bool g_Transfer_Done = false;
+AT_NONCACHEABLE_SECTION_ALIGN(sdma_context_data_t context, 4);
+
+AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint32_t srcAddr[BUFF_LENGTH], 4) = {0x01, 0x02, 0x03, 0x04};
+AT_NONCACHEABLE_SECTION_ALIGN(uint32_t destAddr[BUFF_LENGTH], 16);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* User callback function for SDMA transfer. */
+void SDMA_Callback(sdma_handle_t *handle, void *param, bool transferDone, uint32_t bds)
+{
+ if (transferDone)
+ {
+ g_Transfer_Done = true;
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ uint32_t i = 0;
+ sdma_transfer_config_t transferConfig = {0U};
+ sdma_config_t userConfig;
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ /* Print source buffer */
+ PRINTF("\r\nSDMA memory to memory transfer example begin.\r\n");
+ PRINTF("\r\nDestination Buffer:\r\n");
+ for (i = 0; i < BUFF_LENGTH; i++)
+ {
+ PRINTF("%d\t", destAddr[i]);
+ }
+
+ /* Configure SDMA one shot transfer */
+ SDMA_GetDefaultConfig(&userConfig);
+#if defined DEMO_SDMA_CLOCK_RATIO
+ userConfig.ratio = DEMO_SDMA_CLOCK_RATIO;
+#endif
+ SDMA_Init(EXAMPLE_SDMAARM, &userConfig);
+ SDMA_CreateHandle(&g_SDMA_Handle, EXAMPLE_SDMAARM, 1, &context);
+ SDMA_SetCallback(&g_SDMA_Handle, SDMA_Callback, NULL);
+ SDMA_PrepareTransfer(&transferConfig, (uint32_t)srcAddr, (uint32_t)destAddr, sizeof(srcAddr[0]),
+ sizeof(destAddr[0]), sizeof(srcAddr[0]), sizeof(srcAddr), 0, kSDMA_PeripheralTypeMemory,
+ kSDMA_MemoryToMemory);
+ SDMA_SubmitTransfer(&g_SDMA_Handle, &transferConfig);
+ SDMA_SetChannelPriority(EXAMPLE_SDMAARM, 1, 2U);
+ SDMA_StartTransfer(&g_SDMA_Handle);
+ /* Wait for SDMA transfer finish */
+ while (g_Transfer_Done != true)
+ {
+ }
+ /* Print destination buffer */
+ PRINTF("\r\nSDMA memory to memory transfer example finish.\r\n");
+ PRINTF("Destination Buffer:\r\n");
+ for (i = 0; i < BUFF_LENGTH; i++)
+ {
+ PRINTF("%d\t", destAddr[i]);
+ }
+
+ while (1)
+ {
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/sdma_memory_to_memory_v3_10.xml b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/sdma_memory_to_memory_v3_10.xml
new file mode 100644
index 000000000..18e1d3d7e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/memory_to_memory/sdma_memory_to_memory_v3_10.xml
@@ -0,0 +1,132 @@
+
+
+
+
+
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+
+
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..350b4d3e6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/CMakeLists.txt
@@ -0,0 +1,111 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(sdma_scatter_gather)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME sdma_scatter_gather.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../sdma_scatter_gather.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_cache_lmem_MIMX8MM6)
+
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_sdma_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(driver_memory_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdma_scatter_gather.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/board.c b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/board.c
new file mode 100644
index 000000000..7ac3cfc4e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/board.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+#include "fsl_cache.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /*
+ * Flush the system cache before updating the cache policy. Without flushing, the
+ * previously done initialization of the non-cacheable sections will be discarded
+ * as the cache for this region was enabled with the write-back attribute before.
+ */
+ L1CACHE_CleanSystemCache();
+ __DSB();
+ __ISB();
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/board.h b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/clock_config.c b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/clock_config.h b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/pin_mux.c b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/pin_mux.h b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/readme.txt b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/readme.txt
new file mode 100644
index 000000000..adc465894
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/readme.txt
@@ -0,0 +1,54 @@
+Overview
+========
+The SDMA scatter gather example is a simple demonstration program that uses the SDK software.
+It excuates several shots transfer from source buffer to destination buffer using the SDK SDMA drivers.
+The purpose of this example is to show how to use the SDMA and to provide a scatter gather example for
+debugging and further development.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the example runs successfully, you can see the similar information from the terminal as below.
+
+~~~~~~~~~~~~~~~~~~~~~
+SDMA scatter_gather transfer example begin.
+
+Destination Buffer:
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+
+SDMA scatter_gather transfer example finish.
+
+Destination Buffer:
+0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/sdma_scatter_gather.c b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/sdma_scatter_gather.c
new file mode 100644
index 000000000..0d539a6bc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/sdma_scatter_gather.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_sdma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_DMA SDMAARM3
+#define DEMO_SDMA_CLOCK_RATIO kSDMA_ARMClockFreq
+#define EXAMPLE_CHANNEL (1U)
+#define BUFFER_LEN 8U
+#define BD_QUEUE_SIZE 2U
+#define BUFFER_TOTAL_LEN (BUFFER_LEN * BD_QUEUE_SIZE)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+sdma_handle_t g_sdma_Handle;
+volatile bool g_Transfer_Done = false;
+AT_NONCACHEABLE_SECTION_ALIGN(uint32_t srcAddr[BUFFER_TOTAL_LEN], 4);
+AT_NONCACHEABLE_SECTION_ALIGN(uint32_t destAddr[BUFFER_TOTAL_LEN], 4);
+
+/* SDMA buffer descriptor */
+AT_NONCACHEABLE_SECTION_ALIGN(sdma_buffer_descriptor_t bd[BD_QUEUE_SIZE], 4);
+
+/* SDMA channel context */
+AT_NONCACHEABLE_SECTION_ALIGN(sdma_context_data_t context, 4);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* User callback function for sdma transfer. */
+void sdma_Callback(sdma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
+{
+ if (transferDone)
+ {
+ g_Transfer_Done = true;
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ uint32_t i = 0;
+ sdma_transfer_config_t transferConfig = {0U};
+ sdma_config_t userConfig;
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+ /* Print source buffer */
+ PRINTF("\r\nsdma scatter gather transfer example begin.\r\n\r\n");
+ PRINTF("Destination Buffer:\r\n");
+ for (i = 0; i < BUFFER_TOTAL_LEN; i++)
+ {
+ srcAddr[i] = i;
+ PRINTF("%d\t", destAddr[i]);
+ }
+
+ /* Configure sdma one shot transfer */
+ SDMA_GetDefaultConfig(&userConfig);
+#if defined DEMO_SDMA_CLOCK_RATIO
+ userConfig.ratio = DEMO_SDMA_CLOCK_RATIO;
+#endif
+ SDMA_Init(EXAMPLE_DMA, &userConfig);
+ SDMA_CreateHandle(&g_sdma_Handle, EXAMPLE_DMA, EXAMPLE_CHANNEL, &context);
+ SDMA_SetCallback(&g_sdma_Handle, sdma_Callback, NULL);
+
+ /* Install buffer descritptor list to handle */
+ SDMA_InstallBDMemory(&g_sdma_Handle, bd, BD_QUEUE_SIZE);
+
+ /* Configure the buffer descriptor except the last one */
+ for (i = 0; i < BD_QUEUE_SIZE - 1U; i++)
+ {
+ SDMA_ConfigBufferDescriptor(&bd[i], (uint32_t)&srcAddr[i * BUFFER_LEN], (uint32_t)&destAddr[i * BUFFER_LEN],
+ kSDMA_TransferSize4Bytes, sizeof(uint32_t) * BUFFER_LEN, false, false, false,
+ kSDMA_MemoryToMemory);
+ }
+
+ /* Configure the last buffer descriptor, the last descriptor shall be last one and can generate interrupt */
+ SDMA_ConfigBufferDescriptor(&bd[i], (uint32_t)&srcAddr[i * BUFFER_LEN], (uint32_t)&destAddr[i * BUFFER_LEN],
+ kSDMA_TransferSize4Bytes, sizeof(uint32_t) * BUFFER_LEN, true, true, false,
+ kSDMA_MemoryToMemory);
+
+ /* Prepare transfer */
+ SDMA_PrepareTransfer(&transferConfig, (uint32_t)srcAddr, (uint32_t)destAddr, sizeof(uint32_t), sizeof(uint32_t),
+ sizeof(uint32_t), BUFFER_LEN * sizeof(uint32_t), 0U, kSDMA_PeripheralTypeMemory,
+ kSDMA_MemoryToMemory);
+
+ /* Submit the transfer contents into SDMA core */
+ SDMA_SubmitTransfer(&g_sdma_Handle, &transferConfig);
+
+ /* Set channel priority, or the channel cannot run */
+ SDMA_SetChannelPriority(EXAMPLE_DMA, EXAMPLE_CHANNEL, 2U);
+
+ /* Start transfer */
+ SDMA_StartTransfer(&g_sdma_Handle);
+ /* Wait for sdma transfer finish */
+ while (g_Transfer_Done != true)
+ {
+ }
+ /* Print destination buffer */
+ PRINTF("\r\n\r\nsdma scatter gather transfer example finish.\r\n\r\n");
+ PRINTF("Destination Buffer:\r\n");
+ for (i = 0; i < BUFFER_TOTAL_LEN; i++)
+ {
+ PRINTF("%d\t", destAddr[i]);
+ }
+
+ while (1)
+ {
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/sdma_scatter_gather_v3_10.xml b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/sdma_scatter_gather_v3_10.xml
new file mode 100644
index 000000000..4b8910f00
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sdma/scatter_gather/sdma_scatter_gather_v3_10.xml
@@ -0,0 +1,132 @@
+
+
+
+
+
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+
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+
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..f06494eab
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(sema4_uboot)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME sema4_uboot.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../sema4_uboot.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_sema4_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sema4_uboot.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/board.c b/boards/dart_mx8mm/driver_examples/sema4/uboot/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/board.h b/boards/dart_mx8mm/driver_examples/sema4/uboot/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/clock_config.c b/boards/dart_mx8mm/driver_examples/sema4/uboot/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/clock_config.h b/boards/dart_mx8mm/driver_examples/sema4/uboot/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/sema4/uboot/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/sema4/uboot/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/pin_mux.c b/boards/dart_mx8mm/driver_examples/sema4/uboot/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/pin_mux.h b/boards/dart_mx8mm/driver_examples/sema4/uboot/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/readme.txt b/boards/dart_mx8mm/driver_examples/sema4/uboot/readme.txt
new file mode 100644
index 000000000..eece8e02e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/readme.txt
@@ -0,0 +1,50 @@
+Overview
+========
+The sema4 uboot example shows how to use SEMA4 driver to lock and unlock a sema gate,
+the notification IRQ is also demonstrated in this example.
+This example should work together with uboot. This example runs on Cortex-M core,
+the uboot runs on the Cortex-A core.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- SD card with uboot
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+Prepare the Demo
+================
+1. Prepare an SD card with the prebuilt U-Boot image. Then, insert the SD card to the target board.
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+4. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+Follow the output log, lock and unlock the sema4 gate in uboot. The whole log:
+~~~~~~~~~~~~~~~~~~~
+SEMA4 uboot example start
+Lock sema4 gate in uboot using:
+ > mw.b 0x30ac0000 1 1
+Unlock sema4 gate in uboot using:
+ > mw.b 0x30ac0000 0 1
+SEMA4 uboot example success
+~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/sema4_uboot.c b/boards/dart_mx8mm/driver_examples/sema4/uboot/sema4_uboot.c
new file mode 100644
index 000000000..e2772ac26
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/sema4_uboot.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_sema4.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define APP_SEMA4 SEMA4
+#define APP_PROC_NUM 1
+#define APP_OTHER_PROC_NUM 0
+#define APP_SEMA4_GATE 0
+#define APP_SEMA4_GATE_ADDR ((uint32_t)(&(APP_SEMA4->Gate00)))
+#define SEMA4_IRQHandler HS_CP1_IRQHandler
+#define SOC_EnableSEMA4Intterrupt() NVIC_EnableIRQ(HS_CP1_IRQn)
+#define SOC_DisableSEMA4Intterrupt() NVIC_DisableIRQ(HS_CP1_IRQn)
+#define APP_ASSERT(x) \
+ if (!(x)) \
+ { \
+ PRINTF("Example error\r\n"); \
+ for (;;) \
+ ; \
+ }
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void SEMA4_IRQHandler(void)
+{
+ /* If gate notification IRQ received, then lock the gate. */
+ if (((1U << APP_SEMA4_GATE) & SEMA4_GetGateNotifyStatus(APP_SEMA4, APP_PROC_NUM)))
+ {
+ SEMA4_TryLock(APP_SEMA4, APP_SEMA4_GATE, APP_PROC_NUM);
+ }
+ __DSB();
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ PRINTF("SEMA4 uboot example start\r\n");
+
+ SEMA4_Init(APP_SEMA4);
+
+ SEMA4_EnableGateNotifyInterrupt(APP_SEMA4, APP_PROC_NUM, (1 << APP_SEMA4_GATE));
+
+ SOC_EnableSEMA4Intterrupt();
+
+ /* Step 1: The other core lock the sema4 gate. */
+ PRINTF("Lock sema4 gate in uboot using:\r\n");
+ PRINTF(" > mw.b 0x%08x %d 1 \r\n", APP_SEMA4_GATE_ADDR, APP_OTHER_PROC_NUM + 1);
+
+ /* Wait SEMA4 gate is locked by the other core. */
+ while (SEMA4_GetLockProc(APP_SEMA4, APP_SEMA4_GATE) != APP_OTHER_PROC_NUM)
+ {
+ }
+
+ /* Step 2: Current core try to lock the sema4 gate and lock failed. */
+ APP_ASSERT(kStatus_Fail == SEMA4_TryLock(APP_SEMA4, APP_SEMA4_GATE, APP_PROC_NUM));
+
+ /* Step 3: The other core unlock the sema4 gate. */
+ PRINTF("Unlock sema4 gate in uboot using:\r\n");
+ PRINTF(" > mw.b 0x%08x 0 1 \r\n", APP_SEMA4_GATE_ADDR);
+
+ /* Wait SEMA4 gate is locked by the other core. */
+ while (SEMA4_GetLockProc(APP_SEMA4, APP_SEMA4_GATE) == APP_OTHER_PROC_NUM)
+ {
+ }
+
+ /*
+ * When the other core unlocked the gate, current core receives the notification
+ * interrupt and lock the gate in ISR.
+ */
+ APP_ASSERT(SEMA4_GetLockProc(APP_SEMA4, APP_SEMA4_GATE) == APP_PROC_NUM);
+
+ SEMA4_Unlock(APP_SEMA4, APP_SEMA4_GATE);
+
+ SOC_DisableSEMA4Intterrupt();
+
+ SEMA4_DisableGateNotifyInterrupt(APP_SEMA4, APP_PROC_NUM, (1 << APP_SEMA4_GATE));
+
+ SEMA4_Deinit(APP_SEMA4);
+
+ PRINTF("SEMA4 uboot example success\r\n");
+
+ while (1)
+ {
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/sema4/uboot/sema4_uboot_v3_10.xml b/boards/dart_mx8mm/driver_examples/sema4/uboot/sema4_uboot_v3_10.xml
new file mode 100644
index 000000000..e69b03149
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/sema4/uboot/sema4_uboot_v3_10.xml
@@ -0,0 +1,131 @@
+
+
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+
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..9541cb53a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(tmu_monitor_threshold)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME tmu_monitor_threshold.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../tmu_monitor_threshold.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_tmu_1_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/tmu_1_monitor_threshold.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/board.c b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/board.h b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/clock_config.c b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/clock_config.h b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/pin_mux.c b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/pin_mux.h b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/readme.txt b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/readme.txt
new file mode 100644
index 000000000..170bb3c52
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/readme.txt
@@ -0,0 +1,44 @@
+Overview
+========
+The TMU example shows how to configure TMU register to monitor and report the temperature from
+the temperature measurement site located on the chip.
+
+TMU has access to temperature measurement site located on the chip. It can signal an alarm
+if a programmed threshold is ever exceeded.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+#### Please note this application can't support running with Linux BSP! ####
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the example runs successfully, you will see the temperature output from the terminal
+everytime when the pre-set threshold is reached.
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/tmu_monitor_threshold.c b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/tmu_monitor_threshold.c
new file mode 100644
index 000000000..483a7b885
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/tmu_monitor_threshold.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_tmu.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* @TEST_ANCHOR */
+
+#define DEMO_TMU_BASE TMU
+#define DEMO_TMU_AMPGAIN_VALUE kTMU_AmplifierGain8_08
+#define DEMO_TMU_AMPVREF_VALUE kTMU_AmplifierReferenceVoltage652_5
+#ifndef DEMO_TMU_TEST
+#define DEMO_TMU_IMMEDIATE_THRESOLD (48U - 21U)
+#define DEMO_TMU_AVERAGE_THRESOLD (50U - 21U)
+#define DEMO_TMU_AVERAGE_CRITICAL_THRESOLD (88U - 21U)
+#endif
+#define DEMO_TMU_IRQ TEMPMON_LOW_IRQn
+#define DEMO_TMU_IRQ_HANDLER_FUNC TEMPMON_LOW_IRQHandler
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+volatile tmu_interrupt_status_t g_tmuInterruptStausStruct;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief TMU ISR.
+ */
+void DEMO_TMU_IRQ_HANDLER_FUNC(void)
+{
+ uint32_t temp;
+
+ TMU_GetInterruptStatusFlags(DEMO_TMU_BASE, (tmu_interrupt_status_t *)&g_tmuInterruptStausStruct);
+ TMU_ClearInterruptStatusFlags(DEMO_TMU_BASE, g_tmuInterruptStausStruct.interruptDetectMask);
+
+ TMU_GetAverageTemperature(TMU, &temp);
+ if (temp < 31U || temp > 146U)
+ {
+ PRINTF("Temperature out of scope!\r\n");
+ }
+ else
+ {
+ PRINTF("Threshold reached, average temperature is %d celsius degree\r\n", temp - 21U);
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ tmu_config_t k_tmuConfig;
+ tmu_thresold_config_t k_tmuThresoldConfig;
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ PRINTF("TMU monitor threshold example.\r\n");
+
+ /* Initialize the TMU mode. */
+ k_tmuConfig.averageLPF = kTMU_AverageLowPassFilter0_5;
+ TMU_Init(DEMO_TMU_BASE, &k_tmuConfig);
+
+ /* Set the temperature threshold. */
+ k_tmuThresoldConfig.immediateThresoldEnable = false;
+ k_tmuThresoldConfig.AverageThresoldEnable = true;
+ k_tmuThresoldConfig.AverageCriticalThresoldEnable = false;
+ k_tmuThresoldConfig.immediateThresoldValue = DEMO_TMU_IMMEDIATE_THRESOLD + 21U;
+ k_tmuThresoldConfig.averageThresoldValue = DEMO_TMU_AVERAGE_THRESOLD + 21U;
+ k_tmuThresoldConfig.averageCriticalThresoldValue = DEMO_TMU_AVERAGE_CRITICAL_THRESOLD + 21U;
+ TMU_SetHighTemperatureThresold(DEMO_TMU_BASE, &k_tmuThresoldConfig);
+
+ /* Enable the Average temperature threshold exceeded interrupt. */
+ TMU_EnableInterrupts(DEMO_TMU_BASE, kTMU_AverageTemperatureInterruptEnable);
+ EnableIRQ(DEMO_TMU_IRQ);
+
+ /* Enable the monitor mode. */
+ TMU_Enable(DEMO_TMU_BASE, true);
+
+ while (true)
+ {
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/tmu_monitor_threshold_v3_10.xml b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/tmu_monitor_threshold_v3_10.xml
new file mode 100644
index 000000000..48c586a37
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/monitor_threshold/tmu_monitor_threshold_v3_10.xml
@@ -0,0 +1,131 @@
+
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diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..6cb212e47
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(tmu_temperature_polling)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME tmu_temperature_polling.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../tmu_temperature_polling.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_tmu_1_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/tmu_1_temperature_polling.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/board.c b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/board.h b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/clock_config.c b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/clock_config.h b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/pin_mux.c b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/pin_mux.h b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/readme.txt b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/readme.txt
new file mode 100644
index 000000000..355999a66
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/readme.txt
@@ -0,0 +1,41 @@
+Overview
+========
+The TMU example shows how to configure TMU register to monitor and report the temperature from
+the temperature measurement site located on the chip.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+#### Please note this application can't support running with Linux BSP! ####
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the example runs successfully, you will see the temperature output from the terminal.
+
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/tmu_temperature_polling.c b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/tmu_temperature_polling.c
new file mode 100644
index 000000000..5cf1ef493
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/tmu_temperature_polling.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_tmu.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DEMO_TMU_BASE TMU
+#define DEMO_TMU_AMPGAIN_VALUE kTMU_AmplifierGain8_08
+#define DEMO_TMU_AMPVREF_VALUE kTMU_AmplifierReferenceVoltage652_5
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Delay function
+ *
+ * @param count delay count
+ */
+static void Delay(uint32_t count);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void Delay(uint32_t count)
+{
+ volatile uint32_t i;
+
+ for (i = 0U; i < count; ++i)
+ {
+ __asm("NOP");
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ tmu_config_t k_tmuConfig;
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ PRINTF("TMU temperature polling example.\r\n");
+
+ /* Initialize the TMU mode. */
+ k_tmuConfig.averageLPF = kTMU_AverageLowPassFilter0_5;
+ TMU_Init(DEMO_TMU_BASE, &k_tmuConfig);
+
+ TMU_Enable(DEMO_TMU_BASE, true);
+
+ while (true)
+ {
+ uint32_t temp;
+ TMU_GetAverageTemperature(TMU, &temp);
+ if (temp < 31U || temp > 146U)
+ {
+ PRINTF("Temperature out of scope!\r\n");
+ }
+ else
+ {
+ PRINTF("Average temperature is %d celsius degree\r\n", temp - 21U);
+ }
+ Delay(20000000U);
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/tmu_temperature_polling_v3_10.xml b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/tmu_temperature_polling_v3_10.xml
new file mode 100644
index 000000000..4d08981b3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/tmu/temperature_polling/tmu_temperature_polling_v3_10.xml
@@ -0,0 +1,131 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..05bf106c0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/CMakeLists.txt
@@ -0,0 +1,105 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(iuart_auto_baudrate_detect)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME iuart_auto_baudrate_detect.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../uart_auto_baudrate_detect.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/iuart_auto_baudrate_detect.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/board.c b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/board.h b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/clock_config.c b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/clock_config.h b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/iuart_auto_baudrate_detect_v3_10.xml b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/iuart_auto_baudrate_detect_v3_10.xml
new file mode 100644
index 000000000..a6ff77473
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/iuart_auto_baudrate_detect_v3_10.xml
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/pin_mux.c b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/pin_mux.h b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/readme.txt b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/readme.txt
new file mode 100644
index 000000000..bf7027721
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/readme.txt
@@ -0,0 +1,51 @@
+Overview
+========
+The uart_auto_baudrate_detect example shows how to use uart auto baud rate detect feature:
+
+In this example, one uart instance connect to PC through uart. First, we should send characters a or A to board.
+The boars will set baud rate automatic. After baud rate has set, the board will send back all characters that PC
+send to the board.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+
+Running the demo
+================
+Set any baud rate in your terminal, and send character a or A to board, then
+When the demo runs successfully, the log would be seen on the debug terminal like:
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+UART has detect one character A
+Baud rate has been set automatic!
+Board will send back received characters
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/uart_auto_baudrate_detect.c b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/uart_auto_baudrate_detect.c
new file mode 100644
index 000000000..f0d2821f5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/auto_baudrate_detect/uart_auto_baudrate_detect.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DEMO_UART UART3
+#define DEMO_UART_CLK_FREQ BOARD_DEBUG_UART_CLK_FREQ
+#define DEMO_UART_BAUDRATE 115200U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+uint8_t infobuff[] = "UART has detected one character ";
+uint8_t txbuff[] = "\r\nBaud rate has been set automatic!\r\nBoard will send back received characters\r\n";
+uint8_t rxbuff[20] = {0};
+
+uint8_t fbuffer[] = "";
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ uint8_t ch;
+ status_t status;
+
+ uart_config_t config;
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitMemory();
+
+ /*
+ * config.baudRate_Bps = 115200U;
+ * config.parityMode = kUART_ParityDisabled;
+ * config.stopBitCount = kUART_OneStopBit;
+ * config.txFifoWatermark = 2;
+ * config.rxFifoWatermark = 1;
+ * config.enableTx = false;
+ * config.enableRx = false;
+ */
+ UART_GetDefaultConfig(&config);
+ config.baudRate_Bps = 0U;
+
+ config.enableTx = true;
+ config.enableRx = true;
+
+ status = UART_Init(DEMO_UART, &config, DEMO_UART_CLK_FREQ);
+ if (kStatus_Success != status)
+ {
+ return kStatus_Fail;
+ }
+
+ UART_EnableAutoBaudRate(DEMO_UART, true);
+
+ while (!UART_IsAutoBaudRateComplete(DEMO_UART))
+ {
+ }
+ UART_WriteBlocking(DEMO_UART, infobuff, sizeof(infobuff) - 1);
+ /* Read the detect character from recevier register */
+ UART_ReadBlocking(DEMO_UART, &ch, 1);
+ UART_WriteBlocking(DEMO_UART, &ch, 1);
+
+ UART_WriteBlocking(DEMO_UART, txbuff, sizeof(txbuff) - 1);
+
+ while (1)
+ {
+ UART_ReadBlocking(DEMO_UART, &ch, 1);
+ UART_WriteBlocking(DEMO_UART, &ch, 1);
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..7bc11e21f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/CMakeLists.txt
@@ -0,0 +1,113 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(iuart_idle_detect_sdma_transfer)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME iuart_idle_detect_sdma_transfer.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../uart_idle_detect_sdma_transfer.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_cache_lmem_MIMX8MM6)
+
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_iuart_sdma_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(driver_sdma_MIMX8MM6)
+
+include(driver_memory_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/iuart_idle_detect_sdma_transfer.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/board.c b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/board.c
new file mode 100644
index 000000000..7ac3cfc4e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/board.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+#include "fsl_cache.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /*
+ * Flush the system cache before updating the cache policy. Without flushing, the
+ * previously done initialization of the non-cacheable sections will be discarded
+ * as the cache for this region was enabled with the write-back attribute before.
+ */
+ L1CACHE_CleanSystemCache();
+ __DSB();
+ __ISB();
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/board.h b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/clock_config.c b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/clock_config.h b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/iuart_idle_detect_sdma_transfer_v3_10.xml b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/iuart_idle_detect_sdma_transfer_v3_10.xml
new file mode 100644
index 000000000..5546a6785
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/iuart_idle_detect_sdma_transfer_v3_10.xml
@@ -0,0 +1,133 @@
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diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/pin_mux.c b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/pin_mux.h b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/readme.txt b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/readme.txt
new file mode 100644
index 000000000..9b3983f48
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/readme.txt
@@ -0,0 +1,54 @@
+Overview
+========
+The uart_idle_detect_sdma example shows how to use uart driver in sdma way:
+
+In this example, one uart instance connect to PC through uart, the board will
+send back all characters that PC send to the board.
+
+Uart will receive 8 characters every time, but if the character is less then 8, the idle
+line interrupt will generate, and abort the SDMA receive operation, and send out the received
+characters.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the demo runs successfully, the log would be seen on the debug terminal like:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Uart sdma transfer example!
+Uart will receive 8 charactes every time, if less characters were received,
+Uart will generate the idle line detect interrupt, SDMA receive operation will be aborted.
+Board will send the received characters out.
+Now please input:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/uart_idle_detect_sdma_transfer.c b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/uart_idle_detect_sdma_transfer.c
new file mode 100644
index 000000000..06a1a7483
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/idle_detect_sdma_transfer/uart_idle_detect_sdma_transfer.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_uart.h"
+#include "fsl_uart_sdma.h"
+
+#include "fsl_rdc.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_UART_DMA_BASEADDR SDMAARM1
+#define DEMO_UART UART3
+#define DEMO_IRQn UART3_IRQn
+#define DEMO_UART_CLK_FREQ BOARD_DEBUG_UART_CLK_FREQ
+#define UART_RX_DMA_CHANNEL 1U
+#define UART_TX_DMA_CHANNEL 2U
+#define UART_RX_DMA_REQUEST (26)
+#define UART_TX_DMA_REQUEST (27)
+#define DEMO_UART_IRQHandler UART3_IRQHandler
+#define ECHO_BUFFER_LENGTH 8
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/* UART user callback */
+void UART_UserCallback(UART_Type *base, uart_sdma_handle_t *handle, status_t status, void *userData);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+AT_NONCACHEABLE_SECTION_ALIGN(uart_sdma_handle_t g_uartSdmaHandle, 4);
+AT_NONCACHEABLE_SECTION_ALIGN(sdma_handle_t g_uartTxSdmaHandle, 4);
+AT_NONCACHEABLE_SECTION_ALIGN(sdma_handle_t g_uartRxSdmaHandle, 4);
+
+AT_NONCACHEABLE_SECTION_ALIGN(sdma_context_data_t context_Tx, 4);
+AT_NONCACHEABLE_SECTION_ALIGN(sdma_context_data_t context_Rx, 4);
+
+AT_NONCACHEABLE_SECTION_ALIGN(uart_transfer_t sendXfer, 4);
+AT_NONCACHEABLE_SECTION_ALIGN(uart_transfer_t receiveXfer, 4);
+
+AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint8_t g_tipString[], 4) =
+ "Uart sdma transfer example!\r\nUart will receive 8 charactes every time, if less characters were received, "
+ "\r\nUart will generate the idle line detect interrupt, SDMA receive operation will be aborted.\r\nBoard will send "
+ "the received characters out.\r\nNow please input:\r\n";
+
+AT_NONCACHEABLE_SECTION_ALIGN(uint8_t g_txBuffer[ECHO_BUFFER_LENGTH], 4);
+AT_NONCACHEABLE_SECTION_ALIGN(uint8_t g_rxBuffer[ECHO_BUFFER_LENGTH], 4);
+
+volatile bool rxBufferEmpty = true;
+volatile bool txBufferFull = false;
+volatile bool txOnGoing = false;
+volatile bool rxOnGoing = false;
+volatile uint32_t dataSize = 0U;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* UART IRQHandler function. */
+void DEMO_UART_IRQHandler(uint32_t giccIar, void *param)
+{
+ /* if receiver awake flag was detedted. */
+ if ((UART_GetStatusFlag(DEMO_UART, kUART_WakeFlag)) && (UART_GetEnabledInterrupts(DEMO_UART) & kUART_WakeEnable))
+ {
+ /* Enable the IDLE line detected interrupt. */
+ UART_ClearStatusFlag(DEMO_UART, kUART_IdleFlag);
+ UART_EnableInterrupts(DEMO_UART, kUART_RxDmaIdleEnable);
+ /* Disable the receiver awake interrupt for next transfer. */
+ UART_DisableInterrupts(DEMO_UART, kUART_WakeEnable);
+ UART_ClearStatusFlag(DEMO_UART, kUART_WakeFlag);
+ }
+ UART_TransferSdmaHandleIRQ(DEMO_UART, &g_uartSdmaHandle);
+ __DSB();
+}
+
+/* UART user callback */
+void UART_UserCallback(UART_Type *base, uart_sdma_handle_t *handle, status_t status, void *userData)
+{
+ userData = userData;
+
+ if (kStatus_UART_TxIdle == status)
+ {
+ txBufferFull = false;
+ txOnGoing = false;
+ }
+ if (kStatus_UART_RxIdle == status)
+ {
+ rxBufferEmpty = false;
+ rxOnGoing = false;
+ dataSize = ECHO_BUFFER_LENGTH;
+
+ /* Check if IDLE flag was detedted with idle interrupt enabled.
+ * Please note that, the IDLE flag will always be set if no data received.
+ * If the receiver was not in IDLE status, the idle flag will be cleared by hardware.
+ * That is to say, Idle lines indicate the end or the beginning of a message.
+ */
+ if ((UART_GetStatusFlag(DEMO_UART, kUART_IdleFlag)) &&
+ (UART_GetEnabledInterrupts(DEMO_UART) & kUART_RxDmaIdleEnable))
+ {
+ dataSize = SDMA_GetTransferredBytes(&g_uartRxSdmaHandle);
+ UART_DisableInterrupts(DEMO_UART, kUART_RxDmaIdleEnable);
+ }
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ uart_config_t config;
+ sdma_config_t sdmaConfig;
+ uart_transfer_t xfer;
+ status_t status;
+
+ /* Only configure the RDC if RDC peripheral write access is allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, RDC_GetCurrentMasterDomainId(RDC))) != 0U)
+ {
+ /*set SDMA1 PERIPH to M4 Domain(DID=1),due to UART not be accessible by DID=0 by default*/
+ rdc_domain_assignment_t assignment = {0};
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_SDMA1_PERIPH, &assignment);
+ }
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitMemory();
+
+ /*
+ * config.baudRate_Bps = 115200U;
+ * config.parityMode = kUART_ParityDisabled;
+ * config.dataBitsCount = kUART_EightDataBits;
+ * config.stopBitCount = kUART_OneStopBit;
+ * config.txFifoWatermark = 2;
+ * config.rxFifoWatermark = 1;
+ * config.enableTx = false;
+ * config.enableRx = false;
+ */
+ UART_GetDefaultConfig(&config);
+ config.baudRate_Bps = BOARD_DEBUG_UART_BAUDRATE;
+ config.rxFifoWatermark = 1;
+ config.enableTx = true;
+ config.enableRx = true;
+
+ status = UART_Init(DEMO_UART, &config, DEMO_UART_CLK_FREQ);
+ if (kStatus_Success != status)
+ {
+ return kStatus_Fail;
+ }
+
+ /* Init the SDMA module */
+ SDMA_GetDefaultConfig(&sdmaConfig);
+ SDMA_Init(EXAMPLE_UART_DMA_BASEADDR, &sdmaConfig);
+ SDMA_CreateHandle(&g_uartTxSdmaHandle, EXAMPLE_UART_DMA_BASEADDR, UART_TX_DMA_CHANNEL, &context_Tx);
+ SDMA_CreateHandle(&g_uartRxSdmaHandle, EXAMPLE_UART_DMA_BASEADDR, UART_RX_DMA_CHANNEL, &context_Rx);
+ SDMA_SetChannelPriority(EXAMPLE_UART_DMA_BASEADDR, UART_TX_DMA_CHANNEL, 3U);
+ SDMA_SetChannelPriority(EXAMPLE_UART_DMA_BASEADDR, UART_RX_DMA_CHANNEL, 4U);
+
+ /* Create UART DMA handle. */
+ UART_TransferCreateHandleSDMA(DEMO_UART, &g_uartSdmaHandle, UART_UserCallback, NULL, &g_uartTxSdmaHandle,
+ &g_uartRxSdmaHandle, UART_TX_DMA_REQUEST, UART_RX_DMA_REQUEST);
+
+ /* Send g_tipString out. */
+ xfer.data = g_tipString;
+ xfer.dataSize = sizeof(g_tipString) - 1;
+ txOnGoing = true;
+ UART_SendSDMA(DEMO_UART, &g_uartSdmaHandle, &xfer);
+
+ /* Wait send finished */
+ while (txOnGoing)
+ {
+ }
+ /* Start to echo. */
+ sendXfer.data = g_txBuffer;
+ sendXfer.dataSize = ECHO_BUFFER_LENGTH;
+ receiveXfer.data = g_rxBuffer;
+ receiveXfer.dataSize = ECHO_BUFFER_LENGTH;
+
+ /* Configure the condition of IDLE detected. */
+ UART_SetIdleCondition(DEMO_UART, kUART_IdleFor16Frames);
+ UART_DisableInterrupts(DEMO_UART, kUART_AllInterruptsEnable);
+
+ EnableIRQ(DEMO_IRQn);
+
+ while (1)
+ {
+ /* If TX is idle and g_txBuffer is full, start to send data. */
+ if ((!txOnGoing) && txBufferFull)
+ {
+ txOnGoing = true;
+ UART_SendSDMA(DEMO_UART, &g_uartSdmaHandle, &sendXfer);
+ }
+
+ /* If RX is idle and g_rxBuffer is empty, start to read data to g_rxBuffer. */
+ if ((!rxOnGoing) && rxBufferEmpty)
+ {
+ /* Enable receiver wake interrupt, if the receiver start to receive data,
+ * this interrupt will be generated.
+ */
+ if (UART_GetStatusFlag(DEMO_UART, kUART_IdleFlag))
+ {
+ UART_ClearStatusFlag(DEMO_UART, kUART_WakeFlag);
+ UART_EnableInterrupts(DEMO_UART, kUART_WakeEnable);
+ }
+
+ rxOnGoing = true;
+ UART_ReceiveSDMA(DEMO_UART, &g_uartSdmaHandle, &receiveXfer);
+ }
+
+ /* If g_txBuffer is empty and g_rxBuffer is full, copy g_rxBuffer to g_txBuffer. */
+ if ((!rxBufferEmpty) && (!txBufferFull))
+ {
+ if (dataSize == 0U)
+ {
+ rxBufferEmpty = true;
+ continue;
+ }
+ memcpy(g_txBuffer, g_rxBuffer, dataSize);
+ memset(g_rxBuffer, 0, ECHO_BUFFER_LENGTH);
+ sendXfer.dataSize = dataSize;
+ rxBufferEmpty = true;
+ txBufferFull = true;
+ }
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..770325f8c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/CMakeLists.txt
@@ -0,0 +1,105 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(iuart_interrupt)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME iuart_interrupt.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../uart_interrupt.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/iuart_interrupt.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/board.c b/boards/dart_mx8mm/driver_examples/uart/interrupt/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/board.h b/boards/dart_mx8mm/driver_examples/uart/interrupt/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/clock_config.c b/boards/dart_mx8mm/driver_examples/uart/interrupt/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/clock_config.h b/boards/dart_mx8mm/driver_examples/uart/interrupt/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/uart/interrupt/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/uart/interrupt/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/iuart_interrupt_v3_10.xml b/boards/dart_mx8mm/driver_examples/uart/interrupt/iuart_interrupt_v3_10.xml
new file mode 100644
index 000000000..b5faed524
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/iuart_interrupt_v3_10.xml
@@ -0,0 +1,130 @@
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diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/pin_mux.c b/boards/dart_mx8mm/driver_examples/uart/interrupt/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/pin_mux.h b/boards/dart_mx8mm/driver_examples/uart/interrupt/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/readme.txt b/boards/dart_mx8mm/driver_examples/uart/interrupt/readme.txt
new file mode 100644
index 000000000..b8d4f5896
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/readme.txt
@@ -0,0 +1,50 @@
+Overview
+========
+The uart_functioncal_interrupt example shows how to use uart driver functional
+API to receive data with interrupt method:
+
+In this example, one uart instance connect to PC through uart, the board will
+send back all characters that PC send to the board.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+
+Running the demo
+================
+When the demo runs successfully, the log would be seen on the debug terminal like:
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Uart functional interrupt example
+Board receives characters then sends them out
+Now please input:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt/uart_interrupt.c b/boards/dart_mx8mm/driver_examples/uart/interrupt/uart_interrupt.c
new file mode 100644
index 000000000..d5fbb0a03
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt/uart_interrupt.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DEMO_UART UART3
+#define DEMO_UART_CLK_FREQ BOARD_DEBUG_UART_CLK_FREQ
+#define DEMO_UART_BAUDRATE 115200U
+#define DEMO_IRQn UART3_IRQn
+#define DEMO_UART_IRQHandler UART3_IRQHandler
+
+/*! @brief Ring buffer size (Unit: Byte). */
+#define DEMO_RING_BUFFER_SIZE 16
+
+/*! @brief Ring buffer to save received data. */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+uint8_t g_tipString[] =
+ "Uart functional API interrupt example\r\nBoard receives characters then sends them out\r\nNow please input:\r\n";
+
+/*
+ Ring buffer for data input and output, in this example, input data are saved
+ to ring buffer in IRQ handler. The main function polls the ring buffer status,
+ if there are new data, then send them out.
+ Ring buffer full: (((rxIndex + 1) % DEMO_RING_BUFFER_SIZE) == txIndex)
+ Ring buffer empty: (rxIndex == txIndex)
+*/
+uint8_t demoRingBuffer[DEMO_RING_BUFFER_SIZE];
+volatile uint16_t txIndex; /* Index of the data to send out. */
+volatile uint16_t rxIndex; /* Index of the memory to save new arrived data. */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void DEMO_UART_IRQHandler(void)
+{
+ uint8_t data;
+
+ /* If new data arrived. */
+ if ((UART_GetStatusFlag(DEMO_UART, kUART_RxDataReadyFlag)) || (UART_GetStatusFlag(DEMO_UART, kUART_RxOverrunFlag)))
+ {
+ data = UART_ReadByte(DEMO_UART);
+
+ /* If ring buffer is not full, add data to ring buffer. */
+ if (((rxIndex + 1) % DEMO_RING_BUFFER_SIZE) != txIndex)
+ {
+ demoRingBuffer[rxIndex] = data;
+ rxIndex++;
+ rxIndex %= DEMO_RING_BUFFER_SIZE;
+ }
+ }
+ SDK_ISR_EXIT_BARRIER;
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ status_t status;
+ uart_config_t config;
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitMemory();
+
+ /*
+ * config.baudRate_Bps = 115200U;
+ * config.parityMode = kUART_ParityDisabled;
+ * config.dataBitsCount = kUART_EightDataBits;
+ * config.stopBitCount = kUART_OneStopBit;
+ * config.txFifoWatermark = 2;
+ * config.rxFifoWatermark = 1;
+ * config.enableTx = false;
+ * config.enableRx = false;
+ */
+ UART_GetDefaultConfig(&config);
+ config.baudRate_Bps = DEMO_UART_BAUDRATE;
+ config.enableTx = true;
+ config.enableRx = true;
+
+ status = UART_Init(DEMO_UART, &config, DEMO_UART_CLK_FREQ);
+ if (kStatus_Success != status)
+ {
+ return kStatus_Fail;
+ }
+
+ /* Send g_tipString out. */
+ UART_WriteBlocking(DEMO_UART, g_tipString, sizeof(g_tipString) / sizeof(g_tipString[0]) - 1);
+
+ /* Enable RX interrupt. */
+ UART_EnableInterrupts(DEMO_UART, kUART_RxDataReadyEnable | kUART_RxOverrunEnable);
+ EnableIRQ(DEMO_IRQn);
+
+ while (1)
+ {
+ /* Send data only when UART TX register is empty and ring buffer has data to send out. */
+ while ((UART_GetStatusFlag(DEMO_UART, kUART_TxReadyFlag)) && (rxIndex != txIndex))
+ {
+ UART_WriteByte(DEMO_UART, demoRingBuffer[txIndex]);
+ txIndex++;
+ txIndex %= DEMO_RING_BUFFER_SIZE;
+ }
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..82e86601d
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/CMakeLists.txt
@@ -0,0 +1,105 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(iuart_interrupt_rb_transfer)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME iuart_interrupt_rb_transfer.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../uart_interrupt_rb_transfer.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/iuart_interrupt_rb_transfer.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/board.c b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/board.h b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/clock_config.c b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/clock_config.h b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/iuart_interrupt_rb_transfer_v3_10.xml b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/iuart_interrupt_rb_transfer_v3_10.xml
new file mode 100644
index 000000000..cf6b6405b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/iuart_interrupt_rb_transfer_v3_10.xml
@@ -0,0 +1,130 @@
+
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diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/pin_mux.c b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/pin_mux.h b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/readme.txt b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/readme.txt
new file mode 100644
index 000000000..d13f58995
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/readme.txt
@@ -0,0 +1,52 @@
+Overview
+========
+The uart_interrupt_ring_buffer example shows how to use uart driver in interrupt way with
+RX ring buffer enabled:
+
+In this example, one uart instance connect to PC through uart, the board will
+send back all characters that PC send to the board.
+
+Note: The example echo every 8 characters, so input 8 characters every time.
+
+
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+Running the demo
+================
+When the demo runs successfully, the log would be seen on the debug terminal like:
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+UART RX ring buffer example
+Send back received data
+Echo every 8 bytes
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/uart_interrupt_rb_transfer.c b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/uart_interrupt_rb_transfer.c
new file mode 100644
index 000000000..50b1e6d46
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_rb_transfer/uart_interrupt_rb_transfer.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DEMO_UART UART3
+#define DEMO_UART_CLK_FREQ BOARD_DEBUG_UART_CLK_FREQ
+#define DEMO_UART_BAUDRATE 115200U
+
+#define RX_RING_BUFFER_SIZE 20U
+#define ECHO_BUFFER_SIZE 8U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/* UART user callback */
+void UART_UserCallback(UART_Type *base, uart_handle_t *handle, status_t status, void *userData);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+uart_handle_t g_uartHandle;
+uint8_t g_tipString[] = "UART RX ring buffer example\r\nSend back received data\r\nEcho every 8 bytes\r\n";
+uint8_t g_rxRingBuffer[RX_RING_BUFFER_SIZE] = {0}; /* RX ring buffer. */
+
+uint8_t g_rxBuffer[ECHO_BUFFER_SIZE] = {0}; /* Buffer for receive data to echo. */
+uint8_t g_txBuffer[ECHO_BUFFER_SIZE] = {0}; /* Buffer for send data to echo. */
+volatile bool rxBufferEmpty = true;
+volatile bool txBufferFull = false;
+volatile bool txOnGoing = false;
+volatile bool rxOnGoing = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* UART user callback */
+void UART_UserCallback(UART_Type *base, uart_handle_t *handle, status_t status, void *userData)
+{
+ userData = userData;
+
+ if (kStatus_UART_TxIdle == status)
+ {
+ txBufferFull = false;
+ txOnGoing = false;
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ uart_config_t config;
+ uart_transfer_t xfer;
+ uart_transfer_t sendXfer;
+ uart_transfer_t receiveXfer;
+ size_t receivedBytes;
+ uint32_t i;
+ status_t status;
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitMemory();
+
+ /*
+ * config.baudRate_Bps = 115200U;
+ * config.parityMode = kUART_ParityDisabled;
+ * config.dataBitsCount = kUART_EightDataBits;
+ * config.stopBitCount = kUART_OneStopBit;
+ * config.txFifoWatermark = 2;
+ * config.rxFifoWatermark = 16;
+ * config.enableTx = false;
+ * config.enableRx = false;
+ */
+ UART_GetDefaultConfig(&config);
+ config.baudRate_Bps = DEMO_UART_BAUDRATE;
+ config.txFifoWatermark = 2;
+ config.rxFifoWatermark = 16;
+ config.enableTx = true;
+ config.enableRx = true;
+
+ status = UART_Init(DEMO_UART, &config, DEMO_UART_CLK_FREQ);
+ if (kStatus_Success != status)
+ {
+ return kStatus_Fail;
+ }
+
+ UART_TransferCreateHandle(DEMO_UART, &g_uartHandle, UART_UserCallback, NULL);
+ UART_TransferStartRingBuffer(DEMO_UART, &g_uartHandle, g_rxRingBuffer, RX_RING_BUFFER_SIZE);
+
+ /* Send g_tipString out. */
+ xfer.data = g_tipString;
+ xfer.dataSize = sizeof(g_tipString) - 1;
+ txOnGoing = true;
+ UART_TransferSendNonBlocking(DEMO_UART, &g_uartHandle, &xfer);
+
+ /* Wait send finished */
+ while (txOnGoing)
+ {
+ }
+
+ /* Start to echo. */
+ sendXfer.data = g_txBuffer;
+ sendXfer.dataSize = ECHO_BUFFER_SIZE;
+ receiveXfer.data = g_rxBuffer;
+ receiveXfer.dataSize = ECHO_BUFFER_SIZE;
+
+ while (1)
+ {
+ /* If g_txBuffer is empty and g_rxBuffer is full, copy g_rxBuffer to g_txBuffer. */
+ if ((!rxBufferEmpty) && (!txBufferFull))
+ {
+ memcpy(g_txBuffer, g_rxBuffer, ECHO_BUFFER_SIZE);
+ rxBufferEmpty = true;
+ txBufferFull = true;
+ }
+
+ /* If the data in ring buffer reach ECHO_BUFFER_SIZE, then start to read data from ring buffer. */
+ if (ECHO_BUFFER_SIZE <= UART_TransferGetRxRingBufferLength(&g_uartHandle))
+ {
+ UART_TransferReceiveNonBlocking(DEMO_UART, &g_uartHandle, &receiveXfer, &receivedBytes);
+ rxBufferEmpty = false;
+ }
+
+ /* If TX is idle and g_txBuffer is full, start to send data. */
+ if ((!txOnGoing) && txBufferFull)
+ {
+ txOnGoing = true;
+ UART_TransferSendNonBlocking(DEMO_UART, &g_uartHandle, &sendXfer);
+ }
+
+ /* Delay some time, simulate the app is processing other things, input data save to ring buffer. */
+ i = 0x10U;
+ while (i--)
+ {
+ __NOP();
+ }
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..18c296a2d
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/CMakeLists.txt
@@ -0,0 +1,105 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(iuart_interrupt_transfer)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME iuart_interrupt_transfer.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../uart_interrupt_transfer.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/iuart_interrupt_transfer.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/board.c b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/board.h b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/clock_config.c b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/clock_config.h b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/iuart_interrupt_transfer_v3_10.xml b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/iuart_interrupt_transfer_v3_10.xml
new file mode 100644
index 000000000..5ba16537d
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/iuart_interrupt_transfer_v3_10.xml
@@ -0,0 +1,130 @@
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diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/pin_mux.c b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/pin_mux.h b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/readme.txt b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/readme.txt
new file mode 100644
index 000000000..1889c1cc8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/readme.txt
@@ -0,0 +1,51 @@
+Overview
+========
+The uart_interrupt example shows how to use uart driver in interrupt way:
+
+In this example, one uart instance connect to PC through uart, the board will
+send back all characters that PC send to the board.
+
+Note: The example echo every 8 characters, so input 8 characters every time.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+
+Running the demo
+================
+When the demo runs successfully, the log would be seen on the debug terminal like:
+
+Uart interrupt example
+Board receives 8 characters then sends them out
+Now please input:
+
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/uart_interrupt_transfer.c b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/uart_interrupt_transfer.c
new file mode 100644
index 000000000..dc3b076e6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/interrupt_transfer/uart_interrupt_transfer.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DEMO_UART UART3
+#define DEMO_UART_CLK_FREQ BOARD_DEBUG_UART_CLK_FREQ
+
+#define ECHO_BUFFER_LENGTH 8
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/* UART user callback */
+void UART_UserCallback(UART_Type *base, uart_handle_t *handle, status_t status, void *userData);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+uart_handle_t g_uartHandle;
+
+uint8_t g_tipString[] =
+ "Uart interrupt transfer example\r\nBoard receives 8 characters then sends them out\r\nNow please input:\r\n";
+
+uint8_t g_txBuffer[ECHO_BUFFER_LENGTH] = {0};
+uint8_t g_rxBuffer[ECHO_BUFFER_LENGTH] = {0};
+volatile bool rxBufferEmpty = true;
+volatile bool txBufferFull = false;
+volatile bool txOnGoing = false;
+volatile bool rxOnGoing = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* UART user callback */
+void UART_UserCallback(UART_Type *base, uart_handle_t *handle, status_t status, void *userData)
+{
+ userData = userData;
+
+ if (kStatus_UART_TxIdle == status)
+ {
+ txBufferFull = false;
+ txOnGoing = false;
+ }
+
+ if (kStatus_UART_RxIdle == status)
+ {
+ rxBufferEmpty = false;
+ rxOnGoing = false;
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ status_t status;
+ uart_config_t config;
+ uart_transfer_t xfer;
+ uart_transfer_t sendXfer;
+ uart_transfer_t receiveXfer;
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitMemory();
+ /*
+ * config.baudRate_Bps = 115200U;
+ * config.parityMode = kUART_ParityDisabled;
+ * config.dataBitsCount = kUART_EightDataBits;
+ * config.stopBitCount = kUART_OneStopBit;
+ * config.txFifoWatermark = 2;
+ * config.rxFifoWatermark = 16;
+ * config.enableTx = false;
+ * config.enableRx = false;
+ */
+ UART_GetDefaultConfig(&config);
+ config.baudRate_Bps = BOARD_DEBUG_UART_BAUDRATE;
+ config.rxFifoWatermark = 16;
+ config.enableTx = true;
+ config.enableRx = true;
+
+ status = UART_Init(DEMO_UART, &config, DEMO_UART_CLK_FREQ);
+ if (kStatus_Success != status)
+ {
+ return kStatus_Fail;
+ }
+
+ UART_TransferCreateHandle(DEMO_UART, &g_uartHandle, UART_UserCallback, NULL);
+
+ /* Send g_tipString out. */
+ xfer.data = g_tipString;
+ xfer.dataSize = sizeof(g_tipString) - 1;
+ txOnGoing = true;
+ UART_TransferSendNonBlocking(DEMO_UART, &g_uartHandle, &xfer);
+
+ /* Wait send finished */
+ while (txOnGoing)
+ {
+ }
+
+ /* Start to echo. */
+ sendXfer.data = g_txBuffer;
+ sendXfer.dataSize = ECHO_BUFFER_LENGTH;
+ receiveXfer.data = g_rxBuffer;
+ receiveXfer.dataSize = ECHO_BUFFER_LENGTH;
+
+ while (1)
+ {
+ /* If RX is idle and g_rxBuffer is empty, start to read data to g_rxBuffer. */
+ if ((!rxOnGoing) && rxBufferEmpty)
+ {
+ rxOnGoing = true;
+ UART_TransferReceiveNonBlocking(DEMO_UART, &g_uartHandle, &receiveXfer, NULL);
+ }
+
+ /* If TX is idle and g_txBuffer is full, start to send data. */
+ if ((!txOnGoing) && txBufferFull)
+ {
+ txOnGoing = true;
+ UART_TransferSendNonBlocking(DEMO_UART, &g_uartHandle, &sendXfer);
+ }
+
+ /* If g_txBuffer is empty and g_rxBuffer is full, copy g_rxBuffer to g_txBuffer. */
+ if ((!rxBufferEmpty) && (!txBufferFull))
+ {
+ memcpy(g_txBuffer, g_rxBuffer, ECHO_BUFFER_LENGTH);
+ rxBufferEmpty = true;
+ txBufferFull = true;
+ }
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..8e28a9710
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/CMakeLists.txt
@@ -0,0 +1,105 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(iuart_polling)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME iuart_polling.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../uart_polling.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/iuart_polling.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/board.c b/boards/dart_mx8mm/driver_examples/uart/polling/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/board.h b/boards/dart_mx8mm/driver_examples/uart/polling/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/clock_config.c b/boards/dart_mx8mm/driver_examples/uart/polling/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/clock_config.h b/boards/dart_mx8mm/driver_examples/uart/polling/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/uart/polling/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/uart/polling/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/iuart_polling_v3_10.xml b/boards/dart_mx8mm/driver_examples/uart/polling/iuart_polling_v3_10.xml
new file mode 100644
index 000000000..68e66d902
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/iuart_polling_v3_10.xml
@@ -0,0 +1,130 @@
+
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diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/pin_mux.c b/boards/dart_mx8mm/driver_examples/uart/polling/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/pin_mux.h b/boards/dart_mx8mm/driver_examples/uart/polling/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/readme.txt b/boards/dart_mx8mm/driver_examples/uart/polling/readme.txt
new file mode 100644
index 000000000..c41f9ae1a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/readme.txt
@@ -0,0 +1,48 @@
+Overview
+========
+The uart_polling example shows how to use uart driver in polling way:
+
+In this example, one uart instance connect to PC through uart, the board will send back all characters that PC
+send to the board.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+
+Running the demo
+================
+When the demo runs successfully, the log would be seen on the debug terminal like:
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Uart polling example
+Board will send back received characters
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/uart/polling/uart_polling.c b/boards/dart_mx8mm/driver_examples/uart/polling/uart_polling.c
new file mode 100644
index 000000000..04e12e187
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/polling/uart_polling.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DEMO_UART UART3
+#define DEMO_UART_CLK_FREQ BOARD_DEBUG_UART_CLK_FREQ
+#define DEMO_UART_BAUDRATE 115200U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+uint8_t txbuff[] = "Uart polling example\r\nBoard will send back received characters\r\n";
+uint8_t rxbuff[20] = {0};
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ uint8_t ch;
+ status_t status;
+ uart_config_t config;
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitMemory();
+
+ /*
+ * config.baudRate_Bps = 115200U;
+ * config.parityMode = kUART_ParityDisabled;
+ * config.dataBitsCount = kUART_EightDataBits;
+ * config.stopBitCount = kUART_OneStopBit;
+ * config.txFifoWatermark = 2;
+ * config.rxFifoWatermark = 1;
+ * config.enableTx = false;
+ * config.enableRx = false;
+ */
+ UART_GetDefaultConfig(&config);
+ config.baudRate_Bps = DEMO_UART_BAUDRATE;
+ config.enableTx = true;
+ config.enableRx = true;
+
+ status = UART_Init(DEMO_UART, &config, DEMO_UART_CLK_FREQ);
+ if (kStatus_Success != status)
+ {
+ return kStatus_Fail;
+ }
+
+ UART_WriteBlocking(DEMO_UART, txbuff, sizeof(txbuff) - 1);
+
+ while (1)
+ {
+ UART_ReadBlocking(DEMO_UART, &ch, 1);
+ UART_WriteBlocking(DEMO_UART, &ch, 1);
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..2546a4fed
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/CMakeLists.txt
@@ -0,0 +1,113 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(iuart_sdma_transfer)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME iuart_sdma_transfer.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../uart_sdma_transfer.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_cache_lmem_MIMX8MM6)
+
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_iuart_sdma_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(driver_sdma_MIMX8MM6)
+
+include(driver_memory_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/iuart_sdma_transfer.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/board.c b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/board.c
new file mode 100644
index 000000000..7ac3cfc4e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/board.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+#include "fsl_cache.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /*
+ * Flush the system cache before updating the cache policy. Without flushing, the
+ * previously done initialization of the non-cacheable sections will be discarded
+ * as the cache for this region was enabled with the write-back attribute before.
+ */
+ L1CACHE_CleanSystemCache();
+ __DSB();
+ __ISB();
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/board.h b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/clock_config.c b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/clock_config.h b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/iuart_sdma_transfer_v3_10.xml b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/iuart_sdma_transfer_v3_10.xml
new file mode 100644
index 000000000..0fa9890b5
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/iuart_sdma_transfer_v3_10.xml
@@ -0,0 +1,133 @@
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diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/pin_mux.c b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/pin_mux.h b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/readme.txt b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/readme.txt
new file mode 100644
index 000000000..3369809a9
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/readme.txt
@@ -0,0 +1,51 @@
+Overview
+========
+The uart_sdma example shows how to use uart driver in sdma way:
+
+In this example, one uart instance connect to PC through uart, the board will
+send back all characters that PC send to the board.
+
+Note: The example echo every 8 characters, so input 8 characters every time.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the demo runs successfully, the log would be seen on the debug terminal like:
+
+Uart interrupt example
+Board receives 8 characters then sends them out
+Now please input:
+
+When you input 8 characters, system will echo it by UART and them would be seen on the terminal.
+
diff --git a/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/uart_sdma_transfer.c b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/uart_sdma_transfer.c
new file mode 100644
index 000000000..e72bfee4f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/uart/sdma_transfer/uart_sdma_transfer.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_uart.h"
+#include "fsl_uart_sdma.h"
+
+#include "fsl_rdc.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_UART_DMA_BASEADDR SDMAARM1
+#define DEMO_UART UART3
+#define DEMO_UART_CLK_FREQ BOARD_DEBUG_UART_CLK_FREQ
+#define UART_RX_DMA_CHANNEL 1U
+#define UART_TX_DMA_CHANNEL 2U
+#define UART_RX_DMA_REQUEST (26)
+#define UART_TX_DMA_REQUEST (27)
+#define ECHO_BUFFER_LENGTH 8
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/* UART user callback */
+void UART_UserCallback(UART_Type *base, uart_sdma_handle_t *handle, status_t status, void *userData);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+AT_NONCACHEABLE_SECTION_ALIGN(uart_sdma_handle_t g_uartSdmaHandle, 4);
+AT_NONCACHEABLE_SECTION_ALIGN(sdma_handle_t g_uartTxSdmaHandle, 4);
+AT_NONCACHEABLE_SECTION_ALIGN(sdma_handle_t g_uartRxSdmaHandle, 4);
+
+AT_NONCACHEABLE_SECTION_ALIGN(sdma_context_data_t context_Tx, 4);
+AT_NONCACHEABLE_SECTION_ALIGN(sdma_context_data_t context_Rx, 4);
+
+AT_NONCACHEABLE_SECTION_ALIGN(uart_transfer_t sendXfer, 4);
+AT_NONCACHEABLE_SECTION_ALIGN(uart_transfer_t receiveXfer, 4);
+
+AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint8_t g_tipString[], 4) =
+ "Uart sdma transfer example\r\nBoard receives 8 characters then sends them out\r\nNow please input:\r\n";
+
+AT_NONCACHEABLE_SECTION_ALIGN(uint8_t g_txBuffer[ECHO_BUFFER_LENGTH], 4);
+AT_NONCACHEABLE_SECTION_ALIGN(uint8_t g_rxBuffer[ECHO_BUFFER_LENGTH], 4);
+
+volatile bool rxBufferEmpty = true;
+volatile bool txBufferFull = false;
+volatile bool txOnGoing = false;
+volatile bool rxOnGoing = false;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* UART user callback */
+void UART_UserCallback(UART_Type *base, uart_sdma_handle_t *handle, status_t status, void *userData)
+{
+ userData = userData;
+
+ if (kStatus_UART_TxIdle == status)
+ {
+ txBufferFull = false;
+ txOnGoing = false;
+ }
+
+ if (kStatus_UART_RxIdle == status)
+ {
+ rxBufferEmpty = false;
+ rxOnGoing = false;
+ }
+}
+
+/*!e
+ * @brief Main function
+ */
+int main(void)
+{
+ status_t status;
+ uart_config_t config;
+ sdma_config_t sdmaConfig;
+ uart_transfer_t xfer;
+
+ /* Only configure the RDC if RDC peripheral write access is allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, RDC_GetCurrentMasterDomainId(RDC))) != 0U)
+ {
+ /*set SDMA1 PERIPH to M4 Domain(DID=1),due to UART not be accessible by DID=0 by default*/
+ rdc_domain_assignment_t assignment = {0};
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_SDMA1_PERIPH, &assignment);
+ }
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitMemory();
+ /*
+ * config.baudRate_Bps = 115200U;
+ * config.parityMode = kUART_ParityDisabled;
+ * config.dataBitsCount = kUART_EightDataBits;
+ * config.stopBitCount = kUART_OneStopBit;
+ * config.txFifoWatermark = 2;
+ * config.rxFifoWatermark = 1;
+ * config.enableTx = false;
+ * config.enableRx = false;
+ */
+ UART_GetDefaultConfig(&config);
+ config.baudRate_Bps = BOARD_DEBUG_UART_BAUDRATE;
+ config.rxFifoWatermark = 1;
+ config.enableTx = true;
+ config.enableRx = true;
+
+ status = UART_Init(DEMO_UART, &config, DEMO_UART_CLK_FREQ);
+ if (kStatus_Success != status)
+ {
+ return kStatus_Fail;
+ }
+
+ /* Init the SDMA module */
+ SDMA_GetDefaultConfig(&sdmaConfig);
+ SDMA_Init(EXAMPLE_UART_DMA_BASEADDR, &sdmaConfig);
+ SDMA_CreateHandle(&g_uartTxSdmaHandle, EXAMPLE_UART_DMA_BASEADDR, UART_TX_DMA_CHANNEL, &context_Tx);
+ SDMA_CreateHandle(&g_uartRxSdmaHandle, EXAMPLE_UART_DMA_BASEADDR, UART_RX_DMA_CHANNEL, &context_Rx);
+ SDMA_SetChannelPriority(EXAMPLE_UART_DMA_BASEADDR, UART_TX_DMA_CHANNEL, 3U);
+ SDMA_SetChannelPriority(EXAMPLE_UART_DMA_BASEADDR, UART_RX_DMA_CHANNEL, 4U);
+
+ /* Create UART DMA handle. */
+ UART_TransferCreateHandleSDMA(DEMO_UART, &g_uartSdmaHandle, UART_UserCallback, NULL, &g_uartTxSdmaHandle,
+ &g_uartRxSdmaHandle, UART_TX_DMA_REQUEST, UART_RX_DMA_REQUEST);
+
+ /* Send g_tipString out. */
+ xfer.data = g_tipString;
+ xfer.dataSize = sizeof(g_tipString) - 1;
+ txOnGoing = true;
+ UART_SendSDMA(DEMO_UART, &g_uartSdmaHandle, &xfer);
+
+ /* Wait send finished */
+ while (txOnGoing)
+ {
+ }
+
+ /* Start to echo. */
+ sendXfer.data = g_txBuffer;
+ sendXfer.dataSize = ECHO_BUFFER_LENGTH;
+ receiveXfer.data = g_rxBuffer;
+ receiveXfer.dataSize = ECHO_BUFFER_LENGTH;
+
+ while (1)
+ {
+ /* If RX is idle and g_rxBuffer is empty, start to read data to g_rxBuffer. */
+ if ((!rxOnGoing) && rxBufferEmpty)
+ {
+ rxOnGoing = true;
+ UART_ReceiveSDMA(DEMO_UART, &g_uartSdmaHandle, &receiveXfer);
+ }
+ /* If TX is idle and g_txBuffer is full, start to send data. */
+ if ((!txOnGoing) && txBufferFull)
+ {
+ txOnGoing = true;
+ UART_SendSDMA(DEMO_UART, &g_uartSdmaHandle, &sendXfer);
+ }
+
+ /* If g_txBuffer is empty and g_rxBuffer is full, copy g_rxBuffer to g_txBuffer. */
+ if ((!rxBufferEmpty) && (!txBufferFull))
+ {
+ memcpy(g_txBuffer, g_rxBuffer, ECHO_BUFFER_LENGTH);
+ rxBufferEmpty = true;
+ txBufferFull = true;
+ }
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/CMakeLists.txt b/boards/dart_mx8mm/driver_examples/wdog/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..9399e4299
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/CMakeLists.txt
@@ -0,0 +1,107 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(wdog01)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME wdog01.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../wdog.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities/debug_console_lite
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(utility_debug_console_lite_MIMX8MM6)
+
+include(utility_assert_lite_MIMX8MM6)
+
+include(driver_wdog01_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/wdog01.bin)
+
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/driver_examples/wdog/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/driver_examples/wdog/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/driver_examples/wdog/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_all.bat b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_all.bat
new file mode 100644
index 000000000..02d62fd34
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_all.sh b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_all.sh
new file mode 100755
index 000000000..702783475
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..c84d78542
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..5aa41a2df
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..3fd6f4a78
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c9e344144
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_debug.bat b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_debug.bat
new file mode 100644
index 000000000..15123387e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_debug.sh b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_debug.sh
new file mode 100755
index 000000000..42803761b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..acb3c2d91
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..1ce9d36e7
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_flash_release.bat b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..83f20fc3c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_flash_release.sh b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..f3694ad2e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_release.bat b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_release.bat
new file mode 100644
index 000000000..a88e3d668
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_release.sh b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_release.sh
new file mode 100755
index 000000000..47cfb057c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/clean.bat b/boards/dart_mx8mm/driver_examples/wdog/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/clean.sh b/boards/dart_mx8mm/driver_examples/wdog/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/config.cmake b/boards/dart_mx8mm/driver_examples/wdog/armgcc/config.cmake
new file mode 100755
index 000000000..40f009b9c
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/config.cmake
@@ -0,0 +1,2 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/driver_examples/wdog/armgcc/flags.cmake b/boards/dart_mx8mm/driver_examples/wdog/armgcc/flags.cmake
new file mode 100755
index 000000000..3974febc3
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/armgcc/flags.cmake
@@ -0,0 +1,503 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/driver_examples/wdog/board.c b/boards/dart_mx8mm/driver_examples/wdog/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/driver_examples/wdog/board.h b/boards/dart_mx8mm/driver_examples/wdog/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/wdog/clock_config.c b/boards/dart_mx8mm/driver_examples/wdog/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/driver_examples/wdog/clock_config.h b/boards/dart_mx8mm/driver_examples/wdog/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/wdog/empty_rsc_table.c b/boards/dart_mx8mm/driver_examples/wdog/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/driver_examples/wdog/fsl_iomuxc.h b/boards/dart_mx8mm/driver_examples/wdog/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/driver_examples/wdog/pin_mux.c b/boards/dart_mx8mm/driver_examples/wdog/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/wdog/pin_mux.h b/boards/dart_mx8mm/driver_examples/wdog/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/driver_examples/wdog/readme.txt b/boards/dart_mx8mm/driver_examples/wdog/readme.txt
new file mode 100644
index 000000000..54116040e
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/readme.txt
@@ -0,0 +1,58 @@
+Overview
+========
+The WDOG Example project is to demonstrate usage of the KSDK wdog driver.
+In this example,implemented to test the wdog.
+Please notice that because WDOG control registers are write-once only. And
+for the field WDT, once software performs a write "1" operation to this bit,
+it can not be reset/cleared until the next POR, this bit does not get reset/
+cleared due to any system reset. So the WDOG_Init function can be called
+only once after power reset when WDT set, and the WDOG_Disable function can
+be called only once after reset.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special is needed.
+
+#### Please note this application can't support running with Linux BSP! ####
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+******** System Start ********
+System reset by: Power On Reset!
+
+- 3.Test the WDOG refresh function by using interrupt.
+--- wdog Init done---
+
+WDOG has be refreshed!
+WDOG has be refreshed!
+WDOG has be refreshed!
+WDOG has be refreshed!
+WDOG has be refreshed!
+...
+~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/driver_examples/wdog/wdog.c b/boards/dart_mx8mm/driver_examples/wdog/wdog.c
new file mode 100644
index 000000000..c9ae9177f
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/wdog.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+#include "fsl_wdog.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DEMO_WDOG_BASE WDOG3
+#define DEMO_WDOG_IRQHandler WDOG3_IRQHandler
+
+#define EXAMPLE_DISABLE_WDOG_RESET_FUNCTION (1)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void DEMO_WDOG_IRQHandler(void)
+{
+ WDOG_ClearInterruptStatus(DEMO_WDOG_BASE, kWDOG_InterruptFlag);
+ /* User code. User can do urgent case before timeout reset.
+ * IE. user can backup the ram data or ram log to flash.
+ * the period is set by config.interruptTimeValue, user need to
+ * check the period between interrupt and timeout.
+ */
+}
+
+void delay(uint32_t u32Timeout)
+{
+ while (u32Timeout-- > 0U)
+ {
+ __NOP();
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ uint16_t resetFlag = 0U;
+ wdog_config_t config;
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ PRINTF("\r\n******** System Start ********\r\n");
+ PRINTF("System reset by:");
+
+ resetFlag = WDOG_GetStatusFlags(DEMO_WDOG_BASE);
+
+ switch (resetFlag & (kWDOG_PowerOnResetFlag | kWDOG_TimeoutResetFlag | kWDOG_SoftwareResetFlag))
+ {
+ case kWDOG_PowerOnResetFlag:
+ PRINTF(" Power On Reset!\r\n");
+ break;
+ case kWDOG_TimeoutResetFlag:
+ PRINTF(" Time Out Reset!\r\n");
+ break;
+ case kWDOG_SoftwareResetFlag:
+ PRINTF(" Software Reset!\r\n");
+ break;
+ default:
+ PRINTF(" Error status!\r\n");
+ break;
+ }
+/* Disable wdog reset function test for some devices can't using this feature. */
+#if (!(defined(EXAMPLE_DISABLE_WDOG_RESET_FUNCTION) && EXAMPLE_DISABLE_WDOG_RESET_FUNCTION))
+ /* If system reset from power on, trigger a software reset. */
+ if (resetFlag & kWDOG_PowerOnResetFlag)
+ {
+ PRINTF("\r\n- 1.Testing System reset by software trigger... ");
+ WDOG_TriggerSystemSoftwareReset(DEMO_WDOG_BASE);
+ }
+
+ /* If system reset from software trigger, testing the timeout reset. */
+ if (resetFlag & kWDOG_SoftwareResetFlag)
+ {
+ PRINTF("\r\n- 2.Testing system reset by WDOG timeout.\r\n");
+ /*
+ * wdogConfig->enableWdog = true;
+ * wdogConfig->workMode.enableWait = true;
+ * wdogConfig->workMode.enableStop = false;
+ * wdogConfig->workMode.enableDebug = false;
+ * wdogConfig->enableInterrupt = false;
+ * wdogConfig->enablePowerdown = false;
+ * wdogConfig->resetExtension = flase;
+ * wdogConfig->timeoutValue = 0xFFU;
+ * wdogConfig->interruptTimeValue = 0x04u;
+ */
+ WDOG_GetDefaultConfig(&config);
+ config.timeoutValue = 0xFU; /* Timeout value is (0xF + 1)/2 = 8 sec. */
+ WDOG_Init(DEMO_WDOG_BASE, &config);
+ PRINTF("--- wdog Init done---\r\n");
+
+ /* without feed watch dog, wait until timeout. */
+ while (1)
+ {
+ }
+ }
+
+ /* If system reset from WDOG timeout, testing the refresh function using interrupt. */
+ if (resetFlag & kWDOG_TimeoutResetFlag)
+ {
+#endif
+ PRINTF("\r\n- 3.Test the WDOG refresh function by using interrupt.\r\n");
+ /*
+ * wdogConfig->enableWdog = true;
+ * wdogConfig->workMode.enableWait = true;
+ * wdogConfig->workMode.enableStop = false;
+ * wdogConfig->workMode.enableDebug = false;
+ * wdogConfig->enableInterrupt = false;
+ * wdogConfig->enablePowerdown = false;
+ * wdogConfig->resetExtension = flase;
+ * wdogConfig->timeoutValue = 0xFFU;
+ * wdogConfig->interruptTimeValue = 0x04u;
+ */
+ WDOG_GetDefaultConfig(&config);
+ config.timeoutValue = 0xFU; /* Timeout value is (0xF+1)/2 = 8 sec. */
+ config.enableInterrupt = true;
+ config.interruptTimeValue = 0x4U; /* Interrupt occurred (0x4)/2 = 2 sec before WDOG timeout. */
+ WDOG_Init(DEMO_WDOG_BASE, &config);
+
+ PRINTF("--- wdog Init done---\r\n");
+
+#if (!(defined(EXAMPLE_DISABLE_WDOG_RESET_FUNCTION) && EXAMPLE_DISABLE_WDOG_RESET_FUNCTION))
+ }
+#endif
+
+ while (1)
+ {
+ /* User can feed WDG in their main thread. */
+ WDOG_Refresh(DEMO_WDOG_BASE);
+ PRINTF(" \r\nWDOG has be refreshed!");
+
+ /* Delay. */
+ delay(SystemCoreClock);
+ }
+}
diff --git a/boards/dart_mx8mm/driver_examples/wdog/wdog01_v3_10.xml b/boards/dart_mx8mm/driver_examples/wdog/wdog01_v3_10.xml
new file mode 100644
index 000000000..d8f988a09
--- /dev/null
+++ b/boards/dart_mx8mm/driver_examples/wdog/wdog01_v3_10.xml
@@ -0,0 +1,131 @@
+
+
+
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+
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/FreeRTOSConfig.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/FreeRTOSConfig.h
new file mode 100644
index 000000000..1259531ef
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configCPU_CLOCK_HZ (SystemCoreClock)
+#define configTICK_RATE_HZ ((TickType_t)1000)
+#define configMAX_PRIORITIES 5
+#define configMINIMAL_STACK_SIZE ((unsigned short)90)
+#define configMAX_TASK_NAME_LEN 10
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 0
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c) */
+#define configFRTOS_MEMORY_SCHEME 4
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024))
+#define configAPPLICATION_ALLOCATED_HEAP 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS 1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY 2
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
+
+#define configASSERT_BOOL(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+#define configASSERT(x) configASSERT_BOOL((x)!=0)
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 0
+#define INCLUDE_xTaskGetHandle 0
+#define INCLUDE_xTaskResumeFromISR 1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+ /* Clock manager provides in this variable system core clock frequency */
+ #include
+ extern uint32_t SystemCoreClock;
+#endif
+
+/* Redefine: Mutex is needed for SRTM communication */
+#undef configUSE_MUTEXES
+#define configUSE_MUTEXES 1
+
+#ifndef configTOTAL_HEAP_SIZE
+#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024))
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4 /* 15 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/CMakeLists.txt b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..4b8fe34d9
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/CMakeLists.txt
@@ -0,0 +1,129 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(rpmsg_lite_pingpong_rtos_linux_remote)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME rpmsg_lite_pingpong_rtos_linux_remote.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../main_remote.c"
+"${ProjDirPath}/../FreeRTOSConfig.h"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../rpmsg_config.h"
+"${ProjDirPath}/../rsc_table.c"
+"${ProjDirPath}/../rsc_table.h"
+"${ProjDirPath}/../remoteproc.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/middleware/multicore
+ ${SdkRootDirPath}/rtos/freertos/freertos-kernel
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/serial_manager
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(middleware_multicore_rpmsg_lite_imx8mm_m4_freertos_MIMX8MM6)
+
+include(middleware_multicore_rpmsg_lite_MIMX8MM6)
+
+include(middleware_multicore_rpmsg_lite_freertos_MIMX8MM6)
+
+include(middleware_freertos-kernel_heap_4_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_mu_MIMX8MM6)
+
+include(middleware_freertos-kernel_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(utility_debug_console_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_serial_manager_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(component_serial_manager_uart_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(utility_assert_MIMX8MM6)
+
+include(middleware_freertos-kernel_extension_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/rpmsg_lite_pingpong_rtos_linux_remote.bin)
+
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..1b37e8a39
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..73e32d482
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..6bc389d19
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_all.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_all.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_debug.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_debug.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_flash_release.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_flash_release.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/config.cmake b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/config.cmake
new file mode 100755
index 000000000..525d0fabe
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/config.cmake
@@ -0,0 +1,5 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_middleware_multicore_rpmsg_lite_freertos_MIMX8MM6 true)
+set(CONFIG_USE_component_serial_manager_uart_MIMX8MM6 true)
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
+set(CONFIG_USE_middleware_freertos-kernel_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/flags.cmake b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/flags.cmake
new file mode 100755
index 000000000..e7f4e92f5
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/flags.cmake
@@ -0,0 +1,545 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSDK_OS_FREE_RTOS \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSDK_OS_FREE_RTOS \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSDK_OS_FREE_RTOS \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSDK_OS_FREE_RTOS \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSDK_OS_FREE_RTOS \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSDK_OS_FREE_RTOS \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ -Xlinker \
+ --defsym=__stack_size__=0x400 \
+ -Xlinker \
+ --defsym=__heap_size__=0x400 \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ -Xlinker \
+ --defsym=__stack_size__=0x400 \
+ -Xlinker \
+ --defsym=__heap_size__=0x400 \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ -Xlinker \
+ --defsym=__stack_size__=0x400 \
+ -Xlinker \
+ --defsym=__heap_size__=0x400 \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ -Xlinker \
+ --defsym=__stack_size__=0x400 \
+ -Xlinker \
+ --defsym=__heap_size__=0x400 \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ -Xlinker \
+ --defsym=__stack_size__=0x400 \
+ -Xlinker \
+ --defsym=__heap_size__=0x400 \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ -Xlinker \
+ --defsym=__stack_size__=0x400 \
+ -Xlinker \
+ --defsym=__heap_size__=0x400 \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.c b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.c b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/fsl_iomuxc.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/main_remote.c b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/main_remote.c
new file mode 100644
index 000000000..04191e009
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/main_remote.c
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include
+#include
+#include
+#include "rpmsg_lite.h"
+#include "rpmsg_queue.h"
+#include "rpmsg_ns.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+#include "fsl_uart.h"
+#include "rsc_table.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define RPMSG_LITE_LINK_ID (RL_PLATFORM_IMX8MM_M4_USER_LINK_ID)
+#define RPMSG_LITE_SHMEM_BASE (VDEV0_VRING_BASE)
+#define RPMSG_LITE_NS_ANNOUNCE_STRING "rpmsg-openamp-demo-channel"
+#define RPMSG_LITE_MASTER_IS_LINUX
+
+#define APP_DEBUG_UART_BAUDRATE (115200U) /* Debug console baud rate. */
+#define APP_TASK_STACK_SIZE (256U)
+#ifndef LOCAL_EPT_ADDR
+#define LOCAL_EPT_ADDR (30U)
+#endif
+#define APP_RPMSG_READY_EVENT_DATA (1U)
+
+typedef struct the_message
+{
+ uint32_t DATA;
+} THE_MESSAGE, *THE_MESSAGE_PTR;
+
+static volatile THE_MESSAGE msg = {0};
+#ifdef RPMSG_LITE_MASTER_IS_LINUX
+static char helloMsg[13];
+#endif /* RPMSG_LITE_MASTER_IS_LINUX */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static TaskHandle_t app_task_handle = NULL;
+
+static struct rpmsg_lite_instance *volatile my_rpmsg = NULL;
+
+static struct rpmsg_lite_endpoint *volatile my_ept = NULL;
+static volatile rpmsg_queue_handle my_queue = NULL;
+
+void app_destroy_task(void)
+{
+ if (app_task_handle)
+ {
+ vTaskDelete(app_task_handle);
+ app_task_handle = NULL;
+ }
+
+ if (my_ept)
+ {
+ rpmsg_lite_destroy_ept(my_rpmsg, my_ept);
+ my_ept = NULL;
+ }
+
+ if (my_queue)
+ {
+ rpmsg_queue_destroy(my_rpmsg, my_queue);
+ my_queue = NULL;
+ }
+
+ if (my_rpmsg)
+ {
+ rpmsg_lite_deinit(my_rpmsg);
+ my_rpmsg = NULL;
+ }
+}
+
+static void app_nameservice_isr_cb(uint32_t new_ept, const char *new_ept_name, uint32_t flags, void *user_data)
+{
+}
+
+#ifdef MCMGR_USED
+/*!
+ * @brief Application-specific implementation of the SystemInitHook() weak function.
+ */
+void SystemInitHook(void)
+{
+ /* Initialize MCMGR - low level multicore management library. Call this
+ function as close to the reset entry as possible to allow CoreUp event
+ triggering. The SystemInitHook() weak function overloading is used in this
+ application. */
+ (void)MCMGR_EarlyInit();
+}
+#endif /* MCMGR_USED */
+
+static void app_task(void *param)
+{
+ volatile uint32_t remote_addr;
+ volatile rpmsg_ns_handle ns_handle;
+
+ /* Print the initial banner */
+ (void)PRINTF("\r\nRPMSG Ping-Pong FreeRTOS RTOS API Demo...\r\n");
+
+#ifdef MCMGR_USED
+ uint32_t startupData;
+ mcmgr_status_t status;
+
+ /* Get the startup data */
+ do
+ {
+ status = MCMGR_GetStartupData(&startupData);
+ } while (status != kStatus_MCMGR_Success);
+
+ my_rpmsg = rpmsg_lite_remote_init((void *)(char *)startupData, RPMSG_LITE_LINK_ID, RL_NO_FLAGS);
+
+ /* Signal the other core we are ready by triggering the event and passing the APP_RPMSG_READY_EVENT_DATA */
+ (void)MCMGR_TriggerEvent(kMCMGR_RemoteApplicationEvent, APP_RPMSG_READY_EVENT_DATA);
+#else
+ (void)PRINTF("RPMSG Share Base Addr is 0x%x\r\n", RPMSG_LITE_SHMEM_BASE);
+ my_rpmsg = rpmsg_lite_remote_init((void *)RPMSG_LITE_SHMEM_BASE, RPMSG_LITE_LINK_ID, RL_NO_FLAGS);
+#endif /* MCMGR_USED */
+ rpmsg_lite_wait_for_link_up(my_rpmsg, RL_BLOCK);
+ (void)PRINTF("Link is up!\r\n");
+
+ my_queue = rpmsg_queue_create(my_rpmsg);
+ my_ept = rpmsg_lite_create_ept(my_rpmsg, LOCAL_EPT_ADDR, rpmsg_queue_rx_cb, my_queue);
+ ns_handle = rpmsg_ns_bind(my_rpmsg, app_nameservice_isr_cb, ((void *)0));
+ /* Introduce some delay to avoid NS announce message not being captured by the master side.
+ This could happen when the remote side execution is too fast and the NS announce message is triggered
+ before the nameservice_isr_cb is registered on the master side. */
+ SDK_DelayAtLeastUs(1000000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+ (void)rpmsg_ns_announce(my_rpmsg, my_ept, RPMSG_LITE_NS_ANNOUNCE_STRING, (uint32_t)RL_NS_CREATE);
+ (void)PRINTF("Nameservice announce sent.\r\n");
+
+#ifdef RPMSG_LITE_MASTER_IS_LINUX
+ /* Wait Hello handshake message from Remote Core. */
+ (void)rpmsg_queue_recv(my_rpmsg, my_queue, (uint32_t *)&remote_addr, helloMsg, sizeof(helloMsg), ((void *)0),
+ RL_BLOCK);
+#endif /* RPMSG_LITE_MASTER_IS_LINUX */
+
+ while (msg.DATA <= 100U)
+ {
+ (void)PRINTF("Waiting for ping...\r\n");
+ (void)rpmsg_queue_recv(my_rpmsg, my_queue, (uint32_t *)&remote_addr, (char *)&msg, sizeof(THE_MESSAGE),
+ ((void *)0), RL_BLOCK);
+ msg.DATA++;
+ (void)PRINTF("Sending pong...\r\n");
+ (void)rpmsg_lite_send(my_rpmsg, my_ept, remote_addr, (char *)&msg, sizeof(THE_MESSAGE), RL_BLOCK);
+ }
+
+ (void)PRINTF("Ping pong done, deinitializing...\r\n");
+
+ (void)rpmsg_lite_destroy_ept(my_rpmsg, my_ept);
+ my_ept = ((void *)0);
+ (void)rpmsg_queue_destroy(my_rpmsg, my_queue);
+ my_queue = ((void *)0);
+ (void)rpmsg_ns_unbind(my_rpmsg, ns_handle);
+ (void)rpmsg_lite_deinit(my_rpmsg);
+ my_rpmsg = ((void *)0);
+ msg.DATA = 0U;
+
+ (void)PRINTF("Looping forever...\r\n");
+
+ /* End of the example */
+ for (;;)
+ {
+ }
+}
+
+void app_create_task(void)
+{
+ if (app_task_handle == NULL &&
+ xTaskCreate(app_task, "APP_TASK", APP_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY + 1, &app_task_handle) != pdPASS)
+ {
+ PRINTF("\r\nFailed to create application task\r\n");
+ for (;;)
+ ;
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ /* Initialize standard SDK demo application pins */
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ copyResourceTable();
+
+#ifdef MCMGR_USED
+ /* Initialize MCMGR before calling its API */
+ (void)MCMGR_Init();
+#endif /* MCMGR_USED */
+
+ app_create_task();
+ vTaskStartScheduler();
+
+ (void)PRINTF("Failed to start FreeRTOS on core0.\r\n");
+ for (;;)
+ {
+ }
+}
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.c b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/readme.txt b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/readme.txt
new file mode 100644
index 000000000..54721181f
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/readme.txt
@@ -0,0 +1,84 @@
+Overview
+========
+The Multicore RPMsg-Lite pingpong RTOS project is a simple demonstration program that uses the
+MCUXpresso SDK software and the RPMsg-Lite library and shows how to implement the inter-core
+communicaton between cores of the multicore system. The primary core releases the secondary core
+from the reset and then the inter-core communication is established. Once the RPMsg is initialized
+and endpoints are created the message exchange starts, incrementing a virtual counter that is part
+of the message payload. The message pingpong finishes when the counter reaches the value of 100.
+Then the RPMsg-Lite is deinitialized and the procedure of the data exchange is repeated again.
+
+Shared memory usage
+This multicore example uses the shared memory for data exchange. The shared memory region is
+defined and the size can be adjustable in the linker file. The shared memory region start address
+and the size have to be defined in linker file for each core equally. The shared memory start
+address is then exported from the linker to the application.
+
+Toolchain supported
+===================
+- GCC ARM Embedded 10.3.1
+- IAR embedded Workbench 9.32.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special is needed.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open two serial terminals for A53 core and M4 core with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Using U-Boot command to run the demo.bin file. For details, please refer to Getting Started with MCUXpresso SDK for i.MX 8M Mini.pdf
+5. After running the demo.bin, using the "boot" command to boot the kernel on the A core terminal;
+6. After the kernel is boot, using "root" to login.
+7. After login, make sure imx_rpmsg_pingpong kernel module is inserted (lsmod) or insert it (modprobe imx_rpmsg_pingpong).
+Running the demo
+================
+
+After the boot process succeeds, the ARM Cortex-M4 terminal displays the following information:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+RPMSG Ping-Pong FreeRTOS RTOS API Demo...
+RPMSG Share Base Addr is 0x40000000
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+During boot the Kernel,the ARM Cortex-M4 terminal displays the following information:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Link is up!
+Nameservice announce sent.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+After the Linux RPMsg pingpong module was installed, the ARM Cortex-M4 terminal displays the following information:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Waiting for ping...
+Sending pong...
+Waiting for ping...
+Sending pong...
+Waiting for ping...
+Sending pong...
+......
+Waiting for ping...
+Sending pong...
+Ping pong done, deinitializing...
+Looping forever...
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+The Cortex-A terminal displays the following information:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+get 1 (src: 0x1e)
+get 3 (src: 0x1e)
+......
+get 99 (src: 0x1e)
+get 101 (src: 0x1e)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/remoteproc.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/remoteproc.h
new file mode 100644
index 000000000..7dad9c9eb
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/remoteproc.h
@@ -0,0 +1,372 @@
+/*
+ * Remoteproc Framework
+ *
+ * Copyright 2020 NXP.
+ * Copyright(c) 2018 Xilinx Ltd.
+ * Copyright(c) 2011 Texas Instruments, Inc.
+ * Copyright(c) 2011 Google, Inc.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef REMOTEPROC_H
+#define REMOTEPROC_H
+
+#include
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+#define RSC_NOTIFY_ID_ANY 0xFFFFFFFFUL
+
+#define RPROC_MAX_NAME_LEN 32
+
+/* IAR ARM build tools */
+#if defined(__ICCARM__)
+
+#ifndef METAL_PACKED_BEGIN
+#define METAL_PACKED_BEGIN __packed
+#endif
+
+#ifndef METAL_PACKED_END
+#define METAL_PACKED_END
+#endif
+
+/* GNUC */
+#elif defined(__GNUC__)
+
+#ifndef METAL_PACKED_BEGIN
+#define METAL_PACKED_BEGIN
+#endif
+
+#ifndef METAL_PACKED_END
+#define METAL_PACKED_END __attribute__((__packed__))
+#endif
+
+/* ARMCC */
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+
+#ifndef METAL_PACKED_BEGIN
+#define METAL_PACKED_BEGIN _Pragma("pack(1U)")
+#endif
+
+#ifndef METAL_PACKED_END
+#define METAL_PACKED_END _Pragma("pack()")
+#endif
+
+#else
+/* There is no default definition here to avoid wrong structures packing in case of not supported compiler */
+#error Please implement the structure packing macros for your compiler here!
+#endif
+
+/**
+ * struct resource_table - firmware resource table header
+ * @ver: version number
+ * @num: number of resource entries
+ * @reserved: reserved (must be zero)
+ * @offset: array of offsets pointing at the various resource entries
+ *
+ * A resource table is essentially a list of system resources required
+ * by the remote remoteproc. It may also include configuration entries.
+ * If needed, the remote remoteproc firmware should contain this table
+ * as a dedicated ".resource_table" ELF section.
+ *
+ * Some resources entries are mere announcements, where the host is informed
+ * of specific remoteproc configuration. Other entries require the host to
+ * do something (e.g. allocate a system resource). Sometimes a negotiation
+ * is expected, where the firmware requests a resource, and once allocated,
+ * the host should provide back its details (e.g. address of an allocated
+ * memory region).
+ *
+ * The header of the resource table, as expressed by this structure,
+ * contains a version number (should we need to change this format in the
+ * future), the number of available resource entries, and their offsets
+ * in the table.
+ *
+ * Immediately following this header are the resource entries themselves,
+ * each of which begins with a resource entry header (as described below).
+ */
+METAL_PACKED_BEGIN
+struct resource_table
+{
+ uint32_t ver;
+ uint32_t num;
+ uint32_t reserved[2];
+ uint32_t offset[0];
+} METAL_PACKED_END;
+
+/**
+ * struct fw_rsc_hdr - firmware resource entry header
+ * @type: resource type
+ * @data: resource data
+ *
+ * Every resource entry begins with a 'struct fw_rsc_hdr' header providing
+ * its @type. The content of the entry itself will immediately follow
+ * this header, and it should be parsed according to the resource type.
+ */
+METAL_PACKED_BEGIN
+struct fw_rsc_hdr
+{
+ uint32_t type;
+ uint8_t data[0];
+} METAL_PACKED_END;
+
+/**
+ * enum fw_resource_type - types of resource entries
+ *
+ * @RSC_CARVEOUT: request for allocation of a physically contiguous
+ * memory region.
+ * @RSC_DEVMEM: request to iommu_map a memory-based peripheral.
+ * @RSC_TRACE: announces the availability of a trace buffer into which
+ * the remote remoteproc will be writing logs.
+ * @RSC_VDEV: declare support for a virtio device, and serve as its
+ * virtio header.
+ * @RSC_VENDOR_START: start of the vendor specific resource types range
+ * @RSC_VENDOR_END : end of the vendor specific resource types range
+ * @RSC_LAST: just keep this one at the end
+ *
+ * For more details regarding a specific resource type, please see its
+ * dedicated structure below.
+ *
+ * Please note that these values are used as indices to the rproc_handle_rsc
+ * lookup table, so please keep them sane. Moreover, @RSC_LAST is used to
+ * check the validity of an index before the lookup table is accessed, so
+ * please update it as needed.
+ */
+enum fw_resource_type
+{
+ RSC_CARVEOUT = 0,
+ RSC_DEVMEM = 1,
+ RSC_TRACE = 2,
+ RSC_VDEV = 3,
+ RSC_LAST = 4,
+ RSC_VENDOR_START = 128,
+ RSC_VENDOR_END = 512,
+};
+
+#define FW_RSC_U64_ADDR_ANY 0xFFFFFFFFFFFFFFFFUL
+#define FW_RSC_U32_ADDR_ANY 0xFFFFFFFFUL
+
+/**
+ * struct fw_rsc_carveout - physically contiguous memory request
+ * @da: device address
+ * @pa: physical address
+ * @len: length (in bytes)
+ * @flags: iommu protection flags
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the requested memory region
+ *
+ * This resource entry requests the host to allocate a physically contiguous
+ * memory region.
+ *
+ * These request entries should precede other firmware resource entries,
+ * as other entries might request placing other data objects inside
+ * these memory regions (e.g. data/code segments, trace resource entries, ...).
+ *
+ * Allocating memory this way helps utilizing the reserved physical memory
+ * (e.g. CMA) more efficiently, and also minimizes the number of TLB entries
+ * needed to map it (in case @rproc is using an IOMMU). Reducing the TLB
+ * pressure is important; it may have a substantial impact on performance.
+ *
+ * If the firmware is compiled with static addresses, then @da should specify
+ * the expected device address of this memory region. If @da is set to
+ * FW_RSC_ADDR_ANY, then the host will dynamically allocate it, and then
+ * overwrite @da with the dynamically allocated address.
+ *
+ * We will always use @da to negotiate the device addresses, even if it
+ * isn't using an iommu. In that case, though, it will obviously contain
+ * physical addresses.
+ *
+ * Some remote remoteprocs needs to know the allocated physical address
+ * even if they do use an iommu. This is needed, e.g., if they control
+ * hardware accelerators which access the physical memory directly (this
+ * is the case with OMAP4 for instance). In that case, the host will
+ * overwrite @pa with the dynamically allocated physical address.
+ * Generally we don't want to expose physical addresses if we don't have to
+ * (remote remoteprocs are generally _not_ trusted), so we might want to
+ * change this to happen _only_ when explicitly required by the hardware.
+ *
+ * @flags is used to provide IOMMU protection flags, and @name should
+ * (optionally) contain a human readable name of this carveout region
+ * (mainly for debugging purposes).
+ */
+METAL_PACKED_BEGIN
+struct fw_rsc_carveout
+{
+ uint32_t type;
+ uint32_t da;
+ uint32_t pa;
+ uint32_t len;
+ uint32_t flags;
+ uint32_t reserved;
+ uint8_t name[RPROC_MAX_NAME_LEN];
+} METAL_PACKED_END;
+
+/**
+ * struct fw_rsc_devmem - iommu mapping request
+ * @da: device address
+ * @pa: physical address
+ * @len: length (in bytes)
+ * @flags: iommu protection flags
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the requested region to be mapped
+ *
+ * This resource entry requests the host to iommu map a physically contiguous
+ * memory region. This is needed in case the remote remoteproc requires
+ * access to certain memory-based peripherals; _never_ use it to access
+ * regular memory.
+ *
+ * This is obviously only needed if the remote remoteproc is accessing memory
+ * via an iommu.
+ *
+ * @da should specify the required device address, @pa should specify
+ * the physical address we want to map, @len should specify the size of
+ * the mapping and @flags is the IOMMU protection flags. As always, @name may
+ * (optionally) contain a human readable name of this mapping (mainly for
+ * debugging purposes).
+ *
+ * Note: at this point we just "trust" those devmem entries to contain valid
+ * physical addresses, but this isn't safe and will be changed: eventually we
+ * want remoteproc implementations to provide us ranges of physical addresses
+ * the firmware is allowed to request, and not allow firmwares to request
+ * access to physical addresses that are outside those ranges.
+ */
+METAL_PACKED_BEGIN
+struct fw_rsc_devmem
+{
+ uint32_t type;
+ uint32_t da;
+ uint32_t pa;
+ uint32_t len;
+ uint32_t flags;
+ uint32_t reserved;
+ uint8_t name[RPROC_MAX_NAME_LEN];
+} METAL_PACKED_END;
+
+/**
+ * struct fw_rsc_trace - trace buffer declaration
+ * @da: device address
+ * @len: length (in bytes)
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the trace buffer
+ *
+ * This resource entry provides the host information about a trace buffer
+ * into which the remote remoteproc will write log messages.
+ *
+ * @da specifies the device address of the buffer, @len specifies
+ * its size, and @name may contain a human readable name of the trace buffer.
+ *
+ * After booting the remote remoteproc, the trace buffers are exposed to the
+ * user via debugfs entries (called trace0, trace1, etc..).
+ */
+METAL_PACKED_BEGIN
+struct fw_rsc_trace
+{
+ uint32_t type;
+ uint32_t da;
+ uint32_t len;
+ uint32_t reserved;
+ uint8_t name[RPROC_MAX_NAME_LEN];
+} METAL_PACKED_END;
+
+/**
+ * struct fw_rsc_vdev_vring - vring descriptor entry
+ * @da: device address
+ * @align: the alignment between the consumer and producer parts of the vring
+ * @num: num of buffers supported by this vring (must be power of two)
+ * @notifyid is a unique rproc-wide notify index for this vring. This notify
+ * index is used when kicking a remote remoteproc, to let it know that this
+ * vring is triggered.
+ * @reserved: reserved (must be zero)
+ *
+ * This descriptor is not a resource entry by itself; it is part of the
+ * vdev resource type (see below).
+ *
+ * Note that @da should either contain the device address where
+ * the remote remoteproc is expecting the vring, or indicate that
+ * dynamically allocation of the vring's device address is supported.
+ */
+METAL_PACKED_BEGIN
+struct fw_rsc_vdev_vring
+{
+ uint32_t da;
+ uint32_t align;
+ uint32_t num;
+ uint32_t notifyid;
+ uint32_t reserved;
+} METAL_PACKED_END;
+
+/**
+ * struct fw_rsc_vdev - virtio device header
+ * @id: virtio device id (as in virtio_ids.h)
+ * @notifyid is a unique rproc-wide notify index for this vdev. This notify
+ * index is used when kicking a remote remoteproc, to let it know that the
+ * status/features of this vdev have changes.
+ * @dfeatures specifies the virtio device features supported by the firmware
+ * @gfeatures is a place holder used by the host to write back the
+ * negotiated features that are supported by both sides.
+ * @config_len is the size of the virtio config space of this vdev. The config
+ * space lies in the resource table immediate after this vdev header.
+ * @status is a place holder where the host will indicate its virtio progress.
+ * @num_of_vrings indicates how many vrings are described in this vdev header
+ * @reserved: reserved (must be zero)
+ * @vring is an array of @num_of_vrings entries of 'struct fw_rsc_vdev_vring'.
+ *
+ * This resource is a virtio device header: it provides information about
+ * the vdev, and is then used by the host and its peer remote remoteprocs
+ * to negotiate and share certain virtio properties.
+ *
+ * By providing this resource entry, the firmware essentially asks remoteproc
+ * to statically allocate a vdev upon registration of the rproc (dynamic vdev
+ * allocation is not yet supported).
+ *
+ * Note: unlike virtualization systems, the term 'host' here means
+ * the Linux side which is running remoteproc to control the remote
+ * remoteprocs. We use the name 'gfeatures' to comply with virtio's terms,
+ * though there isn't really any virtualized guest OS here: it's the host
+ * which is responsible for negotiating the final features.
+ * Yeah, it's a bit confusing.
+ *
+ * Note: immediately following this structure is the virtio config space for
+ * this vdev (which is specific to the vdev; for more info, read the virtio
+ * spec). the size of the config space is specified by @config_len.
+ */
+METAL_PACKED_BEGIN
+struct fw_rsc_vdev
+{
+ uint32_t type;
+ uint32_t id;
+ uint32_t notifyid;
+ uint32_t dfeatures;
+ uint32_t gfeatures;
+ uint32_t config_len;
+ uint8_t status;
+ uint8_t num_of_vrings;
+ uint8_t reserved[2];
+ struct fw_rsc_vdev_vring vring[0];
+} METAL_PACKED_END;
+
+/**
+ * struct fw_rsc_vendor - remote processor vendor specific resource
+ * @len: length of the resource
+ *
+ * This resource entry tells the host the vendor specific resource
+ * required by the remote.
+ *
+ * These request entries should precede other shared resource entries
+ * such as vdevs, vrings.
+ */
+METAL_PACKED_BEGIN
+struct fw_rsc_vendor
+{
+ uint32_t type;
+ uint32_t len;
+} METAL_PACKED_END;
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* REMOTEPROC_H_ */
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rpmsg_config.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rpmsg_config.h
new file mode 100644
index 000000000..ff0f400a8
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rpmsg_config.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * Copyright (c) 2015 Xilinx, Inc.
+ * Copyright (c) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RPMSG_CONFIG_H_
+#define RPMSG_CONFIG_H_
+
+/*!
+ * @addtogroup config
+ * @{
+ * @file
+ */
+
+//! @name Configuration options
+//@{
+
+//! @def RL_MS_PER_INTERVAL
+//!
+//! Delay in milliseconds used in non-blocking API functions for polling.
+//! The default value is 1.
+#define RL_MS_PER_INTERVAL (1)
+
+//! @def RL_BUFFER_PAYLOAD_SIZE
+//!
+//! Size of the buffer payload, it must be equal to (240, 496, 1008, ...)
+//! [2^n - 16]. Ensure the same value is defined on both sides of rpmsg
+//! communication. The default value is 496U.
+#define RL_BUFFER_PAYLOAD_SIZE (496U)
+
+//! @def RL_BUFFER_COUNT
+//!
+//! Number of the buffers, it must be power of two (2, 4, ...).
+//! The default value is 2U.
+//! Note this value defines the buffer count for one direction of the rpmsg
+//! communication only, i.e. if the default value of 2 is used
+//! in rpmsg_config.h files for the master and the remote side, 4 buffers
+//! in total are created in the shared memory.
+#define RL_BUFFER_COUNT (256U)
+
+//! @def RL_API_HAS_ZEROCOPY
+//!
+//! Zero-copy API functions enabled/disabled.
+//! The default value is 1 (enabled).
+#define RL_API_HAS_ZEROCOPY (1)
+
+//! @def RL_USE_STATIC_API
+//!
+//! Static API functions (no dynamic allocation) enabled/disabled.
+//! The default value is 0 (static API disabled).
+#define RL_USE_STATIC_API (0)
+
+//! @def RL_CLEAR_USED_BUFFERS
+//!
+//! Clearing used buffers before returning back to the pool of free buffers
+//! enabled/disabled.
+//! The default value is 0 (disabled).
+#define RL_CLEAR_USED_BUFFERS (0)
+
+//! @def RL_USE_MCMGR_IPC_ISR_HANDLER
+//!
+//! When enabled IPC interrupts are managed by the Multicore Manager (IPC
+//! interrupts router), when disabled RPMsg-Lite manages IPC interrupts
+//! by itself.
+//! The default value is 0 (no MCMGR IPC ISR handler used).
+#define RL_USE_MCMGR_IPC_ISR_HANDLER (0)
+
+//! @def RL_USE_ENVIRONMENT_CONTEXT
+//!
+//! When enabled the environment layer uses its own context.
+//! Added for QNX port mainly, but can be used if required.
+//! The default value is 0 (no context, saves some RAM).
+#define RL_USE_ENVIRONMENT_CONTEXT (0)
+
+//! @def RL_DEBUG_CHECK_BUFFERS
+//!
+//! Do not use in RPMsg-Lite to Linux configuration
+#define RL_DEBUG_CHECK_BUFFERS (0)
+//@}
+
+#endif /* RPMSG_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rpmsg_lite_pingpong_rtos_linux_remote_v3_10.xml b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rpmsg_lite_pingpong_rtos_linux_remote_v3_10.xml
new file mode 100644
index 000000000..2dbad8b9f
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rpmsg_lite_pingpong_rtos_linux_remote_v3_10.xml
@@ -0,0 +1,158 @@
+
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diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.c b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.c
new file mode 100644
index 000000000..5346e3dca
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* This file populates resource table for BM remote
+ * for use by the Linux Master */
+
+#include "board.h"
+#include "rsc_table.h"
+#include "rpmsg_lite.h"
+#include
+
+#define NUM_VRINGS 0x02
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const struct remote_resource_table resources = {
+ /* Version */
+ 1,
+
+ /* NUmber of table entries */
+ NO_RESOURCE_ENTRIES,
+ /* reserved fields */
+ {
+ 0,
+ 0,
+ },
+
+ /* Offsets of rsc entries */
+ {
+ offsetof(struct remote_resource_table, user_vdev),
+ },
+
+ /* SRTM virtio device entry */
+ {
+ RSC_VDEV,
+ 7,
+ 0,
+ RSC_VDEV_FEATURE_NS,
+ 0,
+ 0,
+ 0,
+ NUM_VRINGS,
+ {0, 0},
+ },
+
+ /* Vring rsc entry - part of vdev rsc entry */
+ {VDEV0_VRING_BASE, VRING_ALIGN, RL_BUFFER_COUNT, 0, 0},
+ {VDEV0_VRING_BASE + VRING_SIZE, VRING_ALIGN, RL_BUFFER_COUNT, 1, 0},
+};
+
+void copyResourceTable(void)
+{
+ /*
+ * Resource table should be copied to VDEV0_VRING_BASE + RESOURCE_TABLE_OFFSET.
+ * VDEV0_VRING_BASE is temperorily kept for backward compatibility, will be
+ * removed in future release
+ */
+ memcpy((void *)VDEV0_VRING_BASE, &resources, sizeof(resources));
+ memcpy((void *)(VDEV0_VRING_BASE + RESOURCE_TABLE_OFFSET), &resources, sizeof(resources));
+}
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.h
new file mode 100644
index 000000000..9562f6911
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* This file populates resource table for BM remote
+ * for use by the Linux Master */
+
+#ifndef RSC_TABLE_H_
+#define RSC_TABLE_H_
+
+#include
+#include
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+#define NO_RESOURCE_ENTRIES (1)
+#define RSC_VDEV_FEATURE_NS (1) /* Support name service announcement */
+
+/* Resource table for the given remote */
+METAL_PACKED_BEGIN
+struct remote_resource_table
+{
+ uint32_t version;
+ uint32_t num;
+ uint32_t reserved[2];
+ uint32_t offset[NO_RESOURCE_ENTRIES];
+
+ /* rpmsg vdev entry for user app communication */
+ struct fw_rsc_vdev user_vdev;
+ struct fw_rsc_vdev_vring user_vring0;
+ struct fw_rsc_vdev_vring user_vring1;
+} METAL_PACKED_END;
+
+/*
+ * Copy resource table to shared memory base for early M4 boot case.
+ * In M4 early boot case, Linux kernel need to get resource table before file system gets loaded.
+ */
+void copyResourceTable(void);
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* RSC_TABLE_H_ */
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/FreeRTOSConfig.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/FreeRTOSConfig.h
new file mode 100644
index 000000000..367903558
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configCPU_CLOCK_HZ (SystemCoreClock)
+#define configTICK_RATE_HZ ((TickType_t)1000)
+#define configMAX_PRIORITIES 5
+#define configMINIMAL_STACK_SIZE ((unsigned short)90)
+#define configMAX_TASK_NAME_LEN 10
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c) */
+#define configFRTOS_MEMORY_SCHEME 4
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configAPPLICATION_ALLOCATED_HEAP 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS 1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY 2
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
+
+#define configASSERT_BOOL(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+#define configASSERT(x) configASSERT_BOOL((x)!=0)
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 0
+#define INCLUDE_xTaskGetHandle 0
+#define INCLUDE_xTaskResumeFromISR 1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+ /* Clock manager provides in this variable system core clock frequency */
+ #include
+ extern uint32_t SystemCoreClock;
+#endif
+
+/* Redefine: Mutex is needed for SRTM communication */
+#undef configUSE_MUTEXES
+#define configUSE_MUTEXES 1
+
+#ifndef configTOTAL_HEAP_SIZE
+#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024))
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4 /* 15 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/CMakeLists.txt b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..c5bcbe61f
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/CMakeLists.txt
@@ -0,0 +1,129 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(rpmsg_lite_str_echo_rtos_imxcm4)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME rpmsg_lite_str_echo_rtos_imxcm4.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../main_remote.c"
+"${ProjDirPath}/../FreeRTOSConfig.h"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../rpmsg_config.h"
+"${ProjDirPath}/../rsc_table.c"
+"${ProjDirPath}/../rsc_table.h"
+"${ProjDirPath}/../remoteproc.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/middleware/multicore
+ ${SdkRootDirPath}/rtos/freertos/freertos-kernel
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/serial_manager
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(middleware_multicore_rpmsg_lite_imx8mm_m4_freertos_MIMX8MM6)
+
+include(middleware_multicore_rpmsg_lite_MIMX8MM6)
+
+include(middleware_multicore_rpmsg_lite_freertos_MIMX8MM6)
+
+include(middleware_freertos-kernel_heap_4_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(driver_mu_MIMX8MM6)
+
+include(middleware_freertos-kernel_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(utility_debug_console_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_serial_manager_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(component_serial_manager_uart_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(utility_assert_MIMX8MM6)
+
+include(middleware_freertos-kernel_extension_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/rpmsg_lite_str_echo_rtos.bin)
+
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..1b37e8a39
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..73e32d482
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..6bc389d19
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.bat
new file mode 100644
index 000000000..02d62fd34
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.sh
new file mode 100755
index 000000000..702783475
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..c84d78542
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..5aa41a2df
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..3fd6f4a78
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c9e344144
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.bat
new file mode 100644
index 000000000..15123387e
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.sh
new file mode 100755
index 000000000..42803761b
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..acb3c2d91
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..1ce9d36e7
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_flash_release.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..83f20fc3c
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_flash_release.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..f3694ad2e
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_release.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_release.bat
new file mode 100644
index 000000000..a88e3d668
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_release.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_release.sh
new file mode 100755
index 000000000..47cfb057c
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.bat b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.sh b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/config.cmake b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/config.cmake
new file mode 100755
index 000000000..525d0fabe
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/config.cmake
@@ -0,0 +1,5 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_middleware_multicore_rpmsg_lite_freertos_MIMX8MM6 true)
+set(CONFIG_USE_component_serial_manager_uart_MIMX8MM6 true)
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
+set(CONFIG_USE_middleware_freertos-kernel_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/flags.cmake b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/flags.cmake
new file mode 100755
index 000000000..e7f4e92f5
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/flags.cmake
@@ -0,0 +1,545 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSDK_OS_FREE_RTOS \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSDK_OS_FREE_RTOS \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSDK_OS_FREE_RTOS \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSDK_OS_FREE_RTOS \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSDK_OS_FREE_RTOS \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSDK_OS_FREE_RTOS \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ -Xlinker \
+ --defsym=__stack_size__=0x400 \
+ -Xlinker \
+ --defsym=__heap_size__=0x400 \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ -Xlinker \
+ --defsym=__stack_size__=0x400 \
+ -Xlinker \
+ --defsym=__heap_size__=0x400 \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ -Xlinker \
+ --defsym=__stack_size__=0x400 \
+ -Xlinker \
+ --defsym=__heap_size__=0x400 \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ -Xlinker \
+ --defsym=__stack_size__=0x400 \
+ -Xlinker \
+ --defsym=__heap_size__=0x400 \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ -Xlinker \
+ --defsym=__stack_size__=0x400 \
+ -Xlinker \
+ --defsym=__heap_size__=0x400 \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ -Xlinker \
+ --defsym=__stack_size__=0x400 \
+ -Xlinker \
+ --defsym=__heap_size__=0x400 \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/board.c b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/board.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.c b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/fsl_iomuxc.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/main_remote.c b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/main_remote.c
new file mode 100644
index 000000000..04a26b3bb
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/main_remote.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include
+#include
+#include
+#include "rpmsg_lite.h"
+#include "rpmsg_queue.h"
+#include "rpmsg_ns.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+#include "fsl_uart.h"
+#include "rsc_table.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define RPMSG_LITE_SHMEM_BASE (VDEV0_VRING_BASE)
+#define RPMSG_LITE_LINK_ID (RL_PLATFORM_IMX8MM_M4_USER_LINK_ID)
+#define RPMSG_LITE_NS_ANNOUNCE_STRING "rpmsg-virtual-tty-channel-1"
+#define APP_TASK_STACK_SIZE (256)
+#ifndef LOCAL_EPT_ADDR
+#define LOCAL_EPT_ADDR (30)
+#endif
+
+/* Globals */
+static char app_buf[512]; /* Each RPMSG buffer can carry less than 512 payload */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static TaskHandle_t app_task_handle = NULL;
+
+static struct rpmsg_lite_instance *volatile my_rpmsg = NULL;
+
+static struct rpmsg_lite_endpoint *volatile my_ept = NULL;
+static volatile rpmsg_queue_handle my_queue = NULL;
+void app_destroy_task(void)
+{
+ if (app_task_handle)
+ {
+ vTaskDelete(app_task_handle);
+ app_task_handle = NULL;
+ }
+
+ if (my_ept)
+ {
+ rpmsg_lite_destroy_ept(my_rpmsg, my_ept);
+ my_ept = NULL;
+ }
+
+ if (my_queue)
+ {
+ rpmsg_queue_destroy(my_rpmsg, my_queue);
+ my_queue = NULL;
+ }
+
+ if (my_rpmsg)
+ {
+ rpmsg_lite_deinit(my_rpmsg);
+ my_rpmsg = NULL;
+ }
+}
+
+void app_task(void *param)
+{
+ volatile uint32_t remote_addr;
+ void *rx_buf;
+ uint32_t len;
+ int32_t result;
+ void *tx_buf;
+ uint32_t size;
+
+ /* Print the initial banner */
+ PRINTF("\r\nRPMSG String Echo FreeRTOS RTOS API Demo...\r\n");
+
+#ifdef MCMGR_USED
+ uint32_t startupData;
+
+ /* Get the startup data */
+ (void)MCMGR_GetStartupData(kMCMGR_Core1, &startupData);
+
+ my_rpmsg = rpmsg_lite_remote_init((void *)startupData, RPMSG_LITE_LINK_ID, RL_NO_FLAGS);
+
+ /* Signal the other core we are ready */
+ (void)MCMGR_SignalReady(kMCMGR_Core1);
+#else
+ my_rpmsg = rpmsg_lite_remote_init((void *)RPMSG_LITE_SHMEM_BASE, RPMSG_LITE_LINK_ID, RL_NO_FLAGS);
+#endif /* MCMGR_USED */
+
+ rpmsg_lite_wait_for_link_up(my_rpmsg, RL_BLOCK);
+
+ my_queue = rpmsg_queue_create(my_rpmsg);
+ my_ept = rpmsg_lite_create_ept(my_rpmsg, LOCAL_EPT_ADDR, rpmsg_queue_rx_cb, my_queue);
+ (void)rpmsg_ns_announce(my_rpmsg, my_ept, RPMSG_LITE_NS_ANNOUNCE_STRING, RL_NS_CREATE);
+
+ PRINTF("\r\nNameservice sent, ready for incoming messages...\r\n");
+
+ for (;;)
+ {
+ /* Get RPMsg rx buffer with message */
+ result =
+ rpmsg_queue_recv_nocopy(my_rpmsg, my_queue, (uint32_t *)&remote_addr, (char **)&rx_buf, &len, RL_BLOCK);
+ if (result != 0)
+ {
+ assert(false);
+ }
+
+ /* Copy string from RPMsg rx buffer */
+ assert(len < sizeof(app_buf));
+ memcpy(app_buf, rx_buf, len);
+ app_buf[len] = 0; /* End string by '\0' */
+
+ if ((len == 2) && (app_buf[0] == 0xd) && (app_buf[1] == 0xa))
+ PRINTF("Get New Line From Master Side\r\n");
+ else
+ PRINTF("Get Message From Master Side : \"%s\" [len : %d]\r\n", app_buf, len);
+
+ /* Get tx buffer from RPMsg */
+ tx_buf = rpmsg_lite_alloc_tx_buffer(my_rpmsg, &size, RL_BLOCK);
+ assert(tx_buf);
+ /* Copy string to RPMsg tx buffer */
+ memcpy(tx_buf, app_buf, len);
+ /* Echo back received message with nocopy send */
+ result = rpmsg_lite_send_nocopy(my_rpmsg, my_ept, remote_addr, tx_buf, len);
+ if (result != 0)
+ {
+ assert(false);
+ }
+ /* Release held RPMsg rx buffer */
+ result = rpmsg_queue_nocopy_free(my_rpmsg, rx_buf);
+ if (result != 0)
+ {
+ assert(false);
+ }
+ }
+}
+
+void app_create_task(void)
+{
+ if (app_task_handle == NULL &&
+ xTaskCreate(app_task, "APP_TASK", APP_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY + 1, &app_task_handle) != pdPASS)
+ {
+ PRINTF("\r\nFailed to create application task\r\n");
+ for (;;)
+ ;
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ /* Initialize standard SDK demo application pins */
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ copyResourceTable();
+
+#ifdef MCMGR_USED
+ /* Initialize MCMGR before calling its API */
+ (void)MCMGR_Init();
+#endif /* MCMGR_USED */
+
+ app_create_task();
+ vTaskStartScheduler();
+
+ PRINTF("Failed to start FreeRTOS on core0.\n");
+ for (;;)
+ ;
+}
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.c b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/readme.txt b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/readme.txt
new file mode 100644
index 000000000..87e8e0a80
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/readme.txt
@@ -0,0 +1,77 @@
+Overview
+========
+The Multicore RPMsg-Lite string echo project is a simple demonstration program that uses the
+MCUXpresso SDK software and the RPMsg-Lite library and shows how to implement the inter-core
+communicaton between cores of the multicore system.
+
+It works with Linux RPMsg master peer to transfer string content back and forth. The name service
+handshake is performed first to create the communication channels. Next, Linux OS waits for user
+input to the RPMsg virtual tty. Anything which is received is sent to M4. M4 displays what is
+received, and echoes back the same message as an acknowledgement. The tty reader on the Linux side
+can get the message, and start another transaction. The demo demonstrates RPMsg’s ability to send
+arbitrary content back and forth. Note: The maximum message length supported by RPMsg is now 496
+bytes. String longer than 496 will be divided by virtual tty into several messages.
+
+Shared memory usage
+This multicore example uses the shared memory for data exchange. The shared memory region is
+defined and the size can be adjustable in the linker file. The shared memory region start address
+and the size have to be defined in linker file for each core equally. The shared memory start
+address is then exported from the linker to the application.
+
+Toolchain supported
+===================
+- GCC ARM Embedded 10.3.1
+- IAR embedded Workbench 9.32.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special is needed.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open two serial terminals for A53 core and M4 core with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Using U-Boot command to run the demo.bin file. For details, please refer to Getting Started with MCUXpresso SDK for i.MX 8M Mini.pdf
+5. After running the demo.bin, using the "boot" command to boot the kernel on the A core terminal;
+6. After the kernel is boot, using "root" to login.
+7. After login, make sure imx_rpmsg_tty kernel module is inserted (lsmod) or insert it (modprobe imx_rpmsg_tty).
+
+Running the demo
+================
+After the boot process succeeds, the ARM Cortex-M4 terminal displays the following information:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+RPMSG String Echo FreeRTOS RTOS API Demo...
+
+Nameservice sent, ready for incoming messages...
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+After the Linux RPMsg tty module was installed, the ARM Cortex-M4 terminal displays the following
+information:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Get Messgae From Master Side : "hello world!" [len : 12]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+The user can then input an arbitrary string to the virtual RPMsg tty using the following echo command on
+Cortex-A terminal:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+echo test > /dev/ttyRPMSG30 log below shows the output of the RPMsg-Lite str echo demo in the terminal window:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+On the M4 terminal, the received string content and its length is output, as shown in the log.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Get Message From Master Side : "test" [len : 4]
+Get New Line From Master Side
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/remoteproc.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/remoteproc.h
new file mode 100644
index 000000000..7dad9c9eb
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/remoteproc.h
@@ -0,0 +1,372 @@
+/*
+ * Remoteproc Framework
+ *
+ * Copyright 2020 NXP.
+ * Copyright(c) 2018 Xilinx Ltd.
+ * Copyright(c) 2011 Texas Instruments, Inc.
+ * Copyright(c) 2011 Google, Inc.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef REMOTEPROC_H
+#define REMOTEPROC_H
+
+#include
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+#define RSC_NOTIFY_ID_ANY 0xFFFFFFFFUL
+
+#define RPROC_MAX_NAME_LEN 32
+
+/* IAR ARM build tools */
+#if defined(__ICCARM__)
+
+#ifndef METAL_PACKED_BEGIN
+#define METAL_PACKED_BEGIN __packed
+#endif
+
+#ifndef METAL_PACKED_END
+#define METAL_PACKED_END
+#endif
+
+/* GNUC */
+#elif defined(__GNUC__)
+
+#ifndef METAL_PACKED_BEGIN
+#define METAL_PACKED_BEGIN
+#endif
+
+#ifndef METAL_PACKED_END
+#define METAL_PACKED_END __attribute__((__packed__))
+#endif
+
+/* ARMCC */
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+
+#ifndef METAL_PACKED_BEGIN
+#define METAL_PACKED_BEGIN _Pragma("pack(1U)")
+#endif
+
+#ifndef METAL_PACKED_END
+#define METAL_PACKED_END _Pragma("pack()")
+#endif
+
+#else
+/* There is no default definition here to avoid wrong structures packing in case of not supported compiler */
+#error Please implement the structure packing macros for your compiler here!
+#endif
+
+/**
+ * struct resource_table - firmware resource table header
+ * @ver: version number
+ * @num: number of resource entries
+ * @reserved: reserved (must be zero)
+ * @offset: array of offsets pointing at the various resource entries
+ *
+ * A resource table is essentially a list of system resources required
+ * by the remote remoteproc. It may also include configuration entries.
+ * If needed, the remote remoteproc firmware should contain this table
+ * as a dedicated ".resource_table" ELF section.
+ *
+ * Some resources entries are mere announcements, where the host is informed
+ * of specific remoteproc configuration. Other entries require the host to
+ * do something (e.g. allocate a system resource). Sometimes a negotiation
+ * is expected, where the firmware requests a resource, and once allocated,
+ * the host should provide back its details (e.g. address of an allocated
+ * memory region).
+ *
+ * The header of the resource table, as expressed by this structure,
+ * contains a version number (should we need to change this format in the
+ * future), the number of available resource entries, and their offsets
+ * in the table.
+ *
+ * Immediately following this header are the resource entries themselves,
+ * each of which begins with a resource entry header (as described below).
+ */
+METAL_PACKED_BEGIN
+struct resource_table
+{
+ uint32_t ver;
+ uint32_t num;
+ uint32_t reserved[2];
+ uint32_t offset[0];
+} METAL_PACKED_END;
+
+/**
+ * struct fw_rsc_hdr - firmware resource entry header
+ * @type: resource type
+ * @data: resource data
+ *
+ * Every resource entry begins with a 'struct fw_rsc_hdr' header providing
+ * its @type. The content of the entry itself will immediately follow
+ * this header, and it should be parsed according to the resource type.
+ */
+METAL_PACKED_BEGIN
+struct fw_rsc_hdr
+{
+ uint32_t type;
+ uint8_t data[0];
+} METAL_PACKED_END;
+
+/**
+ * enum fw_resource_type - types of resource entries
+ *
+ * @RSC_CARVEOUT: request for allocation of a physically contiguous
+ * memory region.
+ * @RSC_DEVMEM: request to iommu_map a memory-based peripheral.
+ * @RSC_TRACE: announces the availability of a trace buffer into which
+ * the remote remoteproc will be writing logs.
+ * @RSC_VDEV: declare support for a virtio device, and serve as its
+ * virtio header.
+ * @RSC_VENDOR_START: start of the vendor specific resource types range
+ * @RSC_VENDOR_END : end of the vendor specific resource types range
+ * @RSC_LAST: just keep this one at the end
+ *
+ * For more details regarding a specific resource type, please see its
+ * dedicated structure below.
+ *
+ * Please note that these values are used as indices to the rproc_handle_rsc
+ * lookup table, so please keep them sane. Moreover, @RSC_LAST is used to
+ * check the validity of an index before the lookup table is accessed, so
+ * please update it as needed.
+ */
+enum fw_resource_type
+{
+ RSC_CARVEOUT = 0,
+ RSC_DEVMEM = 1,
+ RSC_TRACE = 2,
+ RSC_VDEV = 3,
+ RSC_LAST = 4,
+ RSC_VENDOR_START = 128,
+ RSC_VENDOR_END = 512,
+};
+
+#define FW_RSC_U64_ADDR_ANY 0xFFFFFFFFFFFFFFFFUL
+#define FW_RSC_U32_ADDR_ANY 0xFFFFFFFFUL
+
+/**
+ * struct fw_rsc_carveout - physically contiguous memory request
+ * @da: device address
+ * @pa: physical address
+ * @len: length (in bytes)
+ * @flags: iommu protection flags
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the requested memory region
+ *
+ * This resource entry requests the host to allocate a physically contiguous
+ * memory region.
+ *
+ * These request entries should precede other firmware resource entries,
+ * as other entries might request placing other data objects inside
+ * these memory regions (e.g. data/code segments, trace resource entries, ...).
+ *
+ * Allocating memory this way helps utilizing the reserved physical memory
+ * (e.g. CMA) more efficiently, and also minimizes the number of TLB entries
+ * needed to map it (in case @rproc is using an IOMMU). Reducing the TLB
+ * pressure is important; it may have a substantial impact on performance.
+ *
+ * If the firmware is compiled with static addresses, then @da should specify
+ * the expected device address of this memory region. If @da is set to
+ * FW_RSC_ADDR_ANY, then the host will dynamically allocate it, and then
+ * overwrite @da with the dynamically allocated address.
+ *
+ * We will always use @da to negotiate the device addresses, even if it
+ * isn't using an iommu. In that case, though, it will obviously contain
+ * physical addresses.
+ *
+ * Some remote remoteprocs needs to know the allocated physical address
+ * even if they do use an iommu. This is needed, e.g., if they control
+ * hardware accelerators which access the physical memory directly (this
+ * is the case with OMAP4 for instance). In that case, the host will
+ * overwrite @pa with the dynamically allocated physical address.
+ * Generally we don't want to expose physical addresses if we don't have to
+ * (remote remoteprocs are generally _not_ trusted), so we might want to
+ * change this to happen _only_ when explicitly required by the hardware.
+ *
+ * @flags is used to provide IOMMU protection flags, and @name should
+ * (optionally) contain a human readable name of this carveout region
+ * (mainly for debugging purposes).
+ */
+METAL_PACKED_BEGIN
+struct fw_rsc_carveout
+{
+ uint32_t type;
+ uint32_t da;
+ uint32_t pa;
+ uint32_t len;
+ uint32_t flags;
+ uint32_t reserved;
+ uint8_t name[RPROC_MAX_NAME_LEN];
+} METAL_PACKED_END;
+
+/**
+ * struct fw_rsc_devmem - iommu mapping request
+ * @da: device address
+ * @pa: physical address
+ * @len: length (in bytes)
+ * @flags: iommu protection flags
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the requested region to be mapped
+ *
+ * This resource entry requests the host to iommu map a physically contiguous
+ * memory region. This is needed in case the remote remoteproc requires
+ * access to certain memory-based peripherals; _never_ use it to access
+ * regular memory.
+ *
+ * This is obviously only needed if the remote remoteproc is accessing memory
+ * via an iommu.
+ *
+ * @da should specify the required device address, @pa should specify
+ * the physical address we want to map, @len should specify the size of
+ * the mapping and @flags is the IOMMU protection flags. As always, @name may
+ * (optionally) contain a human readable name of this mapping (mainly for
+ * debugging purposes).
+ *
+ * Note: at this point we just "trust" those devmem entries to contain valid
+ * physical addresses, but this isn't safe and will be changed: eventually we
+ * want remoteproc implementations to provide us ranges of physical addresses
+ * the firmware is allowed to request, and not allow firmwares to request
+ * access to physical addresses that are outside those ranges.
+ */
+METAL_PACKED_BEGIN
+struct fw_rsc_devmem
+{
+ uint32_t type;
+ uint32_t da;
+ uint32_t pa;
+ uint32_t len;
+ uint32_t flags;
+ uint32_t reserved;
+ uint8_t name[RPROC_MAX_NAME_LEN];
+} METAL_PACKED_END;
+
+/**
+ * struct fw_rsc_trace - trace buffer declaration
+ * @da: device address
+ * @len: length (in bytes)
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the trace buffer
+ *
+ * This resource entry provides the host information about a trace buffer
+ * into which the remote remoteproc will write log messages.
+ *
+ * @da specifies the device address of the buffer, @len specifies
+ * its size, and @name may contain a human readable name of the trace buffer.
+ *
+ * After booting the remote remoteproc, the trace buffers are exposed to the
+ * user via debugfs entries (called trace0, trace1, etc..).
+ */
+METAL_PACKED_BEGIN
+struct fw_rsc_trace
+{
+ uint32_t type;
+ uint32_t da;
+ uint32_t len;
+ uint32_t reserved;
+ uint8_t name[RPROC_MAX_NAME_LEN];
+} METAL_PACKED_END;
+
+/**
+ * struct fw_rsc_vdev_vring - vring descriptor entry
+ * @da: device address
+ * @align: the alignment between the consumer and producer parts of the vring
+ * @num: num of buffers supported by this vring (must be power of two)
+ * @notifyid is a unique rproc-wide notify index for this vring. This notify
+ * index is used when kicking a remote remoteproc, to let it know that this
+ * vring is triggered.
+ * @reserved: reserved (must be zero)
+ *
+ * This descriptor is not a resource entry by itself; it is part of the
+ * vdev resource type (see below).
+ *
+ * Note that @da should either contain the device address where
+ * the remote remoteproc is expecting the vring, or indicate that
+ * dynamically allocation of the vring's device address is supported.
+ */
+METAL_PACKED_BEGIN
+struct fw_rsc_vdev_vring
+{
+ uint32_t da;
+ uint32_t align;
+ uint32_t num;
+ uint32_t notifyid;
+ uint32_t reserved;
+} METAL_PACKED_END;
+
+/**
+ * struct fw_rsc_vdev - virtio device header
+ * @id: virtio device id (as in virtio_ids.h)
+ * @notifyid is a unique rproc-wide notify index for this vdev. This notify
+ * index is used when kicking a remote remoteproc, to let it know that the
+ * status/features of this vdev have changes.
+ * @dfeatures specifies the virtio device features supported by the firmware
+ * @gfeatures is a place holder used by the host to write back the
+ * negotiated features that are supported by both sides.
+ * @config_len is the size of the virtio config space of this vdev. The config
+ * space lies in the resource table immediate after this vdev header.
+ * @status is a place holder where the host will indicate its virtio progress.
+ * @num_of_vrings indicates how many vrings are described in this vdev header
+ * @reserved: reserved (must be zero)
+ * @vring is an array of @num_of_vrings entries of 'struct fw_rsc_vdev_vring'.
+ *
+ * This resource is a virtio device header: it provides information about
+ * the vdev, and is then used by the host and its peer remote remoteprocs
+ * to negotiate and share certain virtio properties.
+ *
+ * By providing this resource entry, the firmware essentially asks remoteproc
+ * to statically allocate a vdev upon registration of the rproc (dynamic vdev
+ * allocation is not yet supported).
+ *
+ * Note: unlike virtualization systems, the term 'host' here means
+ * the Linux side which is running remoteproc to control the remote
+ * remoteprocs. We use the name 'gfeatures' to comply with virtio's terms,
+ * though there isn't really any virtualized guest OS here: it's the host
+ * which is responsible for negotiating the final features.
+ * Yeah, it's a bit confusing.
+ *
+ * Note: immediately following this structure is the virtio config space for
+ * this vdev (which is specific to the vdev; for more info, read the virtio
+ * spec). the size of the config space is specified by @config_len.
+ */
+METAL_PACKED_BEGIN
+struct fw_rsc_vdev
+{
+ uint32_t type;
+ uint32_t id;
+ uint32_t notifyid;
+ uint32_t dfeatures;
+ uint32_t gfeatures;
+ uint32_t config_len;
+ uint8_t status;
+ uint8_t num_of_vrings;
+ uint8_t reserved[2];
+ struct fw_rsc_vdev_vring vring[0];
+} METAL_PACKED_END;
+
+/**
+ * struct fw_rsc_vendor - remote processor vendor specific resource
+ * @len: length of the resource
+ *
+ * This resource entry tells the host the vendor specific resource
+ * required by the remote.
+ *
+ * These request entries should precede other shared resource entries
+ * such as vdevs, vrings.
+ */
+METAL_PACKED_BEGIN
+struct fw_rsc_vendor
+{
+ uint32_t type;
+ uint32_t len;
+} METAL_PACKED_END;
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* REMOTEPROC_H_ */
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/rpmsg_config.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/rpmsg_config.h
new file mode 100644
index 000000000..ff0f400a8
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/rpmsg_config.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * Copyright (c) 2015 Xilinx, Inc.
+ * Copyright (c) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RPMSG_CONFIG_H_
+#define RPMSG_CONFIG_H_
+
+/*!
+ * @addtogroup config
+ * @{
+ * @file
+ */
+
+//! @name Configuration options
+//@{
+
+//! @def RL_MS_PER_INTERVAL
+//!
+//! Delay in milliseconds used in non-blocking API functions for polling.
+//! The default value is 1.
+#define RL_MS_PER_INTERVAL (1)
+
+//! @def RL_BUFFER_PAYLOAD_SIZE
+//!
+//! Size of the buffer payload, it must be equal to (240, 496, 1008, ...)
+//! [2^n - 16]. Ensure the same value is defined on both sides of rpmsg
+//! communication. The default value is 496U.
+#define RL_BUFFER_PAYLOAD_SIZE (496U)
+
+//! @def RL_BUFFER_COUNT
+//!
+//! Number of the buffers, it must be power of two (2, 4, ...).
+//! The default value is 2U.
+//! Note this value defines the buffer count for one direction of the rpmsg
+//! communication only, i.e. if the default value of 2 is used
+//! in rpmsg_config.h files for the master and the remote side, 4 buffers
+//! in total are created in the shared memory.
+#define RL_BUFFER_COUNT (256U)
+
+//! @def RL_API_HAS_ZEROCOPY
+//!
+//! Zero-copy API functions enabled/disabled.
+//! The default value is 1 (enabled).
+#define RL_API_HAS_ZEROCOPY (1)
+
+//! @def RL_USE_STATIC_API
+//!
+//! Static API functions (no dynamic allocation) enabled/disabled.
+//! The default value is 0 (static API disabled).
+#define RL_USE_STATIC_API (0)
+
+//! @def RL_CLEAR_USED_BUFFERS
+//!
+//! Clearing used buffers before returning back to the pool of free buffers
+//! enabled/disabled.
+//! The default value is 0 (disabled).
+#define RL_CLEAR_USED_BUFFERS (0)
+
+//! @def RL_USE_MCMGR_IPC_ISR_HANDLER
+//!
+//! When enabled IPC interrupts are managed by the Multicore Manager (IPC
+//! interrupts router), when disabled RPMsg-Lite manages IPC interrupts
+//! by itself.
+//! The default value is 0 (no MCMGR IPC ISR handler used).
+#define RL_USE_MCMGR_IPC_ISR_HANDLER (0)
+
+//! @def RL_USE_ENVIRONMENT_CONTEXT
+//!
+//! When enabled the environment layer uses its own context.
+//! Added for QNX port mainly, but can be used if required.
+//! The default value is 0 (no context, saves some RAM).
+#define RL_USE_ENVIRONMENT_CONTEXT (0)
+
+//! @def RL_DEBUG_CHECK_BUFFERS
+//!
+//! Do not use in RPMsg-Lite to Linux configuration
+#define RL_DEBUG_CHECK_BUFFERS (0)
+//@}
+
+#endif /* RPMSG_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/rpmsg_lite_str_echo_rtos_imxcm4_v3_10.xml b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/rpmsg_lite_str_echo_rtos_imxcm4_v3_10.xml
new file mode 100644
index 000000000..8bb8b8978
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/rpmsg_lite_str_echo_rtos_imxcm4_v3_10.xml
@@ -0,0 +1,158 @@
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diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.c b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.c
new file mode 100644
index 000000000..5346e3dca
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* This file populates resource table for BM remote
+ * for use by the Linux Master */
+
+#include "board.h"
+#include "rsc_table.h"
+#include "rpmsg_lite.h"
+#include
+
+#define NUM_VRINGS 0x02
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const struct remote_resource_table resources = {
+ /* Version */
+ 1,
+
+ /* NUmber of table entries */
+ NO_RESOURCE_ENTRIES,
+ /* reserved fields */
+ {
+ 0,
+ 0,
+ },
+
+ /* Offsets of rsc entries */
+ {
+ offsetof(struct remote_resource_table, user_vdev),
+ },
+
+ /* SRTM virtio device entry */
+ {
+ RSC_VDEV,
+ 7,
+ 0,
+ RSC_VDEV_FEATURE_NS,
+ 0,
+ 0,
+ 0,
+ NUM_VRINGS,
+ {0, 0},
+ },
+
+ /* Vring rsc entry - part of vdev rsc entry */
+ {VDEV0_VRING_BASE, VRING_ALIGN, RL_BUFFER_COUNT, 0, 0},
+ {VDEV0_VRING_BASE + VRING_SIZE, VRING_ALIGN, RL_BUFFER_COUNT, 1, 0},
+};
+
+void copyResourceTable(void)
+{
+ /*
+ * Resource table should be copied to VDEV0_VRING_BASE + RESOURCE_TABLE_OFFSET.
+ * VDEV0_VRING_BASE is temperorily kept for backward compatibility, will be
+ * removed in future release
+ */
+ memcpy((void *)VDEV0_VRING_BASE, &resources, sizeof(resources));
+ memcpy((void *)(VDEV0_VRING_BASE + RESOURCE_TABLE_OFFSET), &resources, sizeof(resources));
+}
diff --git a/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.h b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.h
new file mode 100644
index 000000000..9562f6911
--- /dev/null
+++ b/boards/dart_mx8mm/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* This file populates resource table for BM remote
+ * for use by the Linux Master */
+
+#ifndef RSC_TABLE_H_
+#define RSC_TABLE_H_
+
+#include
+#include
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+#define NO_RESOURCE_ENTRIES (1)
+#define RSC_VDEV_FEATURE_NS (1) /* Support name service announcement */
+
+/* Resource table for the given remote */
+METAL_PACKED_BEGIN
+struct remote_resource_table
+{
+ uint32_t version;
+ uint32_t num;
+ uint32_t reserved[2];
+ uint32_t offset[NO_RESOURCE_ENTRIES];
+
+ /* rpmsg vdev entry for user app communication */
+ struct fw_rsc_vdev user_vdev;
+ struct fw_rsc_vdev_vring user_vring0;
+ struct fw_rsc_vdev_vring user_vring1;
+} METAL_PACKED_END;
+
+/*
+ * Copy resource table to shared memory base for early M4 boot case.
+ * In M4 early boot case, Linux kernel need to get resource table before file system gets loaded.
+ */
+void copyResourceTable(void);
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* RSC_TABLE_H_ */
diff --git a/boards/dart_mx8mm/project_template/board.c b/boards/dart_mx8mm/project_template/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/project_template/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/project_template/board.h b/boards/dart_mx8mm/project_template/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/project_template/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/project_template/clock_config.c b/boards/dart_mx8mm/project_template/clock_config.c
new file mode 100644
index 000000000..19361b0df
--- /dev/null
+++ b/boards/dart_mx8mm/project_template/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 655U,
+ .dsm = 23593U,
+ .preDiv = 5U,
+ .postDiv = 2U, /*!< AUDIO PLL1 frequency = 786432000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 301U,
+ .dsm = 3670U,
+ .preDiv = 5U,
+ .postDiv = 1U, /*!< AUDIO PLL2 frequency = 722534399HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 786432000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 722534399HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/project_template/clock_config.h b/boards/dart_mx8mm/project_template/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/project_template/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/project_template/peripherals.c b/boards/dart_mx8mm/project_template/peripherals.c
new file mode 100644
index 000000000..dd2bddc4a
--- /dev/null
+++ b/boards/dart_mx8mm/project_template/peripherals.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Peripherals v1.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Included files
+ ******************************************************************************/
+#include "peripherals.h"
+
+/*******************************************************************************
+ * BOARD_InitBootPeripherals function
+ ******************************************************************************/
+void BOARD_InitBootPeripherals(void)
+{
+}
diff --git a/boards/dart_mx8mm/project_template/peripherals.h b/boards/dart_mx8mm/project_template/peripherals.h
new file mode 100644
index 000000000..a64c81df4
--- /dev/null
+++ b/boards/dart_mx8mm/project_template/peripherals.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PERIPHERALS_H_
+#define _PERIPHERALS_H_
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus. */
+/*******************************************************************************
+ * BOARD_InitBootPeripherals function
+ ******************************************************************************/
+void BOARD_InitBootPeripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus. */
+
+#endif /* _PERIPHERALS_H_ */
diff --git a/boards/dart_mx8mm/project_template/pin_mux.c b/boards/dart_mx8mm/project_template/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/project_template/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/project_template/pin_mux.h b/boards/dart_mx8mm/project_template/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/project_template/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/FreeRTOSConfig.h b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/FreeRTOSConfig.h
new file mode 100644
index 000000000..7275c1f85
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/FreeRTOSConfig.h
@@ -0,0 +1,163 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configCPU_CLOCK_HZ (SystemCoreClock)
+#define configTICK_RATE_HZ ((TickType_t)200)
+#define configMAX_PRIORITIES 5
+#define configMINIMAL_STACK_SIZE ((unsigned short)90)
+#define configMAX_TASK_NAME_LEN 20
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c) */
+#define configFRTOS_MEMORY_SCHEME 4
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024))
+#define configAPPLICATION_ALLOCATED_HEAP 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
+
+/* Define to trap errors during development. */
+#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 0
+#define INCLUDE_xTaskGetHandle 0
+#define INCLUDE_xTaskResumeFromISR 1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+ /* Clock manager provides in this variable system core clock frequency */
+ #include
+ extern uint32_t SystemCoreClock;
+#endif
+
+/* Redefine: Mutex is needed for SRTM communication */
+#undef configUSE_MUTEXES
+#define configUSE_MUTEXES 1
+
+#ifndef configTOTAL_HEAP_SIZE
+#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024))
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4 /* 15 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/CMakeLists.txt b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..3cccd3cef
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/CMakeLists.txt
@@ -0,0 +1,121 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(freertos_ecspi_loopback)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME freertos_ecspi_loopback.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../freertos_ecspi_loopback.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../FreeRTOSConfig.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/rtos/freertos/freertos-kernel
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/serial_manager
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_clock_MIMX8MM6)
+
+include(driver_ecspi_MIMX8MM6)
+
+include(driver_ecspi_freertos_MIMX8MM6)
+
+include(middleware_freertos-kernel_heap_4_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(utility_debug_console_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_serial_manager_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(component_serial_manager_uart_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(utility_assert_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(middleware_freertos-kernel_MIMX8MM6)
+
+include(middleware_freertos-kernel_extension_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_ecspi_loopback.bin)
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_all.bat b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_all.bat
new file mode 100644
index 000000000..4787726fc
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_all.sh b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_all.sh
new file mode 100755
index 000000000..b0547face
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..dcefedafe
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..3446fb757
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..373514ef3
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c16cafbd5
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_debug.bat
new file mode 100644
index 000000000..98e3af7b8
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_debug.sh
new file mode 100755
index 000000000..bc7d6e8e0
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..7ba253097
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..edcf3f19c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_flash_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..301ca059e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_flash_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..4f1023919
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_release.bat
new file mode 100644
index 000000000..1f9b96808
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_release.sh
new file mode 100755
index 000000000..d89c1a360
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/clean.bat b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/clean.sh b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/config.cmake b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/config.cmake
new file mode 100755
index 000000000..031ad598a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/config.cmake
@@ -0,0 +1,3 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_component_serial_manager_uart_MIMX8MM6 true)
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/flags.cmake b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/flags.cmake
new file mode 100755
index 000000000..4a87a56cb
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/armgcc/flags.cmake
@@ -0,0 +1,521 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/board.c b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/board.h b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/clock_config.c b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/clock_config.h b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/empty_rsc_table.c b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/freertos_ecspi_loopback.c b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/freertos_ecspi_loopback.c
new file mode 100644
index 000000000..23e80c79f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/freertos_ecspi_loopback.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* FreeRTOS kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+/* Freescale includes. */
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "fsl_ecspi.h"
+#include "fsl_ecspi_freertos.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define ECSPI_TRANSFER_SIZE 64
+#define ECSPI_TRANSFER_BAUDRATE 500000U
+#define ECSPI_MASTER_BASEADDR ECSPI1
+#define ECSPI_MASTER_CLK_FREQ \
+ (CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootEcspi1)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootEcspi1)))
+#define ECSPI_MASTER_TRANSFER_CHANNEL kECSPI_Channel0
+#define EXAMPLE_ECSPI_MASTER_IRQN ECSPI1_IRQn
+
+/* Task priorities. */
+#define ecspi_task_PRIORITY (configMAX_PRIORITIES - 2)
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static void ecspi_task(void *pvParameters);
+uint32_t masterRxData[ECSPI_TRANSFER_SIZE] = {0};
+uint32_t masterTxData[ECSPI_TRANSFER_SIZE] = {0};
+static ecspi_master_config_t masterConfig;
+static ecspi_transfer_t masterXfer;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Application entry point.
+ */
+int main(void)
+{
+ /* Init board hardware. */
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ CLOCK_SetRootMux(kCLOCK_RootEcspi1, kCLOCK_EcspiRootmuxSysPll1); /* Set ECSPI1 source to SYSTEM PLL1 800MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootEcspi1, 2U, 5U); /* Set root clock to 800MHZ / 10 = 80MHZ */
+ /* Set IRQ priority for freertos_ecspi */
+ NVIC_SetPriority(EXAMPLE_ECSPI_MASTER_IRQN, 2);
+
+ PRINTF("\r\n***FreeRTOS ECSPI Loopback Demo***\r\n");
+ PRINTF("\r\nThis demo is a loopback transfer test for ECSPI.\r\n");
+ PRINTF("The ECSPI will connect the transmitter and receiver sections internally.\r\n");
+ PRINTF("So, there is no need to connect the MOSI and MISO pins.\r\n");
+
+ if (xTaskCreate(ecspi_task, "Ecspi_task", configMINIMAL_STACK_SIZE + 100, NULL, ecspi_task_PRIORITY, NULL) !=
+ pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+ vTaskStartScheduler();
+ for (;;)
+ ;
+}
+
+/*!
+ * @brief Task responsible for ecspi.
+ */
+static void ecspi_task(void *pvParameters)
+{
+ uint8_t i;
+ status_t status;
+ ecspi_rtos_handle_t master_rtos_handle;
+
+ ECSPI_MasterGetDefaultConfig(&masterConfig);
+
+ masterConfig.baudRate_Bps = ECSPI_TRANSFER_BAUDRATE;
+ masterConfig.enableLoopback = true;
+
+ status = ECSPI_RTOS_Init(&master_rtos_handle, ECSPI_MASTER_BASEADDR, &masterConfig, ECSPI_MASTER_CLK_FREQ);
+
+ if (status != kStatus_Success)
+ {
+ PRINTF("ECSPI meets error during initialization. \r\n");
+ vTaskSuspend(NULL);
+ }
+
+ for (i = 0; i < ECSPI_TRANSFER_SIZE; i++)
+ {
+ masterTxData[i] = i;
+ }
+ masterXfer.txData = masterTxData;
+ masterXfer.rxData = masterRxData;
+ masterXfer.dataSize = ECSPI_TRANSFER_SIZE;
+ masterXfer.channel = ECSPI_MASTER_TRANSFER_CHANNEL;
+ /*Start master transfer*/
+
+ status = ECSPI_RTOS_Transfer(&master_rtos_handle, &masterXfer);
+ if (status != kStatus_Success)
+ {
+ PRINTF("ECSPI transfer completed with error. \r\n\r\n");
+ vTaskSuspend(NULL);
+ }
+
+ /* Compare Tx and Rx data. */
+ for (i = 0; i < ECSPI_TRANSFER_SIZE; i++)
+ {
+ if (masterTxData[i] != masterRxData[i])
+ {
+ break;
+ }
+ }
+
+ if (ECSPI_TRANSFER_SIZE == i)
+ {
+ PRINTF("\r\nFreeRTOS ECSPI loopback test pass!");
+ }
+ else
+ {
+ PRINTF("\r\nFreeRTOS ECSPI loopback test fail!");
+ }
+
+ /* Deinit the ECSPI. */
+ ECSPI_RTOS_Deinit(&master_rtos_handle);
+ vTaskSuspend(NULL);
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/freertos_ecspi_loopback_v3_10.xml b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/freertos_ecspi_loopback_v3_10.xml
new file mode 100644
index 000000000..125fa75df
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/freertos_ecspi_loopback_v3_10.xml
@@ -0,0 +1,143 @@
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diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/fsl_iomuxc.h b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/pin_mux.c b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/pin_mux.h b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/readme.txt b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/readme.txt
new file mode 100644
index 000000000..638202aa3
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_ecspi/ecspi_loopback/readme.txt
@@ -0,0 +1,51 @@
+Overview
+========
+The freertos_ecspi_loopback demo shows how the ecspi do a loopback transfer internally in FreeRTOS.
+The ECSPI connects the transmitter and receiver sections internally, and the data shifted out from the
+most-significant bit of the shift register is looped back into the least-significant bit of the Shift register.
+In this way, a self-test of the complete transmit/receive path can be made. The output pins are not affected,
+and the input pins are ignored.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- MCIMX8MM6-EVK board
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+If the demo run successfully, the below log will be print in the terminal window:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+***FreeRTOS ECSPI Loopback Demo***
+
+This demo is a loopback transfer test for ECSPI.
+The ECSPI will connect the transmitter and receiver sections internally.
+So, there is no need to connect the MOSI and MISO pins.
+
+FreeRTOS ECSPI loopback test pass!
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/FreeRTOSConfig.h b/boards/dart_mx8mm/rtos_examples/freertos_event/FreeRTOSConfig.h
new file mode 100644
index 000000000..f74e29406
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configCPU_CLOCK_HZ (SystemCoreClock)
+#define configTICK_RATE_HZ ((TickType_t)200)
+#define configMAX_PRIORITIES 5
+#define configMINIMAL_STACK_SIZE ((unsigned short)90)
+#define configMAX_TASK_NAME_LEN 20
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c) */
+#define configFRTOS_MEMORY_SCHEME 4
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024))
+#define configAPPLICATION_ALLOCATED_HEAP 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS 1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
+
+/* Define to trap errors during development. */
+#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 0
+#define INCLUDE_xTaskGetHandle 0
+#define INCLUDE_xTaskResumeFromISR 1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+ /* Clock manager provides in this variable system core clock frequency */
+ #include
+ extern uint32_t SystemCoreClock;
+#endif
+
+/* Redefine: Mutex is needed for SRTM communication */
+#undef configUSE_MUTEXES
+#define configUSE_MUTEXES 1
+
+#ifndef configTOTAL_HEAP_SIZE
+#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024))
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4 /* 15 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/CMakeLists.txt b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..419e8cd9c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/CMakeLists.txt
@@ -0,0 +1,117 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(freertos_event)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME freertos_event.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../freertos_event.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../FreeRTOSConfig.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/rtos/freertos/freertos-kernel
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/serial_manager
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_clock_MIMX8MM6)
+
+include(middleware_freertos-kernel_heap_4_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(utility_debug_console_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_serial_manager_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(component_serial_manager_uart_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(utility_assert_MIMX8MM6)
+
+include(middleware_freertos-kernel_MIMX8MM6)
+
+include(middleware_freertos-kernel_extension_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_event.bin)
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_all.bat b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_all.bat
new file mode 100644
index 000000000..02d62fd34
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_all.sh b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_all.sh
new file mode 100755
index 000000000..702783475
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..c84d78542
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..5aa41a2df
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..3fd6f4a78
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c9e344144
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_debug.bat
new file mode 100644
index 000000000..15123387e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_debug.sh
new file mode 100755
index 000000000..42803761b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..acb3c2d91
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..1ce9d36e7
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_flash_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..83f20fc3c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_flash_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..f3694ad2e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_release.bat
new file mode 100644
index 000000000..a88e3d668
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_release.sh
new file mode 100755
index 000000000..47cfb057c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/clean.bat b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/clean.sh b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/config.cmake b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/config.cmake
new file mode 100755
index 000000000..031ad598a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/config.cmake
@@ -0,0 +1,3 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_component_serial_manager_uart_MIMX8MM6 true)
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/flags.cmake b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/flags.cmake
new file mode 100755
index 000000000..4a87a56cb
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/armgcc/flags.cmake
@@ -0,0 +1,521 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/board.c b/boards/dart_mx8mm/rtos_examples/freertos_event/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/board.h b/boards/dart_mx8mm/rtos_examples/freertos_event/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/clock_config.c b/boards/dart_mx8mm/rtos_examples/freertos_event/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/clock_config.h b/boards/dart_mx8mm/rtos_examples/freertos_event/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/empty_rsc_table.c b/boards/dart_mx8mm/rtos_examples/freertos_event/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/freertos_event.c b/boards/dart_mx8mm/rtos_examples/freertos_event/freertos_event.c
new file mode 100644
index 000000000..ccc63eb05
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/freertos_event.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* FreeRTOS kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+#include "event_groups.h"
+
+/* Freescale includes. */
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define B0 (1 << 0)
+#define B1 (1 << 1)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static void write_task_1(void *pvParameters);
+static void write_task_2(void *pvParameters);
+static void read_task(void *pvParameters);
+/*******************************************************************************
+ * Globals
+ ******************************************************************************/
+static EventGroupHandle_t event_group = NULL;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+ event_group = xEventGroupCreate();
+ if (xTaskCreate(write_task_1, "WRITE_TASK_1", configMINIMAL_STACK_SIZE + 100, NULL, tskIDLE_PRIORITY + 1, NULL) !=
+ pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+ if (xTaskCreate(write_task_2, "WRITE_TASK_2", configMINIMAL_STACK_SIZE + 100, NULL, tskIDLE_PRIORITY + 1, NULL) !=
+ pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+ if (xTaskCreate(read_task, "READ_TASK", configMINIMAL_STACK_SIZE + 100, NULL, tskIDLE_PRIORITY + 2, NULL) != pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+ /* Start scheduling. */
+ vTaskStartScheduler();
+ for (;;)
+ ;
+}
+
+/*!
+ * @brief write_task_1 function
+ */
+static void write_task_1(void *pvParameters)
+{
+ while (1)
+ {
+ xEventGroupSetBits(event_group, B0);
+ }
+}
+
+/*!
+ * @brief write_task_2 function
+ */
+static void write_task_2(void *pvParameters)
+{
+ while (1)
+ {
+ xEventGroupSetBits(event_group, B1);
+ }
+}
+
+/*!
+ * @brief read_task function
+ */
+static void read_task(void *pvParameters)
+{
+ EventBits_t event_bits;
+ while (1)
+ {
+ event_bits = xEventGroupWaitBits(event_group, /* The event group handle. */
+ B0 | B1, /* The bit pattern the event group is waiting for. */
+ pdTRUE, /* B0 and B1 will be cleared automatically. */
+ pdFALSE, /* Don't wait for both bits, either bit unblock task. */
+ portMAX_DELAY); /* Block indefinitely to wait for the condition to be met. */
+
+ if ((event_bits & (B0 | B1)) == (B0 | B1))
+ {
+ PRINTF("Both bits are set.");
+ }
+ else if ((event_bits & B0) == B0)
+ {
+ PRINTF("Bit B0 is set.\r\n");
+ }
+ else if ((event_bits & B1) == B1)
+ {
+ PRINTF("Bit B1 is set.\r\n");
+ }
+ }
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/freertos_event_v3_10.xml b/boards/dart_mx8mm/rtos_examples/freertos_event/freertos_event_v3_10.xml
new file mode 100644
index 000000000..3df6a8052
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/freertos_event_v3_10.xml
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diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/fsl_iomuxc.h b/boards/dart_mx8mm/rtos_examples/freertos_event/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/pin_mux.c b/boards/dart_mx8mm/rtos_examples/freertos_event/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/pin_mux.h b/boards/dart_mx8mm/rtos_examples/freertos_event/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_event/readme.txt b/boards/dart_mx8mm/rtos_examples/freertos_event/readme.txt
new file mode 100644
index 000000000..420f3c666
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_event/readme.txt
@@ -0,0 +1,59 @@
+Overview
+========
+This document explains the freertos_event example. It shows how task waits for an event (defined set
+of bits in event group). This event can be set by any other process or interrupt in the system.
+
+The example application creates three tasks. Two write tasks write_task_1 and write_task_2
+continuously setting event bit 0 and bit 1.
+
+Read_task is waiting for any event bit and printing actual state on console. Event bits are
+automatically cleared after read task is entered.
+
+Three possible states can occurre:
+Both bits are set.z
+Bit B0 is set.
+Bit B1 is set.
+
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+After the board is flashed the Tera Term will start printing the state of event bits.
+
+Example output:
+Bit B1 is set.
+Bit B0 is set.
+Bit B1 is set.
+Bit B0 is set.
+Bit B1 is set
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/FreeRTOSConfig.h b/boards/dart_mx8mm/rtos_examples/freertos_generic/FreeRTOSConfig.h
new file mode 100644
index 000000000..55d57e7d2
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configCPU_CLOCK_HZ (SystemCoreClock)
+#define configTICK_RATE_HZ ((TickType_t)200)
+#define configMAX_PRIORITIES 5
+#define configMINIMAL_STACK_SIZE ((unsigned short)90)
+#define configMAX_TASK_NAME_LEN 20
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c) */
+#define configFRTOS_MEMORY_SCHEME 4
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024))
+#define configAPPLICATION_ALLOCATED_HEAP 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 1
+#define configUSE_TICK_HOOK 1
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configUSE_MALLOC_FAILED_HOOK 1
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS 1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
+
+/* Define to trap errors during development. */
+#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 0
+#define INCLUDE_xTaskGetHandle 0
+#define INCLUDE_xTaskResumeFromISR 1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+ /* Clock manager provides in this variable system core clock frequency */
+ #include
+ extern uint32_t SystemCoreClock;
+#endif
+
+/* Redefine: Mutex is needed for SRTM communication */
+#undef configUSE_MUTEXES
+#define configUSE_MUTEXES 1
+
+#ifndef configTOTAL_HEAP_SIZE
+#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024))
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4 /* 15 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/CMakeLists.txt b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..10382970b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/CMakeLists.txt
@@ -0,0 +1,117 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(freertos_generic)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME freertos_generic.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../freertos_generic.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../FreeRTOSConfig.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/rtos/freertos/freertos-kernel
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/serial_manager
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_clock_MIMX8MM6)
+
+include(middleware_freertos-kernel_heap_4_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(utility_debug_console_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_serial_manager_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(component_serial_manager_uart_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(utility_assert_MIMX8MM6)
+
+include(middleware_freertos-kernel_MIMX8MM6)
+
+include(middleware_freertos-kernel_extension_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_generic.bin)
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_all.bat b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_all.bat
new file mode 100644
index 000000000..02d62fd34
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_all.sh b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_all.sh
new file mode 100755
index 000000000..702783475
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..c84d78542
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..5aa41a2df
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..3fd6f4a78
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c9e344144
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_debug.bat
new file mode 100644
index 000000000..15123387e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_debug.sh
new file mode 100755
index 000000000..42803761b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..acb3c2d91
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..1ce9d36e7
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_flash_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..83f20fc3c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_flash_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..f3694ad2e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_release.bat
new file mode 100644
index 000000000..a88e3d668
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_release.sh
new file mode 100755
index 000000000..47cfb057c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/clean.bat b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/clean.sh b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/config.cmake b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/config.cmake
new file mode 100755
index 000000000..031ad598a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/config.cmake
@@ -0,0 +1,3 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_component_serial_manager_uart_MIMX8MM6 true)
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/flags.cmake b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/flags.cmake
new file mode 100755
index 000000000..4a87a56cb
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/armgcc/flags.cmake
@@ -0,0 +1,521 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/board.c b/boards/dart_mx8mm/rtos_examples/freertos_generic/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/board.h b/boards/dart_mx8mm/rtos_examples/freertos_generic/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/clock_config.c b/boards/dart_mx8mm/rtos_examples/freertos_generic/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/clock_config.h b/boards/dart_mx8mm/rtos_examples/freertos_generic/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/empty_rsc_table.c b/boards/dart_mx8mm/rtos_examples/freertos_generic/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/freertos_generic.c b/boards/dart_mx8mm/rtos_examples/freertos_generic/freertos_generic.c
new file mode 100644
index 000000000..f96458c28
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/freertos_generic.c
@@ -0,0 +1,398 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+#include "semphr.h"
+
+/* TODO Add any manufacture supplied header files necessary for CMSIS functions
+to be available here. */
+/* Freescale includes. */
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Priorities at which the tasks are created. The event semaphore task is
+given the maximum priority of ( configMAX_PRIORITIES - 1 ) to ensure it runs as
+soon as the semaphore is given. */
+#define mainQUEUE_RECEIVE_TASK_PRIORITY (tskIDLE_PRIORITY + 2)
+#define mainQUEUE_SEND_TASK_PRIORITY (tskIDLE_PRIORITY + 1)
+#define mainEVENT_SEMAPHORE_TASK_PRIORITY (configMAX_PRIORITIES - 1)
+
+/* The rate at which data is sent to the queue, specified in milliseconds, and
+converted to ticks using the portTICK_PERIOD_MS constant. */
+#define mainQUEUE_SEND_PERIOD_MS (200 / portTICK_PERIOD_MS)
+
+/* The period of the example software timer, specified in milliseconds, and
+converted to ticks using the portTICK_PERIOD_MS constant. */
+#define mainSOFTWARE_TIMER_PERIOD_MS (1000 / portTICK_PERIOD_MS)
+
+/* The number of items the queue can hold. This is 1 as the receive task
+will remove items as they are added, meaning the send task should always find
+the queue empty. */
+#define mainQUEUE_LENGTH (1)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*
+ * The queue send and receive tasks as described in the comments at the top of
+ * this file.
+ */
+static void prvQueueReceiveTask(void *pvParameters);
+static void prvQueueSendTask(void *pvParameters);
+
+/*
+ * The callback function assigned to the example software timer as described at
+ * the top of this file.
+ */
+static void vExampleTimerCallback(TimerHandle_t xTimer);
+
+/*
+ * The event semaphore task as described at the top of this file.
+ */
+static void prvEventSemaphoreTask(void *pvParameters);
+
+/*******************************************************************************
+ * Globals
+ ******************************************************************************/
+/* The queue used by the queue send and queue receive tasks. */
+static QueueHandle_t xQueue = NULL;
+
+/* The semaphore (in this case binary) that is used by the FreeRTOS tick hook
+ * function and the event semaphore task.
+ */
+static SemaphoreHandle_t xEventSemaphore = NULL;
+
+/* The counters used by the various examples. The usage is described in the
+ * comments at the top of this file.
+ */
+static volatile uint32_t ulCountOfTimerCallbackExecutions = 0;
+static volatile uint32_t ulCountOfItemsReceivedOnQueue = 0;
+static volatile uint32_t ulCountOfReceivedSemaphores = 0;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ TimerHandle_t xExampleSoftwareTimer = NULL;
+
+ /* Init board hardware. */
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ /* Create the queue used by the queue send and queue receive tasks. */
+ xQueue = xQueueCreate(/* The number of items the queue can hold. */
+ mainQUEUE_LENGTH,
+ /* The size of each item the queue holds. */
+ sizeof(uint32_t));
+
+ /* Enable queue view in MCUX IDE FreeRTOS TAD plugin. */
+ if (xQueue != NULL)
+ {
+ vQueueAddToRegistry(xQueue, "xQueue");
+ }
+
+ /* Create the semaphore used by the FreeRTOS tick hook function and the
+ event semaphore task. */
+ vSemaphoreCreateBinary(xEventSemaphore);
+
+ /* Create the queue receive task as described in the comments at the top
+ of this file. */
+ if (xTaskCreate(/* The function that implements the task. */
+ prvQueueReceiveTask,
+ /* Text name for the task, just to help debugging. */
+ "Rx",
+ /* The size (in words) of the stack that should be created
+ for the task. */
+ configMINIMAL_STACK_SIZE + 166,
+ /* A parameter that can be passed into the task. Not used
+ in this simple demo. */
+ NULL,
+ /* The priority to assign to the task. tskIDLE_PRIORITY
+ (which is 0) is the lowest priority. configMAX_PRIORITIES - 1
+ is the highest priority. */
+ mainQUEUE_RECEIVE_TASK_PRIORITY,
+ /* Used to obtain a handle to the created task. Not used in
+ this simple demo, so set to NULL. */
+ NULL) != pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+
+ /* Create the queue send task in exactly the same way. Again, this is
+ described in the comments at the top of the file. */
+ if (xTaskCreate(prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE + 166, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL) !=
+ pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+
+ /* Create the task that is synchronised with an interrupt using the
+ xEventSemaphore semaphore. */
+ if (xTaskCreate(prvEventSemaphoreTask, "Sem", configMINIMAL_STACK_SIZE + 166, NULL,
+ mainEVENT_SEMAPHORE_TASK_PRIORITY, NULL) != pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+
+ /* Create the software timer as described in the comments at the top of
+ this file. */
+ xExampleSoftwareTimer = xTimerCreate(/* A text name, purely to help
+ debugging. */
+ "LEDTimer",
+ /* The timer period, in this case
+ 1000ms (1s). */
+ mainSOFTWARE_TIMER_PERIOD_MS,
+ /* This is a periodic timer, so
+ xAutoReload is set to pdTRUE. */
+ pdTRUE,
+ /* The ID is not used, so can be set
+ to anything. */
+ (void *)0,
+ /* The callback function that switches
+ the LED off. */
+ vExampleTimerCallback);
+
+ /* Start the created timer. A block time of zero is used as the timer
+ command queue cannot possibly be full here (this is the first timer to
+ be created, and it is not yet running). */
+ xTimerStart(xExampleSoftwareTimer, 0);
+
+ /* Start the tasks and timer running. */
+ vTaskStartScheduler();
+
+ /* If all is well, the scheduler will now be running, and the following line
+ will never be reached. If the following line does execute, then there was
+ insufficient FreeRTOS heap memory available for the idle and/or timer tasks
+ to be created. See the memory management section on the FreeRTOS web site
+ for more details. */
+ for (;;)
+ ;
+}
+
+/*!
+ * @brief Timer callback.
+ */
+static void vExampleTimerCallback(TimerHandle_t xTimer)
+{
+ /* The timer has expired. Count the number of times this happens. The
+ timer that calls this function is an auto re-load timer, so it will
+ execute periodically. */
+ ulCountOfTimerCallbackExecutions++;
+}
+
+/*!
+ * @brief Task prvQueueSendTask periodically sending message.
+ */
+static void prvQueueSendTask(void *pvParameters)
+{
+ TickType_t xNextWakeTime;
+ const uint32_t ulValueToSend = 100UL;
+
+ /* Initialise xNextWakeTime - this only needs to be done once. */
+ xNextWakeTime = xTaskGetTickCount();
+
+ for (;;)
+ {
+ /* Place this task in the blocked state until it is time to run again.
+ The block time is specified in ticks, the constant used converts ticks
+ to ms. While in the Blocked state this task will not consume any CPU
+ time. */
+ vTaskDelayUntil(&xNextWakeTime, mainQUEUE_SEND_PERIOD_MS);
+
+ /* Send to the queue - causing the queue receive task to unblock and
+ increment its counter. 0 is used as the block time so the sending
+ operation will not block - it shouldn't need to block as the queue
+ should always be empty at this point in the code. */
+ xQueueSend(xQueue, &ulValueToSend, 0);
+ }
+}
+
+/*!
+ * @brief Task prvQueueReceiveTask waiting for message.
+ */
+static void prvQueueReceiveTask(void *pvParameters)
+{
+ uint32_t ulReceivedValue;
+
+ for (;;)
+ {
+ /* Wait until something arrives in the queue - this task will block
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+ FreeRTOSConfig.h. */
+ xQueueReceive(xQueue, &ulReceivedValue, portMAX_DELAY);
+
+ /* To get here something must have been received from the queue, but
+ is it the expected value? If it is, increment the counter. */
+ if (ulReceivedValue == 100UL)
+ {
+ /* Count the number of items that have been received correctly. */
+ ulCountOfItemsReceivedOnQueue++;
+ PRINTF("Receive message counter: %d.\r\n", ulCountOfItemsReceivedOnQueue);
+ }
+ }
+}
+
+/*!
+ * @brief task prvEventSemaphoreTask is waiting for semaphore.
+ */
+static void prvEventSemaphoreTask(void *pvParameters)
+{
+ for (;;)
+ {
+ /* Block until the semaphore is 'given'. */
+ if (xSemaphoreTake(xEventSemaphore, portMAX_DELAY) != pdTRUE)
+ {
+ PRINTF("Failed to take semaphore.\r\n");
+ }
+
+ /* Count the number of times the semaphore is received. */
+ ulCountOfReceivedSemaphores++;
+
+ PRINTF("Event task is running.\r\n");
+ }
+}
+
+/*!
+ * @brief tick hook is executed every tick.
+ */
+void vApplicationTickHook(void)
+{
+ BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ static uint32_t ulCount = 0;
+
+ /* The RTOS tick hook function is enabled by setting configUSE_TICK_HOOK to
+ 1 in FreeRTOSConfig.h.
+
+ "Give" the semaphore on every 500th tick interrupt. */
+ ulCount++;
+ if (ulCount >= 500UL)
+ {
+ /* This function is called from an interrupt context (the RTOS tick
+ interrupt), so only ISR safe API functions can be used (those that end
+ in "FromISR()".
+
+ xHigherPriorityTaskWoken was initialised to pdFALSE, and will be set to
+ pdTRUE by xSemaphoreGiveFromISR() if giving the semaphore unblocked a
+ task that has equal or higher priority than the interrupted task. */
+ xSemaphoreGiveFromISR(xEventSemaphore, &xHigherPriorityTaskWoken);
+ ulCount = 0UL;
+ }
+
+ /* If xHigherPriorityTaskWoken is pdTRUE then a context switch should
+ normally be performed before leaving the interrupt (because during the
+ execution of the interrupt a task of equal or higher priority than the
+ running task was unblocked). The syntax required to context switch from
+ an interrupt is port dependent, so check the documentation of the port you
+ are using.
+
+ In this case, the function is running in the context of the tick interrupt,
+ which will automatically check for the higher priority task to run anyway,
+ so no further action is required. */
+}
+
+/*!
+ * @brief Malloc failed hook.
+ */
+void vApplicationMallocFailedHook(void)
+{
+ /* The malloc failed hook is enabled by setting
+ configUSE_MALLOC_FAILED_HOOK to 1 in FreeRTOSConfig.h.
+
+ Called if a call to pvPortMalloc() fails because there is insufficient
+ free memory available in the FreeRTOS heap. pvPortMalloc() is called
+ internally by FreeRTOS API functions that create tasks, queues, software
+ timers, and semaphores. The size of the FreeRTOS heap is set by the
+ configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */
+ for (;;)
+ ;
+}
+
+/*!
+ * @brief Stack overflow hook.
+ */
+void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName)
+{
+ (void)pcTaskName;
+ (void)xTask;
+
+ /* Run time stack overflow checking is performed if
+ configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
+ function is called if a stack overflow is detected. pxCurrentTCB can be
+ inspected in the debugger if the task name passed into this function is
+ corrupt. */
+ for (;;)
+ ;
+}
+
+/*!
+ * @brief Idle hook.
+ */
+void vApplicationIdleHook(void)
+{
+ volatile size_t xFreeStackSpace;
+
+ /* The idle task hook is enabled by setting configUSE_IDLE_HOOK to 1 in
+ FreeRTOSConfig.h.
+
+ This function is called on each cycle of the idle task. In this case it
+ does nothing useful, other than report the amount of FreeRTOS heap that
+ remains unallocated. */
+ xFreeStackSpace = xPortGetFreeHeapSize();
+
+ if (xFreeStackSpace > 100)
+ {
+ /* By now, the kernel has allocated everything it is going to, so
+ if there is a lot of heap remaining unallocated then
+ the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be
+ reduced accordingly. */
+ }
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/freertos_generic_v3_10.xml b/boards/dart_mx8mm/rtos_examples/freertos_generic/freertos_generic_v3_10.xml
new file mode 100644
index 000000000..e8a52cfcd
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/freertos_generic_v3_10.xml
@@ -0,0 +1,141 @@
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diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/fsl_iomuxc.h b/boards/dart_mx8mm/rtos_examples/freertos_generic/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/pin_mux.c b/boards/dart_mx8mm/rtos_examples/freertos_generic/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/pin_mux.h b/boards/dart_mx8mm/rtos_examples/freertos_generic/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_generic/readme.txt b/boards/dart_mx8mm/rtos_examples/freertos_generic/readme.txt
new file mode 100644
index 000000000..dd2cf77b3
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_generic/readme.txt
@@ -0,0 +1,73 @@
+Overview
+========
+
+This document explains the freertos_generic example. It is based on code FreeRTOS documentation from
+http://www.freertos.org/Hardware-independent-RTOS-example.html. It shows combination of several
+tasks with queue, software timer, tick hook and semaphore.
+
+The example application creates three tasks. The prvQueueSendTask periodically sending data to
+xQueue queue. The prvQueueReceiveTask is waiting for incoming message and counting number of
+received messages. Task prvEventSemaphoreTask is waiting for xEventSemaphore semaphore given from
+vApplicationTickHook. Tick hook give semaphore every 500 ms.
+
+Other hook types used for RTOS and resource statistics are also demonstrated in example:
+* vApplicationIdleHook
+* vApplicationStackOverflowHook
+* vApplicationMallocFailedHook
+
+
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+After the board is flashed the Tera Term will start periodically printing the state of generic example.
+
+Example output:
+Event task is running.
+Receive message counter: 1.
+Receive message counter: 2.
+Receive message counter: 3.
+Receive message counter: 4.
+Receive message counter: 5.
+Receive message counter: 6.
+Receive message counter: 7.
+Receive message counter: 8.
+Receive message counter: 9.
+Receive message counter: 10.
+Receive message counter: 11.
+Receive message counter: 12.
+Event task is running.
+Receive message counter: 13.
+Receive message counter: 14.
+...
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/FreeRTOSConfig.h b/boards/dart_mx8mm/rtos_examples/freertos_hello/FreeRTOSConfig.h
new file mode 100644
index 000000000..f74e29406
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configCPU_CLOCK_HZ (SystemCoreClock)
+#define configTICK_RATE_HZ ((TickType_t)200)
+#define configMAX_PRIORITIES 5
+#define configMINIMAL_STACK_SIZE ((unsigned short)90)
+#define configMAX_TASK_NAME_LEN 20
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c) */
+#define configFRTOS_MEMORY_SCHEME 4
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024))
+#define configAPPLICATION_ALLOCATED_HEAP 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS 1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
+
+/* Define to trap errors during development. */
+#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 0
+#define INCLUDE_xTaskGetHandle 0
+#define INCLUDE_xTaskResumeFromISR 1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+ /* Clock manager provides in this variable system core clock frequency */
+ #include
+ extern uint32_t SystemCoreClock;
+#endif
+
+/* Redefine: Mutex is needed for SRTM communication */
+#undef configUSE_MUTEXES
+#define configUSE_MUTEXES 1
+
+#ifndef configTOTAL_HEAP_SIZE
+#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024))
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4 /* 15 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/CMakeLists.txt b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..05bab13da
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/CMakeLists.txt
@@ -0,0 +1,117 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(freertos_hello)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME freertos_hello.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../freertos_hello.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../FreeRTOSConfig.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/rtos/freertos/freertos-kernel
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/serial_manager
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_clock_MIMX8MM6)
+
+include(middleware_freertos-kernel_heap_4_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(utility_debug_console_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_serial_manager_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(component_serial_manager_uart_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(utility_assert_MIMX8MM6)
+
+include(middleware_freertos-kernel_MIMX8MM6)
+
+include(middleware_freertos-kernel_extension_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_hello.bin)
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_all.bat b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_all.bat
new file mode 100644
index 000000000..02d62fd34
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_all.sh b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_all.sh
new file mode 100755
index 000000000..702783475
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..c84d78542
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..5aa41a2df
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..3fd6f4a78
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c9e344144
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_debug.bat
new file mode 100644
index 000000000..15123387e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_debug.sh
new file mode 100755
index 000000000..42803761b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..acb3c2d91
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..1ce9d36e7
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_flash_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..83f20fc3c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_flash_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..f3694ad2e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_release.bat
new file mode 100644
index 000000000..a88e3d668
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_release.sh
new file mode 100755
index 000000000..47cfb057c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/clean.bat b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/clean.sh b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/config.cmake b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/config.cmake
new file mode 100755
index 000000000..031ad598a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/config.cmake
@@ -0,0 +1,3 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_component_serial_manager_uart_MIMX8MM6 true)
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/flags.cmake b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/flags.cmake
new file mode 100755
index 000000000..4a87a56cb
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/armgcc/flags.cmake
@@ -0,0 +1,521 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/board.c b/boards/dart_mx8mm/rtos_examples/freertos_hello/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/board.h b/boards/dart_mx8mm/rtos_examples/freertos_hello/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/clock_config.c b/boards/dart_mx8mm/rtos_examples/freertos_hello/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/clock_config.h b/boards/dart_mx8mm/rtos_examples/freertos_hello/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/empty_rsc_table.c b/boards/dart_mx8mm/rtos_examples/freertos_hello/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/freertos_hello.c b/boards/dart_mx8mm/rtos_examples/freertos_hello/freertos_hello.c
new file mode 100644
index 000000000..7646f317c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/freertos_hello.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* FreeRTOS kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+/* Freescale includes. */
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Task priorities. */
+#define hello_task_PRIORITY (configMAX_PRIORITIES - 1)
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static void hello_task(void *pvParameters);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Application entry point.
+ */
+int main(void)
+{
+ /* Init board hardware. */
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+ if (xTaskCreate(hello_task, "Hello_task", configMINIMAL_STACK_SIZE + 100, NULL, hello_task_PRIORITY, NULL) !=
+ pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+ vTaskStartScheduler();
+ for (;;)
+ ;
+}
+
+/*!
+ * @brief Task responsible for printing of "Hello world." message.
+ */
+static void hello_task(void *pvParameters)
+{
+ for (;;)
+ {
+ PRINTF("Hello world.\r\n");
+ vTaskSuspend(NULL);
+ }
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/freertos_hello_v3_10.xml b/boards/dart_mx8mm/rtos_examples/freertos_hello/freertos_hello_v3_10.xml
new file mode 100644
index 000000000..0196b94e3
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/freertos_hello_v3_10.xml
@@ -0,0 +1,141 @@
+
+
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diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/fsl_iomuxc.h b/boards/dart_mx8mm/rtos_examples/freertos_hello/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/pin_mux.c b/boards/dart_mx8mm/rtos_examples/freertos_hello/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/pin_mux.h b/boards/dart_mx8mm/rtos_examples/freertos_hello/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_hello/readme.txt b/boards/dart_mx8mm/rtos_examples/freertos_hello/readme.txt
new file mode 100644
index 000000000..3ed0b2f08
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_hello/readme.txt
@@ -0,0 +1,50 @@
+Overview
+========
+The Hello World project is a simple demonstration program that uses the SDK UART drivere in
+combination with FreeRTOS. The purpose of this demo is to show how to use the debug console and to
+provide a simple project for debugging and further development.
+
+The example application creates one task called hello_task. This task print "Hello world." message
+via debug console utility and suspend itself.
+
+
+
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+After the board is flashed the Tera Term will print "Hello world" message on terminal.
+
+Example output:
+Hello world.
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/FreeRTOSConfig.h b/boards/dart_mx8mm/rtos_examples/freertos_i2c/FreeRTOSConfig.h
new file mode 100644
index 000000000..f74e29406
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configCPU_CLOCK_HZ (SystemCoreClock)
+#define configTICK_RATE_HZ ((TickType_t)200)
+#define configMAX_PRIORITIES 5
+#define configMINIMAL_STACK_SIZE ((unsigned short)90)
+#define configMAX_TASK_NAME_LEN 20
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c) */
+#define configFRTOS_MEMORY_SCHEME 4
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024))
+#define configAPPLICATION_ALLOCATED_HEAP 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS 1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
+
+/* Define to trap errors during development. */
+#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 0
+#define INCLUDE_xTaskGetHandle 0
+#define INCLUDE_xTaskResumeFromISR 1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+ /* Clock manager provides in this variable system core clock frequency */
+ #include
+ extern uint32_t SystemCoreClock;
+#endif
+
+/* Redefine: Mutex is needed for SRTM communication */
+#undef configUSE_MUTEXES
+#define configUSE_MUTEXES 1
+
+#ifndef configTOTAL_HEAP_SIZE
+#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024))
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4 /* 15 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/CMakeLists.txt b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..f9a72891a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/CMakeLists.txt
@@ -0,0 +1,121 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(freertos_i2c)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME freertos_i2c.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../freertos_i2c.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../FreeRTOSConfig.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/rtos/freertos/freertos-kernel
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/serial_manager
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_ii2c_MIMX8MM6)
+
+include(driver_ii2c_freertos_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(middleware_freertos-kernel_heap_4_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(utility_debug_console_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_serial_manager_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(component_serial_manager_uart_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(utility_assert_MIMX8MM6)
+
+include(middleware_freertos-kernel_MIMX8MM6)
+
+include(middleware_freertos-kernel_extension_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_i2c.bin)
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_all.bat b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_all.bat
new file mode 100644
index 000000000..02d62fd34
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_all.sh b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_all.sh
new file mode 100755
index 000000000..702783475
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..c84d78542
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..5aa41a2df
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..3fd6f4a78
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c9e344144
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_debug.bat
new file mode 100644
index 000000000..15123387e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_debug.sh
new file mode 100755
index 000000000..42803761b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..acb3c2d91
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..1ce9d36e7
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_flash_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..83f20fc3c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_flash_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..f3694ad2e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_release.bat
new file mode 100644
index 000000000..a88e3d668
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_release.sh
new file mode 100755
index 000000000..47cfb057c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/clean.bat b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/clean.sh b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/config.cmake b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/config.cmake
new file mode 100755
index 000000000..031ad598a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/config.cmake
@@ -0,0 +1,3 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_component_serial_manager_uart_MIMX8MM6 true)
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/flags.cmake b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/flags.cmake
new file mode 100755
index 000000000..4a87a56cb
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/armgcc/flags.cmake
@@ -0,0 +1,521 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/board.c b/boards/dart_mx8mm/rtos_examples/freertos_i2c/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/board.h b/boards/dart_mx8mm/rtos_examples/freertos_i2c/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/clock_config.c b/boards/dart_mx8mm/rtos_examples/freertos_i2c/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/clock_config.h b/boards/dart_mx8mm/rtos_examples/freertos_i2c/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/empty_rsc_table.c b/boards/dart_mx8mm/rtos_examples/freertos_i2c/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/freertos_i2c.c b/boards/dart_mx8mm/rtos_examples/freertos_i2c/freertos_i2c.c
new file mode 100644
index 000000000..7b1cbb2be
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/freertos_i2c.c
@@ -0,0 +1,422 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Standard C Included Files */
+#include
+
+/* FreeRTOS kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+#include "semphr.h"
+
+/* SDK Included Files */
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#include "fsl_debug_console.h"
+#include "fsl_i2c.h"
+#include "fsl_i2c_freertos.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define EXAMPLE_I2C_MASTER_BASE I2C4
+#define EXAMPLE_I2C_MASTER_IRQN I2C4_IRQn
+#define EXAMPLE_I2C_MASTER_CLK_FREQ \
+ (CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootI2c4)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootI2c4)) / 5) /* SYSTEM PLL1 DIV5 */
+#define EXAMPLE_I2C_SLAVE_BASE I2C4
+#define EXAMPLE_I2C_SLAVE_IRQN I2C4_IRQn
+#define EXAMPLE_I2C_SLAVE_CLK_FREQ \
+ (CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootI2c4)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootI2c4)) / 5) /* SYSTEM PLL1 DIV5 */
+#define SINGLE_BOARD 0
+#define BOARD_TO_BOARD 1
+
+#define EXAMPLE_CONNECT_I2C BOARD_TO_BOARD
+#if (EXAMPLE_CONNECT_I2C == BOARD_TO_BOARD)
+#define isMASTER 0
+#define isSLAVE 1
+#define I2C_MASTER_SLAVE isMASTER
+#endif
+
+#if (EXAMPLE_CONNECT_I2C == BOARD_TO_BOARD)
+#define EXAMPLE_I2C_DEALY_COUNT 1000u
+#endif
+
+#define EXAMPLE_I2C_MASTER ((I2C_Type *)EXAMPLE_I2C_MASTER_BASE)
+#define EXAMPLE_I2C_SLAVE ((I2C_Type *)EXAMPLE_I2C_SLAVE_BASE)
+
+#define I2C_MASTER_SLAVE_ADDR_7BIT (0x7EU)
+#define I2C_BAUDRATE (100000) /* 100K */
+#define I2C_DATA_LENGTH (32) /* MAX is 256 */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+uint8_t g_slave_buff[I2C_DATA_LENGTH];
+uint8_t g_master_buff[I2C_DATA_LENGTH];
+
+i2c_master_handle_t *g_m_handle;
+i2c_slave_handle_t g_s_handle;
+SemaphoreHandle_t i2c_sem;
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Task priorities. */
+#define slave_task_PRIORITY (configMAX_PRIORITIES - 1)
+#define master_task_PRIORITY (configMAX_PRIORITIES - 2)
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static void slave_task(void *pvParameters);
+#if ((I2C_MASTER_SLAVE == isMaster) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD))
+static void master_task(void *pvParameters);
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+int main(void)
+{
+ /* Init board hardware. */
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+
+ CLOCK_SetRootMux(kCLOCK_RootI2c4, kCLOCK_I2cRootmuxSysPll1Div5); /* Set I2C source to SysPLL1 Div5 160MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootI2c4, 1U, 10U); /* Set root clock to 160MHZ / 10 = 16MHZ */
+
+ NVIC_SetPriority(EXAMPLE_I2C_SLAVE_IRQN, 2);
+ NVIC_SetPriority(EXAMPLE_I2C_MASTER_IRQN, 3);
+
+ PRINTF("\r\n==FreeRTOS I2C example start.==\r\n");
+#if (EXAMPLE_CONNECT_I2C == SINGLE_BOARD)
+ PRINTF("This example use one i2c instance as master and another as slave on one board.\r\n");
+#elif (EXAMPLE_CONNECT_I2C == BOARD_TO_BOARD)
+ PRINTF("This example use two boards to connect with one as master and another as slave.\r\n");
+#endif
+
+ if (xTaskCreate(slave_task, "Slave_task", configMINIMAL_STACK_SIZE + 100, NULL, slave_task_PRIORITY, NULL) !=
+ pdPASS)
+ {
+ PRINTF("Failed to create slave task");
+ while (1)
+ ;
+ }
+
+ vTaskStartScheduler();
+ for (;;)
+ ;
+}
+
+/*!
+ * @brief Data structure and callback function for slave I2C communication.
+ */
+
+typedef struct _callback_message_t
+{
+ status_t async_status;
+ SemaphoreHandle_t sem;
+} callback_message_t;
+
+#if (I2C_MASTER_SLAVE == isSLAVE)
+static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData)
+{
+ callback_message_t *cb_msg = (callback_message_t *)userData;
+ BaseType_t reschedule = 0;
+
+ switch (xfer->event)
+ {
+ /* Transmit request */
+ case kI2C_SlaveTransmitEvent:
+ /* Update information for transmit process */
+ xfer->data = g_slave_buff;
+ xfer->dataSize = I2C_DATA_LENGTH;
+ break;
+
+ /* Receive request */
+ case kI2C_SlaveReceiveEvent:
+ /* Update information for received process */
+ xfer->data = g_slave_buff;
+ xfer->dataSize = I2C_DATA_LENGTH;
+ break;
+
+ /* Transfer done */
+ case kI2C_SlaveCompletionEvent:
+ cb_msg->async_status = xfer->completionStatus;
+ xSemaphoreGiveFromISR(cb_msg->sem, &reschedule);
+ portYIELD_FROM_ISR(reschedule);
+ break;
+
+ default:
+ break;
+ }
+}
+#endif
+
+/*!
+ * @brief Task responsible for slave I2C communication.
+ */
+
+static void slave_task(void *pvParameters)
+{
+#if ((I2C_MASTER_SLAVE == isSLAVE) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD))
+ i2c_slave_config_t slaveConfig;
+#endif
+
+ callback_message_t cb_msg = {0};
+
+ cb_msg.sem = xSemaphoreCreateBinary();
+ if (cb_msg.sem == NULL)
+ {
+ PRINTF("I2C slave: Error creating semaphore\r\n");
+ vTaskSuspend(NULL);
+ }
+ i2c_sem = cb_msg.sem;
+
+#if ((I2C_MASTER_SLAVE == isSLAVE) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD))
+ /* Set up I2C slave */
+ /*
+ * slaveConfig.addressingMode = kI2C_Address7bit;
+ * slaveConfig.enableGeneralCall = false;
+ * slaveConfig.enableWakeUp = false;
+ * slaveConfig.enableBaudRateCtl = false;
+ * slaveConfig.enableSlave = true;
+ */
+ I2C_SlaveGetDefaultConfig(&slaveConfig);
+ slaveConfig.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT;
+#if defined(FSL_FEATURE_SOC_I2C_COUNT) && FSL_FEATURE_SOC_I2C_COUNT
+ slaveConfig.addressingMode = kI2C_Address7bit;
+ slaveConfig.upperAddress = 0; /* not used for this example */
+ I2C_SlaveInit(EXAMPLE_I2C_SLAVE, &slaveConfig, EXAMPLE_I2C_SLAVE_CLK_FREQ);
+#endif
+#if defined(FSL_FEATURE_SOC_II2C_COUNT) && FSL_FEATURE_SOC_II2C_COUNT
+ I2C_SlaveInit(EXAMPLE_I2C_SLAVE, &slaveConfig);
+#endif
+ for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++)
+ {
+ g_slave_buff[i] = 0;
+ }
+
+ memset(&g_s_handle, 0, sizeof(g_s_handle));
+
+ I2C_SlaveTransferCreateHandle(EXAMPLE_I2C_SLAVE, &g_s_handle, i2c_slave_callback, &cb_msg);
+ I2C_SlaveTransferNonBlocking(EXAMPLE_I2C_SLAVE, &g_s_handle, kI2C_SlaveCompletionEvent);
+#endif /* ((I2C_MASTER_SLAVE == isSLAVE) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD)) */
+
+#if ((I2C_MASTER_SLAVE == isMASTER) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD))
+ if (xTaskCreate(master_task, "Master_task", configMINIMAL_STACK_SIZE + 124, NULL, master_task_PRIORITY, NULL) !=
+ pdPASS)
+ {
+ PRINTF("Failed to create master task");
+ vTaskSuspend(NULL);
+ }
+#endif /* ((I2C_MASTER_SLAVE == isMASTER) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD)) */
+
+ /* Wait for transfer to finish */
+ if (xSemaphoreTake(cb_msg.sem, portMAX_DELAY) != pdTRUE)
+ {
+ PRINTF("Failed to take semaphore.\r\n");
+ }
+
+#if ((I2C_MASTER_SLAVE == isSLAVE) || (EXAMPLE_CONNECT_DSPI == SINGLE_BOARD))
+ if (cb_msg.async_status == kStatus_Success)
+ {
+ PRINTF("I2C slave transfer completed successfully. \r\n\r\n");
+ }
+ else
+ {
+ PRINTF("I2C slave transfer completed with error. \r\n\r\n");
+ }
+
+#if (EXAMPLE_CONNECT_I2C == SINGLE_BOARD)
+ for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++)
+ {
+ if (g_slave_buff[i] != g_master_buff[i])
+ {
+ PRINTF("\r\nError occurred in this transfer ! \r\n");
+ break;
+ }
+ }
+#endif
+
+ PRINTF("Slave received data :");
+ for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++)
+ {
+ if (i % 8 == 0)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF("0x%2x ", g_slave_buff[i]);
+ }
+ PRINTF("\r\n\r\n");
+
+#if (EXAMPLE_CONNECT_I2C == SINGLE_BOARD)
+ /* Set up slave ready to send data to master. */
+ for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++)
+ {
+ g_slave_buff[i] = ~g_slave_buff[i];
+ }
+
+ PRINTF("This time , slave will send data: :");
+ for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++)
+ {
+ if (i % 8 == 0)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF("0x%2x ", g_slave_buff[i]);
+ }
+ PRINTF("\r\n\r\n");
+#endif
+#endif
+
+ /* Wait for transfer to finish */
+ if (xSemaphoreTake(cb_msg.sem, portMAX_DELAY) != pdTRUE)
+ {
+ PRINTF("Failed to take semaphore.\r\n");
+ }
+#if (EXAMPLE_CONNECT_I2C == BOARD_TO_BOARD)
+ PRINTF("\r\nEnd of FreeRTOS I2C example.\r\n");
+#endif
+
+ vTaskSuspend(NULL);
+}
+
+#if ((I2C_MASTER_SLAVE == isMaster) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD))
+static void master_task(void *pvParameters)
+{
+ i2c_rtos_handle_t master_rtos_handle;
+ i2c_master_config_t masterConfig;
+ i2c_master_transfer_t masterXfer;
+ uint32_t sourceClock;
+ status_t status;
+
+ /* Set up i2c master to send data to slave */
+ for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++)
+ {
+ g_master_buff[i] = i;
+ }
+
+ PRINTF("Master will send data :");
+ for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++)
+ {
+ if (i % 8 == 0)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF("0x%2x ", g_master_buff[i]);
+ }
+ PRINTF("\r\n\r\n");
+
+ /*
+ * masterConfig.baudRate_Bps = 100000U;
+ * masterConfig.enableStopHold = false;
+ * masterConfig.glitchFilterWidth = 0U;
+ * masterConfig.enableMaster = true;
+ */
+ I2C_MasterGetDefaultConfig(&masterConfig);
+ masterConfig.baudRate_Bps = I2C_BAUDRATE;
+ sourceClock = EXAMPLE_I2C_MASTER_CLK_FREQ;
+
+ status = I2C_RTOS_Init(&master_rtos_handle, EXAMPLE_I2C_MASTER, &masterConfig, sourceClock);
+ if (status != kStatus_Success)
+ {
+ PRINTF("I2C master: error during init, %d", status);
+ }
+
+ g_m_handle = &master_rtos_handle.drv_handle;
+
+ memset(&masterXfer, 0, sizeof(masterXfer));
+ masterXfer.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT;
+ masterXfer.direction = kI2C_Write;
+ masterXfer.subaddress = 0;
+ masterXfer.subaddressSize = 0;
+ masterXfer.data = g_master_buff;
+ masterXfer.dataSize = I2C_DATA_LENGTH;
+ masterXfer.flags = kI2C_TransferDefaultFlag;
+
+ status = I2C_RTOS_Transfer(&master_rtos_handle, &masterXfer);
+ if (status != kStatus_Success)
+ {
+ PRINTF("I2C master: error during write transaction, %d", status);
+ }
+#if (EXAMPLE_CONNECT_I2C == BOARD_TO_BOARD)
+ /* Delay to wait slave is ready */
+ SDK_DelayAtLeastUs(5000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+#endif
+ /* Set up master to receive data from slave. */
+
+ for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++)
+ {
+ g_master_buff[i] = 0;
+ }
+
+ masterXfer.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT;
+ masterXfer.direction = kI2C_Read;
+ masterXfer.subaddress = 0;
+ masterXfer.subaddressSize = 0;
+ masterXfer.data = g_master_buff;
+ masterXfer.dataSize = I2C_DATA_LENGTH;
+ masterXfer.flags = kI2C_TransferDefaultFlag;
+
+ status = I2C_RTOS_Transfer(&master_rtos_handle, &masterXfer);
+ if (status != kStatus_Success)
+ {
+ PRINTF("I2C master: error during read transaction, %d", status);
+ }
+#if (EXAMPLE_CONNECT_DSPI == BOARD_TO_BOARD)
+ else
+ {
+ xSemaphoreGive(i2c_sem);
+ }
+#endif
+
+#if (EXAMPLE_CONNECT_I2C == SINGLE_BOARD)
+ /* Transfer completed. Check the data. */
+ for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++)
+ {
+ if (g_slave_buff[i] != g_master_buff[i])
+ {
+ PRINTF("\r\nError occurred in the transfer ! \r\n");
+ break;
+ }
+ }
+#endif
+
+ PRINTF("Master received data :");
+ for (uint32_t i = 0; i < I2C_DATA_LENGTH; i++)
+ {
+ if (i % 8 == 0)
+ {
+ PRINTF("\r\n");
+ }
+ PRINTF("0x%2x ", g_master_buff[i]);
+ }
+ PRINTF("\r\n\r\n");
+
+ PRINTF("\r\nEnd of FreeRTOS I2C example.\r\n");
+
+ vTaskSuspend(NULL);
+}
+#endif //((I2C_MASTER_SLAVE == isMaster) || (EXAMPLE_CONNECT_I2C == SINGLE_BOARD))
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/freertos_i2c_v3_10.xml b/boards/dart_mx8mm/rtos_examples/freertos_i2c/freertos_i2c_v3_10.xml
new file mode 100644
index 000000000..db0cd3e71
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/freertos_i2c_v3_10.xml
@@ -0,0 +1,143 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/fsl_iomuxc.h b/boards/dart_mx8mm/rtos_examples/freertos_i2c/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/pin_mux.c b/boards/dart_mx8mm/rtos_examples/freertos_i2c/pin_mux.c
new file mode 100644
index 000000000..5eae3091d
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/pin_mux.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v4.1
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 0.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D13, peripheral: I2C4, signal: i2c_scl, pin_signal: I2C4_SCL, PE: Disabled, HYS: Enabled, SION: ENABLED, DSE: X6_0}
+ - {pin_num: E13, peripheral: I2C4, signal: i2c_sda, pin_signal: I2C4_SDA, PE: Disabled, HYS: Enabled, SION: ENABLED, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SCL_I2C4_SCL, 1U);
+ IOMUXC_SetPinConfig(IOMUXC_I2C4_SCL_I2C4_SCL,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_I2C4_SDA, 1U);
+ IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_I2C4_SDA,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) |
+ IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/pin_mux.h b/boards/dart_mx8mm/rtos_examples/freertos_i2c/pin_mux.h
new file mode 100644
index 000000000..1d906205a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/pin_mux.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_i2c/readme.txt b/boards/dart_mx8mm/rtos_examples/freertos_i2c/readme.txt
new file mode 100644
index 000000000..719a9e34f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_i2c/readme.txt
@@ -0,0 +1,192 @@
+Overview
+========
+The freertos_i2c example shows an application using RTOS tasks with I2C driver:
+
+The example may support 2 different connections (it depends on the specific board):
+On board connection and board to board connection.
+
+With one board connection, 2 I2C instances of the same board are used. One i2c instance used as I2C master and another I2C instance used as I2C slave .
+ Default settings in freertos_i2c.c (in folder boards\\rtos_examples\freertos_i2c) is applied.
+ Two tasks are created. One task is associated with an I2C master operation and another task deals with I2C slave operation.
+ 1. I2C master task sends data to I2C slave task.
+ 2. I2C master task reads data sent back from I2C slave task.
+
+ The transmit data and the receive data of both I2C master task and I2C slave task are printed out on terminal.
+
+With board to board connection, one I2C instance on one board is used as I2C master and the I2C instance on other board is used as I2C slave. Tasks are created to run on each board to handle I2C communication.
+ File freertos_i2c.c should have following definitions:
+ #define EXAMPLE_CONNECT_I2C BOARD_TO_BOARD
+ For board used as I2C master:
+ #define I2C_MASTER_SLAVE isMASTER
+ For board used as I2C slave:
+ #define I2C_MASTER_SLAVE isSLAVE
+
+
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+Please note only board to board connection is supported, on board connection is not supported.
+Transfer data from MASTER_BOARD to SLAVE_BOARD of I2C interface, I2C4 pins of MASTER_BOARD are connected with I2C4 pins of SLAVE_BOARD.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+SLAVE_BOARD CONNECTS TO MASTER_BOARD
+Pin Name Board Location Pin Name Board Location
+For I2C4 connection, refer to: https://variwiki.com/index.php?title=MCUXpresso&release=MCUXPRESSO_2.13.0_V1.0_DART-MX8M-MINI#Demos_pins
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+When the example runs successfully:
+If using 1 board, you can see the similar information from the terminal as below. (Applicable to all boards except TWR-KM34Z75M)
+
+
+
+==FreeRTOS I2C example start.==
+
+This example use one i2c instance as master and another as slave on one board.
+
+Master will send data :
+
+0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7
+
+0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f
+
+0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+
+0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
+
+
+
+I2C slave transfer completed successfully.
+
+
+
+Slave received data :
+
+0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7
+
+0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f
+
+0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+
+0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
+
+
+
+This time , slave will send data: :
+
+0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8
+
+0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0
+
+0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 0xe8
+
+0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0
+
+
+
+Master received data :
+
+0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8
+
+0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0
+
+0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 0xe8
+
+0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0
+
+
+
+
+
+End of FreeRTOS I2C example.
+
+
+If using 2 boards, you can see the similar information from the terminal associated with master board and slave board as below. (Applicable to all boards)
+
+For master:
+
+==FreeRTOS I2C example start.==
+
+This example use two boards to connect with one as master and another as slave.
+
+Master will send data :
+
+0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7
+
+0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f
+
+0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+
+0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
+
+
+
+Master received data :
+
+0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7
+
+0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f
+
+0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+
+0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
+
+
+
+
+
+End of FreeRTOS I2C example.
+
+
+For slave:
+
+
+==FreeRTOS I2C example start.==
+
+This example use two boards to connect with one as master and another as slave.
+
+I2C slave transfer completed successfully.
+
+
+
+Slave received data :
+
+0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x 6 0x 7
+
+0x 8 0x 9 0x a 0x b 0x c 0x d 0x e 0x f
+
+0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
+
+0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
+
+
+
+
+
+End of FreeRTOS I2C example.
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/FreeRTOSConfig.h b/boards/dart_mx8mm/rtos_examples/freertos_mutex/FreeRTOSConfig.h
new file mode 100644
index 000000000..f74e29406
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configCPU_CLOCK_HZ (SystemCoreClock)
+#define configTICK_RATE_HZ ((TickType_t)200)
+#define configMAX_PRIORITIES 5
+#define configMINIMAL_STACK_SIZE ((unsigned short)90)
+#define configMAX_TASK_NAME_LEN 20
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c) */
+#define configFRTOS_MEMORY_SCHEME 4
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024))
+#define configAPPLICATION_ALLOCATED_HEAP 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS 1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
+
+/* Define to trap errors during development. */
+#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 0
+#define INCLUDE_xTaskGetHandle 0
+#define INCLUDE_xTaskResumeFromISR 1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+ /* Clock manager provides in this variable system core clock frequency */
+ #include
+ extern uint32_t SystemCoreClock;
+#endif
+
+/* Redefine: Mutex is needed for SRTM communication */
+#undef configUSE_MUTEXES
+#define configUSE_MUTEXES 1
+
+#ifndef configTOTAL_HEAP_SIZE
+#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024))
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4 /* 15 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/CMakeLists.txt b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..495887616
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/CMakeLists.txt
@@ -0,0 +1,117 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(freertos_mutex)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME freertos_mutex.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../freertos_mutex.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../FreeRTOSConfig.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/rtos/freertos/freertos-kernel
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/serial_manager
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_clock_MIMX8MM6)
+
+include(middleware_freertos-kernel_heap_4_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(utility_debug_console_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_serial_manager_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(component_serial_manager_uart_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(utility_assert_MIMX8MM6)
+
+include(middleware_freertos-kernel_MIMX8MM6)
+
+include(middleware_freertos-kernel_extension_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_mutex.bin)
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_all.bat b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_all.bat
new file mode 100644
index 000000000..02d62fd34
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_all.sh b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_all.sh
new file mode 100755
index 000000000..702783475
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..c84d78542
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..5aa41a2df
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..3fd6f4a78
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c9e344144
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_debug.bat
new file mode 100644
index 000000000..15123387e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_debug.sh
new file mode 100755
index 000000000..42803761b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..acb3c2d91
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..1ce9d36e7
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_flash_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..83f20fc3c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_flash_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..f3694ad2e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_release.bat
new file mode 100644
index 000000000..a88e3d668
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_release.sh
new file mode 100755
index 000000000..47cfb057c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/clean.bat b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/clean.sh b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/config.cmake b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/config.cmake
new file mode 100755
index 000000000..031ad598a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/config.cmake
@@ -0,0 +1,3 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_component_serial_manager_uart_MIMX8MM6 true)
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/flags.cmake b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/flags.cmake
new file mode 100755
index 000000000..4a87a56cb
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/armgcc/flags.cmake
@@ -0,0 +1,521 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/board.c b/boards/dart_mx8mm/rtos_examples/freertos_mutex/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/board.h b/boards/dart_mx8mm/rtos_examples/freertos_mutex/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/clock_config.c b/boards/dart_mx8mm/rtos_examples/freertos_mutex/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/clock_config.h b/boards/dart_mx8mm/rtos_examples/freertos_mutex/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/empty_rsc_table.c b/boards/dart_mx8mm/rtos_examples/freertos_mutex/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/freertos_mutex.c b/boards/dart_mx8mm/rtos_examples/freertos_mutex/freertos_mutex.c
new file mode 100644
index 000000000..1aa612c9b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/freertos_mutex.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+#include "semphr.h"
+
+/* Freescale includes. */
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+SemaphoreHandle_t xMutex;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static void write_task_1(void *pvParameters);
+static void write_task_2(void *pvParameters);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ xMutex = xSemaphoreCreateMutex();
+
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+ if (xTaskCreate(write_task_1, "WRITE_TASK_1", configMINIMAL_STACK_SIZE + 128, NULL, tskIDLE_PRIORITY + 1, NULL) !=
+ pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+ if (xTaskCreate(write_task_2, "WRITE_TASK_2", configMINIMAL_STACK_SIZE + 128, NULL, tskIDLE_PRIORITY + 1, NULL) !=
+ pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+ /* Start scheduling. */
+ vTaskStartScheduler();
+ for (;;)
+ ;
+}
+
+/*!
+ * @brief Write Task 1 function
+ */
+static void write_task_1(void *pvParameters)
+{
+ while (1)
+ {
+ if (xSemaphoreTake(xMutex, portMAX_DELAY) != pdTRUE)
+ {
+ PRINTF("Failed to take semaphore.\r\n");
+ }
+ PRINTF("ABCD |");
+ taskYIELD();
+ PRINTF(" EFGH\r\n");
+ xSemaphoreGive(xMutex);
+ taskYIELD();
+ }
+}
+
+/*!
+ * @brief Write Task 2 function
+ */
+static void write_task_2(void *pvParameters)
+{
+ while (1)
+ {
+ if (xSemaphoreTake(xMutex, portMAX_DELAY) != pdTRUE)
+ {
+ PRINTF("Failed to take semaphore.\r\n");
+ }
+ PRINTF("1234 |");
+ taskYIELD();
+ PRINTF(" 5678\r\n");
+ xSemaphoreGive(xMutex);
+ taskYIELD();
+ }
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/freertos_mutex_v3_10.xml b/boards/dart_mx8mm/rtos_examples/freertos_mutex/freertos_mutex_v3_10.xml
new file mode 100644
index 000000000..7e8daf19d
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/freertos_mutex_v3_10.xml
@@ -0,0 +1,141 @@
+
+
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diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/fsl_iomuxc.h b/boards/dart_mx8mm/rtos_examples/freertos_mutex/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/pin_mux.c b/boards/dart_mx8mm/rtos_examples/freertos_mutex/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/pin_mux.h b/boards/dart_mx8mm/rtos_examples/freertos_mutex/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_mutex/readme.txt b/boards/dart_mx8mm/rtos_examples/freertos_mutex/readme.txt
new file mode 100644
index 000000000..ac9c3e621
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_mutex/readme.txt
@@ -0,0 +1,61 @@
+Overview
+========
+This document explains the freertos_mutex example. It shows how mutex manage access to common
+resource (terminal output).
+
+The example application creates two identical instances of write_task. Each task will lock the mutex
+before printing and unlock it after printing to ensure that the outputs from tasks are not mixed
+together.
+
+The test_task accept output message during creation as function parameter. Output message have two
+parts. If xMutex is unlocked, the write_task_1 acquire xMutex and print first part of message. Then
+rescheduling is performed. In this moment scheduler check if some other task could run, but second
+task write_task+_2 is blocked because xMutex is already locked by first write task. The first
+write_task_1 continue from last point by printing of second message part. Finaly the xMutex is
+unlocked and second instance of write_task_2 is executed.
+
+
+
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+After the board is flashed the Tera Term will start periodically printing strings synchronized by
+mutex.
+
+Example output:
+"ABCD | EFGH"
+"1234 | 5678"
+"ABCD | EFGH"
+"1234 | 5678"
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/FreeRTOSConfig.h b/boards/dart_mx8mm/rtos_examples/freertos_queue/FreeRTOSConfig.h
new file mode 100644
index 000000000..d174f2bf4
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configCPU_CLOCK_HZ (SystemCoreClock)
+#define configTICK_RATE_HZ ((TickType_t)200)
+#define configMAX_PRIORITIES 5
+#define configMINIMAL_STACK_SIZE ((unsigned short)90)
+#define configMAX_TASK_NAME_LEN 20
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c) */
+#define configFRTOS_MEMORY_SCHEME 4
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024))
+#define configAPPLICATION_ALLOCATED_HEAP 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS 1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
+
+#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 0
+#define INCLUDE_xTaskGetHandle 0
+#define INCLUDE_xTaskResumeFromISR 1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+ /* Clock manager provides in this variable system core clock frequency */
+ #include
+ extern uint32_t SystemCoreClock;
+#endif
+
+/* Redefine: Mutex is needed for SRTM communication */
+#undef configUSE_MUTEXES
+#define configUSE_MUTEXES 1
+
+#ifndef configTOTAL_HEAP_SIZE
+#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024))
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4 /* 15 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/CMakeLists.txt b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..3f2aaaa2a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/CMakeLists.txt
@@ -0,0 +1,117 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(freertos_queue)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME freertos_queue.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../freertos_queue.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../FreeRTOSConfig.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/rtos/freertos/freertos-kernel
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/serial_manager
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_clock_MIMX8MM6)
+
+include(middleware_freertos-kernel_heap_4_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(utility_debug_console_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_serial_manager_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(component_serial_manager_uart_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(utility_assert_MIMX8MM6)
+
+include(middleware_freertos-kernel_MIMX8MM6)
+
+include(middleware_freertos-kernel_extension_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_queue.bin)
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_all.bat b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_all.bat
new file mode 100644
index 000000000..02d62fd34
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_all.sh b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_all.sh
new file mode 100755
index 000000000..702783475
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..c84d78542
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..5aa41a2df
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..3fd6f4a78
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c9e344144
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_debug.bat
new file mode 100644
index 000000000..15123387e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_debug.sh
new file mode 100755
index 000000000..42803761b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..acb3c2d91
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..1ce9d36e7
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_flash_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..83f20fc3c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_flash_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..f3694ad2e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_release.bat
new file mode 100644
index 000000000..a88e3d668
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_release.sh
new file mode 100755
index 000000000..47cfb057c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/clean.bat b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/clean.sh b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/config.cmake b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/config.cmake
new file mode 100755
index 000000000..031ad598a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/config.cmake
@@ -0,0 +1,3 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_component_serial_manager_uart_MIMX8MM6 true)
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/flags.cmake b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/flags.cmake
new file mode 100755
index 000000000..4a87a56cb
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/armgcc/flags.cmake
@@ -0,0 +1,521 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/board.c b/boards/dart_mx8mm/rtos_examples/freertos_queue/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/board.h b/boards/dart_mx8mm/rtos_examples/freertos_queue/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/clock_config.c b/boards/dart_mx8mm/rtos_examples/freertos_queue/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/clock_config.h b/boards/dart_mx8mm/rtos_examples/freertos_queue/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/empty_rsc_table.c b/boards/dart_mx8mm/rtos_examples/freertos_queue/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/freertos_queue.c b/boards/dart_mx8mm/rtos_examples/freertos_queue/freertos_queue.c
new file mode 100644
index 000000000..ccc4db5cd
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/freertos_queue.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*System includes.*/
+#include
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+/* Freescale includes. */
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define MAX_LOG_LENGTH 20
+/*******************************************************************************
+ * Globals
+ ******************************************************************************/
+/* Logger queue handle */
+static QueueHandle_t log_queue = NULL;
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/* Application API */
+static void write_task_1(void *pvParameters);
+static void write_task_2(void *pvParameters);
+
+/* Logger API */
+void log_add(char *log);
+void log_init(uint32_t queue_length, uint32_t max_log_lenght);
+static void log_task(void *pvParameters);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+ /* Initialize logger for 10 logs with maximum lenght of one log 20 B */
+ log_init(10, MAX_LOG_LENGTH);
+ if (xTaskCreate(write_task_1, "WRITE_TASK_1", configMINIMAL_STACK_SIZE + 166, NULL, tskIDLE_PRIORITY + 2, NULL) !=
+ pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+ if (xTaskCreate(write_task_2, "WRITE_TASK_2", configMINIMAL_STACK_SIZE + 166, NULL, tskIDLE_PRIORITY + 2, NULL) !=
+ pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+ vTaskStartScheduler();
+ for (;;)
+ ;
+}
+
+/*******************************************************************************
+ * Application functions
+ ******************************************************************************/
+/*!
+ * @brief write_task_1 function
+ */
+static void write_task_1(void *pvParameters)
+{
+ char log[MAX_LOG_LENGTH + 1];
+ uint32_t i = 0;
+ for (i = 0; i < 5; i++)
+ {
+ sprintf(log, "Task1 Message %d", (int)i);
+ log_add(log);
+ taskYIELD();
+ }
+ vTaskSuspend(NULL);
+}
+
+/*!
+ * @brief write_task_2 function
+ */
+static void write_task_2(void *pvParameters)
+{
+ char log[MAX_LOG_LENGTH + 1];
+ uint32_t i = 0;
+ for (i = 0; i < 5; i++)
+ {
+ sprintf(log, "Task2 Message %d", (int)i);
+ log_add(log);
+ taskYIELD();
+ }
+ vTaskSuspend(NULL);
+}
+
+/*******************************************************************************
+ * Logger functions
+ ******************************************************************************/
+/*!
+ * @brief log_add function
+ */
+void log_add(char *log)
+{
+ xQueueSend(log_queue, log, 0);
+}
+
+/*!
+ * @brief log_init function
+ */
+void log_init(uint32_t queue_length, uint32_t max_log_lenght)
+{
+ log_queue = xQueueCreate(queue_length, max_log_lenght);
+ /* Enable queue view in MCUX IDE FreeRTOS TAD plugin. */
+ if (log_queue != NULL)
+ {
+ vQueueAddToRegistry(log_queue, "LogQ");
+ }
+ if (xTaskCreate(log_task, "log_task", configMINIMAL_STACK_SIZE + 166, NULL, tskIDLE_PRIORITY + 1, NULL) != pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+}
+
+/*!
+ * @brief log_print_task function
+ */
+static void log_task(void *pvParameters)
+{
+ uint32_t counter = 0;
+ char log[MAX_LOG_LENGTH + 1];
+ while (1)
+ {
+ if (xQueueReceive(log_queue, log, portMAX_DELAY) != pdTRUE)
+ {
+ PRINTF("Failed to receive queue.\r\n");
+ }
+ PRINTF("Log %d: %s\r\n", counter, log);
+ counter++;
+ }
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/freertos_queue_v3_10.xml b/boards/dart_mx8mm/rtos_examples/freertos_queue/freertos_queue_v3_10.xml
new file mode 100644
index 000000000..dcfb8bdb6
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/freertos_queue_v3_10.xml
@@ -0,0 +1,141 @@
+
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diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/fsl_iomuxc.h b/boards/dart_mx8mm/rtos_examples/freertos_queue/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/pin_mux.c b/boards/dart_mx8mm/rtos_examples/freertos_queue/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/pin_mux.h b/boards/dart_mx8mm/rtos_examples/freertos_queue/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_queue/readme.txt b/boards/dart_mx8mm/rtos_examples/freertos_queue/readme.txt
new file mode 100644
index 000000000..ec8955df9
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_queue/readme.txt
@@ -0,0 +1,64 @@
+Overview
+========
+
+This document explains the freertos_queue example. This example introduce simple logging mechanism
+based on message passing.
+
+Example could be devided in two parts. First part is logger. It contain three tasks:
+log_add().....Add new message into the log. Call xQueueSend function to pass new message into
+ message queue.
+log_init()....Initialize logger (create logging task and message queue log_queue).
+log_task()....Task responsible for printing of log output.
+
+Second part is application of this simple logging mechanism. Each of two tasks write_task_1 and
+write_task_2 print 5 messages into log.
+
+
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+After the board is flashed the Tera Term will show debug console output.
+
+Example output:
+Log 0: Task1 Message 0
+Log 1: Task2 Message 0
+Log 2: Task1 Message 1
+Log 3: Task2 Message 1
+Log 4: Task1 Message 2
+Log 5: Task2 Message 2
+Log 6: Task1 Message 3
+Log 7: Task2 Message 3
+Log 8: Task1 Message 4
+Log 9: Task2 Message 4
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/FreeRTOSConfig.h b/boards/dart_mx8mm/rtos_examples/freertos_sem/FreeRTOSConfig.h
new file mode 100644
index 000000000..63d6c6c8f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configCPU_CLOCK_HZ (SystemCoreClock)
+#define configTICK_RATE_HZ ((TickType_t)200)
+#define configMAX_PRIORITIES 5
+#define configMINIMAL_STACK_SIZE ((unsigned short)90)
+#define configMAX_TASK_NAME_LEN 20
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c) */
+#define configFRTOS_MEMORY_SCHEME 4
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024))
+#define configAPPLICATION_ALLOCATED_HEAP 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS 1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
+
+/* Define to trap errors during development. */
+#define configASSERT(x) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 0
+#define INCLUDE_xTaskGetHandle 0
+#define INCLUDE_xTaskResumeFromISR 1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+ /* Clock manager provides in this variable system core clock frequency */
+ #include
+ extern uint32_t SystemCoreClock;
+#endif
+
+/* Redefine: Mutex is needed for SRTM communication */
+#undef configUSE_MUTEXES
+#define configUSE_MUTEXES 1
+
+#ifndef configTOTAL_HEAP_SIZE
+#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024))
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4 /* 15 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/CMakeLists.txt b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..9faf4b02b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/CMakeLists.txt
@@ -0,0 +1,117 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(freertos_sem)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME freertos_sem.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../freertos_sem.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../FreeRTOSConfig.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/rtos/freertos/freertos-kernel
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/serial_manager
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_clock_MIMX8MM6)
+
+include(middleware_freertos-kernel_heap_4_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(utility_debug_console_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_serial_manager_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(component_serial_manager_uart_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(utility_assert_MIMX8MM6)
+
+include(middleware_freertos-kernel_MIMX8MM6)
+
+include(middleware_freertos-kernel_extension_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_sem.bin)
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_all.bat b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_all.bat
new file mode 100644
index 000000000..02d62fd34
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_all.sh b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_all.sh
new file mode 100755
index 000000000..702783475
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..c84d78542
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..5aa41a2df
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..3fd6f4a78
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c9e344144
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_debug.bat
new file mode 100644
index 000000000..15123387e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_debug.sh
new file mode 100755
index 000000000..42803761b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..acb3c2d91
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..1ce9d36e7
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_flash_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..83f20fc3c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_flash_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..f3694ad2e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_release.bat
new file mode 100644
index 000000000..a88e3d668
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_release.sh
new file mode 100755
index 000000000..47cfb057c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/clean.bat b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/clean.sh b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/config.cmake b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/config.cmake
new file mode 100755
index 000000000..031ad598a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/config.cmake
@@ -0,0 +1,3 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_component_serial_manager_uart_MIMX8MM6 true)
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/flags.cmake b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/flags.cmake
new file mode 100755
index 000000000..4a87a56cb
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/armgcc/flags.cmake
@@ -0,0 +1,521 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/board.c b/boards/dart_mx8mm/rtos_examples/freertos_sem/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/board.h b/boards/dart_mx8mm/rtos_examples/freertos_sem/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/clock_config.c b/boards/dart_mx8mm/rtos_examples/freertos_sem/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/clock_config.h b/boards/dart_mx8mm/rtos_examples/freertos_sem/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/empty_rsc_table.c b/boards/dart_mx8mm/rtos_examples/freertos_sem/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/freertos_sem.c b/boards/dart_mx8mm/rtos_examples/freertos_sem/freertos_sem.c
new file mode 100644
index 000000000..c687f776d
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/freertos_sem.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+#include "semphr.h"
+
+/* Freescale includes. */
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define TASK_PRIO (configMAX_PRIORITIES - 1)
+#define CONSUMER_LINE_SIZE 3
+SemaphoreHandle_t xSemaphore_producer;
+SemaphoreHandle_t xSemaphore_consumer;
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static void producer_task(void *pvParameters);
+static void consumer_task(void *pvParameters);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ /* Init board hardware. */
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+ if (xTaskCreate(producer_task, "PRODUCER_TASK", configMINIMAL_STACK_SIZE + 128, NULL, TASK_PRIO, NULL) != pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+ /* Start scheduling. */
+ vTaskStartScheduler();
+ for (;;)
+ ;
+}
+
+/*!
+ * @brief Task producer_task.
+ */
+static void producer_task(void *pvParameters)
+{
+ uint32_t i;
+
+ PRINTF("Producer_task created.\r\n");
+ xSemaphore_producer = xSemaphoreCreateBinary();
+ if (xSemaphore_producer == NULL)
+ {
+ PRINTF("xSemaphore_producer creation failed.\r\n");
+ vTaskSuspend(NULL);
+ }
+
+ xSemaphore_consumer = xSemaphoreCreateBinary();
+ if (xSemaphore_consumer == NULL)
+ {
+ PRINTF("xSemaphore_consumer creation failed.\r\n");
+ vTaskSuspend(NULL);
+ }
+
+ for (i = 0; i < CONSUMER_LINE_SIZE; i++)
+ {
+ if (xTaskCreate(consumer_task, "CONSUMER_TASK", configMINIMAL_STACK_SIZE + 128, (void *)i, TASK_PRIO, NULL) !=
+ pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ vTaskSuspend(NULL);
+ }
+ else
+ {
+ PRINTF("Consumer_task %d created.\r\n", i);
+ }
+ }
+
+ while (1)
+ {
+ /* Producer is ready to provide item. */
+ xSemaphoreGive(xSemaphore_consumer);
+ /* Producer is waiting when consumer will be ready to accept item. */
+ if (xSemaphoreTake(xSemaphore_producer, portMAX_DELAY) == pdTRUE)
+ {
+ PRINTF("Producer released item.\r\n");
+ }
+ else
+ {
+ PRINTF("Producer is waiting for customer.\r\n");
+ }
+ }
+}
+
+/*!
+ * @brief Task consumer_task.
+ */
+static void consumer_task(void *pvParameters)
+{
+ PRINTF("Consumer number: %d\r\n", pvParameters);
+ while (1)
+ {
+ /* Consumer is ready to accept. */
+ xSemaphoreGive(xSemaphore_producer);
+ /* Consumer is waiting when producer will be ready to produce item. */
+ if (xSemaphoreTake(xSemaphore_consumer, portMAX_DELAY) == pdTRUE)
+ {
+ PRINTF("Consumer %d accepted item.\r\n", pvParameters);
+ }
+ else
+ {
+ PRINTF("Consumer %d is waiting for producer.\r\n", pvParameters);
+ }
+ }
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/freertos_sem_v3_10.xml b/boards/dart_mx8mm/rtos_examples/freertos_sem/freertos_sem_v3_10.xml
new file mode 100644
index 000000000..4eab3da5e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/freertos_sem_v3_10.xml
@@ -0,0 +1,141 @@
+
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diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/fsl_iomuxc.h b/boards/dart_mx8mm/rtos_examples/freertos_sem/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/pin_mux.c b/boards/dart_mx8mm/rtos_examples/freertos_sem/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/pin_mux.h b/boards/dart_mx8mm/rtos_examples/freertos_sem/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_sem/readme.txt b/boards/dart_mx8mm/rtos_examples/freertos_sem/readme.txt
new file mode 100644
index 000000000..a15b311b4
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_sem/readme.txt
@@ -0,0 +1,65 @@
+Overview
+========
+This document explains the freertos_sem example, what to expect when running it and a brief
+introduction to the API. The freertos_sem example code shows how semaphores works. Two different
+tasks are synchronized in bilateral rendezvous model.
+
+The example uses four tasks. One producer_task and three consumer_tasks. The producer_task starts by
+creating of two semaphores (xSemaphore_producer and xSemaphore_consumer). These semaphores control
+access to virtual item. The synchronization is based on bilateral rendezvous pattern. Both of
+consumer and producer must be prepared to enable transaction.
+
+
+
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+After the board is flashed the Tera Term will show debug console output.
+
+Example output:
+Producer_task created.
+Consumer_task 0 created.
+Consumer_task 1 created.
+Consumer_task 2 created.
+Consumer number: 0
+Consumer 0 accepted item.
+Consumer number: 1
+Consumer number: 2
+Producer released item.
+Consumer 0 accepted item.
+Producer released item.
+Consumer 1 accepted item.
+Producer released item.
+Consumer 2 accepted item.
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/FreeRTOSConfig.h b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/FreeRTOSConfig.h
new file mode 100644
index 000000000..f74e29406
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configCPU_CLOCK_HZ (SystemCoreClock)
+#define configTICK_RATE_HZ ((TickType_t)200)
+#define configMAX_PRIORITIES 5
+#define configMINIMAL_STACK_SIZE ((unsigned short)90)
+#define configMAX_TASK_NAME_LEN 20
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c) */
+#define configFRTOS_MEMORY_SCHEME 4
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024))
+#define configAPPLICATION_ALLOCATED_HEAP 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS 1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
+
+/* Define to trap errors during development. */
+#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 0
+#define INCLUDE_xTaskGetHandle 0
+#define INCLUDE_xTaskResumeFromISR 1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+ /* Clock manager provides in this variable system core clock frequency */
+ #include
+ extern uint32_t SystemCoreClock;
+#endif
+
+/* Redefine: Mutex is needed for SRTM communication */
+#undef configUSE_MUTEXES
+#define configUSE_MUTEXES 1
+
+#ifndef configTOTAL_HEAP_SIZE
+#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024))
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4 /* 15 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/CMakeLists.txt b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..f5d6eb31e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/CMakeLists.txt
@@ -0,0 +1,117 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(freertos_swtimer)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME freertos_swtimer.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../freertos_swtimer.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../FreeRTOSConfig.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/rtos/freertos/freertos-kernel
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/serial_manager
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_clock_MIMX8MM6)
+
+include(middleware_freertos-kernel_heap_4_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(utility_debug_console_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_serial_manager_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(component_serial_manager_uart_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(utility_assert_MIMX8MM6)
+
+include(middleware_freertos-kernel_MIMX8MM6)
+
+include(middleware_freertos-kernel_extension_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_swtimer.bin)
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_all.bat b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_all.bat
new file mode 100644
index 000000000..02d62fd34
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_all.sh b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_all.sh
new file mode 100755
index 000000000..702783475
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..c84d78542
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..5aa41a2df
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..3fd6f4a78
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c9e344144
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_debug.bat
new file mode 100644
index 000000000..15123387e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_debug.sh
new file mode 100755
index 000000000..42803761b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..acb3c2d91
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..1ce9d36e7
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_flash_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..83f20fc3c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_flash_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..f3694ad2e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_release.bat
new file mode 100644
index 000000000..a88e3d668
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_release.sh
new file mode 100755
index 000000000..47cfb057c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/clean.bat b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/clean.sh b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/config.cmake b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/config.cmake
new file mode 100755
index 000000000..031ad598a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/config.cmake
@@ -0,0 +1,3 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_component_serial_manager_uart_MIMX8MM6 true)
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/flags.cmake b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/flags.cmake
new file mode 100755
index 000000000..4a87a56cb
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/armgcc/flags.cmake
@@ -0,0 +1,521 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/board.c b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/board.h b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/clock_config.c b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/clock_config.h b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/empty_rsc_table.c b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/freertos_swtimer.c b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/freertos_swtimer.c
new file mode 100644
index 000000000..82f3785ff
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/freertos_swtimer.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Standard includes. */
+#include
+#include
+#include
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+
+/* Freescale includes. */
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* The software timer period. */
+#define SW_TIMER_PERIOD_MS (1000 / portTICK_PERIOD_MS)
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/* The callback function. */
+static void SwTimerCallback(TimerHandle_t xTimer);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+ TimerHandle_t SwTimerHandle = NULL;
+
+ /* Init board hardware. */
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+ SystemCoreClockUpdate();
+ /* Create the software timer. */
+ SwTimerHandle = xTimerCreate("SwTimer", /* Text name. */
+ SW_TIMER_PERIOD_MS, /* Timer period. */
+ pdTRUE, /* Enable auto reload. */
+ 0, /* ID is not used. */
+ SwTimerCallback); /* The callback function. */
+ /* Start timer. */
+ xTimerStart(SwTimerHandle, 0);
+ /* Start scheduling. */
+ vTaskStartScheduler();
+ for (;;)
+ ;
+}
+
+/*!
+ * @brief Software timer callback.
+ */
+static void SwTimerCallback(TimerHandle_t xTimer)
+{
+ PRINTF("Tick.\r\n");
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/freertos_swtimer_v3_10.xml b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/freertos_swtimer_v3_10.xml
new file mode 100644
index 000000000..28fe32f5a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/freertos_swtimer_v3_10.xml
@@ -0,0 +1,141 @@
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diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/fsl_iomuxc.h b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/pin_mux.c b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/pin_mux.h b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_swtimer/readme.txt b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/readme.txt
new file mode 100644
index 000000000..9dffab56f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_swtimer/readme.txt
@@ -0,0 +1,51 @@
+Overview
+========
+This document explains the freertos_swtimer example. It shows usage of software timer and its
+callback.
+
+The example application creates one software timer SwTimer. The timer’s callback SwTimerCallback is
+periodically executed and text “Tick.” is printed to terminal.
+
+
+
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+After the board is flashed the Tera Term will show output message.
+
+Example output:
+Tick.
+Tick.
+Tick.
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/FreeRTOSConfig.h b/boards/dart_mx8mm/rtos_examples/freertos_tickless/FreeRTOSConfig.h
new file mode 100644
index 000000000..4aa048231
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/FreeRTOSConfig.h
@@ -0,0 +1,167 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE 2
+#define configCPU_CLOCK_HZ (SystemCoreClock)
+#define configTICK_RATE_HZ ((TickType_t)1000)
+#define configMAX_PRIORITIES 5
+#define configMINIMAL_STACK_SIZE ((unsigned short)90)
+#define configMAX_TASK_NAME_LEN 20
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 1
+
+/* Used memory allocation (heap_x.c) */
+#define configFRTOS_MEMORY_SCHEME 4
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024))
+#define configAPPLICATION_ALLOCATED_HEAP 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS 1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
+
+/* Define to trap errors during development. */
+#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 0
+#define INCLUDE_xTaskGetHandle 0
+#define INCLUDE_xTaskResumeFromISR 1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+ /* Clock manager provides in this variable system core clock frequency */
+ #include
+ extern uint32_t SystemCoreClock;
+#endif
+
+/* Redefine: Mutex is needed for SRTM communication */
+#undef configUSE_MUTEXES
+#define configUSE_MUTEXES 1
+
+#ifndef configTOTAL_HEAP_SIZE
+#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024))
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4 /* 15 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/CMakeLists.txt b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..8d6117264
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/CMakeLists.txt
@@ -0,0 +1,124 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(freertos_tickless)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME freertos_tickless.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../low_power_tickless/fsl_tickless_gpt.c"
+"${ProjDirPath}/../low_power_tickless/fsl_tickless_gpt.h"
+"${ProjDirPath}/../freertos_tickless.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../FreeRTOSConfig.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+ ${ProjDirPath}/../low_power_tickless
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/rtos/freertos/freertos-kernel
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/serial_manager
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_gpt_MIMX8MM6)
+
+include(driver_igpio_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(middleware_freertos-kernel_heap_4_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(utility_debug_console_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_serial_manager_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(component_serial_manager_uart_MIMX8MM6)
+
+include(driver_iuart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(utility_assert_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(middleware_freertos-kernel_MIMX8MM6)
+
+include(middleware_freertos-kernel_extension_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_tickless.bin)
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_all.bat b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_all.bat
new file mode 100644
index 000000000..02d62fd34
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_all.sh b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_all.sh
new file mode 100755
index 000000000..702783475
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..c84d78542
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..5aa41a2df
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..3fd6f4a78
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c9e344144
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_debug.bat
new file mode 100644
index 000000000..15123387e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_debug.sh
new file mode 100755
index 000000000..42803761b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..acb3c2d91
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..1ce9d36e7
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_flash_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..83f20fc3c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_flash_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..f3694ad2e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_release.bat
new file mode 100644
index 000000000..a88e3d668
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_release.sh
new file mode 100755
index 000000000..47cfb057c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/clean.bat b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/clean.sh b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/config.cmake b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/config.cmake
new file mode 100755
index 000000000..031ad598a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/config.cmake
@@ -0,0 +1,3 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_component_serial_manager_uart_MIMX8MM6 true)
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/flags.cmake b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/flags.cmake
new file mode 100755
index 000000000..10f67acf6
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/armgcc/flags.cmake
@@ -0,0 +1,539 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -DIMX8MSCALE_SERIES \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -DIMX8MSCALE_SERIES \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -DIMX8MSCALE_SERIES \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -DIMX8MSCALE_SERIES \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -DIMX8MSCALE_SERIES \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -DIMX8MSCALE_SERIES \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DIMX8MSCALE_SERIES \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DIMX8MSCALE_SERIES \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DIMX8MSCALE_SERIES \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DIMX8MSCALE_SERIES \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DIMX8MSCALE_SERIES \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DIMX8MSCALE_SERIES \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DIMX8MSCALE_SERIES \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DIMX8MSCALE_SERIES \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DIMX8MSCALE_SERIES \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DIMX8MSCALE_SERIES \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DIMX8MSCALE_SERIES \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DIMX8MSCALE_SERIES \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/board.c b/boards/dart_mx8mm/rtos_examples/freertos_tickless/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/board.h b/boards/dart_mx8mm/rtos_examples/freertos_tickless/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/clock_config.c b/boards/dart_mx8mm/rtos_examples/freertos_tickless/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/clock_config.h b/boards/dart_mx8mm/rtos_examples/freertos_tickless/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/empty_rsc_table.c b/boards/dart_mx8mm/rtos_examples/freertos_tickless/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/freertos_tickless.c b/boards/dart_mx8mm/rtos_examples/freertos_tickless/freertos_tickless.c
new file mode 100644
index 000000000..32505ae8e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/freertos_tickless.c
@@ -0,0 +1,246 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+#include "semphr.h"
+
+#include "fsl_debug_console.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+#if defined(FSL_FEATURE_SOC_PORT_COUNT) && (FSL_FEATURE_SOC_PORT_COUNT > 0)
+#include "fsl_port.h"
+#endif
+#include "fsl_uart.h"
+#if configUSE_TICKLESS_IDLE == 2
+#include "fsl_gpt.h"
+#endif
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Task priorities. */
+/* clang-format off */
+#define tickless_task_PRIORITY ( configMAX_PRIORITIES - 2 )
+#define SW_task_PRIORITY ( configMAX_PRIORITIES - 1 )
+#define TIME_DELAY_SLEEP 5000
+
+/* Interrupt priorities. */
+#define SW_NVIC_PRIO 2
+
+/* clang-format on */
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+extern void vPortGptIsr(void);
+IRQn_Type vPortGetGptIrqn(void);
+GPT_Type *vPortGetGptBase(void);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static void Tickless_task(void *pvParameters);
+static void SW_task(void *pvParameters);
+
+SemaphoreHandle_t xSWSemaphore = NULL;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if configUSE_TICKLESS_IDLE == 2
+/*!
+ * @brief Interrupt service fuction of GPT timer.
+ *
+ * This function to call low power timer ISR
+ */
+void GPT1_IRQHandler(void)
+{
+ vPortGptIsr();
+}
+
+/*!
+ * @brief Fuction of GPT timer.
+ *
+ * This function to return GPT timer base address
+ */
+
+GPT_Type *vPortGetGptBase(void)
+{
+ return GPT1;
+}
+
+/*!
+ * @brief Fuction of GPT timer.
+ *
+ * This function to return GPT timer interrupt number
+ */
+
+IRQn_Type vPortGetGptIrqn(void)
+{
+ return GPT1_IRQn;
+}
+#endif
+/*!
+ * @brief Main function
+ */
+int main(void)
+{
+/* Define the init structure for the input switch pin */
+#ifdef BOARD_SW_NAME
+ gpio_pin_config_t sw_config = {
+ kGPIO_DigitalInput,
+ 0,
+#if defined(FSL_FEATURE_SOC_IGPIO_COUNT) && (FSL_FEATURE_SOC_IGPIO_COUNT > 0)
+ kGPIO_IntRisingEdge,
+#endif
+ };
+#endif
+#if configUSE_TICKLESS_IDLE == 2
+ gpt_config_t gptConfig;
+#endif
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+#if configUSE_TICKLESS_IDLE == 2
+ CLOCK_SetRootMux(kCLOCK_RootGpt1, kCLOCK_GptRootmuxSysPll1Div20); /* Set GPT1 source to SysPLL1 Div20 40MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootGpt1, 1U, 5U); /* Set root clock to 40MHZ / 5 = 8MHZ */
+ GPT_GetDefaultConfig(&gptConfig);
+
+ /* Initialize GPT module */
+ GPT_Init(GPT1, &gptConfig);
+
+ /* Divide GPT clock source frequency by 1 inside GPT module */
+ GPT_SetClockDivider(GPT1, 1);
+
+ /* Enable GPT Output Compare1 interrupt */
+ GPT_EnableInterrupts(GPT1, kGPT_OutputCompare1InterruptEnable);
+
+ /* Enable at the Interrupt */
+ EnableIRQ(GPT1_IRQn);
+#endif
+
+ PRINTF("Press any key to start the example\r\n");
+ GETCHAR();
+
+ /* Print a note to terminal. */
+ PRINTF("Tickless Demo example\r\n");
+#ifdef BOARD_SW_NAME
+ PRINTF("Press or turn on %s to wake up the CPU\r\n", BOARD_SW_NAME);
+
+/* Init input switch GPIO. */
+#if defined(FSL_FEATURE_SOC_PORT_COUNT) && (FSL_FEATURE_SOC_PORT_COUNT > 0)
+#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+ GPIO_SetPinInterruptConfig(BOARD_SW_GPIO, BOARD_SW_GPIO_PIN, kGPIO_InterruptFallingEdge);
+#else
+ PORT_SetPinInterruptConfig(BOARD_SW_PORT, BOARD_SW_GPIO_PIN, kPORT_InterruptFallingEdge);
+#endif
+#endif
+
+#if defined(__CORTEX_M)
+ NVIC_SetPriority(BOARD_SW_IRQ, SW_NVIC_PRIO);
+#else
+ GIC_SetPriority(BOARD_SW_IRQ, BOARD_SW_GIC_PRIO);
+#endif
+
+ EnableIRQ(BOARD_SW_IRQ);
+ GPIO_PinInit(BOARD_SW_GPIO, BOARD_SW_GPIO_PIN, &sw_config);
+#if defined(FSL_FEATURE_SOC_IGPIO_COUNT) && (FSL_FEATURE_SOC_IGPIO_COUNT > 0)
+ GPIO_PortClearInterruptFlags(BOARD_SW_GPIO, 1U << BOARD_SW_GPIO_PIN);
+ GPIO_PortEnableInterrupts(BOARD_SW_GPIO, 1U << BOARD_SW_GPIO_PIN);
+#endif
+#endif
+
+ /*Create tickless task*/
+ if (xTaskCreate(Tickless_task, "Tickless_task", configMINIMAL_STACK_SIZE + 100, NULL, tickless_task_PRIORITY,
+ NULL) != pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+ if (xTaskCreate(SW_task, "Switch_task", configMINIMAL_STACK_SIZE + 100, NULL, SW_task_PRIORITY, NULL) != pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+ PRINTF("\r\nTick count :\r\n");
+ /*Task Scheduler*/
+ vTaskStartScheduler();
+ for (;;)
+ ;
+}
+
+/* Tickless Task */
+static void Tickless_task(void *pvParameters)
+{
+ for (;;)
+ {
+ PRINTF("%d\r\n", xTaskGetTickCount());
+ vTaskDelay(TIME_DELAY_SLEEP);
+ }
+}
+
+/* Switch Task */
+static void SW_task(void *pvParameters)
+{
+ xSWSemaphore = xSemaphoreCreateBinary();
+ for (;;)
+ {
+ if (xSemaphoreTake(xSWSemaphore, portMAX_DELAY) == pdTRUE)
+ {
+ PRINTF("CPU woken up by external interrupt\r\n");
+ }
+ }
+}
+/*!
+ * @brief Interrupt service fuction of switch.
+ *
+ * This function to wake up CPU
+ */
+#ifdef BOARD_SW_NAME
+void BOARD_SW_IRQ_HANDLER(void)
+{
+ portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
+
+/* Clear external interrupt flag. */
+#ifdef BOARD_SW_DELAY
+ volatile uint32_t i = 0;
+ for (i = 0; i < 10000000; ++i)
+ {
+ __NOP(); /* delay */
+ }
+#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+ /* Clear external interrupt flag. */
+ GPIO_GpioClearInterruptFlags(BOARD_SW_GPIO, 1U << BOARD_SW_GPIO_PIN);
+#else
+ /* Clear external interrupt flag. */
+ GPIO_PortClearInterruptFlags(BOARD_SW_GPIO, 1U << BOARD_SW_GPIO_PIN);
+#endif
+ if (1 == GPIO_PinRead(BOARD_SW_GPIO, BOARD_SW_GPIO_PIN))
+ {
+ xSemaphoreGiveFromISR(xSWSemaphore, &xHigherPriorityTaskWoken);
+ }
+#else
+#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+ /* Clear external interrupt flag. */
+ GPIO_GpioClearInterruptFlags(BOARD_SW_GPIO, 1U << BOARD_SW_GPIO_PIN);
+#else
+ /* Clear external interrupt flag. */
+ GPIO_PortClearInterruptFlags(BOARD_SW_GPIO, 1U << BOARD_SW_GPIO_PIN);
+#endif
+ xSemaphoreGiveFromISR(xSWSemaphore, &xHigherPriorityTaskWoken);
+#endif
+}
+#endif
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/freertos_tickless_v3_10.xml b/boards/dart_mx8mm/rtos_examples/freertos_tickless/freertos_tickless_v3_10.xml
new file mode 100644
index 000000000..69f8ca36b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/freertos_tickless_v3_10.xml
@@ -0,0 +1,151 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/fsl_iomuxc.h b/boards/dart_mx8mm/rtos_examples/freertos_tickless/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/low_power_tickless/fsl_tickless_gpt.c b/boards/dart_mx8mm/rtos_examples/freertos_tickless/low_power_tickless/fsl_tickless_gpt.c
new file mode 100644
index 000000000..2b779d5bc
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/low_power_tickless/fsl_tickless_gpt.c
@@ -0,0 +1,219 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/* Compiler includes. */
+#if defined(__ICCARM__)
+#include
+#endif
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if configUSE_TICKLESS_IDLE == 2
+#include "fsl_gpt.h"
+#else
+#include "fsl_device_registers.h"
+#endif
+
+#include "fsl_tickless_gpt.h"
+
+extern uint32_t SystemCoreClock; /* in Kinetis SDK, this contains the system core clock speed */
+
+/*
+ * GPT timer base address and interrupt number
+ */
+
+#if configUSE_TICKLESS_IDLE == 2
+extern GPT_Type *vPortGetGptBase(void);
+extern IRQn_Type vPortGetGptIrqn(void);
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if configUSE_TICKLESS_IDLE == 2
+static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if configUSE_TICKLESS_IDLE == 2
+static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The number of GPT increments that make up one tick period.
+ */
+#if configUSE_TICKLESS_IDLE == 2
+static uint32_t ulLPTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The flag of GPT is occurs or not.
+ */
+#if configUSE_TICKLESS_IDLE == 2
+static volatile bool ulLPTimerInterruptFired = false;
+#endif /* configUSE_TICKLESS_IDLE */
+
+#if configUSE_TICKLESS_IDLE == 2
+void vPortGptIsr(void)
+{
+ ulLPTimerInterruptFired = true;
+ /* Clear interrupt flag.*/
+ GPT_ClearStatusFlags(GPT1, kGPT_OutputCompare1Flag);
+}
+
+void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
+{
+ uint32_t ulReloadValue, ulCompleteTickPeriods;
+ TickType_t xModifiableIdleTime;
+ GPT_Type *pxGptBase;
+
+ pxGptBase = vPortGetGptBase();
+ if (pxGptBase == 0)
+ return;
+ /* Make sure the SysTick reload value does not overflow the counter. */
+ if (xExpectedIdleTime > xMaximumPossibleSuppressedTicks)
+ {
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ }
+ if (xExpectedIdleTime == 0)
+ return;
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ tick periods. -1 is used because this code will execute part way
+ through one of the tick periods. */
+ ulReloadValue = (ulLPTimerCountsForOneTick * (xExpectedIdleTime - 1UL));
+
+ /* Stop the GPT and systick momentarily. The time the GPT and systick is stopped for
+ is accounted for as best it can be, but using the tickless mode will
+ inevitably result in some tiny drift of the time maintained by the
+ kernel with respect to calendar time. */
+ GPT_StopTimer(pxGptBase);
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()
+ method as that will mask interrupts that should exit sleep mode. */
+ __disable_irq();
+ __DSB();
+ __ISB();
+
+ /* If a context switch is pending or a task is waiting for the scheduler
+ to be unsuspended then abandon the low power entry. */
+ if (eTaskConfirmSleepModeStatus() == eAbortSleep)
+ {
+ /* Restart from whatever is left in the count register to complete
+ this tick period. */
+ SysTick->LOAD = SysTick->VAL;
+
+ /* Restart SysTick. */
+ SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+
+ /* Reset the reload register to the value required for normal tick
+ periods. */
+ SysTick->LOAD = ulTimerCountsForOneTick - 1UL;
+
+ /* Re-enable interrupts - see comments above __disable_irq()
+ call above. */
+ __enable_irq();
+ }
+ else
+ {
+ /* Set the new reload value. */
+ GPT_SetOutputCompareValue(pxGptBase, kGPT_OutputCompare_Channel1, ulReloadValue);
+
+ /* Enable GPT. */
+ GPT_StartTimer(pxGptBase);
+
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ set its parameter to 0 to indicate that its implementation contains
+ its own wait for interrupt or wait for event instruction, and so wfi
+ should not be executed again. However, the original expected idle
+ time variable must remain unmodified, so a copy is taken. */
+ xModifiableIdleTime = xExpectedIdleTime;
+ configPRE_SLEEP_PROCESSING(xModifiableIdleTime);
+ if (xModifiableIdleTime > 0)
+ {
+ __DSB();
+ __WFI();
+ __ISB();
+ }
+ configPOST_SLEEP_PROCESSING(xExpectedIdleTime);
+
+ ulLPTimerInterruptFired = false;
+
+ /* Re-enable interrupts - see comments above __disable_irq()
+ call above. */
+ __enable_irq();
+ __NOP();
+ if (ulLPTimerInterruptFired)
+ {
+ /* The tick interrupt handler will already have pended the tick
+ processing in the kernel. As the pending tick will be
+ processed as soon as this function exits, the tick value
+ maintained by the tick is stepped forward by one less than the
+ time spent waiting. */
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ ulLPTimerInterruptFired = false;
+ }
+ else
+ {
+ /* Something other than the tick interrupt ended the sleep.
+ Work out how long the sleep lasted rounded to complete tick
+ periods (not the ulReload value which accounted for part
+ ticks). */
+ ulCompleteTickPeriods = (GPT_GetCurrentTimerCount(pxGptBase)) / ulLPTimerCountsForOneTick;
+ }
+
+ /* Stop GPT when CPU waked up then set SysTick->LOAD back to its standard
+ value. The critical section is used to ensure the tick interrupt
+ can only execute once in the case that the reload register is near
+ zero. */
+ GPT_StopTimer(pxGptBase);
+ portENTER_CRITICAL();
+ {
+ SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+ vTaskStepTick(ulCompleteTickPeriods);
+ SysTick->LOAD = ulTimerCountsForOneTick - 1UL;
+ }
+ portEXIT_CRITICAL();
+ }
+}
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+void vPortSetupTimerInterrupt(void)
+{
+ /* Calculate the constants required to configure the tick interrupt. */
+ ulTimerCountsForOneTick = (configCPU_CLOCK_HZ / configTICK_RATE_HZ);
+ ulLPTimerCountsForOneTick = (configGPT_CLOCK_HZ / configTICK_RATE_HZ);
+ if (ulLPTimerCountsForOneTick != 0)
+ {
+ xMaximumPossibleSuppressedTicks = portMAX_32_BIT_NUMBER / ulLPTimerCountsForOneTick;
+ }
+ else
+ {
+ /* ulLPTimerCountsForOneTick is zero, not allowed state */
+ while (1)
+ ;
+ }
+ NVIC_EnableIRQ(vPortGetGptIrqn());
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ SysTick->LOAD = (configCPU_CLOCK_HZ / configTICK_RATE_HZ) - 1UL;
+ SysTick->VAL = 0UL;
+ SysTick->CTRL = (SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
+}
+#endif /* #if configUSE_TICKLESS_IDLE */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/low_power_tickless/fsl_tickless_gpt.h b/boards/dart_mx8mm/rtos_examples/freertos_tickless/low_power_tickless/fsl_tickless_gpt.h
new file mode 100644
index 000000000..25ddc7e83
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/low_power_tickless/fsl_tickless_gpt.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef FSL_TICKLESS_GPT_H
+#define FSL_TICKLESS_GPT_H
+
+#include "fsl_clock.h"
+
+#if defined(MIMXRT1176_cm7_SERIES) || defined(MIMXRT1176_cm4_SERIES) || defined(MIMXRT1166_cm7_SERIES) || \
+ defined(MIMXRT1166_cm4_SERIES)
+#define configGPT_CLOCK_HZ (CLOCK_GetFreq(kCLOCK_OscRc48MDiv2))
+#elif defined(IMX8MSCALE_SERIES)
+#define configGPT_CLOCK_HZ \
+ (CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootGpt1)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootGpt1)) / 20)
+#else
+#define configGPT_CLOCK_HZ (CLOCK_GetFreq(kCLOCK_IpgClk) / 2)
+#endif
+/* The GPT is a 32-bit counter. */
+#define portMAX_32_BIT_NUMBER (0xffffffffUL)
+
+#endif /* FSL_TICKLESS_GPT_H */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/pin_mux.c b/boards/dart_mx8mm/rtos_examples/freertos_tickless/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/pin_mux.h b/boards/dart_mx8mm/rtos_examples/freertos_tickless/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_tickless/readme.txt b/boards/dart_mx8mm/rtos_examples/freertos_tickless/readme.txt
new file mode 100644
index 000000000..cef312d07
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_tickless/readme.txt
@@ -0,0 +1,70 @@
+Overview
+========
+This document explains the freertos_tickless example. It shows how the CPU enters the sleep mode and then
+it is woken up either by expired time delay using low power timer module or by external interrupt caused by a
+user defined button.
+
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+After flashing the example to the board the console will start printing the number of tick count periodically
+when the CPU is running.
+To wake up the CPU by external interrupt, press the button, that is specified at the beginning of the
+example (SWx where x is the number of the user defined button). When the button is pressed, the console prints
+out the "CPU woken up by external interrupt" message.
+
+Example output:
+
+Press any key to start the example
+Tickless Demo example
+Press or turn on SWx to wake up the CPU
+
+Tick count :
+0
+5000
+10000
+CPU woken up by external interrupt
+15000
+20000
+25000
+
+Explanation of the example
+The example application prints the actual tick count number every time after the specified
+delay. When the vTaskDelay() is called, the CPU enters the sleep mode for that defined period
+of time.
+
+While the CPU is in sleep mode and the user defined button is pressed, the CPU is woken up
+by the external interrupt and continues to sleep after the interrupt is handled.
+The period of time delay is not changed after the external interrupt occurs.
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/FreeRTOSConfig.h b/boards/dart_mx8mm/rtos_examples/freertos_uart/FreeRTOSConfig.h
new file mode 100644
index 000000000..f74e29406
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_TICKLESS_IDLE 0
+#define configCPU_CLOCK_HZ (SystemCoreClock)
+#define configTICK_RATE_HZ ((TickType_t)200)
+#define configMAX_PRIORITIES 5
+#define configMINIMAL_STACK_SIZE ((unsigned short)90)
+#define configMAX_TASK_NAME_LEN 20
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
+
+/* Used memory allocation (heap_x.c) */
+#define configFRTOS_MEMORY_SCHEME 4
+/* Tasks.c additions (e.g. Thread Aware Debug capability) */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024))
+#define configAPPLICATION_ALLOCATED_HEAP 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS 1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)
+
+/* Define to trap errors during development. */
+#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 0
+#define INCLUDE_xTaskGetHandle 0
+#define INCLUDE_xTaskResumeFromISR 1
+
+
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+ /* Clock manager provides in this variable system core clock frequency */
+ #include
+ extern uint32_t SystemCoreClock;
+#endif
+
+/* Redefine: Mutex is needed for SRTM communication */
+#undef configUSE_MUTEXES
+#define configUSE_MUTEXES 1
+
+#ifndef configTOTAL_HEAP_SIZE
+#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024))
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4 /* 15 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/CMakeLists.txt b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/CMakeLists.txt
new file mode 100644
index 000000000..b657b0cc2
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/CMakeLists.txt
@@ -0,0 +1,119 @@
+# CROSS COMPILER SETTING
+SET(CMAKE_SYSTEM_NAME Generic)
+CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
+
+# THE VERSION NUMBER
+SET (Tutorial_VERSION_MAJOR 1)
+SET (Tutorial_VERSION_MINOR 0)
+
+# ENABLE ASM
+ENABLE_LANGUAGE(ASM)
+
+SET(CMAKE_STATIC_LIBRARY_PREFIX)
+SET(CMAKE_STATIC_LIBRARY_SUFFIX)
+
+SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX)
+SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX)
+
+# CURRENT DIRECTORY
+SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR})
+
+SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE})
+
+
+project(freertos_uart)
+
+set(MCUX_BUILD_TYPES debug release ddr_debug ddr_release flash_debug flash_release)
+
+set(MCUX_SDK_PROJECT_NAME freertos_uart.elf)
+
+if (NOT DEFINED SdkRootDirPath)
+ SET(SdkRootDirPath ${ProjDirPath}/../../../../..)
+endif()
+
+include(${ProjDirPath}/flags.cmake)
+
+include(${ProjDirPath}/config.cmake)
+
+add_executable(${MCUX_SDK_PROJECT_NAME}
+"${ProjDirPath}/../freertos_uart.c"
+"${ProjDirPath}/../pin_mux.c"
+"${ProjDirPath}/../pin_mux.h"
+"${ProjDirPath}/../FreeRTOSConfig.h"
+"${ProjDirPath}/../board.c"
+"${ProjDirPath}/../board.h"
+"${ProjDirPath}/../clock_config.c"
+"${ProjDirPath}/../clock_config.h"
+"${ProjDirPath}/../fsl_iomuxc.h"
+"${ProjDirPath}/../empty_rsc_table.c"
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${ProjDirPath}/..
+)
+
+set(CMAKE_MODULE_PATH
+ ${SdkRootDirPath}/devices/MIMX8MM6/drivers
+ ${SdkRootDirPath}/rtos/freertos/freertos-kernel
+ ${SdkRootDirPath}/devices/MIMX8MM6
+ ${SdkRootDirPath}/devices/MIMX8MM6/utilities
+ ${SdkRootDirPath}/components/uart
+ ${SdkRootDirPath}/components/serial_manager
+ ${SdkRootDirPath}/components/lists
+ ${SdkRootDirPath}/CMSIS/Core/Include
+)
+
+# include modules
+include(driver_iuart_MIMX8MM6)
+
+include(driver_iuart_freertos_MIMX8MM6)
+
+include(driver_clock_MIMX8MM6)
+
+include(middleware_freertos-kernel_heap_4_MIMX8MM6)
+
+include(driver_common_MIMX8MM6)
+
+include(driver_rdc_MIMX8MM6)
+
+include(device_MIMX8MM6_CMSIS_MIMX8MM6)
+
+include(utility_debug_console_MIMX8MM6)
+
+include(component_iuart_adapter_MIMX8MM6)
+
+include(component_serial_manager_MIMX8MM6)
+
+include(component_lists_MIMX8MM6)
+
+include(component_serial_manager_uart_MIMX8MM6)
+
+include(device_MIMX8MM6_startup_MIMX8MM6)
+
+include(utility_assert_MIMX8MM6)
+
+include(middleware_freertos-kernel_MIMX8MM6)
+
+include(middleware_freertos-kernel_extension_MIMX8MM6)
+
+include(utilities_misc_utilities_MIMX8MM6)
+
+include(CMSIS_Include_core_cm_MIMX8MM6)
+
+include(device_MIMX8MM6_system_MIMX8MM6)
+
+
+IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES)
+ SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys")
+ENDIF()
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group)
+
+target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES})
+
+TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group)
+
+ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY}
+-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/freertos_uart.bin)
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
new file mode 100644
index 000000000..fc022798e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/MIMX8MM6xxxxx_cm4_ddr_ram.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x7E000000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x7E000240, LENGTH = 0x001FFDC0
+ m_data (RW) : ORIGIN = 0x7E200000, LENGTH = 0x00200000
+ m_data2 (RW) : ORIGIN = 0x7E400000, LENGTH = 0x00C00000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = LENGTH(m_interrupts) + LENGTH(m_text) + LENGTH(m_data);
+
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/MIMX8MM6xxxxx_cm4_flash.ld b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
new file mode 100644
index 000000000..b95a50b5f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/MIMX8MM6xxxxx_cm4_flash.ld
@@ -0,0 +1,228 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000A00
+ m_text (RX) : ORIGIN = 0x08000A00, LENGTH = 0x000FF600
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+ m_tcml (RW) : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/MIMX8MM6xxxxx_cm4_ram.ld b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
new file mode 100644
index 000000000..38e6dcdd3
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/MIMX8MM6xxxxx_cm4_ram.ld
@@ -0,0 +1,227 @@
+/*
+** ###################################################################
+** Processors: MIMX8MM6CVTKZ
+** MIMX8MM6DVTLZ
+**
+** Compiler: GNU C Compiler
+** Reference manual: MX8MMRM, Rev. 0, 02/2019
+** Version: rev. 4.0, 2019-02-18
+** Build: b200330
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x1FFE0240, LENGTH = 0x0001FDC0
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_data2 (RW) : ORIGIN = 0x7E000000, LENGTH = 0x01000000
+}
+
+/* Define output sections */
+SECTIONS
+{
+/* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .resource_table :
+ {
+ . = ALIGN(8);
+ KEEP(*(.resource_table)) /* Resource table */
+ . = ALIGN(8);
+ } > m_text
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __CACHE_REGION_START = ORIGIN(m_interrupts);
+ __CACHE_REGION_SIZE = 0;
+ __NDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for ncache data initialization */
+
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data2
+
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data2
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_all.bat b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_all.bat
new file mode 100644
index 000000000..02d62fd34
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_all.bat
@@ -0,0 +1,43 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j
+
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j
+
+IF "%1" == "" ( pause )
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_all.sh b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_all.sh
new file mode 100755
index 000000000..702783475
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_all.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j
+
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j
+
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_ddr_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_ddr_debug.bat
new file mode 100644
index 000000000..c84d78542
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_ddr_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_ddr_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_ddr_debug.sh
new file mode 100755
index 000000000..5aa41a2df
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_ddr_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_ddr_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_ddr_release.bat
new file mode 100644
index 000000000..3fd6f4a78
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_ddr_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_ddr_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_ddr_release.sh
new file mode 100755
index 000000000..c9e344144
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_ddr_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=ddr_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_debug.bat
new file mode 100644
index 000000000..15123387e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_debug.sh
new file mode 100755
index 000000000..42803761b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_flash_debug.bat b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_flash_debug.bat
new file mode 100644
index 000000000..acb3c2d91
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_flash_debug.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_flash_debug.sh b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_flash_debug.sh
new file mode 100755
index 000000000..1ce9d36e7
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_flash_debug.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_debug .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_flash_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_flash_release.bat
new file mode 100644
index 000000000..83f20fc3c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_flash_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_flash_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_flash_release.sh
new file mode 100755
index 000000000..f3694ad2e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_flash_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=flash_release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_release.bat b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_release.bat
new file mode 100644
index 000000000..a88e3d668
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_release.bat
@@ -0,0 +1,6 @@
+if exist CMakeFiles (RD /s /Q CMakeFiles)
+if exist Makefile (DEL /s /Q /F Makefile)
+if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake)
+if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt)
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release .
+mingw32-make -j 2> build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_release.sh b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_release.sh
new file mode 100755
index 000000000..47cfb057c
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/build_release.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi
+if [ -f "Makefile" ];then rm -f Makefile; fi
+if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi
+if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi
+cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release .
+make -j 2>&1 | tee build_log.txt
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/clean.bat b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/clean.bat
new file mode 100644
index 000000000..d7474444f
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/clean.bat
@@ -0,0 +1,3 @@
+RD /s /Q debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt
+pause
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/clean.sh b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/clean.sh
new file mode 100755
index 000000000..072d433ef
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/clean.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+rm -rf debug release ddr_debug ddr_release flash_debug flash_release CMakeFiles
+rm -rf Makefile cmake_install.cmake CMakeCache.txt
+rm -rf output.map
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/config.cmake b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/config.cmake
new file mode 100755
index 000000000..031ad598a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/config.cmake
@@ -0,0 +1,3 @@
+# config to select component, the format is CONFIG_USE_${component}
+set(CONFIG_USE_component_serial_manager_uart_MIMX8MM6 true)
+set(CONFIG_USE_driver_iuart_MIMX8MM6 true)
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/flags.cmake b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/flags.cmake
new file mode 100755
index 000000000..4a87a56cb
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/armgcc/flags.cmake
@@ -0,0 +1,521 @@
+IF(NOT DEFINED FPU)
+ SET(FPU "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
+ENDIF()
+
+IF(NOT DEFINED SPECS)
+ SET(SPECS "--specs=nano.specs --specs=nosys.specs")
+ENDIF()
+
+IF(NOT DEFINED DEBUG_CONSOLE_CONFIG)
+ SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1")
+ENDIF()
+
+SET(CMAKE_ASM_FLAGS_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DEBUG} \
+ -DDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_RELEASE " \
+ ${CMAKE_ASM_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_DEBUG " \
+ ${CMAKE_ASM_FLAGS_DDR_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_DDR_RELEASE " \
+ ${CMAKE_ASM_FLAGS_DDR_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_ASM_FLAGS_FLASH_DEBUG} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_ASM_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_ASM_FLAGS_FLASH_RELEASE} \
+ -D__STARTUP_CLEAR_BSS \
+ -D__STARTUP_INITIALIZE_NONCACHEDATA \
+ -mcpu=cortex-m4 \
+ -mthumb \
+ ${FPU} \
+")
+SET(CMAKE_C_FLAGS_DEBUG " \
+ ${CMAKE_C_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_RELEASE " \
+ ${CMAKE_C_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_DEBUG " \
+ ${CMAKE_C_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_DDR_RELEASE " \
+ ${CMAKE_C_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_C_FLAGS_FLASH_DEBUG} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_C_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_C_FLAGS_FLASH_RELEASE} \
+ -DFLASH_TARGET \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DSDK_OS_FREE_RTOS \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -std=gnu99 \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DEBUG} \
+ -DDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_RELEASE " \
+ ${CMAKE_CXX_FLAGS_RELEASE} \
+ -DNDEBUG \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_DEBUG " \
+ ${CMAKE_CXX_FLAGS_DDR_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_DDR_RELEASE " \
+ ${CMAKE_CXX_FLAGS_DDR_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_CXX_FLAGS_FLASH_DEBUG} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -g \
+ -O0 \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_CXX_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_CXX_FLAGS_FLASH_RELEASE} \
+ -DCPU_MIMX8MM6DVTLZ \
+ -DCPU_MIMX8MM6DVTLZ_cm4 \
+ -DSERIAL_PORT_TYPE_UART=1 \
+ -DMCUXPRESSO_SDK \
+ -Os \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wno-address-of-packed-member \
+ -mthumb \
+ -MMD \
+ -MP \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mapcs \
+ -fno-rtti \
+ -fno-exceptions \
+ ${FPU} \
+ ${DEBUG_CONSOLE_CONFIG} \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_DDR_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_ddr_ram.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_DEBUG} \
+ -g \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
+SET(CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE " \
+ ${CMAKE_EXE_LINKER_FLAGS_FLASH_RELEASE} \
+ -mcpu=cortex-m4 \
+ -Wall \
+ -Wl,--print-memory-usage \
+ -fno-common \
+ -ffunction-sections \
+ -fdata-sections \
+ -ffreestanding \
+ -fno-builtin \
+ -mthumb \
+ -mapcs \
+ -Xlinker \
+ --gc-sections \
+ -Xlinker \
+ -static \
+ -Xlinker \
+ -z \
+ -Xlinker \
+ muldefs \
+ -Xlinker \
+ -Map=output.map \
+ ${FPU} \
+ ${SPECS} \
+ -T${ProjDirPath}/MIMX8MM6xxxxx_cm4_flash.ld -static \
+")
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/board.c b/boards/dart_mx8mm/rtos_examples/freertos_uart/board.c
new file mode 100644
index 000000000..832015dad
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/board.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_rdc.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+#include "board.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ CLOCK_EnableClock(kCLOCK_Uart3);
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+/* Initialize MPU, configure non-cacheable memory */
+void BOARD_InitMemory(void)
+{
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Load$$LR$$LR_cache_region$$Base[];
+ extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
+ uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
+ uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
+#else
+ extern uint32_t __CACHE_REGION_START[];
+ extern uint32_t __CACHE_REGION_SIZE[];
+ uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
+ uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
+#endif
+ uint32_t i = 0;
+ /* Make sure outstanding transfers are done. */
+ __DMB();
+ /* Disable the MPU. */
+ MPU->CTRL = 0;
+
+ /*
+ * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
+ * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
+ * change the default memory attributes.
+ * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
+ * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
+ * 0x27FFFFFF) to use the
+ * background memory attributes.
+ */
+
+ /* Select Region 0 and set its base address to the M4 code bus start address. */
+ MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
+
+ /* Region 0 setting:
+ * 1) Disable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Non-shared device;
+ * 4) Region Not Shared;
+ * 5) Sub-Region 0,1 Disabled;
+ * 6) MPU Protection Region size = 512M byte;
+ * 7) Enable Region 0.
+ */
+ MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
+ (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /*
+ * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
+ * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
+ * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
+ * region size,
+ * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
+ * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
+ * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
+ * needs.
+ */
+
+ /* Select Region 1 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
+
+ /* Region 1 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 1.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ /* Select Region 2 and set its base address to the DDR start address. */
+ MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
+
+ /* Region 2 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Shared Device;
+ * 4) MPU Protection Region size = 1024M byte;
+ * 5) Enable Region 2.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+
+ while ((size >> i) > 0x1U)
+ {
+ i++;
+ }
+
+ /* If run on DDR, configure text and data section to be cacheable */
+ if (i != 0)
+ {
+ /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
+ assert((size & (size - 1)) == 0);
+ assert(!(cacheStart % size));
+ assert(size == (uint32_t)(1 << i));
+ assert(i >= 5);
+
+ /* Select Region 3 and set its base address to the cache able region start address. */
+ MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
+
+ /* Region 3 setting:
+ * 1) Enable Instruction Access;
+ * 2) AP = 011b, full access;
+ * 3) Outer and inner Cacheable, write and read allocate;
+ * 4) Region Not Shared;
+ * 5) All Sub-Region Enabled;
+ * 6) MPU Protection Region size get from linker file;
+ * 7) Enable Region 3.
+ */
+ MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
+ (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
+ }
+
+ /* Enable Privileged default memory map and the MPU. */
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
+ /* Memory barriers to ensure subsequence data & instruction
+ * transfers using updated MPU settings.
+ */
+ __DSB();
+ __ISB();
+
+ /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
+ * The AXI2AHB bridge is used for masters that access the TCM through system bus.
+ * Please refer to errata for more information */
+ /* Only configure the GPV5 if the M core access type is secure. */
+ if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
+ {
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
+ *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
+ }
+}
+
+void BOARD_RdcInit(void)
+{
+ /* Move M4 core to specific RDC domain 1 */
+ rdc_domain_assignment_t assignment = {0};
+ uint8_t domainId = 0U;
+
+ domainId = RDC_GetCurrentMasterDomainId(RDC);
+ /* Only configure the RDC if RDC peripheral write access allowed. */
+ if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
+ {
+ assignment.domainId = BOARD_DOMAIN_ID;
+ RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
+ }
+
+ /*
+ * The M4 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
+ * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
+ * domain 0.
+ */
+ CLOCK_EnableClock(kCLOCK_Iomux);
+
+ CLOCK_EnableClock(kCLOCK_Ipmux1);
+ CLOCK_EnableClock(kCLOCK_Ipmux2);
+ CLOCK_EnableClock(kCLOCK_Ipmux3);
+ CLOCK_EnableClock(kCLOCK_Ipmux4);
+
+#if defined(FLASH_TARGET)
+ CLOCK_EnableClock(kCLOCK_Qspi);
+#endif
+
+ CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
+ CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/board.h b/boards/dart_mx8mm/rtos_examples/freertos_uart/board.h
new file mode 100644
index 000000000..03378143a
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/board.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+#include "clock_config.h"
+#include "fsl_clock.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "DART-MX8M-MINI"
+#define MANUFACTURER_NAME "Variscite"
+#define BOARD_DOMAIN_ID (1)
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BAUDRATE 115200u
+#define BOARD_DEBUG_UART_BASEADDR UART3_BASE
+#define BOARD_DEBUG_UART_INSTANCE 3U
+#define BOARD_DEBUG_UART_CLK_FREQ \
+ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \
+ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10
+#define BOARD_UART_IRQ UART3_IRQn
+#define BOARD_UART_IRQ_HANDLER UART3_IRQHandler
+
+#define GPV5_BASE_ADDR (0x32500000)
+#define FORCE_INCR_OFFSET (0x4044)
+#define FORCE_INCR_BIT_MASK (0x2)
+#define CSU_SA_ADDR (0x303E0218) /* Secure access register base address. */
+#define CSU_SA_NSN_M_BIT_MASK (0x4U) /* Non-secure access policy indicator bit. */
+
+#define BOARD_GPC_BASEADDR GPC
+#define BOARD_MU_IRQ_NUM MU_M4_IRQn
+
+/* Shared memory base for RPMsg communication. */
+#define VDEV0_VRING_BASE (0x40000000U)
+#define RESOURCE_TABLE_OFFSET (0xFF000)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+void BOARD_InitMemory(void);
+void BOARD_RdcInit(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/clock_config.c b/boards/dart_mx8mm/rtos_examples/freertos_uart/clock_config.c
new file mode 100644
index 000000000..d4e5826a6
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/clock_config.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
+/* AUDIO PLL1 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 262U,
+ .dsm = 9437U,
+ .preDiv = 2U,
+ .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
+};
+
+/* AUDIO PLL2 configuration */
+const ccm_analog_frac_pll_config_t g_audioPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 361U,
+ .dsm = 17511U,
+ .preDiv = 3U,
+ .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
+};
+
+/* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
+/* SYSTEM PLL1 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll1Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 400U,
+ .preDiv = 3U,
+ .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
+};
+
+/* SYSTEM PLL2 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll2Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250U,
+ .preDiv = 3U,
+ .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
+};
+
+/* SYSTEM PLL3 configuration */
+const ccm_analog_integer_pll_config_t g_sysPll3Config = {
+ .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
+ .mainDiv = 250,
+ .preDiv = 2U,
+ .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 750MHZ */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* * The following steps just show how to configure the PLL clock sources using the clock driver on M4 core side .
+ * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
+ * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
+ * Therefore, there is no need to configure the system PLL again on M4 side, otherwise it would have a risk to make
+ * the SOC hang.
+ */
+
+ /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxOsc24M);
+ /* switch AXI M4 root to 24M first in order to configure the SYSTEM PLL2. */
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxOsc24M);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxOsc24M);
+
+ // CLOCK_InitSysPll1(&g_sysPll1Config); /* init SYSTEM PLL1 run at 800MHZ */
+ // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
+ // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 750MHZ */
+
+ CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
+ CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);
+ CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1); /* switch cortex-m4 to SYSTEM PLL1 */
+
+ // CLOCK_SetRootMux(kCLOCK_RootNoc, kCLOCK_NocRootmuxSysPll1); /* change back to SYSTEM PLL1*/
+
+ CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);
+ CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */
+
+ CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock to 800MHZ/ 2= 400MHZ */
+ CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
+
+ // CLOCK_SetRootDivider(kCLOCK_RootAxi, 1U, 2);
+ // CLOCK_SetRootMux(kCLOCK_RootAxi, kCLOCK_AxiRootmuxSysPll1); /* switch AXI to SYSTEM PLL1 800MHZ */
+
+ CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
+ CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
+
+ CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
+ /* The purpose to enable the following modules clock is to make sure the M4 core could work normally when A53 core
+ * enters the low power status.*/
+ CLOCK_EnableClock(kCLOCK_Sim_display);
+ CLOCK_EnableClock(kCLOCK_Sim_m);
+ CLOCK_EnableClock(kCLOCK_Sim_main);
+ CLOCK_EnableClock(kCLOCK_Sim_s);
+ CLOCK_EnableClock(kCLOCK_Sim_wakeup);
+ CLOCK_EnableClock(kCLOCK_Debug);
+ CLOCK_EnableClock(kCLOCK_Dram);
+ CLOCK_EnableClock(kCLOCK_Sec_Debug);
+
+ /* Update core clock */
+ SystemCoreClockUpdate();
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/clock_config.h b/boards/dart_mx8mm/rtos_examples/freertos_uart/clock_config.h
new file mode 100644
index 000000000..0e84c1e0e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/clock_config.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/empty_rsc_table.c b/boards/dart_mx8mm/rtos_examples/freertos_uart/empty_rsc_table.c
new file mode 100644
index 000000000..37bb8dc0b
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/empty_rsc_table.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2015 Xilinx, Inc. All rights reserved.
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file provides the default empty resource table data structure
+ * placed in the .resource_table section of the ELF file. This facilitates
+ * basic support of remoteproc firmware loading from the Linux kernel.
+ *
+ * The .resource_table section has to be present in the ELF file in order
+ * for the remoteproc ELF parser to accept the binary.
+ *
+ * See other multicore examples such as those utilizing rpmsg for a examples
+ * of non-empty resource table.
+ *
+ */
+
+#include
+
+/* Place resource table in special ELF section */
+#if defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".resource_table")))
+#elif defined(__ICCARM__)
+#pragma location = ".resource_table"
+#else
+#error Compiler not supported!
+#endif
+
+const uint32_t resource_table[] = {
+ /* Version */
+ 1,
+
+ /* Number of table entries - resource table empty */
+ 0,
+
+ /* reserved fields */
+ 0, 0};
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/freertos_uart.c b/boards/dart_mx8mm/rtos_examples/freertos_uart/freertos_uart.c
new file mode 100644
index 000000000..638062e30
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/freertos_uart.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* FreeRTOS kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+/* Freescale includes. */
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "board.h"
+
+#include "fsl_uart_freertos.h"
+#include "fsl_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DEMO_UART UART3
+#define DEMO_UART_CLK_FREQ BOARD_DEBUG_UART_CLK_FREQ
+#define DEMO_IRQn UART3_IRQn
+/* Task priorities. */
+#define uart_task_PRIORITY (configMAX_PRIORITIES - 1)
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static void uart_task(void *pvParameters);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+char *to_send = "FreeRTOS UART driver example!\r\n";
+char *send_ring_overrun = "\r\nRing buffer overrun!\r\n";
+char *send_hardware_overrun = "\r\nHardware buffer overrun!\r\n";
+uint8_t background_buffer[32];
+uint8_t recv_buffer[4];
+
+uart_rtos_handle_t handle;
+struct _uart_handle t_handle;
+
+uart_rtos_config_t uart_config = {
+ .baudrate = 115200,
+ .parity = kUART_ParityDisabled,
+ .stopbits = kUART_OneStopBit,
+ .buffer = background_buffer,
+ .buffer_size = sizeof(background_buffer),
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Application entry point.
+ */
+int main(void)
+{
+ /* Init board hardware. */
+ /* Board specific RDC settings */
+ BOARD_RdcInit();
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ BOARD_InitDebugConsole();
+ BOARD_InitMemory();
+ NVIC_SetPriority(DEMO_IRQn, 3);
+ if (xTaskCreate(uart_task, "Uart_task", configMINIMAL_STACK_SIZE + 100, NULL, uart_task_PRIORITY, NULL) != pdPASS)
+ {
+ PRINTF("Task creation failed!.\r\n");
+ while (1)
+ ;
+ }
+ vTaskStartScheduler();
+ for (;;)
+ ;
+}
+
+/*!
+ * @brief Task responsible for loopback.
+ */
+static void uart_task(void *pvParameters)
+{
+ int error;
+ size_t n = 0;
+
+ uart_config.srcclk = DEMO_UART_CLK_FREQ;
+ uart_config.base = DEMO_UART;
+
+ if (kStatus_Success != UART_RTOS_Init(&handle, &t_handle, &uart_config))
+ {
+ vTaskSuspend(NULL);
+ }
+
+ /* Send introduction message. */
+ if (kStatus_Success != UART_RTOS_Send(&handle, (uint8_t *)to_send, strlen(to_send)))
+ {
+ vTaskSuspend(NULL);
+ }
+
+ /* Receive user input and send it back to terminal. */
+ do
+ {
+ error = UART_RTOS_Receive(&handle, recv_buffer, sizeof(recv_buffer), &n);
+ if (error == kStatus_UART_RxHardwareOverrun)
+ {
+ /* Notify about hardware buffer overrun */
+ if (kStatus_Success !=
+ UART_RTOS_Send(&handle, (uint8_t *)send_hardware_overrun, strlen(send_hardware_overrun)))
+ {
+ vTaskSuspend(NULL);
+ }
+ }
+ if (error == kStatus_UART_RxRingBufferOverrun)
+ {
+ /* Notify about ring buffer overrun */
+ if (kStatus_Success != UART_RTOS_Send(&handle, (uint8_t *)send_ring_overrun, strlen(send_ring_overrun)))
+ {
+ vTaskSuspend(NULL);
+ }
+ }
+ if (n > 0)
+ {
+ /* send back the received data */
+ UART_RTOS_Send(&handle, recv_buffer, n);
+ }
+ } while (kStatus_Success == error);
+
+ UART_RTOS_Deinit(&handle);
+ vTaskSuspend(NULL);
+}
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/freertos_uart_v3_10.xml b/boards/dart_mx8mm/rtos_examples/freertos_uart/freertos_uart_v3_10.xml
new file mode 100644
index 000000000..2ce2d29c7
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/freertos_uart_v3_10.xml
@@ -0,0 +1,142 @@
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diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/fsl_iomuxc.h b/boards/dart_mx8mm/rtos_examples/freertos_uart/fsl_iomuxc.h
new file mode 100644
index 000000000..df1c90b3e
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/fsl_iomuxc.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOMUXC_H_
+#define _FSL_IOMUXC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup iomuxc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOMUXC driver version 2.0.2. */
+#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @name Pin function ID
+ * The pin function ID is a tuple of \
+ *
+ * @{
+ */
+#define IOMUXC_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
+#define IOMUXC_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
+#define IOMUXC_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
+#define IOMUXC_POR_B 0x30330020, 0x0, 0x00000000, 0x0, 0x30330288
+#define IOMUXC_RTC_RESET_B 0x30330024, 0x0, 0x00000000, 0x0, 0x3033028C
+#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
+#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
+#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
+#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
+#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
+#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_M4_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
+#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
+#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
+#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
+#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
+#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
+#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
+#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
+#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
+#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
+#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x30330060, 0x1, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330544, 0x2, 0x303302C8
+#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
+#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x30330064, 0x1, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x30330548, 0x2, 0x303302CC
+#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
+#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
+#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
+#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
+#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
+#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
+#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
+#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
+#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
+#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
+#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
+#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
+#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
+#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
+#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
+#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
+#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
+#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
+#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
+#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
+#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
+#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
+#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
+#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
+#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
+#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
+#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
+#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
+#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
+#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
+#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
+#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
+#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
+#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
+#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
+#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
+#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
+#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
+#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
+#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
+#define IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
+#define IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
+#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
+#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
+#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
+#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330544, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
+#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x30330548, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
+#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
+#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
+#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
+#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
+#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
+#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
+#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
+#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
+#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
+#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x30330140, 0x1, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
+#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x30330144, 0x1, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
+#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x30330148, 0x1, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
+#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x3033014C, 0x1, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x3033014C, 0x2, 0x303304CC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
+#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x30330150, 0x1, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x30330150, 0x2, 0x303304CC, 0x1, 0x303303B8
+#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
+#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x30330154, 0x1, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x30330154, 0x2, 0x303304CC, 0x2, 0x303303BC
+#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
+#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
+#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x3033052C, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x30330158, 0x1, 0x303304C8, 0x0, 0x303303C0
+#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
+#define IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x3033015C, 0x0, 0x303304C4, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x3033015C, 0x1, 0x303304E4, 0x1, 0x303303C4
+#define IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x3033015C, 0x4, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXFS_GPIO4_IO00 0x3033015C, 0x5, 0x00000000, 0x0, 0x303303C4
+#define IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x30330160, 0x0, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x30330160, 0x1, 0x303304D0, 0x1, 0x303303C8
+#define IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x30330160, 0x4, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXC_GPIO4_IO01 0x30330160, 0x5, 0x00000000, 0x0, 0x303303C8
+#define IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x30330164, 0x0, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x30330164, 0x1, 0x303304D4, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SAI1_TX_DATA1 0x30330164, 0x2, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_PDM_BIT_STREAM0 0x30330164, 0x3, 0x30330534, 0x1, 0x303303CC
+#define IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x30330164, 0x4, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_GPIO4_IO02 0x30330164, 0x5, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0 0x30330164, 0x6, 0x00000000, 0x0, 0x303303CC
+#define IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x30330168, 0x0, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x30330168, 0x1, 0x303304D8, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_PDM_BIT_STREAM1 0x30330168, 0x3, 0x30330538, 0x1, 0x303303D0
+#define IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x30330168, 0x4, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_GPIO4_IO03 0x30330168, 0x5, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1 0x30330168, 0x6, 0x00000000, 0x0, 0x303303D0
+#define IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x3033016C, 0x0, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x3033016C, 0x1, 0x303304DC, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_PDM_BIT_STREAM2 0x3033016C, 0x3, 0x3033053C, 0x1, 0x303303D4
+#define IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x3033016C, 0x4, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_GPIO4_IO04 0x3033016C, 0x5, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2 0x3033016C, 0x6, 0x00000000, 0x0, 0x303303D4
+#define IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x30330170, 0x0, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x30330170, 0x1, 0x303304E0, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_PDM_BIT_STREAM3 0x30330170, 0x3, 0x30330540, 0x1, 0x303303D8
+#define IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x30330170, 0x4, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_GPIO4_IO05 0x30330170, 0x5, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3 0x30330170, 0x6, 0x00000000, 0x0, 0x303303D8
+#define IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x30330174, 0x0, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x30330174, 0x1, 0x3033051C, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x30330174, 0x2, 0x30330510, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x30330174, 0x4, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_GPIO4_IO06 0x30330174, 0x5, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4 0x30330174, 0x6, 0x00000000, 0x0, 0x303303DC
+#define IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x30330178, 0x0, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x30330178, 0x1, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x30330178, 0x2, 0x30330514, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x30330178, 0x3, 0x303304C4, 0x1, 0x303303E0
+#define IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x30330178, 0x4, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_GPIO4_IO07 0x30330178, 0x5, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5 0x30330178, 0x6, 0x00000000, 0x0, 0x303303E0
+#define IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x3033017C, 0x0, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x3033017C, 0x1, 0x30330520, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x3033017C, 0x2, 0x30330518, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x3033017C, 0x4, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_GPIO4_IO08 0x3033017C, 0x5, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6 0x3033017C, 0x6, 0x00000000, 0x0, 0x303303E4
+#define IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x30330180, 0x0, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI6_MCLK 0x30330180, 0x1, 0x30330530, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x30330180, 0x2, 0x303304CC, 0x4, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x30330180, 0x3, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x30330180, 0x4, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_GPIO4_IO09 0x30330180, 0x5, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7 0x30330180, 0x6, 0x00000000, 0x0, 0x303303E8
+#define IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x30330184, 0x0, 0x303304CC, 0x3, 0x303303EC
+#define IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x30330184, 0x1, 0x303304EC, 0x1, 0x303303EC
+#define IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x30330184, 0x4, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXFS_GPIO4_IO10 0x30330184, 0x5, 0x00000000, 0x0, 0x303303EC
+#define IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x30330188, 0x0, 0x303304C8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x30330188, 0x1, 0x303304E8, 0x1, 0x303303F0
+#define IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x30330188, 0x4, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXC_GPIO4_IO11 0x30330188, 0x5, 0x00000000, 0x0, 0x303303F0
+#define IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x3033018C, 0x0, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x3033018C, 0x1, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x3033018C, 0x4, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_GPIO4_IO12 0x3033018C, 0x5, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8 0x3033018C, 0x6, 0x00000000, 0x0, 0x303303F4
+#define IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x30330190, 0x0, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x30330190, 0x1, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x30330190, 0x4, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_GPIO4_IO13 0x30330190, 0x5, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9 0x30330190, 0x6, 0x00000000, 0x0, 0x303303F8
+#define IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x30330194, 0x0, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x30330194, 0x1, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x30330194, 0x4, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_GPIO4_IO14 0x30330194, 0x5, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10 0x30330194, 0x6, 0x00000000, 0x0, 0x303303FC
+#define IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x30330198, 0x0, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x30330198, 0x1, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x30330198, 0x4, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_GPIO4_IO15 0x30330198, 0x5, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11 0x30330198, 0x6, 0x00000000, 0x0, 0x30330400
+#define IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x3033019C, 0x0, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x3033019C, 0x1, 0x30330510, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x3033019C, 0x2, 0x3033051C, 0x1, 0x30330404
+#define IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x3033019C, 0x4, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_GPIO4_IO16 0x3033019C, 0x5, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12 0x3033019C, 0x6, 0x00000000, 0x0, 0x30330404
+#define IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x303301A0, 0x0, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x303301A0, 0x1, 0x30330514, 0x1, 0x30330408
+#define IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x303301A0, 0x2, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x303301A0, 0x4, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_GPIO4_IO17 0x303301A0, 0x5, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13 0x303301A0, 0x6, 0x00000000, 0x0, 0x30330408
+#define IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x303301A4, 0x0, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x303301A4, 0x1, 0x30330518, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x303301A4, 0x2, 0x30330520, 0x1, 0x3033040C
+#define IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x303301A4, 0x4, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_GPIO4_IO18 0x303301A4, 0x5, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14 0x303301A4, 0x6, 0x00000000, 0x0, 0x3033040C
+#define IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x303301A8, 0x0, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SAI6_MCLK 0x303301A8, 0x1, 0x30330530, 0x1, 0x30330410
+#define IOMUXC_SAI1_TXD7_PDM_CLK 0x303301A8, 0x3, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x303301A8, 0x4, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_GPIO4_IO19 0x303301A8, 0x5, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15 0x303301A8, 0x6, 0x00000000, 0x0, 0x30330410
+#define IOMUXC_SAI1_MCLK_SAI1_MCLK 0x303301AC, 0x0, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI5_MCLK 0x303301AC, 0x1, 0x3033052C, 0x1, 0x30330414
+#define IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x303301AC, 0x2, 0x303304C8, 0x2, 0x30330414
+#define IOMUXC_SAI1_MCLK_PDM_CLK 0x303301AC, 0x3, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI1_MCLK_GPIO4_IO20 0x303301AC, 0x5, 0x00000000, 0x0, 0x30330414
+#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0X0, 0x30330418
+#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
+#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
+#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
+#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0X0, 0x3033041C
+#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
+#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
+#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0X0, 0x30330420
+#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
+#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0X0, 0x30330424
+#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
+#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
+#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
+#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
+#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x3033052C, 0x2, 0x30330430
+#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
+#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
+#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
+#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0X0, 0x30330438
+#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
+#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
+#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
+#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0X0, 0x3033043C
+#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
+#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
+#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0X0, 0x30330440
+#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
+#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x2, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0X0, 0x30330444
+#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
+#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
+#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x2, 0x30330448
+#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
+#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x3033052C, 0x3, 0x3033044C
+#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
+#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
+#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
+#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
+#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0X0, 0x3033045C
+#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
+#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0X0, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
+#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
+#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0X0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
+#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
+#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0X0, 0x30330468
+#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
+#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0X0, 0x3033046C
+#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
+#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0X0, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
+#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
+#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0X0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
+#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
+#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0X0, 0x30330478
+#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
+#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
+#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
+#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
+#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330544, 0x1, 0x30330484
+#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
+#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x30330548, 0x1, 0x30330488
+#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
+#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
+#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
+#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x3033022C, 0x2, 0x30330524, 0x0, 0x30330494
+#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
+#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
+#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0X0, 0x3033049C
+#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
+#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0X0, 0x303304A0
+#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
+#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
+#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0X0, 0x303304A4
+#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
+#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0X0, 0x303304A8
+#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
+#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
+#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
+#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0X0, 0x303304AC
+#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
+#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
+#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0X0, 0x303304B0
+#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
+#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
+#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0X0, 0x303304B4
+#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
+#define IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x3033024C, 0x2, 0x30330524, 0x1, 0x303304B4
+#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
+#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
+#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0X0, 0x303304B8
+#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
+#define IOMUXC_TEST_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
+#define IOMUXC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
+#define IOMUXC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x3033025C
+#define IOMUXC_JTAG_MOD 0x00000000, 0x0, 0x00000000, 0x0, 0x30330260
+#define IOMUXC_JTAG_TRST_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
+#define IOMUXC_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
+#define IOMUXC_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
+#define IOMUXC_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
+#define IOMUXC_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
+#define IOMUXC_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x30330278
+
+/*@}*/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*__cplusplus */
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the IOMUXC pin mux mode.
+ * @note The first five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set the I2C4_SDA as the pwm1_OUT:
+ * @code
+ * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
+ * @endcode
+ *
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param inputOnfield The pad->module input inversion_
+ */
+static inline void IOMUXC_SetPinMux(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t inputOnfield)
+{
+ *((volatile uint32_t *)muxRegister) =
+ IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
+
+ if (inputRegister)
+ {
+ *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
+ }
+}
+/*!
+ * @brief Sets the IOMUXC pin configuration.
+ * @note The previous five parameters can be filled with the pin function ID macros.
+ *
+ * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
+ * @code
+ * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
+ * @endcode
+ *
+ * @param muxRegister The pin mux register_
+ * @param muxMode The pin mux mode_
+ * @param inputRegister The select input register_
+ * @param inputDaisy The input daisy_
+ * @param configRegister The config register_
+ * @param configValue The pin config value_
+ */
+static inline void IOMUXC_SetPinConfig(uintptr_t muxRegister,
+ uint32_t muxMode,
+ uintptr_t inputRegister,
+ uint32_t inputDaisy,
+ uintptr_t configRegister,
+ uint32_t configValue)
+{
+ if (configRegister)
+ {
+ *((volatile uint32_t *)configRegister) = configValue;
+ }
+}
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*__cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_IOMUXC_H_ */
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/pin_mux.c b/boards/dart_mx8mm/rtos_examples/freertos_uart/pin_mux.c
new file mode 100644
index 000000000..77f742171
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/pin_mux.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: MIMX8MM6xxxLZ
+package_id: MIMX8MM6DVTLZ
+mcu_data: ksdk2_0
+processor_version: 9.0.0
+
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: cm4}
+- pin_list:
+ - {pin_num: E18, peripheral: UART3, signal: uart_rx, pin_signal: UART3_RXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ - {pin_num: D18, peripheral: UART3, signal: uart_tx, pin_signal: UART3_TXD, PE: Disabled, PUE: Disabled, DSE: X6_0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[m4] */
+ IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+ IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
+ IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
+ IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/pin_mux.h b/boards/dart_mx8mm/rtos_examples/freertos_uart/pin_mux.h
new file mode 100644
index 000000000..bdb5a9350
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/pin_mux.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#include "board.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[m4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/dart_mx8mm/rtos_examples/freertos_uart/readme.txt b/boards/dart_mx8mm/rtos_examples/freertos_uart/readme.txt
new file mode 100644
index 000000000..476bc4768
--- /dev/null
+++ b/boards/dart_mx8mm/rtos_examples/freertos_uart/readme.txt
@@ -0,0 +1,43 @@
+Overview
+========
+The UART example for FreeRTOS demonstrates the possibility to use the UART driver in the RTOS.
+The example uses single instance of UART IP and writes string into, then reads back chars.
+After every 4B received, these are sent back on UART.
+
+Toolchain supported
+===================
+- IAR embedded Workbench 9.32.1
+- GCC ARM Embedded 10.3.1
+
+Hardware requirements
+=====================
+- Micro USB cable
+- DART-MX8M-MINI SoM
+- J-Link Debug Probe
+- proper power supply
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+
+
+
+Prepare the Demo
+================
+1. Connect proper power supply and J-Link Debug Probe to the board, switch SW8(DT8CustomBoard)/SW7(SymphonyBoard) to power on the board
+2. Connect a proper cable between the host PC and the J12 header(DT8CustomBoard)/J18 header(SymphonyBoard), (pins UART3 TX, RX and GND) on the target board.
+3. Open a serial terminal with the following settings:
+ - 115200 baud rate
+ - 8 data bits
+ - No parity
+ - One stop bit
+ - No flow control
+4. Download the program to the target board.
+5. Launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+You will see the welcome string printed out on the console.
+You can send characters to the console back and they will be printed out onto console in a group of 4 characters.
+